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1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7#include <dt-bindings/pwm/pwm.h>
8#include "imx8mm.dtsi"
9#include "imx8mm-overdrive.dtsi"
10
11/ {
12 chosen {
13 stdout-path = &uart1;
14 };
15
16 aliases {
17 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc;
19 };
20
21 backlight: backlight {
22 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4>;
25 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
26 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
29 power-supply = <®_3p3v>;
30 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
31 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
32 status = "disabled";
33 };
34
35 /* Fixed clock dedicated to SPI CAN controller */
36 clk40m: oscillator {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <40000000>;
40 };
41
42 gpio-keys {
43 compatible = "gpio-keys";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_keys>;
46
47 key-wakeup {
48 debounce-interval = <10>;
49 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
50 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
51 label = "Wake-Up";
52 linux,code = <KEY_WAKEUP>;
53 wakeup-source;
54 };
55 };
56
57 hdmi_connector: hdmi-connector {
58 compatible = "hdmi-connector";
59 ddc-i2c-bus = <&i2c2>;
60 /* Verdin PWM_3_DSI (SODIMM 19) */
61 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
62 label = "hdmi";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
65 type = "a";
66 status = "disabled";
67 };
68
69 panel_lvds: panel-lvds {
70 compatible = "panel-lvds";
71 backlight = <&backlight>;
72 data-mapping = "vesa-24";
73 status = "disabled";
74 };
75
76 /* Carrier Board Supplies */
77 reg_1p8v: regulator-1p8v {
78 compatible = "regulator-fixed";
79 regulator-max-microvolt = <1800000>;
80 regulator-min-microvolt = <1800000>;
81 regulator-name = "+V1.8_SW";
82 };
83
84 reg_3p3v: regulator-3p3v {
85 compatible = "regulator-fixed";
86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <3300000>;
88 regulator-name = "+V3.3_SW";
89 };
90
91 reg_5p0v: regulator-5p0v {
92 compatible = "regulator-fixed";
93 regulator-max-microvolt = <5000000>;
94 regulator-min-microvolt = <5000000>;
95 regulator-name = "+V5_SW";
96 };
97
98 /* Non PMIC On-module Supplies */
99 reg_ethphy: regulator-ethphy {
100 compatible = "regulator-fixed";
101 enable-active-high;
102 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
103 off-on-delay-us = <500000>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_reg_eth>;
106 regulator-always-on;
107 regulator-boot-on;
108 regulator-max-microvolt = <3300000>;
109 regulator-min-microvolt = <3300000>;
110 regulator-name = "On-module +V3.3_ETH";
111 startup-delay-us = <200000>;
112 };
113
114 /*
115 * By default we enable CTRL_SLEEP_MOCI#, this is required to have
116 * peripherals on the carrier board powered.
117 * If more granularity or power saving is required this can be disabled
118 * in the carrier board device tree files.
119 */
120 reg_force_sleep_moci: regulator-force-sleep-moci {
121 compatible = "regulator-fixed";
122 enable-active-high;
123 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
124 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
125 regulator-always-on;
126 regulator-boot-on;
127 regulator-name = "CTRL_SLEEP_MOCI#";
128 };
129
130 reg_usb_otg1_vbus: regulator-usb-otg1 {
131 compatible = "regulator-fixed";
132 enable-active-high;
133 /* Verdin USB_1_EN (SODIMM 155) */
134 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_reg_usb1_en>;
137 regulator-max-microvolt = <5000000>;
138 regulator-min-microvolt = <5000000>;
139 regulator-name = "USB_1_EN";
140 };
141
142 reg_usb_otg2_vbus: regulator-usb-otg2 {
143 compatible = "regulator-fixed";
144 enable-active-high;
145 /* Verdin USB_2_EN (SODIMM 185) */
146 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb2_en>;
149 regulator-max-microvolt = <5000000>;
150 regulator-min-microvolt = <5000000>;
151 regulator-name = "USB_2_EN";
152 };
153
154 reg_usdhc2_vmmc: regulator-usdhc2 {
155 compatible = "regulator-fixed";
156 enable-active-high;
157 /* Verdin SD_1_PWR_EN (SODIMM 76) */
158 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
159 off-on-delay-us = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
162 regulator-max-microvolt = <3300000>;
163 regulator-min-microvolt = <3300000>;
164 regulator-name = "+V3.3_SD";
165 startup-delay-us = <20000>;
166 };
167
168 reserved-memory {
169 #address-cells = <2>;
170 #size-cells = <2>;
171 ranges;
172
173 /* Use the kernel configuration settings instead */
174 /delete-node/ linux,cma;
175 };
176};
177
178&A53_0 {
179 cpu-supply = <®_vdd_arm>;
180};
181
182&A53_1 {
183 cpu-supply = <®_vdd_arm>;
184};
185
186&A53_2 {
187 cpu-supply = <®_vdd_arm>;
188};
189
190&A53_3 {
191 cpu-supply = <®_vdd_arm>;
192};
193
194&cpu_alert0 {
195 temperature = <95000>;
196};
197
198&cpu_crit0 {
199 temperature = <105000>;
200};
201
202&ddrc {
203 operating-points-v2 = <&ddrc_opp_table>;
204
205 ddrc_opp_table: opp-table {
206 compatible = "operating-points-v2";
207
208 opp-25000000 {
209 opp-hz = /bits/ 64 <25000000>;
210 };
211
212 opp-100000000 {
213 opp-hz = /bits/ 64 <100000000>;
214 };
215
216 opp-750000000 {
217 opp-hz = /bits/ 64 <750000000>;
218 };
219 };
220};
221
222/* Verdin SPI_1 */
223&ecspi2 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_ecspi2>;
229};
230
231/* On-module SPI */
232&ecspi3 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>;
238 status = "okay";
239
240 /* Verdin CAN_1 */
241 can1: can@0 {
242 compatible = "microchip,mcp251xfd";
243 clocks = <&clk40m>;
244 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_can1_int>;
247 reg = <0>;
248 spi-max-frequency = <8500000>;
249 };
250
251 verdin_som_tpm: tpm@1 {
252 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
253 reg = <0x1>;
254 spi-max-frequency = <36000000>;
255 };
256};
257
258/* Verdin ETH_1 (On-module PHY) */
259&fec1 {
260 fsl,magic-packet;
261 phy-handle = <ðphy0>;
262 phy-mode = "rgmii-id";
263 phy-supply = <®_ethphy>;
264 pinctrl-names = "default", "sleep";
265 pinctrl-0 = <&pinctrl_fec1>;
266 pinctrl-1 = <&pinctrl_fec1_sleep>;
267
268 mdio {
269 #address-cells = <1>;
270 #size-cells = <0>;
271
272 ethphy0: ethernet-phy@7 {
273 compatible = "ethernet-phy-ieee802.3-c22";
274 interrupt-parent = <&gpio1>;
275 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
276 micrel,led-mode = <0>;
277 reg = <7>;
278 };
279 };
280};
281
282/* Verdin QSPI_1 */
283&flexspi {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_flexspi0>;
286};
287
288&gpio1 {
289 gpio-line-names = "SODIMM_216",
290 "SODIMM_19",
291 "",
292 "",
293 "",
294 "",
295 "",
296 "",
297 "SODIMM_220",
298 "SODIMM_222",
299 "",
300 "SODIMM_218",
301 "SODIMM_155",
302 "SODIMM_157",
303 "SODIMM_185",
304 "SODIMM_187";
305};
306
307&gpio2 {
308 gpio-line-names = "",
309 "",
310 "",
311 "",
312 "",
313 "",
314 "",
315 "",
316 "",
317 "",
318 "",
319 "",
320 "SODIMM_84",
321 "SODIMM_78",
322 "SODIMM_74",
323 "SODIMM_80",
324 "SODIMM_82",
325 "SODIMM_70",
326 "SODIMM_72";
327};
328
329&gpio5 {
330 gpio-line-names = "SODIMM_131",
331 "",
332 "SODIMM_91",
333 "SODIMM_16",
334 "SODIMM_15",
335 "SODIMM_208",
336 "SODIMM_137",
337 "SODIMM_139",
338 "SODIMM_141",
339 "SODIMM_143",
340 "SODIMM_196",
341 "SODIMM_200",
342 "SODIMM_198",
343 "SODIMM_202",
344 "",
345 "",
346 "SODIMM_55",
347 "SODIMM_53",
348 "SODIMM_95",
349 "SODIMM_93",
350 "SODIMM_14",
351 "SODIMM_12",
352 "",
353 "",
354 "",
355 "",
356 "SODIMM_210",
357 "SODIMM_212",
358 "SODIMM_151",
359 "SODIMM_153";
360};
361
362/* On-module I2C */
363&i2c1 {
364 clock-frequency = <400000>;
365 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&pinctrl_i2c1>;
367 pinctrl-1 = <&pinctrl_i2c1_gpio>;
368 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
369 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
370 single-master;
371 status = "okay";
372
373 pca9450: pmic@25 {
374 compatible = "nxp,pca9450a";
375 interrupt-parent = <&gpio1>;
376 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
377 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_pmic>;
380 reg = <0x25>;
381
382 /*
383 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
384 * behind this PMIC.
385 */
386
387 regulators {
388 reg_vdd_soc: BUCK1 {
389 nxp,dvs-run-voltage = <850000>;
390 nxp,dvs-standby-voltage = <800000>;
391 regulator-always-on;
392 regulator-boot-on;
393 regulator-max-microvolt = <850000>;
394 regulator-min-microvolt = <800000>;
395 regulator-name = "On-module +VDD_SOC (BUCK1)";
396 regulator-ramp-delay = <3125>;
397 };
398
399 reg_vdd_arm: BUCK2 {
400 nxp,dvs-run-voltage = <950000>;
401 nxp,dvs-standby-voltage = <850000>;
402 regulator-always-on;
403 regulator-boot-on;
404 regulator-max-microvolt = <1050000>;
405 regulator-min-microvolt = <805000>;
406 regulator-name = "On-module +VDD_ARM (BUCK2)";
407 regulator-ramp-delay = <3125>;
408 };
409
410 reg_vdd_dram: BUCK3 {
411 regulator-always-on;
412 regulator-boot-on;
413 regulator-max-microvolt = <1000000>;
414 regulator-min-microvolt = <805000>;
415 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
416 };
417
418 reg_vdd_3v3: BUCK4 {
419 regulator-always-on;
420 regulator-boot-on;
421 regulator-max-microvolt = <3300000>;
422 regulator-min-microvolt = <3300000>;
423 regulator-name = "On-module +V3.3 (BUCK4)";
424 };
425
426 reg_vdd_1v8: BUCK5 {
427 regulator-always-on;
428 regulator-boot-on;
429 regulator-max-microvolt = <1800000>;
430 regulator-min-microvolt = <1800000>;
431 regulator-name = "PWR_1V8_MOCI (BUCK5)";
432 };
433
434 reg_nvcc_dram: BUCK6 {
435 regulator-always-on;
436 regulator-boot-on;
437 regulator-max-microvolt = <1100000>;
438 regulator-min-microvolt = <1100000>;
439 regulator-name = "On-module +VDD_DDR (BUCK6)";
440 };
441
442 reg_nvcc_snvs: LDO1 {
443 regulator-always-on;
444 regulator-boot-on;
445 regulator-max-microvolt = <1800000>;
446 regulator-min-microvolt = <1800000>;
447 regulator-name = "On-module +V1.8_SNVS (LDO1)";
448 };
449
450 reg_vdd_snvs: LDO2 {
451 regulator-always-on;
452 regulator-boot-on;
453 regulator-max-microvolt = <800000>;
454 regulator-min-microvolt = <800000>;
455 regulator-name = "On-module +V0.8_SNVS (LDO2)";
456 };
457
458 reg_vdda: LDO3 {
459 regulator-always-on;
460 regulator-boot-on;
461 regulator-max-microvolt = <1800000>;
462 regulator-min-microvolt = <1800000>;
463 regulator-name = "On-module +V1.8A (LDO3)";
464 };
465
466 reg_vdd_phy: LDO4 {
467 regulator-always-on;
468 regulator-boot-on;
469 regulator-max-microvolt = <900000>;
470 regulator-min-microvolt = <900000>;
471 regulator-name = "On-module +V0.9_MIPI (LDO4)";
472 };
473
474 reg_nvcc_sd: LDO5 {
475 regulator-max-microvolt = <3300000>;
476 regulator-min-microvolt = <1800000>;
477 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
478 };
479 };
480 };
481
482 rtc_i2c: rtc@32 {
483 compatible = "epson,rx8130";
484 reg = <0x32>;
485 };
486
487 verdin_som_adc: adc@49 {
488 compatible = "ti,ads1015";
489 reg = <0x49>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 #io-channel-cells = <1>;
493
494 /* Verdin I2C_1 (ADC_4 - ADC_3) */
495 channel@0 {
496 reg = <0>;
497 ti,datarate = <4>;
498 ti,gain = <2>;
499 };
500
501 /* Verdin I2C_1 (ADC_4 - ADC_1) */
502 channel@1 {
503 reg = <1>;
504 ti,datarate = <4>;
505 ti,gain = <2>;
506 };
507
508 /* Verdin I2C_1 (ADC_3 - ADC_1) */
509 channel@2 {
510 reg = <2>;
511 ti,datarate = <4>;
512 ti,gain = <2>;
513 };
514
515 /* Verdin I2C_1 (ADC_2 - ADC_1) */
516 channel@3 {
517 reg = <3>;
518 ti,datarate = <4>;
519 ti,gain = <2>;
520 };
521
522 /* Verdin I2C_1 ADC_4 */
523 channel@4 {
524 reg = <4>;
525 ti,datarate = <4>;
526 ti,gain = <2>;
527 };
528
529 /* Verdin I2C_1 ADC_3 */
530 channel@5 {
531 reg = <5>;
532 ti,datarate = <4>;
533 ti,gain = <2>;
534 };
535
536 /* Verdin I2C_1 ADC_2 */
537 channel@6 {
538 reg = <6>;
539 ti,datarate = <4>;
540 ti,gain = <2>;
541 };
542
543 /* Verdin I2C_1 ADC_1 */
544 channel@7 {
545 reg = <7>;
546 ti,datarate = <4>;
547 ti,gain = <2>;
548 };
549 };
550
551 eeprom@50 {
552 compatible = "st,24c02";
553 pagesize = <16>;
554 reg = <0x50>;
555 };
556};
557
558/* Verdin I2C_2_DSI */
559&i2c2 {
560 clock-frequency = <400000>;
561 pinctrl-names = "default", "gpio";
562 pinctrl-0 = <&pinctrl_i2c2>;
563 pinctrl-1 = <&pinctrl_i2c2_gpio>;
564 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
565 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
566 single-master;
567 status = "disabled";
568};
569
570/* Verdin I2C_3_HDMI N/A */
571
572/* Verdin I2C_4_CSI */
573&i2c3 {
574 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio";
576 pinctrl-0 = <&pinctrl_i2c3>;
577 pinctrl-1 = <&pinctrl_i2c3_gpio>;
578 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
580 single-master;
581};
582
583/* Verdin I2C_1 */
584&i2c4 {
585 clock-frequency = <400000>;
586 pinctrl-names = "default", "gpio";
587 pinctrl-0 = <&pinctrl_i2c4>;
588 pinctrl-1 = <&pinctrl_i2c4_gpio>;
589 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
590 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
591 single-master;
592
593 gpio_expander_21: gpio-expander@21 {
594 compatible = "nxp,pcal6416";
595 #gpio-cells = <2>;
596 gpio-controller;
597 reg = <0x21>;
598 vcc-supply = <®_3p3v>;
599 status = "disabled";
600 };
601
602 lvds_ti_sn65dsi84: bridge@2c {
603 compatible = "ti,sn65dsi84";
604 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
605 /* Verdin GPIO_10_DSI (SODIMM 21) */
606 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
609 reg = <0x2c>;
610 status = "disabled";
611 };
612
613 /* Current measurement into module VCC */
614 hwmon: hwmon@40 {
615 compatible = "ti,ina219";
616 reg = <0x40>;
617 shunt-resistor = <10000>;
618 status = "disabled";
619 };
620
621 hdmi_lontium_lt8912: hdmi@48 {
622 compatible = "lontium,lt8912b";
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
625 reg = <0x48>;
626 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
627 /* Verdin GPIO_10_DSI (SODIMM 21) */
628 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
629 status = "disabled";
630 };
631
632 atmel_mxt_ts: touch@4a {
633 compatible = "atmel,maxtouch";
634 /*
635 * Verdin GPIO_9_DSI
636 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
637 */
638 interrupt-parent = <&gpio3>;
639 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
642 reg = <0x4a>;
643 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
644 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
645 status = "disabled";
646 };
647
648 /* Temperature sensor on carrier board */
649 hwmon_temp: sensor@4f {
650 compatible = "ti,tmp75c";
651 reg = <0x4f>;
652 status = "disabled";
653 };
654
655 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
656 eeprom_display_adapter: eeprom@50 {
657 compatible = "st,24c02";
658 pagesize = <16>;
659 reg = <0x50>;
660 status = "disabled";
661 };
662
663 /* EEPROM on carrier board */
664 eeprom_carrier_board: eeprom@57 {
665 compatible = "st,24c02";
666 pagesize = <16>;
667 reg = <0x57>;
668 status = "disabled";
669 };
670};
671
672/* Verdin PCIE_1 */
673&pcie0 {
674 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
675 <&clk IMX8MM_CLK_PCIE1_CTRL>;
676 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
677 <&clk IMX8MM_SYS_PLL2_250M>;
678 assigned-clock-rates = <10000000>, <250000000>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_pcie0>;
681 /* PCIE_1_RESET# (SODIMM 244) */
682 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
683};
684
685&pcie_phy {
686 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
687 clock-names = "ref";
688 fsl,clkreq-unsupported;
689 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
690 fsl,tx-deemph-gen1 = <0x2d>;
691 fsl,tx-deemph-gen2 = <0xf>;
692};
693
694/* Verdin PWM_3_DSI */
695&pwm1 {
696 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_pwm_1>;
698 #pwm-cells = <3>;
699};
700
701/* Verdin PWM_1 */
702&pwm2 {
703 pinctrl-names = "default";
704 pinctrl-0 = <&pinctrl_pwm_2>;
705 #pwm-cells = <3>;
706};
707
708/* Verdin PWM_2 */
709&pwm3 {
710 pinctrl-names = "default";
711 pinctrl-0 = <&pinctrl_pwm_3>;
712 #pwm-cells = <3>;
713};
714
715/* Verdin I2S_1 */
716&sai2 {
717 #sound-dai-cells = <0>;
718 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
719 assigned-clock-rates = <24576000>;
720 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
721 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_sai2>;
723};
724
725&snvs_pwrkey {
726 status = "okay";
727};
728
729/* Verdin UART_3, used as the Linux console */
730&uart1 {
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_uart1>;
733};
734
735/* Verdin UART_1 */
736&uart2 {
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_uart2>;
739 uart-has-rtscts;
740};
741
742/* Verdin UART_2 */
743&uart3 {
744 pinctrl-names = "default";
745 pinctrl-0 = <&pinctrl_uart3>;
746 uart-has-rtscts;
747};
748
749/*
750 * Verdin UART_4
751 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
752 */
753&uart4 {
754 pinctrl-names = "default";
755 pinctrl-0 = <&pinctrl_uart4>;
756};
757
758/* Verdin USB_1 */
759&usbotg1 {
760 adp-disable;
761 dr_mode = "otg";
762 hnp-disable;
763 samsung,picophy-dc-vol-level-adjust = <7>;
764 samsung,picophy-pre-emp-curr-control = <3>;
765 srp-disable;
766 vbus-supply = <®_usb_otg1_vbus>;
767};
768
769/* Verdin USB_2 */
770&usbotg2 {
771 dr_mode = "host";
772 samsung,picophy-dc-vol-level-adjust = <7>;
773 samsung,picophy-pre-emp-curr-control = <3>;
774 vbus-supply = <®_usb_otg2_vbus>;
775};
776
777&usbphynop1 {
778 vcc-supply = <®_vdd_3v3>;
779};
780
781&usbphynop2 {
782 power-domains = <&pgc_otg2>;
783 vcc-supply = <®_vdd_3v3>;
784};
785
786/* On-module eMMC */
787&usdhc1 {
788 bus-width = <8>;
789 keep-power-in-suspend;
790 non-removable;
791 pinctrl-names = "default", "state_100mhz", "state_200mhz";
792 pinctrl-0 = <&pinctrl_usdhc1>;
793 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
794 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
795 status = "okay";
796};
797
798/* Verdin SD_1 */
799&usdhc2 {
800 bus-width = <4>;
801 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
802 disable-wp;
803 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
804 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
805 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
806 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
807 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
808 vmmc-supply = <®_usdhc2_vmmc>;
809};
810
811&wdog1 {
812 fsl,ext-reset-output;
813 pinctrl-names = "default";
814 pinctrl-0 = <&pinctrl_wdog>;
815 status = "okay";
816};
817
818&iomuxc {
819 pinctrl-names = "default";
820 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
821 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
822 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
823 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
824
825 pinctrl_can1_int: can1intgrp {
826 fsl,pins =
827 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
828 };
829
830 pinctrl_can2_int: can2intgrp {
831 fsl,pins =
832 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
833 };
834
835 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
836 fsl,pins =
837 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
838 };
839
840 pinctrl_ecspi2: ecspi2grp {
841 fsl,pins =
842 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
843 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
844 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
845 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
846 };
847
848 pinctrl_ecspi3: ecspi3grp {
849 fsl,pins =
850 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
851 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
852 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
853 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
854 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
855 };
856
857 pinctrl_fec1: fec1grp {
858 fsl,pins =
859 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
860 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
861 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
862 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
863 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
864 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
865 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
866 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
867 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
868 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
869 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
870 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
871 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
872 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
873 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
874 };
875
876 pinctrl_fec1_sleep: fec1-sleepgrp {
877 fsl,pins =
878 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
879 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
880 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
881 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
882 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
883 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
884 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
885 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
886 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
887 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
888 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
889 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
890 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
891 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
892 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
893 };
894
895 pinctrl_flexspi0: flexspi0grp {
896 fsl,pins =
897 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
898 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
899 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
900 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
901 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
902 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
903 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
904 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
905 };
906
907 pinctrl_gpio1: gpio1grp {
908 fsl,pins =
909 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
910 };
911
912 pinctrl_gpio2: gpio2grp {
913 fsl,pins =
914 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
915 };
916
917 pinctrl_gpio3: gpio3grp {
918 fsl,pins =
919 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
920 };
921
922 pinctrl_gpio4: gpio4grp {
923 fsl,pins =
924 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
925 };
926
927 pinctrl_gpio5: gpio5grp {
928 fsl,pins =
929 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
930 };
931
932 pinctrl_gpio6: gpio6grp {
933 fsl,pins =
934 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
935 };
936
937 pinctrl_gpio7: gpio7grp {
938 fsl,pins =
939 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
940 };
941
942 pinctrl_gpio8: gpio8grp {
943 fsl,pins =
944 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
945 };
946
947 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
948 pinctrl_gpio_9_dsi: gpio9dsigrp {
949 fsl,pins =
950 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */
951 };
952
953 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
954 pinctrl_gpio_10_dsi: gpio10dsigrp {
955 fsl,pins =
956 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
957 };
958
959 pinctrl_gpio_hog1: gpiohog1grp {
960 fsl,pins =
961 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
962 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
963 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
964 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
965 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
966 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
967 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
968 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
969 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
970 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
971 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
972 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
973 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
974 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
975 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
976 };
977
978 pinctrl_gpio_hog2: gpiohog2grp {
979 fsl,pins =
980 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
981 };
982
983 pinctrl_gpio_hog3: gpiohog3grp {
984 fsl,pins =
985 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
986 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
987 };
988
989 pinctrl_gpio_keys: gpiokeysgrp {
990 fsl,pins =
991 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
992 };
993
994 /* On-module I2C */
995 pinctrl_i2c1: i2c1grp {
996 fsl,pins =
997 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
998 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
999 };
1000
1001 pinctrl_i2c1_gpio: i2c1gpiogrp {
1002 fsl,pins =
1003 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
1004 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
1005 };
1006
1007 /* Verdin I2C_4_CSI */
1008 pinctrl_i2c2: i2c2grp {
1009 fsl,pins =
1010 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
1011 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
1012 };
1013
1014 pinctrl_i2c2_gpio: i2c2gpiogrp {
1015 fsl,pins =
1016 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
1017 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
1018 };
1019
1020 /* Verdin I2C_2_DSI */
1021 pinctrl_i2c3: i2c3grp {
1022 fsl,pins =
1023 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
1024 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
1025 };
1026
1027 pinctrl_i2c3_gpio: i2c3gpiogrp {
1028 fsl,pins =
1029 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
1030 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
1031 };
1032
1033 /* Verdin I2C_1 */
1034 pinctrl_i2c4: i2c4grp {
1035 fsl,pins =
1036 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1037 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1038 };
1039
1040 pinctrl_i2c4_gpio: i2c4gpiogrp {
1041 fsl,pins =
1042 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1043 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1044 };
1045
1046 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1047 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1048 fsl,pins =
1049 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1050 };
1051
1052 /* Verdin I2S_2_D_OUT shared with SAI5 */
1053 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1054 fsl,pins =
1055 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1056 };
1057
1058 pinctrl_pcie0: pcie0grp {
1059 fsl,pins =
1060 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1061 /* PMIC_EN_PCIe_CLK, unused */
1062 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1063 };
1064
1065 pinctrl_pmic: pmicirqgrp {
1066 fsl,pins =
1067 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1068 };
1069
1070 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1071 pinctrl_pwm_1: pwm1grp {
1072 fsl,pins =
1073 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1074 };
1075
1076 pinctrl_pwm_2: pwm2grp {
1077 fsl,pins =
1078 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1079 };
1080
1081 pinctrl_pwm_3: pwm3grp {
1082 fsl,pins =
1083 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1084 };
1085
1086 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1087 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1088 fsl,pins =
1089 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1090 };
1091
1092 pinctrl_reg_eth: regethgrp {
1093 fsl,pins =
1094 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1095 };
1096
1097 pinctrl_reg_usb1_en: regusb1engrp {
1098 fsl,pins =
1099 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1100 };
1101
1102 pinctrl_reg_usb2_en: regusb2engrp {
1103 fsl,pins =
1104 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1105 };
1106
1107 pinctrl_sai2: sai2grp {
1108 fsl,pins =
1109 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1110 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1111 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1112 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1113 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1114 };
1115
1116 pinctrl_sai5: sai5grp {
1117 fsl,pins =
1118 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1119 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1120 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1121 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1122 };
1123
1124 /* control signal for optional ATTPM20P or SE050 */
1125 pinctrl_tpm_spi_cs: tpmspicsgrp {
1126 fsl,pins =
1127 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1128 };
1129
1130 pinctrl_tsp: tspgrp {
1131 fsl,pins =
1132 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1133 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1134 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1135 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1136 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1137 };
1138
1139 pinctrl_uart1: uart1grp {
1140 fsl,pins =
1141 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1142 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1143 };
1144
1145 pinctrl_uart2: uart2grp {
1146 fsl,pins =
1147 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1148 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1149 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1150 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1151 };
1152
1153 pinctrl_uart3: uart3grp {
1154 fsl,pins =
1155 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1156 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1157 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1158 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1159 };
1160
1161 pinctrl_uart4: uart4grp {
1162 fsl,pins =
1163 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1164 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1165 };
1166
1167 pinctrl_usdhc1: usdhc1grp {
1168 fsl,pins =
1169 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1170 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1171 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1172 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1173 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1174 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1175 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1176 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1177 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1178 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1179 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1180 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1181 };
1182
1183 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1184 fsl,pins =
1185 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1186 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1187 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1188 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1189 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1190 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1191 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1192 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1193 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1194 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1195 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1196 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1197 };
1198
1199 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1200 fsl,pins =
1201 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1202 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1203 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1204 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1205 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1206 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1207 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1208 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1209 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1210 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1211 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1212 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1213 };
1214
1215 pinctrl_usdhc2_cd: usdhc2cdgrp {
1216 fsl,pins =
1217 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1218 };
1219
1220 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1221 fsl,pins =
1222 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1223 };
1224
1225 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1226 fsl,pins =
1227 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1228 };
1229
1230 /*
1231 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1232 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1233 */
1234 pinctrl_usdhc2: usdhc2grp {
1235 fsl,pins =
1236 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1237 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1238 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1239 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1240 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1241 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1242 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1243 };
1244
1245 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1246 fsl,pins =
1247 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1248 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1249 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1250 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1251 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1252 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1253 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1254 };
1255
1256 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1257 fsl,pins =
1258 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1259 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1260 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1261 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1262 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1263 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1264 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1265 };
1266
1267 /* Avoid backfeeding with removed card power */
1268 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1269 fsl,pins =
1270 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1271 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1272 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1273 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1274 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1275 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1276 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1277 };
1278
1279 /*
1280 * On-module Wi-Fi/BT or type specific SDHC interface
1281 * (e.g. on X52 extension slot of Verdin Development Board)
1282 */
1283 pinctrl_usdhc3: usdhc3grp {
1284 fsl,pins =
1285 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1286 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1287 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1288 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1289 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1290 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1291 };
1292
1293 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1294 fsl,pins =
1295 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1296 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1297 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1298 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1299 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1300 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1301 };
1302
1303 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1304 fsl,pins =
1305 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1306 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1307 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1308 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1309 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1310 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1311 };
1312
1313 pinctrl_wdog: wdoggrp {
1314 fsl,pins =
1315 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1316 };
1317
1318 pinctrl_wifi_ctrl: wifictrlgrp {
1319 fsl,pins =
1320 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1321 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1322 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1323 };
1324
1325 pinctrl_wifi_i2s: bti2sgrp {
1326 fsl,pins =
1327 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1328 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1329 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1330 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1331 };
1332
1333 pinctrl_wifi_pwr_en: wifipwrengrp {
1334 fsl,pins =
1335 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1336 };
1337};