1// SPDX-License-Identifier: GPL-2.0+
 2/*
 3 * Copyright 2024 NXP
 4 */
 5
 6&hsio_subsys {
 7	phyx1_lpcg: clock-controller@5f090000 {
 8		compatible = "fsl,imx8qxp-lpcg";
 9		reg = <0x5f090000 0x10000>;
10		clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
11			 <&hsio_per_clk>, <&hsio_per_clk>;
12		#clock-cells = <1>;
13		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
14				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
15		clock-output-names = "hsio_phyx1_pclk",
16				     "hsio_phyx1_epcs_tx_clk",
17				     "hsio_phyx1_epcs_rx_clk",
18				     "hsio_phyx1_apb_clk";
19		power-domains = <&pd IMX_SC_R_SERDES_1>;
20	};
21
22	hsio_phy: phy@5f1a0000 {
23		compatible = "fsl,imx8qxp-hsio";
24		reg = <0x5f1a0000 0x10000>,
25		      <0x5f120000 0x10000>,
26		      <0x5f140000 0x10000>,
27		      <0x5f160000 0x10000>;
28		reg-names = "reg", "phy", "ctrl", "misc";
29		clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
30			 <&phyx1_lpcg IMX_LPCG_CLK_4>,
31			 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
32			 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
33			 <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
34		clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
35			      "misc_crr";
36		#phy-cells = <3>;
37		power-domains = <&pd IMX_SC_R_SERDES_1>;
38		status = "disabled";
39	};
40};
41
42&pcieb {
43	#interrupt-cells = <1>;
44	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
45	interrupt-names = "msi";
46	interrupt-map = <0 0 0 1 &gic 0 47 4>,
47			 <0 0 0 2 &gic 0 48 4>,
48			 <0 0 0 3 &gic 0 49 4>,
49			 <0 0 0 4 &gic 0 50 4>;
50	interrupt-map-mask = <0 0 0 0x7>;
51};