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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
5 */
6
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/mfd/syscon.h>
12#include <linux/regmap.h>
13#include "common.h"
14#include "hardware.h"
15
16#define REG_SET 0x4
17#define REG_CLR 0x8
18
19#define ANADIG_REG_2P5 0x130
20#define ANADIG_REG_CORE 0x140
21#define ANADIG_ANA_MISC0 0x150
22#define ANADIG_DIGPROG 0x260
23#define ANADIG_DIGPROG_IMX6SL 0x280
24#define ANADIG_DIGPROG_IMX7D 0x800
25
26#define SRC_SBMR2 0x1c
27
28#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
29#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
30#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
31#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
32/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
33#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
34
35static struct regmap *anatop;
36
37static void imx_anatop_enable_weak2p5(bool enable)
38{
39 u32 reg, val;
40
41 regmap_read(anatop, ANADIG_ANA_MISC0, &val);
42
43 /* can only be enabled when stop_mode_config is clear. */
44 reg = ANADIG_REG_2P5;
45 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
46 REG_SET : REG_CLR;
47 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
48}
49
50static void imx_anatop_enable_fet_odrive(bool enable)
51{
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
53 BM_ANADIG_REG_CORE_FET_ODRIVE);
54}
55
56static inline void imx_anatop_enable_2p5_pulldown(bool enable)
57{
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
59 BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
60}
61
62static inline void imx_anatop_disconnect_high_snvs(bool enable)
63{
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
65 BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
66}
67
68void imx_anatop_pre_suspend(void)
69{
70 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
71 imx_anatop_enable_2p5_pulldown(true);
72 else
73 imx_anatop_enable_weak2p5(true);
74
75 imx_anatop_enable_fet_odrive(true);
76
77 if (cpu_is_imx6sl())
78 imx_anatop_disconnect_high_snvs(true);
79}
80
81void imx_anatop_post_resume(void)
82{
83 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
84 imx_anatop_enable_2p5_pulldown(false);
85 else
86 imx_anatop_enable_weak2p5(false);
87
88 imx_anatop_enable_fet_odrive(false);
89
90 if (cpu_is_imx6sl())
91 imx_anatop_disconnect_high_snvs(false);
92}
93
94void __init imx_init_revision_from_anatop(void)
95{
96 struct device_node *np, *src_np;
97 void __iomem *anatop_base;
98 unsigned int revision;
99 u32 digprog;
100 u16 offset = ANADIG_DIGPROG;
101 u8 major_part, minor_part;
102
103 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
104 anatop_base = of_iomap(np, 0);
105 WARN_ON(!anatop_base);
106 if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
107 offset = ANADIG_DIGPROG_IMX6SL;
108 if (of_device_is_compatible(np, "fsl,imx7d-anatop"))
109 offset = ANADIG_DIGPROG_IMX7D;
110 digprog = readl_relaxed(anatop_base + offset);
111 iounmap(anatop_base);
112
113 /*
114 * On i.MX7D digprog value match linux version format, so
115 * it needn't map again and we can use register value directly.
116 */
117 if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
118 revision = digprog & 0xff;
119 } else {
120 /*
121 * MAJOR: [15:8], the major silicon revison;
122 * MINOR: [7: 0], the minor silicon revison;
123 *
124 * please refer to the i.MX RM for the detailed
125 * silicon revison bit define.
126 * format the major part and minor part to match the
127 * linux kernel soc version format.
128 */
129 major_part = (digprog >> 8) & 0xf;
130 minor_part = digprog & 0xf;
131 revision = ((major_part + 1) << 4) | minor_part;
132
133 if ((digprog >> 16) == MXC_CPU_IMX6ULL) {
134 void __iomem *src_base;
135 u32 sbmr2;
136
137 src_np = of_find_compatible_node(NULL, NULL,
138 "fsl,imx6ul-src");
139 src_base = of_iomap(src_np, 0);
140 of_node_put(src_np);
141 WARN_ON(!src_base);
142 sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
143 iounmap(src_base);
144
145 /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */
146 if (sbmr2 & (1 << 6)) {
147 digprog &= ~(0xff << 16);
148 digprog |= (MXC_CPU_IMX6ULZ << 16);
149 }
150 }
151 }
152 of_node_put(np);
153
154 mxc_set_cpu_type(digprog >> 16 & 0xff);
155 imx_set_soc_revision(revision);
156}
157
158void __init imx_anatop_init(void)
159{
160 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
161 if (IS_ERR(anatop))
162 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
163}
1/*
2 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18#include "common.h"
19#include "hardware.h"
20
21#define REG_SET 0x4
22#define REG_CLR 0x8
23
24#define ANADIG_REG_2P5 0x130
25#define ANADIG_REG_CORE 0x140
26#define ANADIG_ANA_MISC0 0x150
27#define ANADIG_USB1_CHRG_DETECT 0x1b0
28#define ANADIG_USB2_CHRG_DETECT 0x210
29#define ANADIG_DIGPROG 0x260
30#define ANADIG_DIGPROG_IMX6SL 0x280
31#define ANADIG_DIGPROG_IMX7D 0x800
32
33#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
34#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
35#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
36#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
37/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
38#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
39#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
40#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
41
42static struct regmap *anatop;
43
44static void imx_anatop_enable_weak2p5(bool enable)
45{
46 u32 reg, val;
47
48 regmap_read(anatop, ANADIG_ANA_MISC0, &val);
49
50 /* can only be enabled when stop_mode_config is clear. */
51 reg = ANADIG_REG_2P5;
52 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
53 REG_SET : REG_CLR;
54 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
55}
56
57static void imx_anatop_enable_fet_odrive(bool enable)
58{
59 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
60 BM_ANADIG_REG_CORE_FET_ODRIVE);
61}
62
63static inline void imx_anatop_enable_2p5_pulldown(bool enable)
64{
65 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
66 BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
67}
68
69static inline void imx_anatop_disconnect_high_snvs(bool enable)
70{
71 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
72 BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
73}
74
75void imx_anatop_pre_suspend(void)
76{
77 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
78 imx_anatop_enable_2p5_pulldown(true);
79 else
80 imx_anatop_enable_weak2p5(true);
81
82 imx_anatop_enable_fet_odrive(true);
83
84 if (cpu_is_imx6sl())
85 imx_anatop_disconnect_high_snvs(true);
86}
87
88void imx_anatop_post_resume(void)
89{
90 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
91 imx_anatop_enable_2p5_pulldown(false);
92 else
93 imx_anatop_enable_weak2p5(false);
94
95 imx_anatop_enable_fet_odrive(false);
96
97 if (cpu_is_imx6sl())
98 imx_anatop_disconnect_high_snvs(false);
99
100}
101
102static void imx_anatop_usb_chrg_detect_disable(void)
103{
104 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
105 BM_ANADIG_USB_CHRG_DETECT_EN_B
106 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
107 regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
108 BM_ANADIG_USB_CHRG_DETECT_EN_B |
109 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
110}
111
112void __init imx_init_revision_from_anatop(void)
113{
114 struct device_node *np;
115 void __iomem *anatop_base;
116 unsigned int revision;
117 u32 digprog;
118 u16 offset = ANADIG_DIGPROG;
119
120 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
121 anatop_base = of_iomap(np, 0);
122 WARN_ON(!anatop_base);
123 if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
124 offset = ANADIG_DIGPROG_IMX6SL;
125 if (of_device_is_compatible(np, "fsl,imx7d-anatop"))
126 offset = ANADIG_DIGPROG_IMX7D;
127 digprog = readl_relaxed(anatop_base + offset);
128 iounmap(anatop_base);
129
130 switch (digprog & 0xff) {
131 case 0:
132 /*
133 * For i.MX6QP, most of the code for i.MX6Q can be resued,
134 * so internally, we identify it as i.MX6Q Rev 2.0
135 */
136 if (digprog >> 8 & 0x01)
137 revision = IMX_CHIP_REVISION_2_0;
138 else
139 revision = IMX_CHIP_REVISION_1_0;
140 break;
141 case 1:
142 revision = IMX_CHIP_REVISION_1_1;
143 break;
144 case 2:
145 revision = IMX_CHIP_REVISION_1_2;
146 break;
147 case 3:
148 revision = IMX_CHIP_REVISION_1_3;
149 break;
150 case 4:
151 revision = IMX_CHIP_REVISION_1_4;
152 break;
153 case 5:
154 /*
155 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
156 * as 'D' in Part Number last character.
157 */
158 revision = IMX_CHIP_REVISION_1_5;
159 break;
160 default:
161 /*
162 * Fail back to return raw register value instead of 0xff.
163 * It will be easy to know version information in SOC if it
164 * can't be recognized by known version. And some chip's (i.MX7D)
165 * digprog value match linux version format, so it needn't map
166 * again and we can use register value directly.
167 */
168 revision = digprog & 0xff;
169 }
170
171 mxc_set_cpu_type(digprog >> 16 & 0xff);
172 imx_set_soc_revision(revision);
173}
174
175void __init imx_anatop_init(void)
176{
177 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
178 if (IS_ERR(anatop)) {
179 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
180 return;
181 }
182
183 imx_anatop_usb_chrg_detect_disable();
184}