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1/*
2 * Copyright (C) 2011 - 2014 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14
15/ {
16 compatible = "xlnx,zynq-7000";
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0>;
26 clocks = <&clkc 3>;
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
29 operating-points = <
30 /* kHz uV */
31 666667 1000000
32 333334 1000000
33 >;
34 };
35
36 cpu1: cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 clocks = <&clkc 3>;
41 };
42 };
43
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
49 };
50
51 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
60 amba: amba {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 interrupt-parent = <&intc>;
65 ranges;
66
67 adc: adc@f8007100 {
68 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
70 interrupts = <0 7 4>;
71 interrupt-parent = <&intc>;
72 clocks = <&clkc 12>;
73 };
74
75 can0: can@e0008000 {
76 compatible = "xlnx,zynq-can-1.0";
77 status = "disabled";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
85 };
86
87 can1: can@e0009000 {
88 compatible = "xlnx,zynq-can-1.0";
89 status = "disabled";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
97 };
98
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
101 #gpio-cells = <2>;
102 clocks = <&clkc 42>;
103 gpio-controller;
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 interrupt-parent = <&intc>;
107 interrupts = <0 20 4>;
108 reg = <0xe000a000 0x1000>;
109 };
110
111 i2c0: i2c@e0004000 {
112 compatible = "cdns,i2c-r1p10";
113 status = "disabled";
114 clocks = <&clkc 38>;
115 interrupt-parent = <&intc>;
116 interrupts = <0 25 4>;
117 reg = <0xe0004000 0x1000>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 };
121
122 i2c1: i2c@e0005000 {
123 compatible = "cdns,i2c-r1p10";
124 status = "disabled";
125 clocks = <&clkc 39>;
126 interrupt-parent = <&intc>;
127 interrupts = <0 48 4>;
128 reg = <0xe0005000 0x1000>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132
133 intc: interrupt-controller@f8f01000 {
134 compatible = "arm,cortex-a9-gic";
135 #interrupt-cells = <3>;
136 interrupt-controller;
137 reg = <0xF8F01000 0x1000>,
138 <0xF8F00100 0x100>;
139 };
140
141 L2: cache-controller@f8f02000 {
142 compatible = "arm,pl310-cache";
143 reg = <0xF8F02000 0x1000>;
144 interrupts = <0 2 4>;
145 arm,data-latency = <3 2 2>;
146 arm,tag-latency = <2 2 2>;
147 cache-unified;
148 cache-level = <2>;
149 };
150
151 mc: memory-controller@f8006000 {
152 compatible = "xlnx,zynq-ddrc-a05";
153 reg = <0xf8006000 0x1000>;
154 };
155
156 uart0: serial@e0000000 {
157 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
158 status = "disabled";
159 clocks = <&clkc 23>, <&clkc 40>;
160 clock-names = "uart_clk", "pclk";
161 reg = <0xE0000000 0x1000>;
162 interrupts = <0 27 4>;
163 };
164
165 uart1: serial@e0001000 {
166 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
167 status = "disabled";
168 clocks = <&clkc 24>, <&clkc 41>;
169 clock-names = "uart_clk", "pclk";
170 reg = <0xE0001000 0x1000>;
171 interrupts = <0 50 4>;
172 };
173
174 spi0: spi@e0006000 {
175 compatible = "xlnx,zynq-spi-r1p6";
176 reg = <0xe0006000 0x1000>;
177 status = "disabled";
178 interrupt-parent = <&intc>;
179 interrupts = <0 26 4>;
180 clocks = <&clkc 25>, <&clkc 34>;
181 clock-names = "ref_clk", "pclk";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
185
186 spi1: spi@e0007000 {
187 compatible = "xlnx,zynq-spi-r1p6";
188 reg = <0xe0007000 0x1000>;
189 status = "disabled";
190 interrupt-parent = <&intc>;
191 interrupts = <0 49 4>;
192 clocks = <&clkc 26>, <&clkc 35>;
193 clock-names = "ref_clk", "pclk";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
197
198 gem0: ethernet@e000b000 {
199 compatible = "cdns,zynq-gem", "cdns,gem";
200 reg = <0xe000b000 0x1000>;
201 status = "disabled";
202 interrupts = <0 22 4>;
203 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
204 clock-names = "pclk", "hclk", "tx_clk";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 };
208
209 gem1: ethernet@e000c000 {
210 compatible = "cdns,zynq-gem", "cdns,gem";
211 reg = <0xe000c000 0x1000>;
212 status = "disabled";
213 interrupts = <0 45 4>;
214 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
215 clock-names = "pclk", "hclk", "tx_clk";
216 #address-cells = <1>;
217 #size-cells = <0>;
218 };
219
220 sdhci0: sdhci@e0100000 {
221 compatible = "arasan,sdhci-8.9a";
222 status = "disabled";
223 clock-names = "clk_xin", "clk_ahb";
224 clocks = <&clkc 21>, <&clkc 32>;
225 interrupt-parent = <&intc>;
226 interrupts = <0 24 4>;
227 reg = <0xe0100000 0x1000>;
228 };
229
230 sdhci1: sdhci@e0101000 {
231 compatible = "arasan,sdhci-8.9a";
232 status = "disabled";
233 clock-names = "clk_xin", "clk_ahb";
234 clocks = <&clkc 22>, <&clkc 33>;
235 interrupt-parent = <&intc>;
236 interrupts = <0 47 4>;
237 reg = <0xe0101000 0x1000>;
238 };
239
240 slcr: slcr@f8000000 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
244 reg = <0xF8000000 0x1000>;
245 ranges;
246 clkc: clkc@100 {
247 #clock-cells = <1>;
248 compatible = "xlnx,ps7-clkc";
249 fclk-enable = <0>;
250 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
251 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
252 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
253 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
254 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
255 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
256 "gem1_aper", "sdio0_aper", "sdio1_aper",
257 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
258 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
259 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
260 "dbg_trc", "dbg_apb";
261 reg = <0x100 0x100>;
262 };
263
264 rstc: rstc@200 {
265 compatible = "xlnx,zynq-reset";
266 reg = <0x200 0x48>;
267 #reset-cells = <1>;
268 syscon = <&slcr>;
269 };
270
271 pinctrl0: pinctrl@700 {
272 compatible = "xlnx,pinctrl-zynq";
273 reg = <0x700 0x200>;
274 syscon = <&slcr>;
275 };
276 };
277
278 dmac_s: dmac@f8003000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0xf8003000 0x1000>;
281 interrupt-parent = <&intc>;
282 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
283 "dma4", "dma5", "dma6", "dma7";
284 interrupts = <0 13 4>,
285 <0 14 4>, <0 15 4>,
286 <0 16 4>, <0 17 4>,
287 <0 40 4>, <0 41 4>,
288 <0 42 4>, <0 43 4>;
289 #dma-cells = <1>;
290 #dma-channels = <8>;
291 #dma-requests = <4>;
292 clocks = <&clkc 27>;
293 clock-names = "apb_pclk";
294 };
295
296 devcfg: devcfg@f8007000 {
297 compatible = "xlnx,zynq-devcfg-1.0";
298 reg = <0xf8007000 0x100>;
299 interrupt-parent = <&intc>;
300 interrupts = <0 8 4>;
301 clocks = <&clkc 12>;
302 clock-names = "ref_clk";
303 syscon = <&slcr>;
304 };
305
306 global_timer: timer@f8f00200 {
307 compatible = "arm,cortex-a9-global-timer";
308 reg = <0xf8f00200 0x20>;
309 interrupts = <1 11 0x301>;
310 interrupt-parent = <&intc>;
311 clocks = <&clkc 4>;
312 };
313
314 ttc0: timer@f8001000 {
315 interrupt-parent = <&intc>;
316 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
317 compatible = "cdns,ttc";
318 clocks = <&clkc 6>;
319 reg = <0xF8001000 0x1000>;
320 };
321
322 ttc1: timer@f8002000 {
323 interrupt-parent = <&intc>;
324 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
325 compatible = "cdns,ttc";
326 clocks = <&clkc 6>;
327 reg = <0xF8002000 0x1000>;
328 };
329
330 scutimer: timer@f8f00600 {
331 interrupt-parent = <&intc>;
332 interrupts = <1 13 0x301>;
333 compatible = "arm,cortex-a9-twd-timer";
334 reg = <0xf8f00600 0x20>;
335 clocks = <&clkc 4>;
336 };
337
338 usb0: usb@e0002000 {
339 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
340 status = "disabled";
341 clocks = <&clkc 28>;
342 interrupt-parent = <&intc>;
343 interrupts = <0 21 4>;
344 reg = <0xe0002000 0x1000>;
345 phy_type = "ulpi";
346 };
347
348 usb1: usb@e0003000 {
349 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
350 status = "disabled";
351 clocks = <&clkc 29>;
352 interrupt-parent = <&intc>;
353 interrupts = <0 44 4>;
354 reg = <0xe0003000 0x1000>;
355 phy_type = "ulpi";
356 };
357
358 watchdog0: watchdog@f8005000 {
359 clocks = <&clkc 45>;
360 compatible = "cdns,wdt-r1p2";
361 interrupt-parent = <&intc>;
362 interrupts = <0 9 1>;
363 reg = <0xf8005000 0x1000>;
364 timeout-sec = <10>;
365 };
366 };
367};