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1/*
2 * Copyright 2015 Vishnu Patekar
3 *
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43
44 */
45
46#include "skeleton.dtsi"
47
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49
50#include <dt-bindings/pinctrl/sun4i-a10.h>
51
52/ {
53 interrupt-parent = <&gic>;
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu@0 {
60 compatible = "arm,cortex-a7";
61 device_type = "cpu";
62 reg = <0>;
63 };
64
65 cpu@1 {
66 compatible = "arm,cortex-a7";
67 device_type = "cpu";
68 reg = <1>;
69 };
70
71 cpu@2 {
72 compatible = "arm,cortex-a7";
73 device_type = "cpu";
74 reg = <2>;
75 };
76
77 cpu@3 {
78 compatible = "arm,cortex-a7";
79 device_type = "cpu";
80 reg = <3>;
81 };
82
83 cpu@100 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <0x100>;
87 };
88
89 cpu@101 {
90 compatible = "arm,cortex-a7";
91 device_type = "cpu";
92 reg = <0x101>;
93 };
94
95 cpu@102 {
96 compatible = "arm,cortex-a7";
97 device_type = "cpu";
98 reg = <0x102>;
99 };
100
101 cpu@103 {
102 compatible = "arm,cortex-a7";
103 device_type = "cpu";
104 reg = <0x103>;
105 };
106 };
107
108 timer {
109 compatible = "arm,armv7-timer";
110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
114 };
115
116 clocks {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges;
120
121 /* TODO: PRCM block has a mux for this. */
122 osc24M: osc24M_clk {
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "osc24M";
127 };
128
129 /*
130 * This is called "internal OSC" in some places.
131 * It is an internal RC-based oscillator.
132 * TODO: Its controls are in the PRCM block.
133 */
134 osc16M: osc16M_clk {
135 #clock-cells = <0>;
136 compatible = "fixed-clock";
137 clock-frequency = <16000000>;
138 clock-output-names = "osc16M";
139 };
140
141 osc16Md512: osc16Md512_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-factor-clock";
144 clock-div = <512>;
145 clock-mult = <1>;
146 clocks = <&osc16M>;
147 clock-output-names = "osc16M-d512";
148 };
149 };
150
151 soc {
152 compatible = "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges;
156
157 pio: pinctrl@01c20800 {
158 compatible = "allwinner,sun8i-a83t-pinctrl";
159 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
162 reg = <0x01c20800 0x400>;
163 clocks = <&osc24M>;
164 gpio-controller;
165 interrupt-controller;
166 #interrupt-cells = <3>;
167 #gpio-cells = <3>;
168
169 mmc0_pins_a: mmc0@0 {
170 allwinner,pins = "PF0", "PF1", "PF2",
171 "PF3", "PF4", "PF5";
172 allwinner,function = "mmc0";
173 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
174 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
175 };
176
177 uart0_pins_a: uart0@0 {
178 allwinner,pins = "PF2", "PF4";
179 allwinner,function = "uart0";
180 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
181 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
182 };
183
184 uart0_pins_b: uart0@1 {
185 allwinner,pins = "PB9", "PB10";
186 allwinner,function = "uart0";
187 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
188 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
189 };
190 };
191
192 timer@01c20c00 {
193 compatible = "allwinner,sun4i-a10-timer";
194 reg = <0x01c20c00 0xa0>;
195 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&osc24M>;
198 };
199
200 watchdog@01c20ca0 {
201 compatible = "allwinner,sun6i-a31-wdt";
202 reg = <0x01c20ca0 0x20>;
203 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&osc24M>;
205 };
206
207 uart0: serial@01c28000 {
208 compatible = "snps,dw-apb-uart";
209 reg = <0x01c28000 0x400>;
210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
211 reg-shift = <2>;
212 reg-io-width = <4>;
213 clocks = <&osc24M>;
214 status = "disabled";
215 };
216
217 gic: interrupt-controller@01c81000 {
218 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
219 reg = <0x01c81000 0x1000>,
220 <0x01c82000 0x1000>,
221 <0x01c84000 0x2000>,
222 <0x01c86000 0x2000>;
223 interrupt-controller;
224 #interrupt-cells = <3>;
225 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
226 };
227 };
228};