1/*
  2 * Samsung's S3C64xx SoC series common device tree source
  3 *
  4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
  5 *
  6 * Samsung's S3C64xx SoC series device nodes are listed in this file.
  7 * Particular SoCs from S3C64xx series can include this file and provide
  8 * values for SoCs specfic bindings.
  9 *
 10 * Note: This file does not include device nodes for all the controllers in
 11 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
 12 * nodes can be added to this file.
 13 *
 14 * This program is free software; you can redistribute it and/or modify
 15 * it under the terms of the GNU General Public License version 2 as
 16 * published by the Free Software Foundation.
 17 */
 18
 19#include "skeleton.dtsi"
 20#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
 21
 22/ {
 23	aliases {
 24		i2c0 = &i2c0;
 25		pinctrl0 = &pinctrl0;
 26		serial0 = &uart0;
 27		serial1 = &uart1;
 28		serial2 = &uart2;
 29		serial3 = &uart3;
 30	};
 31
 32	cpus {
 33		#address-cells = <1>;
 34		#size-cells = <0>;
 35
 36		cpu@0 {
 37			device_type = "cpu";
 38			compatible = "arm,arm1176jzf-s", "arm,arm1176";
 39			reg = <0x0>;
 40		};
 41	};
 42
 43	soc: soc {
 44		compatible = "simple-bus";
 45		#address-cells = <1>;
 46		#size-cells = <1>;
 47		ranges;
 48
 49		vic0: interrupt-controller@71200000 {
 50			compatible = "arm,pl192-vic";
 51			interrupt-controller;
 52			reg = <0x71200000 0x1000>;
 53			#interrupt-cells = <1>;
 54		};
 55
 56		vic1: interrupt-controller@71300000 {
 57			compatible = "arm,pl192-vic";
 58			interrupt-controller;
 59			reg = <0x71300000 0x1000>;
 60			#interrupt-cells = <1>;
 61		};
 62
 63		sdhci0: sdhci@7c200000 {
 64			compatible = "samsung,s3c6410-sdhci";
 65			reg = <0x7c200000 0x100>;
 66			interrupt-parent = <&vic1>;
 67			interrupts = <24>;
 68			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
 69			clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
 70					<&clocks SCLK_MMC0>;
 71			status = "disabled";
 72		};
 73
 74		sdhci1: sdhci@7c300000 {
 75			compatible = "samsung,s3c6410-sdhci";
 76			reg = <0x7c300000 0x100>;
 77			interrupt-parent = <&vic1>;
 78			interrupts = <25>;
 79			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
 80			clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
 81					<&clocks SCLK_MMC1>;
 82			status = "disabled";
 83		};
 84
 85		sdhci2: sdhci@7c400000 {
 86			compatible = "samsung,s3c6410-sdhci";
 87			reg = <0x7c400000 0x100>;
 88			interrupt-parent = <&vic1>;
 89			interrupts = <17>;
 90			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
 91			clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
 92					<&clocks SCLK_MMC2>;
 93			status = "disabled";
 94		};
 95
 96		watchdog: watchdog@7e004000 {
 97			compatible = "samsung,s3c2410-wdt";
 98			reg = <0x7e004000 0x1000>;
 99			interrupt-parent = <&vic0>;
100			interrupts = <26>;
101			clock-names = "watchdog";
102			clocks = <&clocks PCLK_WDT>;
103			status = "disabled";
104		};
105
106		i2c0: i2c@7f004000 {
107			compatible = "samsung,s3c2440-i2c";
108			reg = <0x7f004000 0x1000>;
109			interrupt-parent = <&vic1>;
110			interrupts = <18>;
111			clock-names = "i2c";
112			clocks = <&clocks PCLK_IIC0>;
113			status = "disabled";
114			#address-cells = <1>;
115			#size-cells = <0>;
116		};
117
118		uart0: serial@7f005000 {
119			compatible = "samsung,s3c6400-uart";
120			reg = <0x7f005000 0x100>;
121			interrupt-parent = <&vic1>;
122			interrupts = <5>;
123			clock-names = "uart", "clk_uart_baud2",
124					"clk_uart_baud3";
125			clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
126					<&clocks SCLK_UART>;
127			status = "disabled";
128		};
129
130		uart1: serial@7f005400 {
131			compatible = "samsung,s3c6400-uart";
132			reg = <0x7f005400 0x100>;
133			interrupt-parent = <&vic1>;
134			interrupts = <6>;
135			clock-names = "uart", "clk_uart_baud2",
136					"clk_uart_baud3";
137			clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
138					<&clocks SCLK_UART>;
139			status = "disabled";
140		};
141
142		uart2: serial@7f005800 {
143			compatible = "samsung,s3c6400-uart";
144			reg = <0x7f005800 0x100>;
145			interrupt-parent = <&vic1>;
146			interrupts = <7>;
147			clock-names = "uart", "clk_uart_baud2",
148					"clk_uart_baud3";
149			clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
150					<&clocks SCLK_UART>;
151			status = "disabled";
152		};
153
154		uart3: serial@7f005c00 {
155			compatible = "samsung,s3c6400-uart";
156			reg = <0x7f005c00 0x100>;
157			interrupt-parent = <&vic1>;
158			interrupts = <8>;
159			clock-names = "uart", "clk_uart_baud2",
160					"clk_uart_baud3";
161			clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
162					<&clocks SCLK_UART>;
163			status = "disabled";
164		};
165
166		pwm: pwm@7f006000 {
167			compatible = "samsung,s3c6400-pwm";
168			reg = <0x7f006000 0x1000>;
169			interrupt-parent = <&vic0>;
170			interrupts = <23>, <24>, <25>, <27>, <28>;
171			clock-names = "timers";
172			clocks = <&clocks PCLK_PWM>;
173			samsung,pwm-outputs = <0>, <1>;
174			#pwm-cells = <3>;
175		};
176
177		pinctrl0: pinctrl@7f008000 {
178			compatible = "samsung,s3c64xx-pinctrl";
179			reg = <0x7f008000 0x1000>;
180			interrupt-parent = <&vic1>;
181			interrupts = <21>;
182
183			pctrl_int_map: pinctrl-interrupt-map {
184				interrupt-map = <0 &vic0 0>,
185						<1 &vic0 1>,
186						<2 &vic1 0>,
187						<3 &vic1 1>;
188				#address-cells = <0>;
189				#size-cells = <0>;
190				#interrupt-cells = <1>;
191			};
192
193			wakeup-interrupt-controller {
194				compatible = "samsung,s3c64xx-wakeup-eint";
195				interrupts = <0>, <1>, <2>, <3>;
196				interrupt-parent = <&pctrl_int_map>;
197			};
198		};
199	};
200};
201
202#include "s3c64xx-pinctrl.dtsi"