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1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <dt-bindings/clock/r8a7790-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
32 spi0 = &qspi;
33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
55 next-level-cache = <&L2_CA15>;
56
57 /* kHz - uV - OPPs unknown yet */
58 operating-points = <1400000 1000000>,
59 <1225000 1000000>,
60 <1050000 1000000>,
61 < 875000 1000000>,
62 < 700000 1000000>,
63 < 350000 1000000>;
64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <1>;
70 clock-frequency = <1300000000>;
71 next-level-cache = <&L2_CA15>;
72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <2>;
78 clock-frequency = <1300000000>;
79 next-level-cache = <&L2_CA15>;
80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <3>;
86 clock-frequency = <1300000000>;
87 next-level-cache = <&L2_CA15>;
88 };
89
90 cpu4: cpu@4 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <780000000>;
95 next-level-cache = <&L2_CA7>;
96 };
97
98 cpu5: cpu@5 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <780000000>;
103 next-level-cache = <&L2_CA7>;
104 };
105
106 cpu6: cpu@6 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <780000000>;
111 next-level-cache = <&L2_CA7>;
112 };
113
114 cpu7: cpu@7 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <780000000>;
119 next-level-cache = <&L2_CA7>;
120 };
121 };
122
123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay-passive = <0>;
126 polling-delay = <0>;
127
128 thermal-sensors = <&thermal>;
129
130 trips {
131 cpu-crit {
132 temperature = <115000>;
133 hysteresis = <0>;
134 type = "critical";
135 };
136 };
137 cooling-maps {
138 };
139 };
140 };
141
142 L2_CA15: cache-controller@0 {
143 compatible = "cache";
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 L2_CA7: cache-controller@1 {
149 compatible = "cache";
150 cache-unified;
151 cache-level = <2>;
152 };
153
154 gic: interrupt-controller@f1001000 {
155 compatible = "arm,gic-400";
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0 0xf1001000 0 0x1000>,
160 <0 0xf1002000 0 0x1000>,
161 <0 0xf1004000 0 0x2000>,
162 <0 0xf1006000 0 0x2000>;
163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
164 };
165
166 gpio0: gpio@e6050000 {
167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
168 reg = <0 0xe6050000 0 0x50>;
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 0 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
176 power-domains = <&cpg_clocks>;
177 };
178
179 gpio1: gpio@e6051000 {
180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
181 reg = <0 0xe6051000 0 0x50>;
182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 32 30>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
189 power-domains = <&cpg_clocks>;
190 };
191
192 gpio2: gpio@e6052000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6052000 0 0x50>;
195 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 64 30>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
202 power-domains = <&cpg_clocks>;
203 };
204
205 gpio3: gpio@e6053000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6053000 0 0x50>;
208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 96 32>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
215 power-domains = <&cpg_clocks>;
216 };
217
218 gpio4: gpio@e6054000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6054000 0 0x50>;
221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 128 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
228 power-domains = <&cpg_clocks>;
229 };
230
231 gpio5: gpio@e6055000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6055000 0 0x50>;
234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 160 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
241 power-domains = <&cpg_clocks>;
242 };
243
244 thermal: thermal@e61f0000 {
245 compatible = "renesas,thermal-r8a7790",
246 "renesas,rcar-gen2-thermal",
247 "renesas,rcar-thermal";
248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
251 power-domains = <&cpg_clocks>;
252 #thermal-sensor-cells = <0>;
253 };
254
255 timer {
256 compatible = "arm,armv7-timer";
257 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
258 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
260 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
261 };
262
263 cmt0: timer@ffca0000 {
264 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
265 reg = <0 0xffca0000 0 0x1004>;
266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
269 clock-names = "fck";
270 power-domains = <&cpg_clocks>;
271
272 renesas,channels-mask = <0x60>;
273
274 status = "disabled";
275 };
276
277 cmt1: timer@e6130000 {
278 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
279 reg = <0 0xe6130000 0 0x1004>;
280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
289 clock-names = "fck";
290 power-domains = <&cpg_clocks>;
291
292 renesas,channels-mask = <0xff>;
293
294 status = "disabled";
295 };
296
297 irqc0: interrupt-controller@e61c0000 {
298 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 reg = <0 0xe61c0000 0 0x200>;
302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
307 power-domains = <&cpg_clocks>;
308 };
309
310 dmac0: dma-controller@e6700000 {
311 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
312 reg = <0 0xe6700000 0 0x20000>;
313 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "error",
330 "ch0", "ch1", "ch2", "ch3",
331 "ch4", "ch5", "ch6", "ch7",
332 "ch8", "ch9", "ch10", "ch11",
333 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
335 clock-names = "fck";
336 power-domains = <&cpg_clocks>;
337 #dma-cells = <1>;
338 dma-channels = <15>;
339 };
340
341 dmac1: dma-controller@e6720000 {
342 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
343 reg = <0 0xe6720000 0 0x20000>;
344 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "error",
361 "ch0", "ch1", "ch2", "ch3",
362 "ch4", "ch5", "ch6", "ch7",
363 "ch8", "ch9", "ch10", "ch11",
364 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
366 clock-names = "fck";
367 power-domains = <&cpg_clocks>;
368 #dma-cells = <1>;
369 dma-channels = <15>;
370 };
371
372 audma0: dma-controller@ec700000 {
373 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
374 reg = <0 0xec700000 0 0x10000>;
375 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "error",
390 "ch0", "ch1", "ch2", "ch3",
391 "ch4", "ch5", "ch6", "ch7",
392 "ch8", "ch9", "ch10", "ch11",
393 "ch12";
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
395 clock-names = "fck";
396 power-domains = <&cpg_clocks>;
397 #dma-cells = <1>;
398 dma-channels = <13>;
399 };
400
401 audma1: dma-controller@ec720000 {
402 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
403 reg = <0 0xec720000 0 0x10000>;
404 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "error",
419 "ch0", "ch1", "ch2", "ch3",
420 "ch4", "ch5", "ch6", "ch7",
421 "ch8", "ch9", "ch10", "ch11",
422 "ch12";
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
424 clock-names = "fck";
425 power-domains = <&cpg_clocks>;
426 #dma-cells = <1>;
427 dma-channels = <13>;
428 };
429
430 usb_dmac0: dma-controller@e65a0000 {
431 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
432 reg = <0 0xe65a0000 0 0x100>;
433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
437 power-domains = <&cpg_clocks>;
438 #dma-cells = <1>;
439 dma-channels = <2>;
440 };
441
442 usb_dmac1: dma-controller@e65b0000 {
443 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
444 reg = <0 0xe65b0000 0 0x100>;
445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
449 power-domains = <&cpg_clocks>;
450 #dma-cells = <1>;
451 dma-channels = <2>;
452 };
453
454 i2c0: i2c@e6508000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "renesas,i2c-r8a7790";
458 reg = <0 0xe6508000 0 0x40>;
459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
461 power-domains = <&cpg_clocks>;
462 i2c-scl-internal-delay-ns = <110>;
463 status = "disabled";
464 };
465
466 i2c1: i2c@e6518000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,i2c-r8a7790";
470 reg = <0 0xe6518000 0 0x40>;
471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
473 power-domains = <&cpg_clocks>;
474 i2c-scl-internal-delay-ns = <6>;
475 status = "disabled";
476 };
477
478 i2c2: i2c@e6530000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "renesas,i2c-r8a7790";
482 reg = <0 0xe6530000 0 0x40>;
483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
485 power-domains = <&cpg_clocks>;
486 i2c-scl-internal-delay-ns = <6>;
487 status = "disabled";
488 };
489
490 i2c3: i2c@e6540000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a7790";
494 reg = <0 0xe6540000 0 0x40>;
495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
497 power-domains = <&cpg_clocks>;
498 i2c-scl-internal-delay-ns = <110>;
499 status = "disabled";
500 };
501
502 iic0: i2c@e6500000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
506 reg = <0 0xe6500000 0 0x425>;
507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
509 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx";
511 power-domains = <&cpg_clocks>;
512 status = "disabled";
513 };
514
515 iic1: i2c@e6510000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6510000 0 0x425>;
520 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
522 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx";
524 power-domains = <&cpg_clocks>;
525 status = "disabled";
526 };
527
528 iic2: i2c@e6520000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6520000 0 0x425>;
533 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx";
537 power-domains = <&cpg_clocks>;
538 status = "disabled";
539 };
540
541 iic3: i2c@e60b0000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
545 reg = <0 0xe60b0000 0 0x425>;
546 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
548 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx";
550 power-domains = <&cpg_clocks>;
551 status = "disabled";
552 };
553
554 mmcif0: mmc@ee200000 {
555 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
556 reg = <0 0xee200000 0 0x80>;
557 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx";
561 power-domains = <&cpg_clocks>;
562 reg-io-width = <4>;
563 status = "disabled";
564 max-frequency = <97500000>;
565 };
566
567 mmcif1: mmc@ee220000 {
568 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
569 reg = <0 0xee220000 0 0x80>;
570 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx";
574 power-domains = <&cpg_clocks>;
575 reg-io-width = <4>;
576 status = "disabled";
577 max-frequency = <97500000>;
578 };
579
580 pfc: pfc@e6060000 {
581 compatible = "renesas,pfc-r8a7790";
582 reg = <0 0xe6060000 0 0x250>;
583 };
584
585 sdhi0: sd@ee100000 {
586 compatible = "renesas,sdhi-r8a7790";
587 reg = <0 0xee100000 0 0x328>;
588 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx";
592 power-domains = <&cpg_clocks>;
593 status = "disabled";
594 };
595
596 sdhi1: sd@ee120000 {
597 compatible = "renesas,sdhi-r8a7790";
598 reg = <0 0xee120000 0 0x328>;
599 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
601 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
602 dma-names = "tx", "rx";
603 power-domains = <&cpg_clocks>;
604 status = "disabled";
605 };
606
607 sdhi2: sd@ee140000 {
608 compatible = "renesas,sdhi-r8a7790";
609 reg = <0 0xee140000 0 0x100>;
610 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
612 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
613 dma-names = "tx", "rx";
614 power-domains = <&cpg_clocks>;
615 status = "disabled";
616 };
617
618 sdhi3: sd@ee160000 {
619 compatible = "renesas,sdhi-r8a7790";
620 reg = <0 0xee160000 0 0x100>;
621 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
623 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
624 dma-names = "tx", "rx";
625 power-domains = <&cpg_clocks>;
626 status = "disabled";
627 };
628
629 scifa0: serial@e6c40000 {
630 compatible = "renesas,scifa-r8a7790",
631 "renesas,rcar-gen2-scifa", "renesas,scifa";
632 reg = <0 0xe6c40000 0 64>;
633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
635 clock-names = "fck";
636 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
637 dma-names = "tx", "rx";
638 power-domains = <&cpg_clocks>;
639 status = "disabled";
640 };
641
642 scifa1: serial@e6c50000 {
643 compatible = "renesas,scifa-r8a7790",
644 "renesas,rcar-gen2-scifa", "renesas,scifa";
645 reg = <0 0xe6c50000 0 64>;
646 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
648 clock-names = "fck";
649 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
650 dma-names = "tx", "rx";
651 power-domains = <&cpg_clocks>;
652 status = "disabled";
653 };
654
655 scifa2: serial@e6c60000 {
656 compatible = "renesas,scifa-r8a7790",
657 "renesas,rcar-gen2-scifa", "renesas,scifa";
658 reg = <0 0xe6c60000 0 64>;
659 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
661 clock-names = "fck";
662 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
663 dma-names = "tx", "rx";
664 power-domains = <&cpg_clocks>;
665 status = "disabled";
666 };
667
668 scifb0: serial@e6c20000 {
669 compatible = "renesas,scifb-r8a7790",
670 "renesas,rcar-gen2-scifb", "renesas,scifb";
671 reg = <0 0xe6c20000 0 64>;
672 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
674 clock-names = "fck";
675 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
676 dma-names = "tx", "rx";
677 power-domains = <&cpg_clocks>;
678 status = "disabled";
679 };
680
681 scifb1: serial@e6c30000 {
682 compatible = "renesas,scifb-r8a7790",
683 "renesas,rcar-gen2-scifb", "renesas,scifb";
684 reg = <0 0xe6c30000 0 64>;
685 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
687 clock-names = "fck";
688 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
689 dma-names = "tx", "rx";
690 power-domains = <&cpg_clocks>;
691 status = "disabled";
692 };
693
694 scifb2: serial@e6ce0000 {
695 compatible = "renesas,scifb-r8a7790",
696 "renesas,rcar-gen2-scifb", "renesas,scifb";
697 reg = <0 0xe6ce0000 0 64>;
698 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
700 clock-names = "fck";
701 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
702 dma-names = "tx", "rx";
703 power-domains = <&cpg_clocks>;
704 status = "disabled";
705 };
706
707 scif0: serial@e6e60000 {
708 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
709 "renesas,scif";
710 reg = <0 0xe6e60000 0 64>;
711 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
713 <&scif_clk>;
714 clock-names = "fck", "brg_int", "scif_clk";
715 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
716 dma-names = "tx", "rx";
717 power-domains = <&cpg_clocks>;
718 status = "disabled";
719 };
720
721 scif1: serial@e6e68000 {
722 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
723 "renesas,scif";
724 reg = <0 0xe6e68000 0 64>;
725 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
727 <&scif_clk>;
728 clock-names = "fck", "brg_int", "scif_clk";
729 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
730 dma-names = "tx", "rx";
731 power-domains = <&cpg_clocks>;
732 status = "disabled";
733 };
734
735 hscif0: serial@e62c0000 {
736 compatible = "renesas,hscif-r8a7790",
737 "renesas,rcar-gen2-hscif", "renesas,hscif";
738 reg = <0 0xe62c0000 0 96>;
739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
741 <&scif_clk>;
742 clock-names = "fck", "brg_int", "scif_clk";
743 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
744 dma-names = "tx", "rx";
745 power-domains = <&cpg_clocks>;
746 status = "disabled";
747 };
748
749 hscif1: serial@e62c8000 {
750 compatible = "renesas,hscif-r8a7790",
751 "renesas,rcar-gen2-hscif", "renesas,hscif";
752 reg = <0 0xe62c8000 0 96>;
753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
755 <&scif_clk>;
756 clock-names = "fck", "brg_int", "scif_clk";
757 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
758 dma-names = "tx", "rx";
759 power-domains = <&cpg_clocks>;
760 status = "disabled";
761 };
762
763 ether: ethernet@ee700000 {
764 compatible = "renesas,ether-r8a7790";
765 reg = <0 0xee700000 0 0x400>;
766 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
768 power-domains = <&cpg_clocks>;
769 phy-mode = "rmii";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 status = "disabled";
773 };
774
775 avb: ethernet@e6800000 {
776 compatible = "renesas,etheravb-r8a7790",
777 "renesas,etheravb-rcar-gen2";
778 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
779 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
781 power-domains = <&cpg_clocks>;
782 #address-cells = <1>;
783 #size-cells = <0>;
784 status = "disabled";
785 };
786
787 sata0: sata@ee300000 {
788 compatible = "renesas,sata-r8a7790";
789 reg = <0 0xee300000 0 0x2000>;
790 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
792 power-domains = <&cpg_clocks>;
793 status = "disabled";
794 };
795
796 sata1: sata@ee500000 {
797 compatible = "renesas,sata-r8a7790";
798 reg = <0 0xee500000 0 0x2000>;
799 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
801 power-domains = <&cpg_clocks>;
802 status = "disabled";
803 };
804
805 hsusb: usb@e6590000 {
806 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
807 reg = <0 0xe6590000 0 0x100>;
808 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
810 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
811 <&usb_dmac1 0>, <&usb_dmac1 1>;
812 dma-names = "ch0", "ch1", "ch2", "ch3";
813 power-domains = <&cpg_clocks>;
814 renesas,buswait = <4>;
815 phys = <&usb0 1>;
816 phy-names = "usb";
817 status = "disabled";
818 };
819
820 usbphy: usb-phy@e6590100 {
821 compatible = "renesas,usb-phy-r8a7790";
822 reg = <0 0xe6590100 0 0x100>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
826 clock-names = "usbhs";
827 power-domains = <&cpg_clocks>;
828 status = "disabled";
829
830 usb0: usb-channel@0 {
831 reg = <0>;
832 #phy-cells = <1>;
833 };
834 usb2: usb-channel@2 {
835 reg = <2>;
836 #phy-cells = <1>;
837 };
838 };
839
840 vin0: video@e6ef0000 {
841 compatible = "renesas,vin-r8a7790";
842 reg = <0 0xe6ef0000 0 0x1000>;
843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
845 power-domains = <&cpg_clocks>;
846 status = "disabled";
847 };
848
849 vin1: video@e6ef1000 {
850 compatible = "renesas,vin-r8a7790";
851 reg = <0 0xe6ef1000 0 0x1000>;
852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
854 power-domains = <&cpg_clocks>;
855 status = "disabled";
856 };
857
858 vin2: video@e6ef2000 {
859 compatible = "renesas,vin-r8a7790";
860 reg = <0 0xe6ef2000 0 0x1000>;
861 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
863 power-domains = <&cpg_clocks>;
864 status = "disabled";
865 };
866
867 vin3: video@e6ef3000 {
868 compatible = "renesas,vin-r8a7790";
869 reg = <0 0xe6ef3000 0 0x1000>;
870 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
872 power-domains = <&cpg_clocks>;
873 status = "disabled";
874 };
875
876 vsp1@fe920000 {
877 compatible = "renesas,vsp1";
878 reg = <0 0xfe920000 0 0x8000>;
879 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
881 power-domains = <&cpg_clocks>;
882
883 renesas,has-sru;
884 renesas,#rpf = <5>;
885 renesas,#uds = <1>;
886 renesas,#wpf = <4>;
887 };
888
889 vsp1@fe928000 {
890 compatible = "renesas,vsp1";
891 reg = <0 0xfe928000 0 0x8000>;
892 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
894 power-domains = <&cpg_clocks>;
895
896 renesas,has-lut;
897 renesas,has-sru;
898 renesas,#rpf = <5>;
899 renesas,#uds = <3>;
900 renesas,#wpf = <4>;
901 };
902
903 vsp1@fe930000 {
904 compatible = "renesas,vsp1";
905 reg = <0 0xfe930000 0 0x8000>;
906 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
908 power-domains = <&cpg_clocks>;
909
910 renesas,has-lif;
911 renesas,has-lut;
912 renesas,#rpf = <4>;
913 renesas,#uds = <1>;
914 renesas,#wpf = <4>;
915 };
916
917 vsp1@fe938000 {
918 compatible = "renesas,vsp1";
919 reg = <0 0xfe938000 0 0x8000>;
920 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
922 power-domains = <&cpg_clocks>;
923
924 renesas,has-lif;
925 renesas,has-lut;
926 renesas,#rpf = <4>;
927 renesas,#uds = <1>;
928 renesas,#wpf = <4>;
929 };
930
931 du: display@feb00000 {
932 compatible = "renesas,du-r8a7790";
933 reg = <0 0xfeb00000 0 0x70000>,
934 <0 0xfeb90000 0 0x1c>,
935 <0 0xfeb94000 0 0x1c>;
936 reg-names = "du", "lvds.0", "lvds.1";
937 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
941 <&mstp7_clks R8A7790_CLK_DU1>,
942 <&mstp7_clks R8A7790_CLK_DU2>,
943 <&mstp7_clks R8A7790_CLK_LVDS0>,
944 <&mstp7_clks R8A7790_CLK_LVDS1>;
945 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
946 status = "disabled";
947
948 ports {
949 #address-cells = <1>;
950 #size-cells = <0>;
951
952 port@0 {
953 reg = <0>;
954 du_out_rgb: endpoint {
955 };
956 };
957 port@1 {
958 reg = <1>;
959 du_out_lvds0: endpoint {
960 };
961 };
962 port@2 {
963 reg = <2>;
964 du_out_lvds1: endpoint {
965 };
966 };
967 };
968 };
969
970 can0: can@e6e80000 {
971 compatible = "renesas,can-r8a7790";
972 reg = <0 0xe6e80000 0 0x1000>;
973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
975 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
976 clock-names = "clkp1", "clkp2", "can_clk";
977 power-domains = <&cpg_clocks>;
978 status = "disabled";
979 };
980
981 can1: can@e6e88000 {
982 compatible = "renesas,can-r8a7790";
983 reg = <0 0xe6e88000 0 0x1000>;
984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
986 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
987 clock-names = "clkp1", "clkp2", "can_clk";
988 power-domains = <&cpg_clocks>;
989 status = "disabled";
990 };
991
992 jpu: jpeg-codec@fe980000 {
993 compatible = "renesas,jpu-r8a7790";
994 reg = <0 0xfe980000 0 0x10300>;
995 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
997 power-domains = <&cpg_clocks>;
998 };
999
1000 clocks {
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 ranges;
1004
1005 /* External root clock */
1006 extal_clk: extal_clk {
1007 compatible = "fixed-clock";
1008 #clock-cells = <0>;
1009 /* This value must be overriden by the board. */
1010 clock-frequency = <0>;
1011 clock-output-names = "extal";
1012 };
1013
1014 /* External PCIe clock - can be overridden by the board */
1015 pcie_bus_clk: pcie_bus_clk {
1016 compatible = "fixed-clock";
1017 #clock-cells = <0>;
1018 clock-frequency = <100000000>;
1019 clock-output-names = "pcie_bus";
1020 status = "disabled";
1021 };
1022
1023 /*
1024 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1025 * default. Boards that provide audio clocks should override them.
1026 */
1027 audio_clk_a: audio_clk_a {
1028 compatible = "fixed-clock";
1029 #clock-cells = <0>;
1030 clock-frequency = <0>;
1031 clock-output-names = "audio_clk_a";
1032 };
1033 audio_clk_b: audio_clk_b {
1034 compatible = "fixed-clock";
1035 #clock-cells = <0>;
1036 clock-frequency = <0>;
1037 clock-output-names = "audio_clk_b";
1038 };
1039 audio_clk_c: audio_clk_c {
1040 compatible = "fixed-clock";
1041 #clock-cells = <0>;
1042 clock-frequency = <0>;
1043 clock-output-names = "audio_clk_c";
1044 };
1045
1046 /* External SCIF clock */
1047 scif_clk: scif {
1048 compatible = "fixed-clock";
1049 #clock-cells = <0>;
1050 /* This value must be overridden by the board. */
1051 clock-frequency = <0>;
1052 status = "disabled";
1053 };
1054
1055 /* External USB clock - can be overridden by the board */
1056 usb_extal_clk: usb_extal_clk {
1057 compatible = "fixed-clock";
1058 #clock-cells = <0>;
1059 clock-frequency = <48000000>;
1060 clock-output-names = "usb_extal";
1061 };
1062
1063 /* External CAN clock */
1064 can_clk: can_clk {
1065 compatible = "fixed-clock";
1066 #clock-cells = <0>;
1067 /* This value must be overridden by the board. */
1068 clock-frequency = <0>;
1069 clock-output-names = "can_clk";
1070 status = "disabled";
1071 };
1072
1073 /* Special CPG clocks */
1074 cpg_clocks: cpg_clocks@e6150000 {
1075 compatible = "renesas,r8a7790-cpg-clocks",
1076 "renesas,rcar-gen2-cpg-clocks";
1077 reg = <0 0xe6150000 0 0x1000>;
1078 clocks = <&extal_clk &usb_extal_clk>;
1079 #clock-cells = <1>;
1080 clock-output-names = "main", "pll0", "pll1", "pll3",
1081 "lb", "qspi", "sdh", "sd0", "sd1",
1082 "z", "rcan", "adsp";
1083 #power-domain-cells = <0>;
1084 };
1085
1086 /* Variable factor clocks */
1087 sd2_clk: sd2_clk@e6150078 {
1088 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1089 reg = <0 0xe6150078 0 4>;
1090 clocks = <&pll1_div2_clk>;
1091 #clock-cells = <0>;
1092 clock-output-names = "sd2";
1093 };
1094 sd3_clk: sd3_clk@e615026c {
1095 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1096 reg = <0 0xe615026c 0 4>;
1097 clocks = <&pll1_div2_clk>;
1098 #clock-cells = <0>;
1099 clock-output-names = "sd3";
1100 };
1101 mmc0_clk: mmc0_clk@e6150240 {
1102 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1103 reg = <0 0xe6150240 0 4>;
1104 clocks = <&pll1_div2_clk>;
1105 #clock-cells = <0>;
1106 clock-output-names = "mmc0";
1107 };
1108 mmc1_clk: mmc1_clk@e6150244 {
1109 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1110 reg = <0 0xe6150244 0 4>;
1111 clocks = <&pll1_div2_clk>;
1112 #clock-cells = <0>;
1113 clock-output-names = "mmc1";
1114 };
1115 ssp_clk: ssp_clk@e6150248 {
1116 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1117 reg = <0 0xe6150248 0 4>;
1118 clocks = <&pll1_div2_clk>;
1119 #clock-cells = <0>;
1120 clock-output-names = "ssp";
1121 };
1122 ssprs_clk: ssprs_clk@e615024c {
1123 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1124 reg = <0 0xe615024c 0 4>;
1125 clocks = <&pll1_div2_clk>;
1126 #clock-cells = <0>;
1127 clock-output-names = "ssprs";
1128 };
1129
1130 /* Fixed factor clocks */
1131 pll1_div2_clk: pll1_div2_clk {
1132 compatible = "fixed-factor-clock";
1133 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1134 #clock-cells = <0>;
1135 clock-div = <2>;
1136 clock-mult = <1>;
1137 clock-output-names = "pll1_div2";
1138 };
1139 z2_clk: z2_clk {
1140 compatible = "fixed-factor-clock";
1141 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1142 #clock-cells = <0>;
1143 clock-div = <2>;
1144 clock-mult = <1>;
1145 clock-output-names = "z2";
1146 };
1147 zg_clk: zg_clk {
1148 compatible = "fixed-factor-clock";
1149 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1150 #clock-cells = <0>;
1151 clock-div = <3>;
1152 clock-mult = <1>;
1153 clock-output-names = "zg";
1154 };
1155 zx_clk: zx_clk {
1156 compatible = "fixed-factor-clock";
1157 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1158 #clock-cells = <0>;
1159 clock-div = <3>;
1160 clock-mult = <1>;
1161 clock-output-names = "zx";
1162 };
1163 zs_clk: zs_clk {
1164 compatible = "fixed-factor-clock";
1165 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1166 #clock-cells = <0>;
1167 clock-div = <6>;
1168 clock-mult = <1>;
1169 clock-output-names = "zs";
1170 };
1171 hp_clk: hp_clk {
1172 compatible = "fixed-factor-clock";
1173 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1174 #clock-cells = <0>;
1175 clock-div = <12>;
1176 clock-mult = <1>;
1177 clock-output-names = "hp";
1178 };
1179 i_clk: i_clk {
1180 compatible = "fixed-factor-clock";
1181 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1182 #clock-cells = <0>;
1183 clock-div = <2>;
1184 clock-mult = <1>;
1185 clock-output-names = "i";
1186 };
1187 b_clk: b_clk {
1188 compatible = "fixed-factor-clock";
1189 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1190 #clock-cells = <0>;
1191 clock-div = <12>;
1192 clock-mult = <1>;
1193 clock-output-names = "b";
1194 };
1195 p_clk: p_clk {
1196 compatible = "fixed-factor-clock";
1197 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1198 #clock-cells = <0>;
1199 clock-div = <24>;
1200 clock-mult = <1>;
1201 clock-output-names = "p";
1202 };
1203 cl_clk: cl_clk {
1204 compatible = "fixed-factor-clock";
1205 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1206 #clock-cells = <0>;
1207 clock-div = <48>;
1208 clock-mult = <1>;
1209 clock-output-names = "cl";
1210 };
1211 m2_clk: m2_clk {
1212 compatible = "fixed-factor-clock";
1213 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1214 #clock-cells = <0>;
1215 clock-div = <8>;
1216 clock-mult = <1>;
1217 clock-output-names = "m2";
1218 };
1219 imp_clk: imp_clk {
1220 compatible = "fixed-factor-clock";
1221 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1222 #clock-cells = <0>;
1223 clock-div = <4>;
1224 clock-mult = <1>;
1225 clock-output-names = "imp";
1226 };
1227 rclk_clk: rclk_clk {
1228 compatible = "fixed-factor-clock";
1229 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1230 #clock-cells = <0>;
1231 clock-div = <(48 * 1024)>;
1232 clock-mult = <1>;
1233 clock-output-names = "rclk";
1234 };
1235 oscclk_clk: oscclk_clk {
1236 compatible = "fixed-factor-clock";
1237 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1238 #clock-cells = <0>;
1239 clock-div = <(12 * 1024)>;
1240 clock-mult = <1>;
1241 clock-output-names = "oscclk";
1242 };
1243 zb3_clk: zb3_clk {
1244 compatible = "fixed-factor-clock";
1245 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1246 #clock-cells = <0>;
1247 clock-div = <4>;
1248 clock-mult = <1>;
1249 clock-output-names = "zb3";
1250 };
1251 zb3d2_clk: zb3d2_clk {
1252 compatible = "fixed-factor-clock";
1253 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1254 #clock-cells = <0>;
1255 clock-div = <8>;
1256 clock-mult = <1>;
1257 clock-output-names = "zb3d2";
1258 };
1259 ddr_clk: ddr_clk {
1260 compatible = "fixed-factor-clock";
1261 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1262 #clock-cells = <0>;
1263 clock-div = <8>;
1264 clock-mult = <1>;
1265 clock-output-names = "ddr";
1266 };
1267 mp_clk: mp_clk {
1268 compatible = "fixed-factor-clock";
1269 clocks = <&pll1_div2_clk>;
1270 #clock-cells = <0>;
1271 clock-div = <15>;
1272 clock-mult = <1>;
1273 clock-output-names = "mp";
1274 };
1275 cp_clk: cp_clk {
1276 compatible = "fixed-factor-clock";
1277 clocks = <&extal_clk>;
1278 #clock-cells = <0>;
1279 clock-div = <2>;
1280 clock-mult = <1>;
1281 clock-output-names = "cp";
1282 };
1283
1284 /* Gate clocks */
1285 mstp0_clks: mstp0_clks@e6150130 {
1286 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1287 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1288 clocks = <&mp_clk>;
1289 #clock-cells = <1>;
1290 clock-indices = <R8A7790_CLK_MSIOF0>;
1291 clock-output-names = "msiof0";
1292 };
1293 mstp1_clks: mstp1_clks@e6150134 {
1294 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1295 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1296 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1297 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1298 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1299 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1300 #clock-cells = <1>;
1301 clock-indices = <
1302 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1303 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1304 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1305 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1306 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1307 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1308 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1309 >;
1310 clock-output-names =
1311 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1312 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1313 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1314 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1315 };
1316 mstp2_clks: mstp2_clks@e6150138 {
1317 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1318 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1319 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1320 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1321 <&zs_clk>;
1322 #clock-cells = <1>;
1323 clock-indices = <
1324 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1325 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1326 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1327 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1328 >;
1329 clock-output-names =
1330 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1331 "scifb1", "msiof1", "msiof3", "scifb2",
1332 "sys-dmac1", "sys-dmac0";
1333 };
1334 mstp3_clks: mstp3_clks@e615013c {
1335 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1336 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1337 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1338 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1339 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1340 <&hp_clk>, <&hp_clk>;
1341 #clock-cells = <1>;
1342 clock-indices = <
1343 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1344 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1345 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1346 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1347 >;
1348 clock-output-names =
1349 "iic2", "tpu0", "mmcif1", "sdhi3",
1350 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1351 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1352 "usbdmac0", "usbdmac1";
1353 };
1354 mstp4_clks: mstp4_clks@e6150140 {
1355 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1356 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1357 clocks = <&cp_clk>;
1358 #clock-cells = <1>;
1359 clock-indices = <R8A7790_CLK_IRQC>;
1360 clock-output-names = "irqc";
1361 };
1362 mstp5_clks: mstp5_clks@e6150144 {
1363 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1364 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1365 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1366 <&extal_clk>, <&p_clk>;
1367 #clock-cells = <1>;
1368 clock-indices = <
1369 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1370 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1371 R8A7790_CLK_PWM
1372 >;
1373 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1374 "thermal", "pwm";
1375 };
1376 mstp7_clks: mstp7_clks@e615014c {
1377 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1378 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1379 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1380 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1381 <&zx_clk>;
1382 #clock-cells = <1>;
1383 clock-indices = <
1384 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1385 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1386 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1387 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1388 >;
1389 clock-output-names =
1390 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1391 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1392 };
1393 mstp8_clks: mstp8_clks@e6150990 {
1394 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1395 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1396 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1397 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1398 <&zs_clk>;
1399 #clock-cells = <1>;
1400 clock-indices = <
1401 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1402 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1403 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1404 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1405 >;
1406 clock-output-names =
1407 "mlb", "vin3", "vin2", "vin1", "vin0",
1408 "etheravb", "ether", "sata1", "sata0";
1409 };
1410 mstp9_clks: mstp9_clks@e6150994 {
1411 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1412 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1413 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1414 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1415 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1416 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1417 #clock-cells = <1>;
1418 clock-indices = <
1419 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1420 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1421 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1422 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1423 >;
1424 clock-output-names =
1425 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1426 "rcan1", "rcan0", "qspi_mod", "iic3",
1427 "i2c3", "i2c2", "i2c1", "i2c0";
1428 };
1429 mstp10_clks: mstp10_clks@e6150998 {
1430 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1431 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1432 clocks = <&p_clk>,
1433 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1434 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1435 <&p_clk>,
1436 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1437 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1438 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1439 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1440 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1441 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1442 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1443
1444 #clock-cells = <1>;
1445 clock-indices = <
1446 R8A7790_CLK_SSI_ALL
1447 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1448 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1449 R8A7790_CLK_SCU_ALL
1450 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1451 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1452 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1453 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1454 >;
1455 clock-output-names =
1456 "ssi-all",
1457 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1458 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1459 "scu-all",
1460 "scu-dvc1", "scu-dvc0",
1461 "scu-ctu1-mix1", "scu-ctu0-mix0",
1462 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1463 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1464 };
1465 };
1466
1467 qspi: spi@e6b10000 {
1468 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1469 reg = <0 0xe6b10000 0 0x2c>;
1470 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1472 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1473 dma-names = "tx", "rx";
1474 power-domains = <&cpg_clocks>;
1475 num-cs = <1>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 status = "disabled";
1479 };
1480
1481 msiof0: spi@e6e20000 {
1482 compatible = "renesas,msiof-r8a7790";
1483 reg = <0 0xe6e20000 0 0x0064>;
1484 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1486 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1487 dma-names = "tx", "rx";
1488 power-domains = <&cpg_clocks>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 status = "disabled";
1492 };
1493
1494 msiof1: spi@e6e10000 {
1495 compatible = "renesas,msiof-r8a7790";
1496 reg = <0 0xe6e10000 0 0x0064>;
1497 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1499 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1500 dma-names = "tx", "rx";
1501 power-domains = <&cpg_clocks>;
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504 status = "disabled";
1505 };
1506
1507 msiof2: spi@e6e00000 {
1508 compatible = "renesas,msiof-r8a7790";
1509 reg = <0 0xe6e00000 0 0x0064>;
1510 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1512 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1513 dma-names = "tx", "rx";
1514 power-domains = <&cpg_clocks>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1517 status = "disabled";
1518 };
1519
1520 msiof3: spi@e6c90000 {
1521 compatible = "renesas,msiof-r8a7790";
1522 reg = <0 0xe6c90000 0 0x0064>;
1523 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1524 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1525 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1526 dma-names = "tx", "rx";
1527 power-domains = <&cpg_clocks>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 xhci: usb@ee000000 {
1534 compatible = "renesas,xhci-r8a7790";
1535 reg = <0 0xee000000 0 0xc00>;
1536 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1538 power-domains = <&cpg_clocks>;
1539 phys = <&usb2 1>;
1540 phy-names = "usb";
1541 status = "disabled";
1542 };
1543
1544 pci0: pci@ee090000 {
1545 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1546 device_type = "pci";
1547 reg = <0 0xee090000 0 0xc00>,
1548 <0 0xee080000 0 0x1100>;
1549 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1550 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1551 power-domains = <&cpg_clocks>;
1552 status = "disabled";
1553
1554 bus-range = <0 0>;
1555 #address-cells = <3>;
1556 #size-cells = <2>;
1557 #interrupt-cells = <1>;
1558 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1559 interrupt-map-mask = <0xff00 0 0 0x7>;
1560 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1561 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1562 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1563
1564 usb@0,1 {
1565 reg = <0x800 0 0 0 0>;
1566 device_type = "pci";
1567 phys = <&usb0 0>;
1568 phy-names = "usb";
1569 };
1570
1571 usb@0,2 {
1572 reg = <0x1000 0 0 0 0>;
1573 device_type = "pci";
1574 phys = <&usb0 0>;
1575 phy-names = "usb";
1576 };
1577 };
1578
1579 pci1: pci@ee0b0000 {
1580 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1581 device_type = "pci";
1582 reg = <0 0xee0b0000 0 0xc00>,
1583 <0 0xee0a0000 0 0x1100>;
1584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1586 power-domains = <&cpg_clocks>;
1587 status = "disabled";
1588
1589 bus-range = <1 1>;
1590 #address-cells = <3>;
1591 #size-cells = <2>;
1592 #interrupt-cells = <1>;
1593 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1594 interrupt-map-mask = <0xff00 0 0 0x7>;
1595 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1596 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1597 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1598 };
1599
1600 pci2: pci@ee0d0000 {
1601 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1602 device_type = "pci";
1603 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1604 power-domains = <&cpg_clocks>;
1605 reg = <0 0xee0d0000 0 0xc00>,
1606 <0 0xee0c0000 0 0x1100>;
1607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1608 status = "disabled";
1609
1610 bus-range = <2 2>;
1611 #address-cells = <3>;
1612 #size-cells = <2>;
1613 #interrupt-cells = <1>;
1614 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1615 interrupt-map-mask = <0xff00 0 0 0x7>;
1616 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1617 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1618 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1619
1620 usb@0,1 {
1621 reg = <0x800 0 0 0 0>;
1622 device_type = "pci";
1623 phys = <&usb2 0>;
1624 phy-names = "usb";
1625 };
1626
1627 usb@0,2 {
1628 reg = <0x1000 0 0 0 0>;
1629 device_type = "pci";
1630 phys = <&usb2 0>;
1631 phy-names = "usb";
1632 };
1633 };
1634
1635 pciec: pcie@fe000000 {
1636 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1637 reg = <0 0xfe000000 0 0x80000>;
1638 #address-cells = <3>;
1639 #size-cells = <2>;
1640 bus-range = <0x00 0xff>;
1641 device_type = "pci";
1642 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1643 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1644 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1645 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1646 /* Map all possible DDR as inbound ranges */
1647 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1648 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1649 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1652 #interrupt-cells = <1>;
1653 interrupt-map-mask = <0 0 0 0>;
1654 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1656 clock-names = "pcie", "pcie_bus";
1657 power-domains = <&cpg_clocks>;
1658 status = "disabled";
1659 };
1660
1661 rcar_sound: sound@ec500000 {
1662 /*
1663 * #sound-dai-cells is required
1664 *
1665 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1666 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1667 */
1668 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1669 reg = <0 0xec500000 0 0x1000>, /* SCU */
1670 <0 0xec5a0000 0 0x100>, /* ADG */
1671 <0 0xec540000 0 0x1000>, /* SSIU */
1672 <0 0xec541000 0 0x280>, /* SSI */
1673 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1674 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1675
1676 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1677 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1678 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1679 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1680 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1681 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1682 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1683 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1684 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1685 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1686 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1687 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1688 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1689 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1690 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1691 clock-names = "ssi-all",
1692 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1693 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1694 "src.9", "src.8", "src.7", "src.6", "src.5",
1695 "src.4", "src.3", "src.2", "src.1", "src.0",
1696 "ctu.0", "ctu.1",
1697 "mix.0", "mix.1",
1698 "dvc.0", "dvc.1",
1699 "clk_a", "clk_b", "clk_c", "clk_i";
1700 power-domains = <&cpg_clocks>;
1701
1702 status = "disabled";
1703
1704 rcar_sound,dvc {
1705 dvc0: dvc@0 {
1706 dmas = <&audma0 0xbc>;
1707 dma-names = "tx";
1708 };
1709 dvc1: dvc@1 {
1710 dmas = <&audma0 0xbe>;
1711 dma-names = "tx";
1712 };
1713 };
1714
1715 rcar_sound,mix {
1716 mix0: mix@0 { };
1717 mix1: mix@1 { };
1718 };
1719
1720 rcar_sound,ctu {
1721 ctu00: ctu@0 { };
1722 ctu01: ctu@1 { };
1723 ctu02: ctu@2 { };
1724 ctu03: ctu@3 { };
1725 ctu10: ctu@4 { };
1726 ctu11: ctu@5 { };
1727 ctu12: ctu@6 { };
1728 ctu13: ctu@7 { };
1729 };
1730
1731 rcar_sound,src {
1732 src0: src@0 {
1733 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1734 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1735 dma-names = "rx", "tx";
1736 };
1737 src1: src@1 {
1738 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1740 dma-names = "rx", "tx";
1741 };
1742 src2: src@2 {
1743 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1744 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1745 dma-names = "rx", "tx";
1746 };
1747 src3: src@3 {
1748 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1749 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1750 dma-names = "rx", "tx";
1751 };
1752 src4: src@4 {
1753 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1754 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1755 dma-names = "rx", "tx";
1756 };
1757 src5: src@5 {
1758 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1760 dma-names = "rx", "tx";
1761 };
1762 src6: src@6 {
1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1764 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1765 dma-names = "rx", "tx";
1766 };
1767 src7: src@7 {
1768 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1769 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1770 dma-names = "rx", "tx";
1771 };
1772 src8: src@8 {
1773 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1774 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1775 dma-names = "rx", "tx";
1776 };
1777 src9: src@9 {
1778 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1779 dmas = <&audma0 0x97>, <&audma1 0xba>;
1780 dma-names = "rx", "tx";
1781 };
1782 };
1783
1784 rcar_sound,ssi {
1785 ssi0: ssi@0 {
1786 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1788 dma-names = "rx", "tx", "rxu", "txu";
1789 };
1790 ssi1: ssi@1 {
1791 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1793 dma-names = "rx", "tx", "rxu", "txu";
1794 };
1795 ssi2: ssi@2 {
1796 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1798 dma-names = "rx", "tx", "rxu", "txu";
1799 };
1800 ssi3: ssi@3 {
1801 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1803 dma-names = "rx", "tx", "rxu", "txu";
1804 };
1805 ssi4: ssi@4 {
1806 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1808 dma-names = "rx", "tx", "rxu", "txu";
1809 };
1810 ssi5: ssi@5 {
1811 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1813 dma-names = "rx", "tx", "rxu", "txu";
1814 };
1815 ssi6: ssi@6 {
1816 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1818 dma-names = "rx", "tx", "rxu", "txu";
1819 };
1820 ssi7: ssi@7 {
1821 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1823 dma-names = "rx", "tx", "rxu", "txu";
1824 };
1825 ssi8: ssi@8 {
1826 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1828 dma-names = "rx", "tx", "rxu", "txu";
1829 };
1830 ssi9: ssi@9 {
1831 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1832 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1833 dma-names = "rx", "tx", "rxu", "txu";
1834 };
1835 };
1836 };
1837
1838 ipmmu_sy0: mmu@e6280000 {
1839 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1840 reg = <0 0xe6280000 0 0x1000>;
1841 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1843 #iommu-cells = <1>;
1844 status = "disabled";
1845 };
1846
1847 ipmmu_sy1: mmu@e6290000 {
1848 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1849 reg = <0 0xe6290000 0 0x1000>;
1850 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1851 #iommu-cells = <1>;
1852 status = "disabled";
1853 };
1854
1855 ipmmu_ds: mmu@e6740000 {
1856 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1857 reg = <0 0xe6740000 0 0x1000>;
1858 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1860 #iommu-cells = <1>;
1861 status = "disabled";
1862 };
1863
1864 ipmmu_mp: mmu@ec680000 {
1865 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1866 reg = <0 0xec680000 0 0x1000>;
1867 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1868 #iommu-cells = <1>;
1869 status = "disabled";
1870 };
1871
1872 ipmmu_mx: mmu@fe951000 {
1873 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1874 reg = <0 0xfe951000 0 0x1000>;
1875 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1877 #iommu-cells = <1>;
1878 status = "disabled";
1879 };
1880
1881 ipmmu_rt: mmu@ffc80000 {
1882 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1883 reg = <0 0xffc80000 0 0x1000>;
1884 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1885 #iommu-cells = <1>;
1886 status = "disabled";
1887 };
1888};