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1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "skeleton.dtsi"
21#include "exynos4-cpu-thermal.dtsi"
22#include "exynos-syscon-restart.dtsi"
23#include <dt-bindings/clock/exynos3250.h>
24
25/ {
26 compatible = "samsung,exynos3250";
27 interrupt-parent = <&gic>;
28
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 mshc0 = &mshc_0;
33 mshc1 = &mshc_1;
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 i2c0 = &i2c_0;
37 i2c1 = &i2c_1;
38 i2c2 = &i2c_2;
39 i2c3 = &i2c_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 serial0 = &serial_0;
45 serial1 = &serial_1;
46 };
47
48 cpus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0>;
56 clock-frequency = <1000000000>;
57 clocks = <&cmu CLK_ARM_CLK>;
58 clock-names = "cpu";
59 #cooling-cells = <2>;
60
61 operating-points = <
62 1000000 1150000
63 900000 1112500
64 800000 1075000
65 700000 1037500
66 600000 1000000
67 500000 962500
68 400000 925000
69 300000 887500
70 200000 850000
71 100000 850000
72 >;
73 };
74
75 cpu1: cpu@1 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a7";
78 reg = <1>;
79 clock-frequency = <1000000000>;
80 };
81 };
82
83 soc: soc {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88
89 fixed-rate-clocks {
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 xusbxti: clock@0 {
94 compatible = "fixed-clock";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <0>;
98 clock-frequency = <0>;
99 #clock-cells = <0>;
100 clock-output-names = "xusbxti";
101 };
102
103 xxti: clock@1 {
104 compatible = "fixed-clock";
105 reg = <1>;
106 clock-frequency = <0>;
107 #clock-cells = <0>;
108 clock-output-names = "xxti";
109 };
110
111 xtcxo: clock@2 {
112 compatible = "fixed-clock";
113 reg = <2>;
114 clock-frequency = <0>;
115 #clock-cells = <0>;
116 clock-output-names = "xtcxo";
117 };
118 };
119
120 sysram@02020000 {
121 compatible = "mmio-sram";
122 reg = <0x02020000 0x40000>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x02020000 0x40000>;
126
127 smp-sysram@0 {
128 compatible = "samsung,exynos4210-sysram";
129 reg = <0x0 0x1000>;
130 };
131
132 smp-sysram@3f000 {
133 compatible = "samsung,exynos4210-sysram-ns";
134 reg = <0x3f000 0x1000>;
135 };
136 };
137
138 chipid@10000000 {
139 compatible = "samsung,exynos4210-chipid";
140 reg = <0x10000000 0x100>;
141 };
142
143 sys_reg: syscon@10010000 {
144 compatible = "samsung,exynos3-sysreg", "syscon";
145 reg = <0x10010000 0x400>;
146 };
147
148 pmu_system_controller: system-controller@10020000 {
149 compatible = "samsung,exynos3250-pmu", "syscon";
150 reg = <0x10020000 0x4000>;
151 interrupt-controller;
152 #interrupt-cells = <3>;
153 interrupt-parent = <&gic>;
154 };
155
156 mipi_phy: video-phy@10020710 {
157 compatible = "samsung,s5pv210-mipi-video-phy";
158 #phy-cells = <1>;
159 syscon = <&pmu_system_controller>;
160 };
161
162 pd_cam: cam-power-domain@10023C00 {
163 compatible = "samsung,exynos4210-pd";
164 reg = <0x10023C00 0x20>;
165 #power-domain-cells = <0>;
166 };
167
168 pd_mfc: mfc-power-domain@10023C40 {
169 compatible = "samsung,exynos4210-pd";
170 reg = <0x10023C40 0x20>;
171 #power-domain-cells = <0>;
172 };
173
174 pd_g3d: g3d-power-domain@10023C60 {
175 compatible = "samsung,exynos4210-pd";
176 reg = <0x10023C60 0x20>;
177 #power-domain-cells = <0>;
178 };
179
180 pd_lcd0: lcd0-power-domain@10023C80 {
181 compatible = "samsung,exynos4210-pd";
182 reg = <0x10023C80 0x20>;
183 #power-domain-cells = <0>;
184 };
185
186 pd_isp: isp-power-domain@10023CA0 {
187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10023CA0 0x20>;
189 #power-domain-cells = <0>;
190 };
191
192 cmu: clock-controller@10030000 {
193 compatible = "samsung,exynos3250-cmu";
194 reg = <0x10030000 0x20000>;
195 #clock-cells = <1>;
196 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
197 <&cmu CLK_MOUT_ACLK_266_SUB>;
198 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
199 <&cmu CLK_FIN_PLL>;
200 };
201
202 cmu_dmc: clock-controller@105C0000 {
203 compatible = "samsung,exynos3250-cmu-dmc";
204 reg = <0x105C0000 0x2000>;
205 #clock-cells = <1>;
206 };
207
208 rtc: rtc@10070000 {
209 compatible = "samsung,s3c6410-rtc";
210 reg = <0x10070000 0x100>;
211 interrupts = <0 73 0>, <0 74 0>;
212 interrupt-parent = <&pmu_system_controller>;
213 status = "disabled";
214 };
215
216 tmu: tmu@100C0000 {
217 compatible = "samsung,exynos3250-tmu";
218 reg = <0x100C0000 0x100>;
219 interrupts = <0 216 0>;
220 clocks = <&cmu CLK_TMU_APBIF>;
221 clock-names = "tmu_apbif";
222 #include "exynos4412-tmu-sensor-conf.dtsi"
223 status = "disabled";
224 };
225
226 gic: interrupt-controller@10481000 {
227 compatible = "arm,cortex-a15-gic";
228 #interrupt-cells = <3>;
229 interrupt-controller;
230 reg = <0x10481000 0x1000>,
231 <0x10482000 0x1000>,
232 <0x10484000 0x2000>,
233 <0x10486000 0x2000>;
234 interrupts = <1 9 0xf04>;
235 };
236
237 mct@10050000 {
238 compatible = "samsung,exynos4210-mct";
239 reg = <0x10050000 0x800>;
240 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
241 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
242 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
243 clock-names = "fin_pll", "mct";
244 };
245
246 pinctrl_1: pinctrl@11000000 {
247 compatible = "samsung,exynos3250-pinctrl";
248 reg = <0x11000000 0x1000>;
249 interrupts = <0 225 0>;
250
251 wakeup-interrupt-controller {
252 compatible = "samsung,exynos4210-wakeup-eint";
253 interrupts = <0 48 0>;
254 };
255 };
256
257 pinctrl_0: pinctrl@11400000 {
258 compatible = "samsung,exynos3250-pinctrl";
259 reg = <0x11400000 0x1000>;
260 interrupts = <0 240 0>;
261 };
262
263 jpeg: codec@11830000 {
264 compatible = "samsung,exynos3250-jpeg";
265 reg = <0x11830000 0x1000>;
266 interrupts = <0 171 0>;
267 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
268 clock-names = "jpeg", "sclk";
269 power-domains = <&pd_cam>;
270 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
271 assigned-clock-rates = <0>, <150000000>;
272 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
273 iommus = <&sysmmu_jpeg>;
274 status = "disabled";
275 };
276
277 sysmmu_jpeg: sysmmu@11A60000 {
278 compatible = "samsung,exynos-sysmmu";
279 reg = <0x11a60000 0x1000>;
280 interrupts = <0 156 0>, <0 161 0>;
281 clock-names = "sysmmu", "master";
282 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
283 power-domains = <&pd_cam>;
284 #iommu-cells = <0>;
285 };
286
287 fimd: fimd@11c00000 {
288 compatible = "samsung,exynos3250-fimd";
289 reg = <0x11c00000 0x30000>;
290 interrupt-names = "fifo", "vsync", "lcd_sys";
291 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
292 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
293 clock-names = "sclk_fimd", "fimd";
294 power-domains = <&pd_lcd0>;
295 iommus = <&sysmmu_fimd0>;
296 samsung,sysreg = <&sys_reg>;
297 status = "disabled";
298 };
299
300 dsi_0: dsi@11C80000 {
301 compatible = "samsung,exynos3250-mipi-dsi";
302 reg = <0x11C80000 0x10000>;
303 interrupts = <0 83 0>;
304 samsung,phy-type = <0>;
305 power-domains = <&pd_lcd0>;
306 phys = <&mipi_phy 1>;
307 phy-names = "dsim";
308 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
309 clock-names = "bus_clk", "pll_clk";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 sysmmu_fimd0: sysmmu@11E20000 {
316 compatible = "samsung,exynos-sysmmu";
317 reg = <0x11e20000 0x1000>;
318 interrupts = <0 80 0>, <0 81 0>;
319 clock-names = "sysmmu", "master";
320 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
321 power-domains = <&pd_lcd0>;
322 #iommu-cells = <0>;
323 };
324
325 hsotg: hsotg@12480000 {
326 compatible = "snps,dwc2";
327 reg = <0x12480000 0x20000>;
328 interrupts = <0 141 0>;
329 clocks = <&cmu CLK_USBOTG>;
330 clock-names = "otg";
331 phys = <&exynos_usbphy 0>;
332 phy-names = "usb2-phy";
333 status = "disabled";
334 };
335
336 mshc_0: mshc@12510000 {
337 compatible = "samsung,exynos5420-dw-mshc";
338 reg = <0x12510000 0x1000>;
339 interrupts = <0 142 0>;
340 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
341 clock-names = "biu", "ciu";
342 fifo-depth = <0x80>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 mshc_1: mshc@12520000 {
349 compatible = "samsung,exynos5420-dw-mshc";
350 reg = <0x12520000 0x1000>;
351 interrupts = <0 143 0>;
352 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
353 clock-names = "biu", "ciu";
354 fifo-depth = <0x80>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 status = "disabled";
358 };
359
360 exynos_usbphy: exynos-usbphy@125B0000 {
361 compatible = "samsung,exynos3250-usb2-phy";
362 reg = <0x125B0000 0x100>;
363 samsung,pmureg-phandle = <&pmu_system_controller>;
364 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
365 clock-names = "phy", "ref";
366 #phy-cells = <1>;
367 status = "disabled";
368 };
369
370 amba {
371 compatible = "simple-bus";
372 #address-cells = <1>;
373 #size-cells = <1>;
374 ranges;
375
376 pdma0: pdma@12680000 {
377 compatible = "arm,pl330", "arm,primecell";
378 reg = <0x12680000 0x1000>;
379 interrupts = <0 138 0>;
380 clocks = <&cmu CLK_PDMA0>;
381 clock-names = "apb_pclk";
382 #dma-cells = <1>;
383 #dma-channels = <8>;
384 #dma-requests = <32>;
385 };
386
387 pdma1: pdma@12690000 {
388 compatible = "arm,pl330", "arm,primecell";
389 reg = <0x12690000 0x1000>;
390 interrupts = <0 139 0>;
391 clocks = <&cmu CLK_PDMA1>;
392 clock-names = "apb_pclk";
393 #dma-cells = <1>;
394 #dma-channels = <8>;
395 #dma-requests = <32>;
396 };
397 };
398
399 adc: adc@126C0000 {
400 compatible = "samsung,exynos3250-adc",
401 "samsung,exynos-adc-v2";
402 reg = <0x126C0000 0x100>;
403 interrupts = <0 137 0>;
404 clock-names = "adc", "sclk";
405 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
406 #io-channel-cells = <1>;
407 io-channel-ranges;
408 samsung,syscon-phandle = <&pmu_system_controller>;
409 status = "disabled";
410 };
411
412 mfc: codec@13400000 {
413 compatible = "samsung,mfc-v7";
414 reg = <0x13400000 0x10000>;
415 interrupts = <0 102 0>;
416 clock-names = "mfc", "sclk_mfc";
417 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
418 power-domains = <&pd_mfc>;
419 iommus = <&sysmmu_mfc>;
420 status = "disabled";
421 };
422
423 sysmmu_mfc: sysmmu@13620000 {
424 compatible = "samsung,exynos-sysmmu";
425 reg = <0x13620000 0x1000>;
426 interrupts = <0 96 0>, <0 98 0>;
427 clock-names = "sysmmu", "master";
428 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
429 power-domains = <&pd_mfc>;
430 #iommu-cells = <0>;
431 };
432
433 serial_0: serial@13800000 {
434 compatible = "samsung,exynos4210-uart";
435 reg = <0x13800000 0x100>;
436 interrupts = <0 109 0>;
437 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
438 clock-names = "uart", "clk_uart_baud0";
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart0_data &uart0_fctl>;
441 status = "disabled";
442 };
443
444 serial_1: serial@13810000 {
445 compatible = "samsung,exynos4210-uart";
446 reg = <0x13810000 0x100>;
447 interrupts = <0 110 0>;
448 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
449 clock-names = "uart", "clk_uart_baud0";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart1_data>;
452 status = "disabled";
453 };
454
455 i2c_0: i2c@13860000 {
456 #address-cells = <1>;
457 #size-cells = <0>;
458 compatible = "samsung,s3c2440-i2c";
459 reg = <0x13860000 0x100>;
460 interrupts = <0 113 0>;
461 clocks = <&cmu CLK_I2C0>;
462 clock-names = "i2c";
463 pinctrl-names = "default";
464 pinctrl-0 = <&i2c0_bus>;
465 status = "disabled";
466 };
467
468 i2c_1: i2c@13870000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "samsung,s3c2440-i2c";
472 reg = <0x13870000 0x100>;
473 interrupts = <0 114 0>;
474 clocks = <&cmu CLK_I2C1>;
475 clock-names = "i2c";
476 pinctrl-names = "default";
477 pinctrl-0 = <&i2c1_bus>;
478 status = "disabled";
479 };
480
481 i2c_2: i2c@13880000 {
482 #address-cells = <1>;
483 #size-cells = <0>;
484 compatible = "samsung,s3c2440-i2c";
485 reg = <0x13880000 0x100>;
486 interrupts = <0 115 0>;
487 clocks = <&cmu CLK_I2C2>;
488 clock-names = "i2c";
489 pinctrl-names = "default";
490 pinctrl-0 = <&i2c2_bus>;
491 status = "disabled";
492 };
493
494 i2c_3: i2c@13890000 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 compatible = "samsung,s3c2440-i2c";
498 reg = <0x13890000 0x100>;
499 interrupts = <0 116 0>;
500 clocks = <&cmu CLK_I2C3>;
501 clock-names = "i2c";
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2c3_bus>;
504 status = "disabled";
505 };
506
507 i2c_4: i2c@138A0000 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "samsung,s3c2440-i2c";
511 reg = <0x138A0000 0x100>;
512 interrupts = <0 117 0>;
513 clocks = <&cmu CLK_I2C4>;
514 clock-names = "i2c";
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c4_bus>;
517 status = "disabled";
518 };
519
520 i2c_5: i2c@138B0000 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 compatible = "samsung,s3c2440-i2c";
524 reg = <0x138B0000 0x100>;
525 interrupts = <0 118 0>;
526 clocks = <&cmu CLK_I2C5>;
527 clock-names = "i2c";
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c5_bus>;
530 status = "disabled";
531 };
532
533 i2c_6: i2c@138C0000 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 compatible = "samsung,s3c2440-i2c";
537 reg = <0x138C0000 0x100>;
538 interrupts = <0 119 0>;
539 clocks = <&cmu CLK_I2C6>;
540 clock-names = "i2c";
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c6_bus>;
543 status = "disabled";
544 };
545
546 i2c_7: i2c@138D0000 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "samsung,s3c2440-i2c";
550 reg = <0x138D0000 0x100>;
551 interrupts = <0 120 0>;
552 clocks = <&cmu CLK_I2C7>;
553 clock-names = "i2c";
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c7_bus>;
556 status = "disabled";
557 };
558
559 spi_0: spi@13920000 {
560 compatible = "samsung,exynos4210-spi";
561 reg = <0x13920000 0x100>;
562 interrupts = <0 121 0>;
563 dmas = <&pdma0 7>, <&pdma0 6>;
564 dma-names = "tx", "rx";
565 #address-cells = <1>;
566 #size-cells = <0>;
567 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
568 clock-names = "spi", "spi_busclk0";
569 samsung,spi-src-clk = <0>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&spi0_bus>;
572 status = "disabled";
573 };
574
575 spi_1: spi@13930000 {
576 compatible = "samsung,exynos4210-spi";
577 reg = <0x13930000 0x100>;
578 interrupts = <0 122 0>;
579 dmas = <&pdma1 7>, <&pdma1 6>;
580 dma-names = "tx", "rx";
581 #address-cells = <1>;
582 #size-cells = <0>;
583 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
584 clock-names = "spi", "spi_busclk0";
585 samsung,spi-src-clk = <0>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&spi1_bus>;
588 status = "disabled";
589 };
590
591 i2s2: i2s@13970000 {
592 compatible = "samsung,s3c6410-i2s";
593 reg = <0x13970000 0x100>;
594 interrupts = <0 126 0>;
595 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
596 clock-names = "iis", "i2s_opclk0";
597 dmas = <&pdma0 14>, <&pdma0 13>;
598 dma-names = "tx", "rx";
599 pinctrl-0 = <&i2s2_bus>;
600 pinctrl-names = "default";
601 status = "disabled";
602 };
603
604 pwm: pwm@139D0000 {
605 compatible = "samsung,exynos4210-pwm";
606 reg = <0x139D0000 0x1000>;
607 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
608 <0 107 0>, <0 108 0>;
609 #pwm-cells = <3>;
610 status = "disabled";
611 };
612
613 pmu {
614 compatible = "arm,cortex-a7-pmu";
615 interrupts = <0 18 0>, <0 19 0>;
616 };
617
618 ppmu_dmc0: ppmu_dmc0@106a0000 {
619 compatible = "samsung,exynos-ppmu";
620 reg = <0x106a0000 0x2000>;
621 status = "disabled";
622 };
623
624 ppmu_dmc1: ppmu_dmc1@106b0000 {
625 compatible = "samsung,exynos-ppmu";
626 reg = <0x106b0000 0x2000>;
627 status = "disabled";
628 };
629
630 ppmu_cpu: ppmu_cpu@106c0000 {
631 compatible = "samsung,exynos-ppmu";
632 reg = <0x106c0000 0x2000>;
633 status = "disabled";
634 };
635
636 ppmu_rightbus: ppmu_rightbus@112a0000 {
637 compatible = "samsung,exynos-ppmu";
638 reg = <0x112a0000 0x2000>;
639 clocks = <&cmu CLK_PPMURIGHT>;
640 clock-names = "ppmu";
641 status = "disabled";
642 };
643
644 ppmu_leftbus: ppmu_leftbus0@116a0000 {
645 compatible = "samsung,exynos-ppmu";
646 reg = <0x116a0000 0x2000>;
647 clocks = <&cmu CLK_PPMULEFT>;
648 clock-names = "ppmu";
649 status = "disabled";
650 };
651
652 ppmu_camif: ppmu_camif@11ac0000 {
653 compatible = "samsung,exynos-ppmu";
654 reg = <0x11ac0000 0x2000>;
655 clocks = <&cmu CLK_PPMUCAMIF>;
656 clock-names = "ppmu";
657 status = "disabled";
658 };
659
660 ppmu_lcd0: ppmu_lcd0@11e40000 {
661 compatible = "samsung,exynos-ppmu";
662 reg = <0x11e40000 0x2000>;
663 clocks = <&cmu CLK_PPMULCD0>;
664 clock-names = "ppmu";
665 status = "disabled";
666 };
667
668 ppmu_fsys: ppmu_fsys@12630000 {
669 compatible = "samsung,exynos-ppmu";
670 reg = <0x12630000 0x2000>;
671 clocks = <&cmu CLK_PPMUFILE>;
672 clock-names = "ppmu";
673 status = "disabled";
674 };
675
676 ppmu_g3d: ppmu_g3d@13220000 {
677 compatible = "samsung,exynos-ppmu";
678 reg = <0x13220000 0x2000>;
679 clocks = <&cmu CLK_PPMUG3D>;
680 clock-names = "ppmu";
681 status = "disabled";
682 };
683
684 ppmu_mfc: ppmu_mfc@13660000 {
685 compatible = "samsung,exynos-ppmu";
686 reg = <0x13660000 0x2000>;
687 clocks = <&cmu CLK_PPMUMFC_L>;
688 clock-names = "ppmu";
689 status = "disabled";
690 };
691 };
692};
693
694#include "exynos3250-pinctrl.dtsi"