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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI-Engine SPI controller driver
4 * Copyright 2015 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 */
7
8#include <linux/clk.h>
9#include <linux/completion.h>
10#include <linux/fpga/adi-axi-common.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/module.h>
15#include <linux/overflow.h>
16#include <linux/platform_device.h>
17#include <linux/spi/spi.h>
18#include <trace/events/spi.h>
19
20#define SPI_ENGINE_REG_RESET 0x40
21
22#define SPI_ENGINE_REG_INT_ENABLE 0x80
23#define SPI_ENGINE_REG_INT_PENDING 0x84
24#define SPI_ENGINE_REG_INT_SOURCE 0x88
25
26#define SPI_ENGINE_REG_SYNC_ID 0xc0
27
28#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
29#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
30#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
31
32#define SPI_ENGINE_REG_CMD_FIFO 0xe0
33#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
34#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
35#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
36
37#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
38#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
39#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
40#define SPI_ENGINE_INT_SYNC BIT(3)
41
42#define SPI_ENGINE_CONFIG_CPHA BIT(0)
43#define SPI_ENGINE_CONFIG_CPOL BIT(1)
44#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
45#define SPI_ENGINE_CONFIG_SDO_IDLE_HIGH BIT(3)
46
47#define SPI_ENGINE_INST_TRANSFER 0x0
48#define SPI_ENGINE_INST_ASSERT 0x1
49#define SPI_ENGINE_INST_WRITE 0x2
50#define SPI_ENGINE_INST_MISC 0x3
51#define SPI_ENGINE_INST_CS_INV 0x4
52
53#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
54#define SPI_ENGINE_CMD_REG_CONFIG 0x1
55#define SPI_ENGINE_CMD_REG_XFER_BITS 0x2
56
57#define SPI_ENGINE_MISC_SYNC 0x0
58#define SPI_ENGINE_MISC_SLEEP 0x1
59
60#define SPI_ENGINE_TRANSFER_WRITE 0x1
61#define SPI_ENGINE_TRANSFER_READ 0x2
62
63/* Arbitrary sync ID for use by host->cur_msg */
64#define AXI_SPI_ENGINE_CUR_MSG_SYNC_ID 0x1
65
66#define SPI_ENGINE_CMD(inst, arg1, arg2) \
67 (((inst) << 12) | ((arg1) << 8) | (arg2))
68
69#define SPI_ENGINE_CMD_TRANSFER(flags, n) \
70 SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
71#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
72 SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
73#define SPI_ENGINE_CMD_WRITE(reg, val) \
74 SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
75#define SPI_ENGINE_CMD_SLEEP(delay) \
76 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
77#define SPI_ENGINE_CMD_SYNC(id) \
78 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
79#define SPI_ENGINE_CMD_CS_INV(flags) \
80 SPI_ENGINE_CMD(SPI_ENGINE_INST_CS_INV, 0, (flags))
81
82struct spi_engine_program {
83 unsigned int length;
84 uint16_t instructions[] __counted_by(length);
85};
86
87/**
88 * struct spi_engine_message_state - SPI engine per-message state
89 */
90struct spi_engine_message_state {
91 /** @cmd_length: Number of elements in cmd_buf array. */
92 unsigned cmd_length;
93 /** @cmd_buf: Array of commands not yet written to CMD FIFO. */
94 const uint16_t *cmd_buf;
95 /** @tx_xfer: Next xfer with tx_buf not yet fully written to TX FIFO. */
96 struct spi_transfer *tx_xfer;
97 /** @tx_length: Size of tx_buf in bytes. */
98 unsigned int tx_length;
99 /** @tx_buf: Bytes not yet written to TX FIFO. */
100 const uint8_t *tx_buf;
101 /** @rx_xfer: Next xfer with rx_buf not yet fully written to RX FIFO. */
102 struct spi_transfer *rx_xfer;
103 /** @rx_length: Size of tx_buf in bytes. */
104 unsigned int rx_length;
105 /** @rx_buf: Bytes not yet written to the RX FIFO. */
106 uint8_t *rx_buf;
107};
108
109struct spi_engine {
110 struct clk *clk;
111 struct clk *ref_clk;
112
113 spinlock_t lock;
114
115 void __iomem *base;
116 struct spi_engine_message_state msg_state;
117 struct completion msg_complete;
118 unsigned int int_enable;
119 /* shadows hardware CS inversion flag state */
120 u8 cs_inv;
121};
122
123static void spi_engine_program_add_cmd(struct spi_engine_program *p,
124 bool dry, uint16_t cmd)
125{
126 p->length++;
127
128 if (!dry)
129 p->instructions[p->length - 1] = cmd;
130}
131
132static unsigned int spi_engine_get_config(struct spi_device *spi)
133{
134 unsigned int config = 0;
135
136 if (spi->mode & SPI_CPOL)
137 config |= SPI_ENGINE_CONFIG_CPOL;
138 if (spi->mode & SPI_CPHA)
139 config |= SPI_ENGINE_CONFIG_CPHA;
140 if (spi->mode & SPI_3WIRE)
141 config |= SPI_ENGINE_CONFIG_3WIRE;
142 if (spi->mode & SPI_MOSI_IDLE_HIGH)
143 config |= SPI_ENGINE_CONFIG_SDO_IDLE_HIGH;
144 if (spi->mode & SPI_MOSI_IDLE_LOW)
145 config &= ~SPI_ENGINE_CONFIG_SDO_IDLE_HIGH;
146
147 return config;
148}
149
150static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
151 struct spi_transfer *xfer)
152{
153 unsigned int len;
154
155 if (xfer->bits_per_word <= 8)
156 len = xfer->len;
157 else if (xfer->bits_per_word <= 16)
158 len = xfer->len / 2;
159 else
160 len = xfer->len / 4;
161
162 while (len) {
163 unsigned int n = min(len, 256U);
164 unsigned int flags = 0;
165
166 if (xfer->tx_buf)
167 flags |= SPI_ENGINE_TRANSFER_WRITE;
168 if (xfer->rx_buf)
169 flags |= SPI_ENGINE_TRANSFER_READ;
170
171 spi_engine_program_add_cmd(p, dry,
172 SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
173 len -= n;
174 }
175}
176
177static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
178 int delay_ns, int inst_ns, u32 sclk_hz)
179{
180 unsigned int t;
181
182 /*
183 * Negative delay indicates error, e.g. from spi_delay_to_ns(). And if
184 * delay is less that the instruction execution time, there is no need
185 * for an extra sleep instruction since the instruction execution time
186 * will already cover the required delay.
187 */
188 if (delay_ns < 0 || delay_ns <= inst_ns)
189 return;
190
191 t = DIV_ROUND_UP_ULL((u64)(delay_ns - inst_ns) * sclk_hz, NSEC_PER_SEC);
192 while (t) {
193 unsigned int n = min(t, 256U);
194
195 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
196 t -= n;
197 }
198}
199
200static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
201 struct spi_device *spi, bool assert)
202{
203 unsigned int mask = 0xff;
204
205 if (assert)
206 mask ^= BIT(spi_get_chipselect(spi, 0));
207
208 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(0, mask));
209}
210
211/*
212 * Performs precompile steps on the message.
213 *
214 * The SPI core does most of the message/transfer validation and filling in
215 * fields for us via __spi_validate(). This fixes up anything remaining not
216 * done there.
217 *
218 * NB: This is separate from spi_engine_compile_message() because the latter
219 * is called twice and would otherwise result in double-evaluation.
220 */
221static void spi_engine_precompile_message(struct spi_message *msg)
222{
223 unsigned int clk_div, max_hz = msg->spi->controller->max_speed_hz;
224 struct spi_transfer *xfer;
225
226 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
227 clk_div = DIV_ROUND_UP(max_hz, xfer->speed_hz);
228 xfer->effective_speed_hz = max_hz / min(clk_div, 256U);
229 }
230}
231
232static void spi_engine_compile_message(struct spi_message *msg, bool dry,
233 struct spi_engine_program *p)
234{
235 struct spi_device *spi = msg->spi;
236 struct spi_controller *host = spi->controller;
237 struct spi_transfer *xfer;
238 int clk_div, new_clk_div, inst_ns;
239 bool keep_cs = false;
240 u8 bits_per_word = 0;
241
242 /*
243 * Take into account instruction execution time for more accurate sleep
244 * times, especially when the delay is small.
245 */
246 inst_ns = DIV_ROUND_UP(NSEC_PER_SEC, host->max_speed_hz);
247
248 clk_div = 1;
249
250 spi_engine_program_add_cmd(p, dry,
251 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
252 spi_engine_get_config(spi)));
253
254 xfer = list_first_entry(&msg->transfers, struct spi_transfer, transfer_list);
255 spi_engine_gen_cs(p, dry, spi, !xfer->cs_off);
256
257 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
258 new_clk_div = host->max_speed_hz / xfer->effective_speed_hz;
259 if (new_clk_div != clk_div) {
260 clk_div = new_clk_div;
261 /* actual divider used is register value + 1 */
262 spi_engine_program_add_cmd(p, dry,
263 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
264 clk_div - 1));
265 }
266
267 if (bits_per_word != xfer->bits_per_word && xfer->len) {
268 bits_per_word = xfer->bits_per_word;
269 spi_engine_program_add_cmd(p, dry,
270 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_XFER_BITS,
271 bits_per_word));
272 }
273
274 spi_engine_gen_xfer(p, dry, xfer);
275 spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer),
276 inst_ns, xfer->effective_speed_hz);
277
278 if (xfer->cs_change) {
279 if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
280 keep_cs = true;
281 } else {
282 if (!xfer->cs_off)
283 spi_engine_gen_cs(p, dry, spi, false);
284
285 spi_engine_gen_sleep(p, dry, spi_delay_to_ns(
286 &xfer->cs_change_delay, xfer), inst_ns,
287 xfer->effective_speed_hz);
288
289 if (!list_next_entry(xfer, transfer_list)->cs_off)
290 spi_engine_gen_cs(p, dry, spi, true);
291 }
292 } else if (!list_is_last(&xfer->transfer_list, &msg->transfers) &&
293 xfer->cs_off != list_next_entry(xfer, transfer_list)->cs_off) {
294 spi_engine_gen_cs(p, dry, spi, xfer->cs_off);
295 }
296 }
297
298 if (!keep_cs)
299 spi_engine_gen_cs(p, dry, spi, false);
300
301 /*
302 * Restore clockdiv to default so that future gen_sleep commands don't
303 * have to be aware of the current register state.
304 */
305 if (clk_div != 1)
306 spi_engine_program_add_cmd(p, dry,
307 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0));
308}
309
310static void spi_engine_xfer_next(struct spi_message *msg,
311 struct spi_transfer **_xfer)
312{
313 struct spi_transfer *xfer = *_xfer;
314
315 if (!xfer) {
316 xfer = list_first_entry(&msg->transfers,
317 struct spi_transfer, transfer_list);
318 } else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
319 xfer = NULL;
320 } else {
321 xfer = list_next_entry(xfer, transfer_list);
322 }
323
324 *_xfer = xfer;
325}
326
327static void spi_engine_tx_next(struct spi_message *msg)
328{
329 struct spi_engine_message_state *st = msg->state;
330 struct spi_transfer *xfer = st->tx_xfer;
331
332 do {
333 spi_engine_xfer_next(msg, &xfer);
334 } while (xfer && !xfer->tx_buf);
335
336 st->tx_xfer = xfer;
337 if (xfer) {
338 st->tx_length = xfer->len;
339 st->tx_buf = xfer->tx_buf;
340 } else {
341 st->tx_buf = NULL;
342 }
343}
344
345static void spi_engine_rx_next(struct spi_message *msg)
346{
347 struct spi_engine_message_state *st = msg->state;
348 struct spi_transfer *xfer = st->rx_xfer;
349
350 do {
351 spi_engine_xfer_next(msg, &xfer);
352 } while (xfer && !xfer->rx_buf);
353
354 st->rx_xfer = xfer;
355 if (xfer) {
356 st->rx_length = xfer->len;
357 st->rx_buf = xfer->rx_buf;
358 } else {
359 st->rx_buf = NULL;
360 }
361}
362
363static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine,
364 struct spi_message *msg)
365{
366 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
367 struct spi_engine_message_state *st = msg->state;
368 unsigned int n, m, i;
369 const uint16_t *buf;
370
371 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
372 while (n && st->cmd_length) {
373 m = min(n, st->cmd_length);
374 buf = st->cmd_buf;
375 for (i = 0; i < m; i++)
376 writel_relaxed(buf[i], addr);
377 st->cmd_buf += m;
378 st->cmd_length -= m;
379 n -= m;
380 }
381
382 return st->cmd_length != 0;
383}
384
385static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine,
386 struct spi_message *msg)
387{
388 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
389 struct spi_engine_message_state *st = msg->state;
390 unsigned int n, m, i;
391
392 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
393 while (n && st->tx_length) {
394 if (st->tx_xfer->bits_per_word <= 8) {
395 const u8 *buf = st->tx_buf;
396
397 m = min(n, st->tx_length);
398 for (i = 0; i < m; i++)
399 writel_relaxed(buf[i], addr);
400 st->tx_buf += m;
401 st->tx_length -= m;
402 } else if (st->tx_xfer->bits_per_word <= 16) {
403 const u16 *buf = (const u16 *)st->tx_buf;
404
405 m = min(n, st->tx_length / 2);
406 for (i = 0; i < m; i++)
407 writel_relaxed(buf[i], addr);
408 st->tx_buf += m * 2;
409 st->tx_length -= m * 2;
410 } else {
411 const u32 *buf = (const u32 *)st->tx_buf;
412
413 m = min(n, st->tx_length / 4);
414 for (i = 0; i < m; i++)
415 writel_relaxed(buf[i], addr);
416 st->tx_buf += m * 4;
417 st->tx_length -= m * 4;
418 }
419 n -= m;
420 if (st->tx_length == 0)
421 spi_engine_tx_next(msg);
422 }
423
424 return st->tx_length != 0;
425}
426
427static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine,
428 struct spi_message *msg)
429{
430 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
431 struct spi_engine_message_state *st = msg->state;
432 unsigned int n, m, i;
433
434 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
435 while (n && st->rx_length) {
436 if (st->rx_xfer->bits_per_word <= 8) {
437 u8 *buf = st->rx_buf;
438
439 m = min(n, st->rx_length);
440 for (i = 0; i < m; i++)
441 buf[i] = readl_relaxed(addr);
442 st->rx_buf += m;
443 st->rx_length -= m;
444 } else if (st->rx_xfer->bits_per_word <= 16) {
445 u16 *buf = (u16 *)st->rx_buf;
446
447 m = min(n, st->rx_length / 2);
448 for (i = 0; i < m; i++)
449 buf[i] = readl_relaxed(addr);
450 st->rx_buf += m * 2;
451 st->rx_length -= m * 2;
452 } else {
453 u32 *buf = (u32 *)st->rx_buf;
454
455 m = min(n, st->rx_length / 4);
456 for (i = 0; i < m; i++)
457 buf[i] = readl_relaxed(addr);
458 st->rx_buf += m * 4;
459 st->rx_length -= m * 4;
460 }
461 n -= m;
462 if (st->rx_length == 0)
463 spi_engine_rx_next(msg);
464 }
465
466 return st->rx_length != 0;
467}
468
469static irqreturn_t spi_engine_irq(int irq, void *devid)
470{
471 struct spi_controller *host = devid;
472 struct spi_message *msg = host->cur_msg;
473 struct spi_engine *spi_engine = spi_controller_get_devdata(host);
474 unsigned int disable_int = 0;
475 unsigned int pending;
476 int completed_id = -1;
477
478 pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
479
480 if (pending & SPI_ENGINE_INT_SYNC) {
481 writel_relaxed(SPI_ENGINE_INT_SYNC,
482 spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
483 completed_id = readl_relaxed(
484 spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
485 }
486
487 spin_lock(&spi_engine->lock);
488
489 if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
490 if (!spi_engine_write_cmd_fifo(spi_engine, msg))
491 disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
492 }
493
494 if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
495 if (!spi_engine_write_tx_fifo(spi_engine, msg))
496 disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
497 }
498
499 if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
500 if (!spi_engine_read_rx_fifo(spi_engine, msg))
501 disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
502 }
503
504 if (pending & SPI_ENGINE_INT_SYNC && msg) {
505 if (completed_id == AXI_SPI_ENGINE_CUR_MSG_SYNC_ID) {
506 msg->status = 0;
507 msg->actual_length = msg->frame_length;
508 complete(&spi_engine->msg_complete);
509 disable_int |= SPI_ENGINE_INT_SYNC;
510 }
511 }
512
513 if (disable_int) {
514 spi_engine->int_enable &= ~disable_int;
515 writel_relaxed(spi_engine->int_enable,
516 spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
517 }
518
519 spin_unlock(&spi_engine->lock);
520
521 return IRQ_HANDLED;
522}
523
524static int spi_engine_optimize_message(struct spi_message *msg)
525{
526 struct spi_engine_program p_dry, *p;
527
528 spi_engine_precompile_message(msg);
529
530 p_dry.length = 0;
531 spi_engine_compile_message(msg, true, &p_dry);
532
533 p = kzalloc(struct_size(p, instructions, p_dry.length + 1), GFP_KERNEL);
534 if (!p)
535 return -ENOMEM;
536
537 spi_engine_compile_message(msg, false, p);
538
539 spi_engine_program_add_cmd(p, false, SPI_ENGINE_CMD_SYNC(
540 AXI_SPI_ENGINE_CUR_MSG_SYNC_ID));
541
542 msg->opt_state = p;
543
544 return 0;
545}
546
547static int spi_engine_unoptimize_message(struct spi_message *msg)
548{
549 kfree(msg->opt_state);
550
551 return 0;
552}
553
554static int spi_engine_setup(struct spi_device *device)
555{
556 struct spi_controller *host = device->controller;
557 struct spi_engine *spi_engine = spi_controller_get_devdata(host);
558
559 if (device->mode & SPI_CS_HIGH)
560 spi_engine->cs_inv |= BIT(spi_get_chipselect(device, 0));
561 else
562 spi_engine->cs_inv &= ~BIT(spi_get_chipselect(device, 0));
563
564 writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv),
565 spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
566
567 /*
568 * In addition to setting the flags, we have to do a CS assert command
569 * to make the new setting actually take effect.
570 */
571 writel_relaxed(SPI_ENGINE_CMD_ASSERT(0, 0xff),
572 spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
573
574 return 0;
575}
576
577static int spi_engine_transfer_one_message(struct spi_controller *host,
578 struct spi_message *msg)
579{
580 struct spi_engine *spi_engine = spi_controller_get_devdata(host);
581 struct spi_engine_message_state *st = &spi_engine->msg_state;
582 struct spi_engine_program *p = msg->opt_state;
583 unsigned int int_enable = 0;
584 unsigned long flags;
585
586 /* reinitialize message state for this transfer */
587 memset(st, 0, sizeof(*st));
588 st->cmd_buf = p->instructions;
589 st->cmd_length = p->length;
590 msg->state = st;
591
592 reinit_completion(&spi_engine->msg_complete);
593
594 if (trace_spi_transfer_start_enabled()) {
595 struct spi_transfer *xfer;
596
597 list_for_each_entry(xfer, &msg->transfers, transfer_list)
598 trace_spi_transfer_start(msg, xfer);
599 }
600
601 spin_lock_irqsave(&spi_engine->lock, flags);
602
603 if (spi_engine_write_cmd_fifo(spi_engine, msg))
604 int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
605
606 spi_engine_tx_next(msg);
607 if (spi_engine_write_tx_fifo(spi_engine, msg))
608 int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
609
610 spi_engine_rx_next(msg);
611 if (st->rx_length != 0)
612 int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
613
614 int_enable |= SPI_ENGINE_INT_SYNC;
615
616 writel_relaxed(int_enable,
617 spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
618 spi_engine->int_enable = int_enable;
619 spin_unlock_irqrestore(&spi_engine->lock, flags);
620
621 if (!wait_for_completion_timeout(&spi_engine->msg_complete,
622 msecs_to_jiffies(5000))) {
623 dev_err(&host->dev,
624 "Timeout occurred while waiting for transfer to complete. Hardware is probably broken.\n");
625 msg->status = -ETIMEDOUT;
626 }
627
628 if (trace_spi_transfer_stop_enabled()) {
629 struct spi_transfer *xfer;
630
631 list_for_each_entry(xfer, &msg->transfers, transfer_list)
632 trace_spi_transfer_stop(msg, xfer);
633 }
634
635 spi_finalize_current_message(host);
636
637 return msg->status;
638}
639
640static void spi_engine_release_hw(void *p)
641{
642 struct spi_engine *spi_engine = p;
643
644 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
645 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
646 writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
647}
648
649static int spi_engine_probe(struct platform_device *pdev)
650{
651 struct spi_engine *spi_engine;
652 struct spi_controller *host;
653 unsigned int version;
654 int irq;
655 int ret;
656
657 irq = platform_get_irq(pdev, 0);
658 if (irq < 0)
659 return irq;
660
661 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi_engine));
662 if (!host)
663 return -ENOMEM;
664
665 spi_engine = spi_controller_get_devdata(host);
666
667 spin_lock_init(&spi_engine->lock);
668 init_completion(&spi_engine->msg_complete);
669
670 spi_engine->clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
671 if (IS_ERR(spi_engine->clk))
672 return PTR_ERR(spi_engine->clk);
673
674 spi_engine->ref_clk = devm_clk_get_enabled(&pdev->dev, "spi_clk");
675 if (IS_ERR(spi_engine->ref_clk))
676 return PTR_ERR(spi_engine->ref_clk);
677
678 spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
679 if (IS_ERR(spi_engine->base))
680 return PTR_ERR(spi_engine->base);
681
682 version = readl(spi_engine->base + ADI_AXI_REG_VERSION);
683 if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) {
684 dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n",
685 ADI_AXI_PCORE_VER_MAJOR(version),
686 ADI_AXI_PCORE_VER_MINOR(version),
687 ADI_AXI_PCORE_VER_PATCH(version));
688 return -ENODEV;
689 }
690
691 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
692 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
693 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
694
695 ret = devm_add_action_or_reset(&pdev->dev, spi_engine_release_hw,
696 spi_engine);
697 if (ret)
698 return ret;
699
700 ret = devm_request_irq(&pdev->dev, irq, spi_engine_irq, 0, pdev->name,
701 host);
702 if (ret)
703 return ret;
704
705 host->dev.of_node = pdev->dev.of_node;
706 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
707 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
708 host->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
709 host->transfer_one_message = spi_engine_transfer_one_message;
710 host->optimize_message = spi_engine_optimize_message;
711 host->unoptimize_message = spi_engine_unoptimize_message;
712 host->num_chipselect = 8;
713
714 /* Some features depend of the IP core version. */
715 if (ADI_AXI_PCORE_VER_MAJOR(version) >= 1) {
716 if (ADI_AXI_PCORE_VER_MINOR(version) >= 2) {
717 host->mode_bits |= SPI_CS_HIGH;
718 host->setup = spi_engine_setup;
719 }
720 if (ADI_AXI_PCORE_VER_MINOR(version) >= 3)
721 host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH;
722 }
723
724 if (host->max_speed_hz == 0)
725 return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");
726
727 return devm_spi_register_controller(&pdev->dev, host);
728}
729
730static const struct of_device_id spi_engine_match_table[] = {
731 { .compatible = "adi,axi-spi-engine-1.00.a" },
732 { },
733};
734MODULE_DEVICE_TABLE(of, spi_engine_match_table);
735
736static struct platform_driver spi_engine_driver = {
737 .probe = spi_engine_probe,
738 .driver = {
739 .name = "spi-engine",
740 .of_match_table = spi_engine_match_table,
741 },
742};
743module_platform_driver(spi_engine_driver);
744
745MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
746MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
747MODULE_LICENSE("GPL");
1/*
2 * SPI-Engine SPI controller driver
3 * Copyright 2015 Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/clk.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/of.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16
17#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
18#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
19#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
20
21#define SPI_ENGINE_REG_VERSION 0x00
22
23#define SPI_ENGINE_REG_RESET 0x40
24
25#define SPI_ENGINE_REG_INT_ENABLE 0x80
26#define SPI_ENGINE_REG_INT_PENDING 0x84
27#define SPI_ENGINE_REG_INT_SOURCE 0x88
28
29#define SPI_ENGINE_REG_SYNC_ID 0xc0
30
31#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
32#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
33#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
34
35#define SPI_ENGINE_REG_CMD_FIFO 0xe0
36#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
37#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
38#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
39
40#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
41#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
42#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
43#define SPI_ENGINE_INT_SYNC BIT(3)
44
45#define SPI_ENGINE_CONFIG_CPHA BIT(0)
46#define SPI_ENGINE_CONFIG_CPOL BIT(1)
47#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
48
49#define SPI_ENGINE_INST_TRANSFER 0x0
50#define SPI_ENGINE_INST_ASSERT 0x1
51#define SPI_ENGINE_INST_WRITE 0x2
52#define SPI_ENGINE_INST_MISC 0x3
53
54#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
55#define SPI_ENGINE_CMD_REG_CONFIG 0x1
56
57#define SPI_ENGINE_MISC_SYNC 0x0
58#define SPI_ENGINE_MISC_SLEEP 0x1
59
60#define SPI_ENGINE_TRANSFER_WRITE 0x1
61#define SPI_ENGINE_TRANSFER_READ 0x2
62
63#define SPI_ENGINE_CMD(inst, arg1, arg2) \
64 (((inst) << 12) | ((arg1) << 8) | (arg2))
65
66#define SPI_ENGINE_CMD_TRANSFER(flags, n) \
67 SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
68#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
69 SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
70#define SPI_ENGINE_CMD_WRITE(reg, val) \
71 SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
72#define SPI_ENGINE_CMD_SLEEP(delay) \
73 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
74#define SPI_ENGINE_CMD_SYNC(id) \
75 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
76
77struct spi_engine_program {
78 unsigned int length;
79 uint16_t instructions[];
80};
81
82struct spi_engine {
83 struct clk *clk;
84 struct clk *ref_clk;
85
86 spinlock_t lock;
87
88 void __iomem *base;
89
90 struct spi_message *msg;
91 struct spi_engine_program *p;
92 unsigned cmd_length;
93 const uint16_t *cmd_buf;
94
95 struct spi_transfer *tx_xfer;
96 unsigned int tx_length;
97 const uint8_t *tx_buf;
98
99 struct spi_transfer *rx_xfer;
100 unsigned int rx_length;
101 uint8_t *rx_buf;
102
103 unsigned int sync_id;
104 unsigned int completed_id;
105
106 unsigned int int_enable;
107};
108
109static void spi_engine_program_add_cmd(struct spi_engine_program *p,
110 bool dry, uint16_t cmd)
111{
112 if (!dry)
113 p->instructions[p->length] = cmd;
114 p->length++;
115}
116
117static unsigned int spi_engine_get_config(struct spi_device *spi)
118{
119 unsigned int config = 0;
120
121 if (spi->mode & SPI_CPOL)
122 config |= SPI_ENGINE_CONFIG_CPOL;
123 if (spi->mode & SPI_CPHA)
124 config |= SPI_ENGINE_CONFIG_CPHA;
125 if (spi->mode & SPI_3WIRE)
126 config |= SPI_ENGINE_CONFIG_3WIRE;
127
128 return config;
129}
130
131static unsigned int spi_engine_get_clk_div(struct spi_engine *spi_engine,
132 struct spi_device *spi, struct spi_transfer *xfer)
133{
134 unsigned int clk_div;
135
136 clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk),
137 xfer->speed_hz * 2);
138 if (clk_div > 255)
139 clk_div = 255;
140 else if (clk_div > 0)
141 clk_div -= 1;
142
143 return clk_div;
144}
145
146static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
147 struct spi_transfer *xfer)
148{
149 unsigned int len = xfer->len;
150
151 while (len) {
152 unsigned int n = min(len, 256U);
153 unsigned int flags = 0;
154
155 if (xfer->tx_buf)
156 flags |= SPI_ENGINE_TRANSFER_WRITE;
157 if (xfer->rx_buf)
158 flags |= SPI_ENGINE_TRANSFER_READ;
159
160 spi_engine_program_add_cmd(p, dry,
161 SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
162 len -= n;
163 }
164}
165
166static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
167 struct spi_engine *spi_engine, unsigned int clk_div, unsigned int delay)
168{
169 unsigned int spi_clk = clk_get_rate(spi_engine->ref_clk);
170 unsigned int t;
171
172 if (delay == 0)
173 return;
174
175 t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2);
176 while (t) {
177 unsigned int n = min(t, 256U);
178
179 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
180 t -= n;
181 }
182}
183
184static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
185 struct spi_device *spi, bool assert)
186{
187 unsigned int mask = 0xff;
188
189 if (assert)
190 mask ^= BIT(spi->chip_select);
191
192 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
193}
194
195static int spi_engine_compile_message(struct spi_engine *spi_engine,
196 struct spi_message *msg, bool dry, struct spi_engine_program *p)
197{
198 struct spi_device *spi = msg->spi;
199 struct spi_transfer *xfer;
200 int clk_div, new_clk_div;
201 bool cs_change = true;
202
203 clk_div = -1;
204
205 spi_engine_program_add_cmd(p, dry,
206 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
207 spi_engine_get_config(spi)));
208
209 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
210 new_clk_div = spi_engine_get_clk_div(spi_engine, spi, xfer);
211 if (new_clk_div != clk_div) {
212 clk_div = new_clk_div;
213 spi_engine_program_add_cmd(p, dry,
214 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
215 clk_div));
216 }
217
218 if (cs_change)
219 spi_engine_gen_cs(p, dry, spi, true);
220
221 spi_engine_gen_xfer(p, dry, xfer);
222 spi_engine_gen_sleep(p, dry, spi_engine, clk_div,
223 xfer->delay_usecs);
224
225 cs_change = xfer->cs_change;
226 if (list_is_last(&xfer->transfer_list, &msg->transfers))
227 cs_change = !cs_change;
228
229 if (cs_change)
230 spi_engine_gen_cs(p, dry, spi, false);
231 }
232
233 return 0;
234}
235
236static void spi_engine_xfer_next(struct spi_engine *spi_engine,
237 struct spi_transfer **_xfer)
238{
239 struct spi_message *msg = spi_engine->msg;
240 struct spi_transfer *xfer = *_xfer;
241
242 if (!xfer) {
243 xfer = list_first_entry(&msg->transfers,
244 struct spi_transfer, transfer_list);
245 } else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
246 xfer = NULL;
247 } else {
248 xfer = list_next_entry(xfer, transfer_list);
249 }
250
251 *_xfer = xfer;
252}
253
254static void spi_engine_tx_next(struct spi_engine *spi_engine)
255{
256 struct spi_transfer *xfer = spi_engine->tx_xfer;
257
258 do {
259 spi_engine_xfer_next(spi_engine, &xfer);
260 } while (xfer && !xfer->tx_buf);
261
262 spi_engine->tx_xfer = xfer;
263 if (xfer) {
264 spi_engine->tx_length = xfer->len;
265 spi_engine->tx_buf = xfer->tx_buf;
266 } else {
267 spi_engine->tx_buf = NULL;
268 }
269}
270
271static void spi_engine_rx_next(struct spi_engine *spi_engine)
272{
273 struct spi_transfer *xfer = spi_engine->rx_xfer;
274
275 do {
276 spi_engine_xfer_next(spi_engine, &xfer);
277 } while (xfer && !xfer->rx_buf);
278
279 spi_engine->rx_xfer = xfer;
280 if (xfer) {
281 spi_engine->rx_length = xfer->len;
282 spi_engine->rx_buf = xfer->rx_buf;
283 } else {
284 spi_engine->rx_buf = NULL;
285 }
286}
287
288static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine)
289{
290 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
291 unsigned int n, m, i;
292 const uint16_t *buf;
293
294 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
295 while (n && spi_engine->cmd_length) {
296 m = min(n, spi_engine->cmd_length);
297 buf = spi_engine->cmd_buf;
298 for (i = 0; i < m; i++)
299 writel_relaxed(buf[i], addr);
300 spi_engine->cmd_buf += m;
301 spi_engine->cmd_length -= m;
302 n -= m;
303 }
304
305 return spi_engine->cmd_length != 0;
306}
307
308static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine)
309{
310 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
311 unsigned int n, m, i;
312 const uint8_t *buf;
313
314 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
315 while (n && spi_engine->tx_length) {
316 m = min(n, spi_engine->tx_length);
317 buf = spi_engine->tx_buf;
318 for (i = 0; i < m; i++)
319 writel_relaxed(buf[i], addr);
320 spi_engine->tx_buf += m;
321 spi_engine->tx_length -= m;
322 n -= m;
323 if (spi_engine->tx_length == 0)
324 spi_engine_tx_next(spi_engine);
325 }
326
327 return spi_engine->tx_length != 0;
328}
329
330static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine)
331{
332 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
333 unsigned int n, m, i;
334 uint8_t *buf;
335
336 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
337 while (n && spi_engine->rx_length) {
338 m = min(n, spi_engine->rx_length);
339 buf = spi_engine->rx_buf;
340 for (i = 0; i < m; i++)
341 buf[i] = readl_relaxed(addr);
342 spi_engine->rx_buf += m;
343 spi_engine->rx_length -= m;
344 n -= m;
345 if (spi_engine->rx_length == 0)
346 spi_engine_rx_next(spi_engine);
347 }
348
349 return spi_engine->rx_length != 0;
350}
351
352static irqreturn_t spi_engine_irq(int irq, void *devid)
353{
354 struct spi_master *master = devid;
355 struct spi_engine *spi_engine = spi_master_get_devdata(master);
356 unsigned int disable_int = 0;
357 unsigned int pending;
358
359 pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
360
361 if (pending & SPI_ENGINE_INT_SYNC) {
362 writel_relaxed(SPI_ENGINE_INT_SYNC,
363 spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
364 spi_engine->completed_id = readl_relaxed(
365 spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
366 }
367
368 spin_lock(&spi_engine->lock);
369
370 if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
371 if (!spi_engine_write_cmd_fifo(spi_engine))
372 disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
373 }
374
375 if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
376 if (!spi_engine_write_tx_fifo(spi_engine))
377 disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
378 }
379
380 if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
381 if (!spi_engine_read_rx_fifo(spi_engine))
382 disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
383 }
384
385 if (pending & SPI_ENGINE_INT_SYNC) {
386 if (spi_engine->msg &&
387 spi_engine->completed_id == spi_engine->sync_id) {
388 struct spi_message *msg = spi_engine->msg;
389
390 kfree(spi_engine->p);
391 msg->status = 0;
392 msg->actual_length = msg->frame_length;
393 spi_engine->msg = NULL;
394 spi_finalize_current_message(master);
395 disable_int |= SPI_ENGINE_INT_SYNC;
396 }
397 }
398
399 if (disable_int) {
400 spi_engine->int_enable &= ~disable_int;
401 writel_relaxed(spi_engine->int_enable,
402 spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
403 }
404
405 spin_unlock(&spi_engine->lock);
406
407 return IRQ_HANDLED;
408}
409
410static int spi_engine_transfer_one_message(struct spi_master *master,
411 struct spi_message *msg)
412{
413 struct spi_engine_program p_dry, *p;
414 struct spi_engine *spi_engine = spi_master_get_devdata(master);
415 unsigned int int_enable = 0;
416 unsigned long flags;
417 size_t size;
418
419 p_dry.length = 0;
420 spi_engine_compile_message(spi_engine, msg, true, &p_dry);
421
422 size = sizeof(*p->instructions) * (p_dry.length + 1);
423 p = kzalloc(sizeof(*p) + size, GFP_KERNEL);
424 if (!p)
425 return -ENOMEM;
426 spi_engine_compile_message(spi_engine, msg, false, p);
427
428 spin_lock_irqsave(&spi_engine->lock, flags);
429 spi_engine->sync_id = (spi_engine->sync_id + 1) & 0xff;
430 spi_engine_program_add_cmd(p, false,
431 SPI_ENGINE_CMD_SYNC(spi_engine->sync_id));
432
433 spi_engine->msg = msg;
434 spi_engine->p = p;
435
436 spi_engine->cmd_buf = p->instructions;
437 spi_engine->cmd_length = p->length;
438 if (spi_engine_write_cmd_fifo(spi_engine))
439 int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
440
441 spi_engine_tx_next(spi_engine);
442 if (spi_engine_write_tx_fifo(spi_engine))
443 int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
444
445 spi_engine_rx_next(spi_engine);
446 if (spi_engine->rx_length != 0)
447 int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
448
449 int_enable |= SPI_ENGINE_INT_SYNC;
450
451 writel_relaxed(int_enable,
452 spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
453 spi_engine->int_enable = int_enable;
454 spin_unlock_irqrestore(&spi_engine->lock, flags);
455
456 return 0;
457}
458
459static int spi_engine_probe(struct platform_device *pdev)
460{
461 struct spi_engine *spi_engine;
462 struct spi_master *master;
463 unsigned int version;
464 struct resource *res;
465 int irq;
466 int ret;
467
468 irq = platform_get_irq(pdev, 0);
469 if (irq <= 0)
470 return -ENXIO;
471
472 spi_engine = devm_kzalloc(&pdev->dev, sizeof(*spi_engine), GFP_KERNEL);
473 if (!spi_engine)
474 return -ENOMEM;
475
476 master = spi_alloc_master(&pdev->dev, 0);
477 if (!master)
478 return -ENOMEM;
479
480 spi_master_set_devdata(master, spi_engine);
481
482 spin_lock_init(&spi_engine->lock);
483
484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 spi_engine->base = devm_ioremap_resource(&pdev->dev, res);
486 if (IS_ERR(spi_engine->base)) {
487 ret = PTR_ERR(spi_engine->base);
488 goto err_put_master;
489 }
490
491 version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION);
492 if (SPI_ENGINE_VERSION_MAJOR(version) != 1) {
493 dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n",
494 SPI_ENGINE_VERSION_MAJOR(version),
495 SPI_ENGINE_VERSION_MINOR(version),
496 SPI_ENGINE_VERSION_PATCH(version));
497 return -ENODEV;
498 }
499
500 spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
501 if (IS_ERR(spi_engine->clk)) {
502 ret = PTR_ERR(spi_engine->clk);
503 goto err_put_master;
504 }
505
506 spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk");
507 if (IS_ERR(spi_engine->ref_clk)) {
508 ret = PTR_ERR(spi_engine->ref_clk);
509 goto err_put_master;
510 }
511
512 ret = clk_prepare_enable(spi_engine->clk);
513 if (ret)
514 goto err_put_master;
515
516 ret = clk_prepare_enable(spi_engine->ref_clk);
517 if (ret)
518 goto err_clk_disable;
519
520 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
521 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
522 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
523
524 ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master);
525 if (ret)
526 goto err_ref_clk_disable;
527
528 master->dev.parent = &pdev->dev;
529 master->dev.of_node = pdev->dev.of_node;
530 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
531 master->bits_per_word_mask = SPI_BPW_MASK(8);
532 master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
533 master->transfer_one_message = spi_engine_transfer_one_message;
534 master->num_chipselect = 8;
535
536 ret = spi_register_master(master);
537 if (ret)
538 goto err_free_irq;
539
540 platform_set_drvdata(pdev, master);
541
542 return 0;
543err_free_irq:
544 free_irq(irq, master);
545err_ref_clk_disable:
546 clk_disable_unprepare(spi_engine->ref_clk);
547err_clk_disable:
548 clk_disable_unprepare(spi_engine->clk);
549err_put_master:
550 spi_master_put(master);
551 return ret;
552}
553
554static int spi_engine_remove(struct platform_device *pdev)
555{
556 struct spi_master *master = platform_get_drvdata(pdev);
557 struct spi_engine *spi_engine = spi_master_get_devdata(master);
558 int irq = platform_get_irq(pdev, 0);
559
560 spi_unregister_master(master);
561
562 free_irq(irq, master);
563
564 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
565 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
566 writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
567
568 clk_disable_unprepare(spi_engine->ref_clk);
569 clk_disable_unprepare(spi_engine->clk);
570
571 return 0;
572}
573
574static const struct of_device_id spi_engine_match_table[] = {
575 { .compatible = "adi,axi-spi-engine-1.00.a" },
576 { },
577};
578
579static struct platform_driver spi_engine_driver = {
580 .probe = spi_engine_probe,
581 .remove = spi_engine_remove,
582 .driver = {
583 .name = "spi-engine",
584 .of_match_table = spi_engine_match_table,
585 },
586};
587module_platform_driver(spi_engine_driver);
588
589MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
590MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
591MODULE_LICENSE("GPL");