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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/pwm.h>
13
14#define PWM_CONTROL 0x000
15#define PWM_CONTROL_SHIFT(x) ((x) * 8)
16#define PWM_CONTROL_MASK 0xff
17#define PWM_MODE 0x80 /* set timer in PWM mode */
18#define PWM_ENABLE (1 << 0)
19#define PWM_POLARITY (1 << 4)
20
21#define PERIOD(x) (((x) * 0x10) + 0x10)
22#define DUTY(x) (((x) * 0x10) + 0x14)
23
24#define PERIOD_MIN 0x2
25
26struct bcm2835_pwm {
27 void __iomem *base;
28 struct clk *clk;
29 unsigned long rate;
30};
31
32static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
33{
34 return pwmchip_get_drvdata(chip);
35}
36
37static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
38{
39 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
40 u32 value;
41
42 value = readl(pc->base + PWM_CONTROL);
43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
45 writel(value, pc->base + PWM_CONTROL);
46
47 return 0;
48}
49
50static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
51{
52 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
53 u32 value;
54
55 value = readl(pc->base + PWM_CONTROL);
56 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
57 writel(value, pc->base + PWM_CONTROL);
58}
59
60static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
61 const struct pwm_state *state)
62{
63
64 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
65 unsigned long long period_cycles;
66 u64 max_period;
67
68 u32 val;
69
70 /*
71 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
72 * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
73 * multiplication period * rate doesn't overflow.
74 * To calculate the maximal possible period that guarantees the
75 * above inequality:
76 *
77 * round(period * rate / NSEC_PER_SEC) <= U32_MAX
78 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
79 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
80 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
81 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
82 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
83 */
84 max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
85
86 if (state->period > max_period)
87 return -EINVAL;
88
89 /* set period */
90 period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
91
92 /* don't accept a period that is too small */
93 if (period_cycles < PERIOD_MIN)
94 return -EINVAL;
95
96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
97
98 /* set duty cycle */
99 val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
100 writel(val, pc->base + DUTY(pwm->hwpwm));
101
102 /* set polarity */
103 val = readl(pc->base + PWM_CONTROL);
104
105 if (state->polarity == PWM_POLARITY_NORMAL)
106 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
107 else
108 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
109
110 /* enable/disable */
111 if (state->enabled)
112 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
113 else
114 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
115
116 writel(val, pc->base + PWM_CONTROL);
117
118 return 0;
119}
120
121static const struct pwm_ops bcm2835_pwm_ops = {
122 .request = bcm2835_pwm_request,
123 .free = bcm2835_pwm_free,
124 .apply = bcm2835_pwm_apply,
125};
126
127static int bcm2835_pwm_probe(struct platform_device *pdev)
128{
129 struct device *dev = &pdev->dev;
130 struct pwm_chip *chip;
131 struct bcm2835_pwm *pc;
132 int ret;
133
134 chip = devm_pwmchip_alloc(dev, 2, sizeof(*pc));
135 if (IS_ERR(chip))
136 return PTR_ERR(chip);
137 pc = to_bcm2835_pwm(chip);
138
139 pc->base = devm_platform_ioremap_resource(pdev, 0);
140 if (IS_ERR(pc->base))
141 return PTR_ERR(pc->base);
142
143 pc->clk = devm_clk_get_enabled(dev, NULL);
144 if (IS_ERR(pc->clk))
145 return dev_err_probe(dev, PTR_ERR(pc->clk),
146 "clock not found\n");
147
148 ret = devm_clk_rate_exclusive_get(dev, pc->clk);
149 if (ret)
150 return dev_err_probe(dev, ret,
151 "fail to get exclusive rate\n");
152
153 pc->rate = clk_get_rate(pc->clk);
154 if (!pc->rate)
155 return dev_err_probe(dev, -EINVAL,
156 "failed to get clock rate\n");
157
158 chip->ops = &bcm2835_pwm_ops;
159 chip->atomic = true;
160
161 platform_set_drvdata(pdev, pc);
162
163 ret = devm_pwmchip_add(dev, chip);
164 if (ret < 0)
165 return dev_err_probe(dev, ret, "failed to add pwmchip\n");
166
167 return 0;
168}
169
170static int bcm2835_pwm_suspend(struct device *dev)
171{
172 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
173
174 clk_disable_unprepare(pc->clk);
175
176 return 0;
177}
178
179static int bcm2835_pwm_resume(struct device *dev)
180{
181 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
182
183 return clk_prepare_enable(pc->clk);
184}
185
186static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend,
187 bcm2835_pwm_resume);
188
189static const struct of_device_id bcm2835_pwm_of_match[] = {
190 { .compatible = "brcm,bcm2835-pwm", },
191 { /* sentinel */ }
192};
193MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
194
195static struct platform_driver bcm2835_pwm_driver = {
196 .driver = {
197 .name = "bcm2835-pwm",
198 .of_match_table = bcm2835_pwm_of_match,
199 .pm = pm_ptr(&bcm2835_pwm_pm_ops),
200 },
201 .probe = bcm2835_pwm_probe,
202};
203module_platform_driver(bcm2835_pwm_driver);
204
205MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
206MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
207MODULE_LICENSE("GPL v2");
1/*
2 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2.
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16
17#define PWM_CONTROL 0x000
18#define PWM_CONTROL_SHIFT(x) ((x) * 8)
19#define PWM_CONTROL_MASK 0xff
20#define PWM_MODE 0x80 /* set timer in PWM mode */
21#define PWM_ENABLE (1 << 0)
22#define PWM_POLARITY (1 << 4)
23
24#define PERIOD(x) (((x) * 0x10) + 0x10)
25#define DUTY(x) (((x) * 0x10) + 0x14)
26
27#define MIN_PERIOD 108 /* 9.2 MHz max. PWM clock */
28
29struct bcm2835_pwm {
30 struct pwm_chip chip;
31 struct device *dev;
32 void __iomem *base;
33 struct clk *clk;
34};
35
36static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
37{
38 return container_of(chip, struct bcm2835_pwm, chip);
39}
40
41static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
42{
43 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
44 u32 value;
45
46 value = readl(pc->base + PWM_CONTROL);
47 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
48 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
49 writel(value, pc->base + PWM_CONTROL);
50
51 return 0;
52}
53
54static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
55{
56 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
57 u32 value;
58
59 value = readl(pc->base + PWM_CONTROL);
60 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
61 writel(value, pc->base + PWM_CONTROL);
62}
63
64static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
65 int duty_ns, int period_ns)
66{
67 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
68 unsigned long rate = clk_get_rate(pc->clk);
69 unsigned long scaler;
70
71 if (!rate) {
72 dev_err(pc->dev, "failed to get clock rate\n");
73 return -EINVAL;
74 }
75
76 scaler = NSEC_PER_SEC / rate;
77
78 if (period_ns <= MIN_PERIOD) {
79 dev_err(pc->dev, "period %d not supported, minimum %d\n",
80 period_ns, MIN_PERIOD);
81 return -EINVAL;
82 }
83
84 writel(duty_ns / scaler, pc->base + DUTY(pwm->hwpwm));
85 writel(period_ns / scaler, pc->base + PERIOD(pwm->hwpwm));
86
87 return 0;
88}
89
90static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
91{
92 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
93 u32 value;
94
95 value = readl(pc->base + PWM_CONTROL);
96 value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
97 writel(value, pc->base + PWM_CONTROL);
98
99 return 0;
100}
101
102static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
103{
104 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
105 u32 value;
106
107 value = readl(pc->base + PWM_CONTROL);
108 value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
109 writel(value, pc->base + PWM_CONTROL);
110}
111
112static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
113 enum pwm_polarity polarity)
114{
115 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
116 u32 value;
117
118 value = readl(pc->base + PWM_CONTROL);
119
120 if (polarity == PWM_POLARITY_NORMAL)
121 value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
122 else
123 value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
124
125 writel(value, pc->base + PWM_CONTROL);
126
127 return 0;
128}
129
130static const struct pwm_ops bcm2835_pwm_ops = {
131 .request = bcm2835_pwm_request,
132 .free = bcm2835_pwm_free,
133 .config = bcm2835_pwm_config,
134 .enable = bcm2835_pwm_enable,
135 .disable = bcm2835_pwm_disable,
136 .set_polarity = bcm2835_set_polarity,
137 .owner = THIS_MODULE,
138};
139
140static int bcm2835_pwm_probe(struct platform_device *pdev)
141{
142 struct bcm2835_pwm *pc;
143 struct resource *res;
144 int ret;
145
146 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
147 if (!pc)
148 return -ENOMEM;
149
150 pc->dev = &pdev->dev;
151
152 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
153 pc->base = devm_ioremap_resource(&pdev->dev, res);
154 if (IS_ERR(pc->base))
155 return PTR_ERR(pc->base);
156
157 pc->clk = devm_clk_get(&pdev->dev, NULL);
158 if (IS_ERR(pc->clk)) {
159 dev_err(&pdev->dev, "clock not found: %ld\n", PTR_ERR(pc->clk));
160 return PTR_ERR(pc->clk);
161 }
162
163 ret = clk_prepare_enable(pc->clk);
164 if (ret)
165 return ret;
166
167 pc->chip.dev = &pdev->dev;
168 pc->chip.ops = &bcm2835_pwm_ops;
169 pc->chip.npwm = 2;
170
171 platform_set_drvdata(pdev, pc);
172
173 ret = pwmchip_add(&pc->chip);
174 if (ret < 0)
175 goto add_fail;
176
177 return 0;
178
179add_fail:
180 clk_disable_unprepare(pc->clk);
181 return ret;
182}
183
184static int bcm2835_pwm_remove(struct platform_device *pdev)
185{
186 struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
187
188 clk_disable_unprepare(pc->clk);
189
190 return pwmchip_remove(&pc->chip);
191}
192
193static const struct of_device_id bcm2835_pwm_of_match[] = {
194 { .compatible = "brcm,bcm2835-pwm", },
195 { /* sentinel */ }
196};
197MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
198
199static struct platform_driver bcm2835_pwm_driver = {
200 .driver = {
201 .name = "bcm2835-pwm",
202 .of_match_table = bcm2835_pwm_of_match,
203 },
204 .probe = bcm2835_pwm_probe,
205 .remove = bcm2835_pwm_remove,
206};
207module_platform_driver(bcm2835_pwm_driver);
208
209MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
210MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
211MODULE_LICENSE("GPL v2");