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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/irqdomain.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/msi.h>
17#include <linux/of_address.h>
18#include <linux/of_pci.h>
19#include <linux/of_platform.h>
20#include <linux/pci.h>
21#include <linux/pci-ecam.h>
22#include <linux/phy/phy.h>
23#include <linux/platform_device.h>
24#include <linux/irqchip/chained_irq.h>
25
26#include "../pci.h"
27
28/* Bridge core config registers */
29#define BRCFG_PCIE_RX0 0x00000000
30#define BRCFG_PCIE_RX1 0x00000004
31#define BRCFG_INTERRUPT 0x00000010
32#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
33
34/* Egress - Bridge translation registers */
35#define E_BREG_CAPABILITIES 0x00000200
36#define E_BREG_CONTROL 0x00000208
37#define E_BREG_BASE_LO 0x00000210
38#define E_BREG_BASE_HI 0x00000214
39#define E_ECAM_CAPABILITIES 0x00000220
40#define E_ECAM_CONTROL 0x00000228
41#define E_ECAM_BASE_LO 0x00000230
42#define E_ECAM_BASE_HI 0x00000234
43
44/* Ingress - address translations */
45#define I_MSII_CAPABILITIES 0x00000300
46#define I_MSII_CONTROL 0x00000308
47#define I_MSII_BASE_LO 0x00000310
48#define I_MSII_BASE_HI 0x00000314
49
50#define I_ISUB_CONTROL 0x000003E8
51#define SET_ISUB_CONTROL BIT(0)
52/* Rxed msg fifo - Interrupt status registers */
53#define MSGF_MISC_STATUS 0x00000400
54#define MSGF_MISC_MASK 0x00000404
55#define MSGF_LEG_STATUS 0x00000420
56#define MSGF_LEG_MASK 0x00000424
57#define MSGF_MSI_STATUS_LO 0x00000440
58#define MSGF_MSI_STATUS_HI 0x00000444
59#define MSGF_MSI_MASK_LO 0x00000448
60#define MSGF_MSI_MASK_HI 0x0000044C
61
62/* Msg filter mask bits */
63#define CFG_ENABLE_PM_MSG_FWD BIT(1)
64#define CFG_ENABLE_INT_MSG_FWD BIT(2)
65#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
66#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
67 CFG_ENABLE_INT_MSG_FWD | \
68 CFG_ENABLE_ERR_MSG_FWD)
69
70/* Misc interrupt status mask bits */
71#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
72#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
73#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
74#define MSGF_MISC_SR_MASTER_ERR BIT(5)
75#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
76#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
77#define MSGF_MISC_SR_FATAL_AER BIT(16)
78#define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
79#define MSGF_MISC_SR_CORR_AER BIT(18)
80#define MSGF_MISC_SR_UR_DETECT BIT(20)
81#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
82#define MSGF_MISC_SR_FATAL_DEV BIT(23)
83#define MSGF_MISC_SR_LINK_DOWN BIT(24)
84#define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25)
85#define MSGF_MISC_SR_LINK_BWIDTH BIT(26)
86
87#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
88 MSGF_MISC_SR_RXMSG_OVER | \
89 MSGF_MISC_SR_SLAVE_ERR | \
90 MSGF_MISC_SR_MASTER_ERR | \
91 MSGF_MISC_SR_I_ADDR_ERR | \
92 MSGF_MISC_SR_E_ADDR_ERR | \
93 MSGF_MISC_SR_FATAL_AER | \
94 MSGF_MISC_SR_NON_FATAL_AER | \
95 MSGF_MISC_SR_CORR_AER | \
96 MSGF_MISC_SR_UR_DETECT | \
97 MSGF_MISC_SR_NON_FATAL_DEV | \
98 MSGF_MISC_SR_FATAL_DEV | \
99 MSGF_MISC_SR_LINK_DOWN | \
100 MSGF_MISC_SR_LINK_AUTO_BWIDTH | \
101 MSGF_MISC_SR_LINK_BWIDTH)
102
103/* Legacy interrupt status mask bits */
104#define MSGF_LEG_SR_INTA BIT(0)
105#define MSGF_LEG_SR_INTB BIT(1)
106#define MSGF_LEG_SR_INTC BIT(2)
107#define MSGF_LEG_SR_INTD BIT(3)
108#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
109 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
110
111/* MSI interrupt status mask bits */
112#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
113#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
114
115#define MSII_PRESENT BIT(0)
116#define MSII_ENABLE BIT(0)
117#define MSII_STATUS_ENABLE BIT(15)
118
119/* Bridge config interrupt mask */
120#define BRCFG_INTERRUPT_MASK BIT(0)
121#define BREG_PRESENT BIT(0)
122#define BREG_ENABLE BIT(0)
123#define BREG_ENABLE_FORCE BIT(1)
124
125/* E_ECAM status mask bits */
126#define E_ECAM_PRESENT BIT(0)
127#define E_ECAM_CR_ENABLE BIT(0)
128#define E_ECAM_SIZE_LOC GENMASK(20, 16)
129#define E_ECAM_SIZE_SHIFT 16
130#define NWL_ECAM_MAX_SIZE 16
131
132#define CFG_DMA_REG_BAR GENMASK(2, 0)
133#define CFG_PCIE_CACHE GENMASK(7, 0)
134
135#define INT_PCI_MSI_NR (2 * 32)
136
137/* Readin the PS_LINKUP */
138#define PS_LINKUP_OFFSET 0x00000238
139#define PCIE_PHY_LINKUP_BIT BIT(0)
140#define PHY_RDY_LINKUP_BIT BIT(1)
141
142/* Parameters for the waiting for link up routine */
143#define LINK_WAIT_MAX_RETRIES 10
144#define LINK_WAIT_USLEEP_MIN 90000
145#define LINK_WAIT_USLEEP_MAX 100000
146
147struct nwl_msi { /* MSI information */
148 struct irq_domain *msi_domain;
149 DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
150 struct irq_domain *dev_domain;
151 struct mutex lock; /* protect bitmap variable */
152 int irq_msi0;
153 int irq_msi1;
154};
155
156struct nwl_pcie {
157 struct device *dev;
158 void __iomem *breg_base;
159 void __iomem *pcireg_base;
160 void __iomem *ecam_base;
161 struct phy *phy[4];
162 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
164 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
165 u32 breg_size;
166 u32 pcie_reg_size;
167 u32 ecam_size;
168 int irq_intx;
169 int irq_misc;
170 struct nwl_msi msi;
171 struct irq_domain *intx_irq_domain;
172 struct clk *clk;
173 raw_spinlock_t leg_mask_lock;
174};
175
176static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
177{
178 return readl(pcie->breg_base + off);
179}
180
181static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
182{
183 writel(val, pcie->breg_base + off);
184}
185
186static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
187{
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
189 return true;
190 return false;
191}
192
193static bool nwl_phy_link_up(struct nwl_pcie *pcie)
194{
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
196 return true;
197 return false;
198}
199
200static int nwl_wait_for_link(struct nwl_pcie *pcie)
201{
202 struct device *dev = pcie->dev;
203 int retries;
204
205 /* check if the link is up or not */
206 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
207 if (nwl_phy_link_up(pcie))
208 return 0;
209 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
210 }
211
212 dev_err(dev, "PHY link never came up\n");
213 return -ETIMEDOUT;
214}
215
216static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
217{
218 struct nwl_pcie *pcie = bus->sysdata;
219
220 /* Check link before accessing downstream ports */
221 if (!pci_is_root_bus(bus)) {
222 if (!nwl_pcie_link_up(pcie))
223 return false;
224 } else if (devfn > 0)
225 /* Only one device down on each root port */
226 return false;
227
228 return true;
229}
230
231/**
232 * nwl_pcie_map_bus - Get configuration base
233 *
234 * @bus: Bus structure of current bus
235 * @devfn: Device/function
236 * @where: Offset from base
237 *
238 * Return: Base address of the configuration space needed to be
239 * accessed.
240 */
241static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
242 int where)
243{
244 struct nwl_pcie *pcie = bus->sysdata;
245
246 if (!nwl_pcie_valid_device(bus, devfn))
247 return NULL;
248
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
250}
251
252/* PCIe operations */
253static struct pci_ops nwl_pcie_ops = {
254 .map_bus = nwl_pcie_map_bus,
255 .read = pci_generic_config_read,
256 .write = pci_generic_config_write,
257};
258
259static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
260{
261 struct nwl_pcie *pcie = data;
262 struct device *dev = pcie->dev;
263 u32 misc_stat;
264
265 /* Checking for misc interrupts */
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
267 MSGF_MISC_SR_MASKALL;
268 if (!misc_stat)
269 return IRQ_NONE;
270
271 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
272 dev_err_ratelimited(dev, "Received Message FIFO Overflow\n");
273
274 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
275 dev_err_ratelimited(dev, "Slave error\n");
276
277 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
278 dev_err_ratelimited(dev, "Master error\n");
279
280 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
281 dev_err_ratelimited(dev, "In Misc Ingress address translation error\n");
282
283 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
284 dev_err_ratelimited(dev, "In Misc Egress address translation error\n");
285
286 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
287 dev_err_ratelimited(dev, "Fatal Error in AER Capability\n");
288
289 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
290 dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n");
291
292 if (misc_stat & MSGF_MISC_SR_CORR_AER)
293 dev_err_ratelimited(dev, "Correctable Error in AER Capability\n");
294
295 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
296 dev_err_ratelimited(dev, "Unsupported request Detected\n");
297
298 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
299 dev_err_ratelimited(dev, "Non-Fatal Error Detected\n");
300
301 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
302 dev_err_ratelimited(dev, "Fatal Error Detected\n");
303
304 if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
305 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
306
307 if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH)
308 dev_info(dev, "Link Bandwidth Management Status bit set\n");
309
310 /* Clear misc interrupt status */
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
312
313 return IRQ_HANDLED;
314}
315
316static void nwl_pcie_leg_handler(struct irq_desc *desc)
317{
318 struct irq_chip *chip = irq_desc_get_chip(desc);
319 struct nwl_pcie *pcie;
320 unsigned long status;
321 u32 bit;
322
323 chained_irq_enter(chip, desc);
324 pcie = irq_desc_get_handler_data(desc);
325
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
327 MSGF_LEG_SR_MASKALL) != 0) {
328 for_each_set_bit(bit, &status, PCI_NUM_INTX)
329 generic_handle_domain_irq(pcie->intx_irq_domain, bit);
330 }
331
332 chained_irq_exit(chip, desc);
333}
334
335static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
336{
337 struct nwl_msi *msi = &pcie->msi;
338 unsigned long status;
339 u32 bit;
340
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
342 for_each_set_bit(bit, &status, 32) {
343 nwl_bridge_writel(pcie, 1 << bit, status_reg);
344 generic_handle_domain_irq(msi->dev_domain, bit);
345 }
346 }
347}
348
349static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
350{
351 struct irq_chip *chip = irq_desc_get_chip(desc);
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
353
354 chained_irq_enter(chip, desc);
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
356 chained_irq_exit(chip, desc);
357}
358
359static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
360{
361 struct irq_chip *chip = irq_desc_get_chip(desc);
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
363
364 chained_irq_enter(chip, desc);
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
366 chained_irq_exit(chip, desc);
367}
368
369static void nwl_mask_intx_irq(struct irq_data *data)
370{
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
372 unsigned long flags;
373 u32 mask;
374 u32 val;
375
376 mask = 1 << data->hwirq;
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
381}
382
383static void nwl_unmask_intx_irq(struct irq_data *data)
384{
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
386 unsigned long flags;
387 u32 mask;
388 u32 val;
389
390 mask = 1 << data->hwirq;
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
395}
396
397static struct irq_chip nwl_intx_irq_chip = {
398 .name = "nwl_pcie:legacy",
399 .irq_enable = nwl_unmask_intx_irq,
400 .irq_disable = nwl_mask_intx_irq,
401 .irq_mask = nwl_mask_intx_irq,
402 .irq_unmask = nwl_unmask_intx_irq,
403};
404
405static int nwl_intx_map(struct irq_domain *domain, unsigned int irq,
406 irq_hw_number_t hwirq)
407{
408 irq_set_chip_and_handler(irq, &nwl_intx_irq_chip, handle_level_irq);
409 irq_set_chip_data(irq, domain->host_data);
410 irq_set_status_flags(irq, IRQ_LEVEL);
411
412 return 0;
413}
414
415static const struct irq_domain_ops intx_domain_ops = {
416 .map = nwl_intx_map,
417 .xlate = pci_irqd_intx_xlate,
418};
419
420#ifdef CONFIG_PCI_MSI
421static struct irq_chip nwl_msi_irq_chip = {
422 .name = "nwl_pcie:msi",
423 .irq_enable = pci_msi_unmask_irq,
424 .irq_disable = pci_msi_mask_irq,
425 .irq_mask = pci_msi_mask_irq,
426 .irq_unmask = pci_msi_unmask_irq,
427};
428
429static struct msi_domain_info nwl_msi_domain_info = {
430 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
431 MSI_FLAG_NO_AFFINITY | MSI_FLAG_MULTI_PCI_MSI,
432 .chip = &nwl_msi_irq_chip,
433};
434#endif
435
436static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
437{
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
440
441 msg->address_lo = lower_32_bits(msi_addr);
442 msg->address_hi = upper_32_bits(msi_addr);
443 msg->data = data->hwirq;
444}
445
446static struct irq_chip nwl_irq_chip = {
447 .name = "Xilinx MSI",
448 .irq_compose_msi_msg = nwl_compose_msi_msg,
449};
450
451static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
452 unsigned int nr_irqs, void *args)
453{
454 struct nwl_pcie *pcie = domain->host_data;
455 struct nwl_msi *msi = &pcie->msi;
456 int bit;
457 int i;
458
459 mutex_lock(&msi->lock);
460 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
461 get_count_order(nr_irqs));
462 if (bit < 0) {
463 mutex_unlock(&msi->lock);
464 return -ENOSPC;
465 }
466
467 for (i = 0; i < nr_irqs; i++) {
468 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
469 domain->host_data, handle_simple_irq,
470 NULL, NULL);
471 }
472 mutex_unlock(&msi->lock);
473 return 0;
474}
475
476static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
477 unsigned int nr_irqs)
478{
479 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
480 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
481 struct nwl_msi *msi = &pcie->msi;
482
483 mutex_lock(&msi->lock);
484 bitmap_release_region(msi->bitmap, data->hwirq,
485 get_count_order(nr_irqs));
486 mutex_unlock(&msi->lock);
487}
488
489static const struct irq_domain_ops dev_msi_domain_ops = {
490 .alloc = nwl_irq_domain_alloc,
491 .free = nwl_irq_domain_free,
492};
493
494static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
495{
496#ifdef CONFIG_PCI_MSI
497 struct device *dev = pcie->dev;
498 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
499 struct nwl_msi *msi = &pcie->msi;
500
501 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
502 &dev_msi_domain_ops, pcie);
503 if (!msi->dev_domain) {
504 dev_err(dev, "failed to create dev IRQ domain\n");
505 return -ENOMEM;
506 }
507 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
508 &nwl_msi_domain_info,
509 msi->dev_domain);
510 if (!msi->msi_domain) {
511 dev_err(dev, "failed to create msi IRQ domain\n");
512 irq_domain_remove(msi->dev_domain);
513 return -ENOMEM;
514 }
515#endif
516 return 0;
517}
518
519static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i)
520{
521 int err = phy_power_off(pcie->phy[i]);
522
523 if (err)
524 dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i,
525 err);
526}
527
528static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i)
529{
530 int err = phy_exit(pcie->phy[i]);
531
532 if (err)
533 dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err);
534}
535
536static int nwl_pcie_phy_enable(struct nwl_pcie *pcie)
537{
538 int i, ret;
539
540 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
541 ret = phy_init(pcie->phy[i]);
542 if (ret)
543 goto err;
544
545 ret = phy_power_on(pcie->phy[i]);
546 if (ret) {
547 nwl_pcie_phy_exit(pcie, i);
548 goto err;
549 }
550 }
551
552 return 0;
553
554err:
555 while (i--) {
556 nwl_pcie_phy_power_off(pcie, i);
557 nwl_pcie_phy_exit(pcie, i);
558 }
559
560 return ret;
561}
562
563static void nwl_pcie_phy_disable(struct nwl_pcie *pcie)
564{
565 int i;
566
567 for (i = ARRAY_SIZE(pcie->phy); i--;) {
568 nwl_pcie_phy_power_off(pcie, i);
569 nwl_pcie_phy_exit(pcie, i);
570 }
571}
572
573static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
574{
575 struct device *dev = pcie->dev;
576 struct device_node *node = dev->of_node;
577 struct device_node *intc_node;
578
579 intc_node = of_get_next_child(node, NULL);
580 if (!intc_node) {
581 dev_err(dev, "No legacy intc node found\n");
582 return -EINVAL;
583 }
584
585 pcie->intx_irq_domain = irq_domain_add_linear(intc_node,
586 PCI_NUM_INTX,
587 &intx_domain_ops,
588 pcie);
589 of_node_put(intc_node);
590 if (!pcie->intx_irq_domain) {
591 dev_err(dev, "failed to create IRQ domain\n");
592 return -ENOMEM;
593 }
594
595 raw_spin_lock_init(&pcie->leg_mask_lock);
596 nwl_pcie_init_msi_irq_domain(pcie);
597 return 0;
598}
599
600static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
601{
602 struct device *dev = pcie->dev;
603 struct platform_device *pdev = to_platform_device(dev);
604 struct nwl_msi *msi = &pcie->msi;
605 unsigned long base;
606 int ret;
607
608 mutex_init(&msi->lock);
609
610 /* Get msi_1 IRQ number */
611 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
612 if (msi->irq_msi1 < 0)
613 return -EINVAL;
614
615 irq_set_chained_handler_and_data(msi->irq_msi1,
616 nwl_pcie_msi_handler_high, pcie);
617
618 /* Get msi_0 IRQ number */
619 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
620 if (msi->irq_msi0 < 0)
621 return -EINVAL;
622
623 irq_set_chained_handler_and_data(msi->irq_msi0,
624 nwl_pcie_msi_handler_low, pcie);
625
626 /* Check for msii_present bit */
627 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
628 if (!ret) {
629 dev_err(dev, "MSI not present\n");
630 return -EIO;
631 }
632
633 /* Enable MSII */
634 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
635 MSII_ENABLE, I_MSII_CONTROL);
636
637 /* Enable MSII status */
638 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
639 MSII_STATUS_ENABLE, I_MSII_CONTROL);
640
641 /* setup AFI/FPCI range */
642 base = pcie->phys_pcie_reg_base;
643 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
644 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
645
646 /*
647 * For high range MSI interrupts: disable, clear any pending,
648 * and enable
649 */
650 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
651
652 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
653 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
654
655 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
656
657 /*
658 * For low range MSI interrupts: disable, clear any pending,
659 * and enable
660 */
661 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
662
663 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
664 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
665
666 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
667
668 return 0;
669}
670
671static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
672{
673 struct device *dev = pcie->dev;
674 struct platform_device *pdev = to_platform_device(dev);
675 u32 breg_val, ecam_val;
676 int err;
677
678 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
679 if (!breg_val) {
680 dev_err(dev, "BREG is not present\n");
681 return breg_val;
682 }
683
684 /* Write bridge_off to breg base */
685 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
686 E_BREG_BASE_LO);
687 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
688 E_BREG_BASE_HI);
689
690 /* Enable BREG */
691 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
692 E_BREG_CONTROL);
693
694 /* Disable DMA channel registers */
695 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
696 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
697
698 /* Enable Ingress subtractive decode translation */
699 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
700
701 /* Enable msg filtering details */
702 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
703 BRCFG_PCIE_RX_MSG_FILTER);
704
705 /* This routes the PCIe DMA traffic to go through CCI path */
706 if (of_dma_is_coherent(dev->of_node))
707 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
708 CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
709
710 err = nwl_wait_for_link(pcie);
711 if (err)
712 return err;
713
714 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
715 if (!ecam_val) {
716 dev_err(dev, "ECAM is not present\n");
717 return ecam_val;
718 }
719
720 /* Enable ECAM */
721 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
722 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
723
724 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
725 (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),
726 E_ECAM_CONTROL);
727
728 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
729 E_ECAM_BASE_LO);
730 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
731 E_ECAM_BASE_HI);
732
733 if (nwl_pcie_link_up(pcie))
734 dev_info(dev, "Link is UP\n");
735 else
736 dev_info(dev, "Link is DOWN\n");
737
738 /* Get misc IRQ number */
739 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
740 if (pcie->irq_misc < 0)
741 return -EINVAL;
742
743 err = devm_request_irq(dev, pcie->irq_misc,
744 nwl_pcie_misc_handler, IRQF_SHARED,
745 "nwl_pcie:misc", pcie);
746 if (err) {
747 dev_err(dev, "fail to register misc IRQ#%d\n",
748 pcie->irq_misc);
749 return err;
750 }
751
752 /* Disable all misc interrupts */
753 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
754
755 /* Clear pending misc interrupts */
756 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
757 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
758
759 /* Enable all misc interrupts */
760 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
761
762 /* Disable all INTX interrupts */
763 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
764
765 /* Clear pending INTX interrupts */
766 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
767 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
768
769 /* Enable all INTX interrupts */
770 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
771
772 /* Enable the bridge config interrupt */
773 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
774 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
775
776 return 0;
777}
778
779static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
780 struct platform_device *pdev)
781{
782 struct device *dev = pcie->dev;
783 struct resource *res;
784 int i;
785
786 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
787 pcie->breg_base = devm_ioremap_resource(dev, res);
788 if (IS_ERR(pcie->breg_base))
789 return PTR_ERR(pcie->breg_base);
790 pcie->phys_breg_base = res->start;
791
792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
793 pcie->pcireg_base = devm_ioremap_resource(dev, res);
794 if (IS_ERR(pcie->pcireg_base))
795 return PTR_ERR(pcie->pcireg_base);
796 pcie->phys_pcie_reg_base = res->start;
797
798 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
799 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
800 if (IS_ERR(pcie->ecam_base))
801 return PTR_ERR(pcie->ecam_base);
802 pcie->phys_ecam_base = res->start;
803
804 /* Get intx IRQ number */
805 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
806 if (pcie->irq_intx < 0)
807 return pcie->irq_intx;
808
809 irq_set_chained_handler_and_data(pcie->irq_intx,
810 nwl_pcie_leg_handler, pcie);
811
812
813 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
814 pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i);
815 if (PTR_ERR(pcie->phy[i]) == -ENODEV) {
816 pcie->phy[i] = NULL;
817 break;
818 }
819
820 if (IS_ERR(pcie->phy[i]))
821 return PTR_ERR(pcie->phy[i]);
822 }
823
824 return 0;
825}
826
827static const struct of_device_id nwl_pcie_of_match[] = {
828 { .compatible = "xlnx,nwl-pcie-2.11", },
829 {}
830};
831
832static int nwl_pcie_probe(struct platform_device *pdev)
833{
834 struct device *dev = &pdev->dev;
835 struct nwl_pcie *pcie;
836 struct pci_host_bridge *bridge;
837 int err;
838
839 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
840 if (!bridge)
841 return -ENODEV;
842
843 pcie = pci_host_bridge_priv(bridge);
844 platform_set_drvdata(pdev, pcie);
845
846 pcie->dev = dev;
847
848 err = nwl_pcie_parse_dt(pcie, pdev);
849 if (err) {
850 dev_err(dev, "Parsing DT failed\n");
851 return err;
852 }
853
854 pcie->clk = devm_clk_get(dev, NULL);
855 if (IS_ERR(pcie->clk))
856 return PTR_ERR(pcie->clk);
857
858 err = clk_prepare_enable(pcie->clk);
859 if (err) {
860 dev_err(dev, "can't enable PCIe ref clock\n");
861 return err;
862 }
863
864 err = nwl_pcie_phy_enable(pcie);
865 if (err) {
866 dev_err(dev, "could not enable PHYs\n");
867 goto err_clk;
868 }
869
870 err = nwl_pcie_bridge_init(pcie);
871 if (err) {
872 dev_err(dev, "HW Initialization failed\n");
873 goto err_phy;
874 }
875
876 err = nwl_pcie_init_irq_domain(pcie);
877 if (err) {
878 dev_err(dev, "Failed creating IRQ Domain\n");
879 goto err_phy;
880 }
881
882 bridge->sysdata = pcie;
883 bridge->ops = &nwl_pcie_ops;
884
885 if (IS_ENABLED(CONFIG_PCI_MSI)) {
886 err = nwl_pcie_enable_msi(pcie);
887 if (err < 0) {
888 dev_err(dev, "failed to enable MSI support: %d\n", err);
889 goto err_phy;
890 }
891 }
892
893 err = pci_host_probe(bridge);
894 if (!err)
895 return 0;
896
897err_phy:
898 nwl_pcie_phy_disable(pcie);
899err_clk:
900 clk_disable_unprepare(pcie->clk);
901 return err;
902}
903
904static void nwl_pcie_remove(struct platform_device *pdev)
905{
906 struct nwl_pcie *pcie = platform_get_drvdata(pdev);
907
908 nwl_pcie_phy_disable(pcie);
909 clk_disable_unprepare(pcie->clk);
910}
911
912static struct platform_driver nwl_pcie_driver = {
913 .driver = {
914 .name = "nwl-pcie",
915 .suppress_bind_attrs = true,
916 .of_match_table = nwl_pcie_of_match,
917 },
918 .probe = nwl_pcie_probe,
919 .remove = nwl_pcie_remove,
920};
921builtin_platform_driver(nwl_pcie_driver);