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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe Endpoint controller driver
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/align.h>
10#include <linux/bitfield.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13
14#include "pcie-designware.h"
15#include <linux/pci-epc.h>
16#include <linux/pci-epf.h>
17
18/**
19 * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to
20 * the endpoint function
21 * @ep: DWC EP device
22 * @func_no: Function number of the endpoint device
23 *
24 * Return: struct dw_pcie_ep_func if success, NULL otherwise.
25 */
26struct dw_pcie_ep_func *
27dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
28{
29 struct dw_pcie_ep_func *ep_func;
30
31 list_for_each_entry(ep_func, &ep->func_list, list) {
32 if (ep_func->func_no == func_no)
33 return ep_func;
34 }
35
36 return NULL;
37}
38
39static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
40 enum pci_barno bar, int flags)
41{
42 struct dw_pcie_ep *ep = &pci->ep;
43 u32 reg;
44
45 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
46 dw_pcie_dbi_ro_wr_en(pci);
47 dw_pcie_ep_writel_dbi2(ep, func_no, reg, 0x0);
48 dw_pcie_ep_writel_dbi(ep, func_no, reg, 0x0);
49 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
50 dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0x0);
51 dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0x0);
52 }
53 dw_pcie_dbi_ro_wr_dis(pci);
54}
55
56/**
57 * dw_pcie_ep_reset_bar - Reset endpoint BAR
58 * @pci: DWC PCI device
59 * @bar: BAR number of the endpoint
60 */
61void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
62{
63 u8 func_no, funcs;
64
65 funcs = pci->ep.epc->max_functions;
66
67 for (func_no = 0; func_no < funcs; func_no++)
68 __dw_pcie_ep_reset_bar(pci, func_no, bar, 0);
69}
70EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
71
72static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
73 u8 cap_ptr, u8 cap)
74{
75 u8 cap_id, next_cap_ptr;
76 u16 reg;
77
78 if (!cap_ptr)
79 return 0;
80
81 reg = dw_pcie_ep_readw_dbi(ep, func_no, cap_ptr);
82 cap_id = (reg & 0x00ff);
83
84 if (cap_id > PCI_CAP_ID_MAX)
85 return 0;
86
87 if (cap_id == cap)
88 return cap_ptr;
89
90 next_cap_ptr = (reg & 0xff00) >> 8;
91 return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
92}
93
94static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap)
95{
96 u8 next_cap_ptr;
97 u16 reg;
98
99 reg = dw_pcie_ep_readw_dbi(ep, func_no, PCI_CAPABILITY_LIST);
100 next_cap_ptr = (reg & 0x00ff);
101
102 return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
103}
104
105static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
106 struct pci_epf_header *hdr)
107{
108 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
109 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
110
111 dw_pcie_dbi_ro_wr_en(pci);
112 dw_pcie_ep_writew_dbi(ep, func_no, PCI_VENDOR_ID, hdr->vendorid);
113 dw_pcie_ep_writew_dbi(ep, func_no, PCI_DEVICE_ID, hdr->deviceid);
114 dw_pcie_ep_writeb_dbi(ep, func_no, PCI_REVISION_ID, hdr->revid);
115 dw_pcie_ep_writeb_dbi(ep, func_no, PCI_CLASS_PROG, hdr->progif_code);
116 dw_pcie_ep_writew_dbi(ep, func_no, PCI_CLASS_DEVICE,
117 hdr->subclass_code | hdr->baseclass_code << 8);
118 dw_pcie_ep_writeb_dbi(ep, func_no, PCI_CACHE_LINE_SIZE,
119 hdr->cache_line_size);
120 dw_pcie_ep_writew_dbi(ep, func_no, PCI_SUBSYSTEM_VENDOR_ID,
121 hdr->subsys_vendor_id);
122 dw_pcie_ep_writew_dbi(ep, func_no, PCI_SUBSYSTEM_ID, hdr->subsys_id);
123 dw_pcie_ep_writeb_dbi(ep, func_no, PCI_INTERRUPT_PIN,
124 hdr->interrupt_pin);
125 dw_pcie_dbi_ro_wr_dis(pci);
126
127 return 0;
128}
129
130static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
131 dma_addr_t cpu_addr, enum pci_barno bar)
132{
133 int ret;
134 u32 free_win;
135 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
136
137 if (!ep->bar_to_atu[bar])
138 free_win = find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows);
139 else
140 free_win = ep->bar_to_atu[bar] - 1;
141
142 if (free_win >= pci->num_ib_windows) {
143 dev_err(pci->dev, "No free inbound window\n");
144 return -EINVAL;
145 }
146
147 ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type,
148 cpu_addr, bar);
149 if (ret < 0) {
150 dev_err(pci->dev, "Failed to program IB window\n");
151 return ret;
152 }
153
154 /*
155 * Always increment free_win before assignment, since value 0 is used to identify
156 * unallocated mapping.
157 */
158 ep->bar_to_atu[bar] = free_win + 1;
159 set_bit(free_win, ep->ib_window_map);
160
161 return 0;
162}
163
164static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
165 struct dw_pcie_ob_atu_cfg *atu)
166{
167 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
168 u32 free_win;
169 int ret;
170
171 free_win = find_first_zero_bit(ep->ob_window_map, pci->num_ob_windows);
172 if (free_win >= pci->num_ob_windows) {
173 dev_err(pci->dev, "No free outbound window\n");
174 return -EINVAL;
175 }
176
177 atu->index = free_win;
178 ret = dw_pcie_prog_outbound_atu(pci, atu);
179 if (ret)
180 return ret;
181
182 set_bit(free_win, ep->ob_window_map);
183 ep->outbound_addr[free_win] = atu->cpu_addr;
184
185 return 0;
186}
187
188static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
189 struct pci_epf_bar *epf_bar)
190{
191 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
192 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
193 enum pci_barno bar = epf_bar->barno;
194 u32 atu_index = ep->bar_to_atu[bar] - 1;
195
196 if (!ep->bar_to_atu[bar])
197 return;
198
199 __dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags);
200
201 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index);
202 clear_bit(atu_index, ep->ib_window_map);
203 ep->epf_bar[bar] = NULL;
204 ep->bar_to_atu[bar] = 0;
205}
206
207static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
208 struct pci_epf_bar *epf_bar)
209{
210 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
211 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
212 enum pci_barno bar = epf_bar->barno;
213 size_t size = epf_bar->size;
214 int flags = epf_bar->flags;
215 int ret, type;
216 u32 reg;
217
218 /*
219 * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs
220 * 1 and 2 to form a 64-bit BAR.
221 */
222 if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1))
223 return -EINVAL;
224
225 /*
226 * Certain EPF drivers dynamically change the physical address of a BAR
227 * (i.e. they call set_bar() twice, without ever calling clear_bar(), as
228 * calling clear_bar() would clear the BAR's PCI address assigned by the
229 * host).
230 */
231 if (ep->epf_bar[bar]) {
232 /*
233 * We can only dynamically change a BAR if the new BAR size and
234 * BAR flags do not differ from the existing configuration.
235 */
236 if (ep->epf_bar[bar]->barno != bar ||
237 ep->epf_bar[bar]->size != size ||
238 ep->epf_bar[bar]->flags != flags)
239 return -EINVAL;
240
241 /*
242 * When dynamically changing a BAR, skip writing the BAR reg, as
243 * that would clear the BAR's PCI address assigned by the host.
244 */
245 goto config_atu;
246 }
247
248 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
249
250 dw_pcie_dbi_ro_wr_en(pci);
251
252 dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1));
253 dw_pcie_ep_writel_dbi(ep, func_no, reg, flags);
254
255 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
256 dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1));
257 dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0);
258 }
259
260 dw_pcie_dbi_ro_wr_dis(pci);
261
262config_atu:
263 if (!(flags & PCI_BASE_ADDRESS_SPACE))
264 type = PCIE_ATU_TYPE_MEM;
265 else
266 type = PCIE_ATU_TYPE_IO;
267
268 ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar);
269 if (ret)
270 return ret;
271
272 ep->epf_bar[bar] = epf_bar;
273
274 return 0;
275}
276
277static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
278 u32 *atu_index)
279{
280 u32 index;
281 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
282
283 for (index = 0; index < pci->num_ob_windows; index++) {
284 if (ep->outbound_addr[index] != addr)
285 continue;
286 *atu_index = index;
287 return 0;
288 }
289
290 return -EINVAL;
291}
292
293static u64 dw_pcie_ep_align_addr(struct pci_epc *epc, u64 pci_addr,
294 size_t *pci_size, size_t *offset)
295{
296 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
297 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
298 u64 mask = pci->region_align - 1;
299 size_t ofst = pci_addr & mask;
300
301 *pci_size = ALIGN(ofst + *pci_size, epc->mem->window.page_size);
302 *offset = ofst;
303
304 return pci_addr & ~mask;
305}
306
307static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
308 phys_addr_t addr)
309{
310 int ret;
311 u32 atu_index;
312 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
313 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
314
315 ret = dw_pcie_find_index(ep, addr, &atu_index);
316 if (ret < 0)
317 return;
318
319 ep->outbound_addr[atu_index] = 0;
320 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, atu_index);
321 clear_bit(atu_index, ep->ob_window_map);
322}
323
324static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
325 phys_addr_t addr, u64 pci_addr, size_t size)
326{
327 int ret;
328 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
329 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
330 struct dw_pcie_ob_atu_cfg atu = { 0 };
331
332 atu.func_no = func_no;
333 atu.type = PCIE_ATU_TYPE_MEM;
334 atu.cpu_addr = addr;
335 atu.pci_addr = pci_addr;
336 atu.size = size;
337 ret = dw_pcie_ep_outbound_atu(ep, &atu);
338 if (ret) {
339 dev_err(pci->dev, "Failed to enable address\n");
340 return ret;
341 }
342
343 return 0;
344}
345
346static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
347{
348 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
349 struct dw_pcie_ep_func *ep_func;
350 u32 val, reg;
351
352 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
353 if (!ep_func || !ep_func->msi_cap)
354 return -EINVAL;
355
356 reg = ep_func->msi_cap + PCI_MSI_FLAGS;
357 val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
358 if (!(val & PCI_MSI_FLAGS_ENABLE))
359 return -EINVAL;
360
361 val = FIELD_GET(PCI_MSI_FLAGS_QSIZE, val);
362
363 return val;
364}
365
366static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
367 u8 interrupts)
368{
369 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
370 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
371 struct dw_pcie_ep_func *ep_func;
372 u32 val, reg;
373
374 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
375 if (!ep_func || !ep_func->msi_cap)
376 return -EINVAL;
377
378 reg = ep_func->msi_cap + PCI_MSI_FLAGS;
379 val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
380 val &= ~PCI_MSI_FLAGS_QMASK;
381 val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, interrupts);
382 dw_pcie_dbi_ro_wr_en(pci);
383 dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
384 dw_pcie_dbi_ro_wr_dis(pci);
385
386 return 0;
387}
388
389static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
390{
391 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
392 struct dw_pcie_ep_func *ep_func;
393 u32 val, reg;
394
395 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
396 if (!ep_func || !ep_func->msix_cap)
397 return -EINVAL;
398
399 reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
400 val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
401 if (!(val & PCI_MSIX_FLAGS_ENABLE))
402 return -EINVAL;
403
404 val &= PCI_MSIX_FLAGS_QSIZE;
405
406 return val;
407}
408
409static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
410 u16 interrupts, enum pci_barno bir, u32 offset)
411{
412 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
413 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
414 struct dw_pcie_ep_func *ep_func;
415 u32 val, reg;
416
417 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
418 if (!ep_func || !ep_func->msix_cap)
419 return -EINVAL;
420
421 dw_pcie_dbi_ro_wr_en(pci);
422
423 reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
424 val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
425 val &= ~PCI_MSIX_FLAGS_QSIZE;
426 val |= interrupts;
427 dw_pcie_writew_dbi(pci, reg, val);
428
429 reg = ep_func->msix_cap + PCI_MSIX_TABLE;
430 val = offset | bir;
431 dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
432
433 reg = ep_func->msix_cap + PCI_MSIX_PBA;
434 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
435 dw_pcie_ep_writel_dbi(ep, func_no, reg, val);
436
437 dw_pcie_dbi_ro_wr_dis(pci);
438
439 return 0;
440}
441
442static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
443 unsigned int type, u16 interrupt_num)
444{
445 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
446
447 if (!ep->ops->raise_irq)
448 return -EINVAL;
449
450 return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
451}
452
453static void dw_pcie_ep_stop(struct pci_epc *epc)
454{
455 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
456 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
457
458 dw_pcie_stop_link(pci);
459}
460
461static int dw_pcie_ep_start(struct pci_epc *epc)
462{
463 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
464 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
465
466 return dw_pcie_start_link(pci);
467}
468
469static const struct pci_epc_features*
470dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
471{
472 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
473
474 if (!ep->ops->get_features)
475 return NULL;
476
477 return ep->ops->get_features(ep);
478}
479
480static const struct pci_epc_ops epc_ops = {
481 .write_header = dw_pcie_ep_write_header,
482 .set_bar = dw_pcie_ep_set_bar,
483 .clear_bar = dw_pcie_ep_clear_bar,
484 .align_addr = dw_pcie_ep_align_addr,
485 .map_addr = dw_pcie_ep_map_addr,
486 .unmap_addr = dw_pcie_ep_unmap_addr,
487 .set_msi = dw_pcie_ep_set_msi,
488 .get_msi = dw_pcie_ep_get_msi,
489 .set_msix = dw_pcie_ep_set_msix,
490 .get_msix = dw_pcie_ep_get_msix,
491 .raise_irq = dw_pcie_ep_raise_irq,
492 .start = dw_pcie_ep_start,
493 .stop = dw_pcie_ep_stop,
494 .get_features = dw_pcie_ep_get_features,
495};
496
497/**
498 * dw_pcie_ep_raise_intx_irq - Raise INTx IRQ to the host
499 * @ep: DWC EP device
500 * @func_no: Function number of the endpoint
501 *
502 * Return: 0 if success, errono otherwise.
503 */
504int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
505{
506 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
507 struct device *dev = pci->dev;
508
509 dev_err(dev, "EP cannot raise INTX IRQs\n");
510
511 return -EINVAL;
512}
513EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
514
515/**
516 * dw_pcie_ep_raise_msi_irq - Raise MSI IRQ to the host
517 * @ep: DWC EP device
518 * @func_no: Function number of the endpoint
519 * @interrupt_num: Interrupt number to be raised
520 *
521 * Return: 0 if success, errono otherwise.
522 */
523int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
524 u8 interrupt_num)
525{
526 u32 msg_addr_lower, msg_addr_upper, reg;
527 struct dw_pcie_ep_func *ep_func;
528 struct pci_epc *epc = ep->epc;
529 size_t map_size = sizeof(u32);
530 size_t offset;
531 u16 msg_ctrl, msg_data;
532 bool has_upper;
533 u64 msg_addr;
534 int ret;
535
536 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
537 if (!ep_func || !ep_func->msi_cap)
538 return -EINVAL;
539
540 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
541 reg = ep_func->msi_cap + PCI_MSI_FLAGS;
542 msg_ctrl = dw_pcie_ep_readw_dbi(ep, func_no, reg);
543 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
544 reg = ep_func->msi_cap + PCI_MSI_ADDRESS_LO;
545 msg_addr_lower = dw_pcie_ep_readl_dbi(ep, func_no, reg);
546 if (has_upper) {
547 reg = ep_func->msi_cap + PCI_MSI_ADDRESS_HI;
548 msg_addr_upper = dw_pcie_ep_readl_dbi(ep, func_no, reg);
549 reg = ep_func->msi_cap + PCI_MSI_DATA_64;
550 msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
551 } else {
552 msg_addr_upper = 0;
553 reg = ep_func->msi_cap + PCI_MSI_DATA_32;
554 msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
555 }
556 msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
557
558 msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset);
559 ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
560 map_size);
561 if (ret)
562 return ret;
563
564 writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);
565
566 dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
567
568 return 0;
569}
570EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msi_irq);
571
572/**
573 * dw_pcie_ep_raise_msix_irq_doorbell - Raise MSI-X to the host using Doorbell
574 * method
575 * @ep: DWC EP device
576 * @func_no: Function number of the endpoint device
577 * @interrupt_num: Interrupt number to be raised
578 *
579 * Return: 0 if success, errno otherwise.
580 */
581int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
582 u16 interrupt_num)
583{
584 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
585 struct dw_pcie_ep_func *ep_func;
586 u32 msg_data;
587
588 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
589 if (!ep_func || !ep_func->msix_cap)
590 return -EINVAL;
591
592 msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
593 (interrupt_num - 1);
594
595 dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
596
597 return 0;
598}
599
600/**
601 * dw_pcie_ep_raise_msix_irq - Raise MSI-X to the host
602 * @ep: DWC EP device
603 * @func_no: Function number of the endpoint device
604 * @interrupt_num: Interrupt number to be raised
605 *
606 * Return: 0 if success, errno otherwise.
607 */
608int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
609 u16 interrupt_num)
610{
611 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
612 struct pci_epf_msix_tbl *msix_tbl;
613 struct dw_pcie_ep_func *ep_func;
614 struct pci_epc *epc = ep->epc;
615 size_t map_size = sizeof(u32);
616 size_t offset;
617 u32 reg, msg_data, vec_ctrl;
618 u32 tbl_offset;
619 u64 msg_addr;
620 int ret;
621 u8 bir;
622
623 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
624 if (!ep_func || !ep_func->msix_cap)
625 return -EINVAL;
626
627 reg = ep_func->msix_cap + PCI_MSIX_TABLE;
628 tbl_offset = dw_pcie_ep_readl_dbi(ep, func_no, reg);
629 bir = FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset);
630 tbl_offset &= PCI_MSIX_TABLE_OFFSET;
631
632 msix_tbl = ep->epf_bar[bir]->addr + tbl_offset;
633 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
634 msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
635 vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl;
636
637 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) {
638 dev_dbg(pci->dev, "MSI-X entry ctrl set\n");
639 return -EPERM;
640 }
641
642 msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &map_size, &offset);
643 ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
644 map_size);
645 if (ret)
646 return ret;
647
648 writel(msg_data, ep->msi_mem + offset);
649
650 dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
651
652 return 0;
653}
654
655/**
656 * dw_pcie_ep_cleanup - Cleanup DWC EP resources after fundamental reset
657 * @ep: DWC EP device
658 *
659 * Cleans up the DWC EP specific resources like eDMA etc... after fundamental
660 * reset like PERST#. Note that this API is only applicable for drivers
661 * supporting PERST# or any other methods of fundamental reset.
662 */
663void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep)
664{
665 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
666
667 dw_pcie_edma_remove(pci);
668}
669EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup);
670
671/**
672 * dw_pcie_ep_deinit - Deinitialize the endpoint device
673 * @ep: DWC EP device
674 *
675 * Deinitialize the endpoint device. EPC device is not destroyed since that will
676 * be taken care by Devres.
677 */
678void dw_pcie_ep_deinit(struct dw_pcie_ep *ep)
679{
680 struct pci_epc *epc = ep->epc;
681
682 dw_pcie_ep_cleanup(ep);
683
684 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
685 epc->mem->window.page_size);
686
687 pci_epc_mem_exit(epc);
688}
689EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit);
690
691static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
692{
693 u32 header;
694 int pos = PCI_CFG_SPACE_SIZE;
695
696 while (pos) {
697 header = dw_pcie_readl_dbi(pci, pos);
698 if (PCI_EXT_CAP_ID(header) == cap)
699 return pos;
700
701 pos = PCI_EXT_CAP_NEXT(header);
702 if (!pos)
703 break;
704 }
705
706 return 0;
707}
708
709static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
710{
711 unsigned int offset;
712 unsigned int nbars;
713 u32 reg, i;
714
715 offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
716
717 dw_pcie_dbi_ro_wr_en(pci);
718
719 if (offset) {
720 reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
721 nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
722 PCI_REBAR_CTRL_NBAR_SHIFT;
723
724 /*
725 * PCIe r6.0, sec 7.8.6.2 require us to support at least one
726 * size in the range from 1 MB to 512 GB. Advertise support
727 * for 1 MB BAR size only.
728 */
729 for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
730 dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4));
731 }
732
733 dw_pcie_setup(pci);
734 dw_pcie_dbi_ro_wr_dis(pci);
735}
736
737/**
738 * dw_pcie_ep_init_registers - Initialize DWC EP specific registers
739 * @ep: DWC EP device
740 *
741 * Initialize the registers (CSRs) specific to DWC EP. This API should be called
742 * only when the endpoint receives an active refclk (either from host or
743 * generated locally).
744 */
745int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
746{
747 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
748 struct dw_pcie_ep_func *ep_func;
749 struct device *dev = pci->dev;
750 struct pci_epc *epc = ep->epc;
751 u32 ptm_cap_base, reg;
752 u8 hdr_type;
753 u8 func_no;
754 void *addr;
755 int ret;
756
757 hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) &
758 PCI_HEADER_TYPE_MASK;
759 if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
760 dev_err(pci->dev,
761 "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
762 hdr_type);
763 return -EIO;
764 }
765
766 dw_pcie_version_detect(pci);
767
768 dw_pcie_iatu_detect(pci);
769
770 ret = dw_pcie_edma_detect(pci);
771 if (ret)
772 return ret;
773
774 if (!ep->ib_window_map) {
775 ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
776 GFP_KERNEL);
777 if (!ep->ib_window_map)
778 goto err_remove_edma;
779 }
780
781 if (!ep->ob_window_map) {
782 ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
783 GFP_KERNEL);
784 if (!ep->ob_window_map)
785 goto err_remove_edma;
786 }
787
788 if (!ep->outbound_addr) {
789 addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
790 GFP_KERNEL);
791 if (!addr)
792 goto err_remove_edma;
793 ep->outbound_addr = addr;
794 }
795
796 for (func_no = 0; func_no < epc->max_functions; func_no++) {
797
798 ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
799 if (ep_func)
800 continue;
801
802 ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
803 if (!ep_func)
804 goto err_remove_edma;
805
806 ep_func->func_no = func_no;
807 ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
808 PCI_CAP_ID_MSI);
809 ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
810 PCI_CAP_ID_MSIX);
811
812 list_add_tail(&ep_func->list, &ep->func_list);
813 }
814
815 if (ep->ops->init)
816 ep->ops->init(ep);
817
818 ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
819
820 /*
821 * PTM responder capability can be disabled only after disabling
822 * PTM root capability.
823 */
824 if (ptm_cap_base) {
825 dw_pcie_dbi_ro_wr_en(pci);
826 reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
827 reg &= ~PCI_PTM_CAP_ROOT;
828 dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
829
830 reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP);
831 reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK);
832 dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg);
833 dw_pcie_dbi_ro_wr_dis(pci);
834 }
835
836 dw_pcie_ep_init_non_sticky_registers(pci);
837
838 return 0;
839
840err_remove_edma:
841 dw_pcie_edma_remove(pci);
842
843 return ret;
844}
845EXPORT_SYMBOL_GPL(dw_pcie_ep_init_registers);
846
847/**
848 * dw_pcie_ep_linkup - Notify EPF drivers about Link Up event
849 * @ep: DWC EP device
850 */
851void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
852{
853 struct pci_epc *epc = ep->epc;
854
855 pci_epc_linkup(epc);
856}
857EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup);
858
859/**
860 * dw_pcie_ep_linkdown - Notify EPF drivers about Link Down event
861 * @ep: DWC EP device
862 *
863 * Non-sticky registers are also initialized before sending the notification to
864 * the EPF drivers. This is needed since the registers need to be initialized
865 * before the link comes back again.
866 */
867void dw_pcie_ep_linkdown(struct dw_pcie_ep *ep)
868{
869 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
870 struct pci_epc *epc = ep->epc;
871
872 /*
873 * Initialize the non-sticky DWC registers as they would've reset post
874 * Link Down. This is specifically needed for drivers not supporting
875 * PERST# as they have no way to reinitialize the registers before the
876 * link comes back again.
877 */
878 dw_pcie_ep_init_non_sticky_registers(pci);
879
880 pci_epc_linkdown(epc);
881}
882EXPORT_SYMBOL_GPL(dw_pcie_ep_linkdown);
883
884/**
885 * dw_pcie_ep_init - Initialize the endpoint device
886 * @ep: DWC EP device
887 *
888 * Initialize the endpoint device. Allocate resources and create the EPC
889 * device with the endpoint framework.
890 *
891 * Return: 0 if success, errno otherwise.
892 */
893int dw_pcie_ep_init(struct dw_pcie_ep *ep)
894{
895 int ret;
896 struct resource *res;
897 struct pci_epc *epc;
898 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
899 struct device *dev = pci->dev;
900 struct platform_device *pdev = to_platform_device(dev);
901 struct device_node *np = dev->of_node;
902
903 INIT_LIST_HEAD(&ep->func_list);
904
905 ret = dw_pcie_get_resources(pci);
906 if (ret)
907 return ret;
908
909 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
910 if (!res)
911 return -EINVAL;
912
913 ep->phys_base = res->start;
914 ep->addr_size = resource_size(res);
915
916 if (ep->ops->pre_init)
917 ep->ops->pre_init(ep);
918
919 epc = devm_pci_epc_create(dev, &epc_ops);
920 if (IS_ERR(epc)) {
921 dev_err(dev, "Failed to create epc device\n");
922 return PTR_ERR(epc);
923 }
924
925 ep->epc = epc;
926 epc_set_drvdata(epc, ep);
927
928 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
929 if (ret < 0)
930 epc->max_functions = 1;
931
932 ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
933 ep->page_size);
934 if (ret < 0) {
935 dev_err(dev, "Failed to initialize address space\n");
936 return ret;
937 }
938
939 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
940 epc->mem->window.page_size);
941 if (!ep->msi_mem) {
942 ret = -ENOMEM;
943 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
944 goto err_exit_epc_mem;
945 }
946
947 return 0;
948
949err_exit_epc_mem:
950 pci_epc_mem_exit(epc);
951
952 return ret;
953}
954EXPORT_SYMBOL_GPL(dw_pcie_ep_init);