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1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33
34#include <drm/drm.h>
35#include <drm/drm_drv.h>
36
37#include "amdgpu.h"
38#include "amdgpu_pm.h"
39#include "amdgpu_uvd.h"
40#include "amdgpu_cs.h"
41#include "cikd.h"
42#include "uvd/uvd_4_2_d.h"
43
44#include "amdgpu_ras.h"
45
46/* 1 second timeout */
47#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
48
49/* Firmware versions for VI */
50#define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
51#define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
52#define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
53#define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
54
55/* Polaris10/11 firmware version */
56#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
57
58/* Firmware Names */
59#ifdef CONFIG_DRM_AMDGPU_SI
60#define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin"
61#define FIRMWARE_VERDE "amdgpu/verde_uvd.bin"
62#define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin"
63#define FIRMWARE_OLAND "amdgpu/oland_uvd.bin"
64#endif
65#ifdef CONFIG_DRM_AMDGPU_CIK
66#define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin"
67#define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
68#define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
69#define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
70#define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin"
71#endif
72#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
73#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
74#define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
75#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
76#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
77#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
78#define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
79#define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin"
80
81#define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"
82#define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin"
83#define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin"
84
85/* These are common relative offsets for all asics, from uvd_7_0_offset.h, */
86#define UVD_GPCOM_VCPU_CMD 0x03c3
87#define UVD_GPCOM_VCPU_DATA0 0x03c4
88#define UVD_GPCOM_VCPU_DATA1 0x03c5
89#define UVD_NO_OP 0x03ff
90#define UVD_BASE_SI 0x3800
91
92/*
93 * amdgpu_uvd_cs_ctx - Command submission parser context
94 *
95 * Used for emulating virtual memory support on UVD 4.2.
96 */
97struct amdgpu_uvd_cs_ctx {
98 struct amdgpu_cs_parser *parser;
99 unsigned int reg, count;
100 unsigned int data0, data1;
101 unsigned int idx;
102 struct amdgpu_ib *ib;
103
104 /* does the IB has a msg command */
105 bool has_msg_cmd;
106
107 /* minimum buffer sizes */
108 unsigned int *buf_sizes;
109};
110
111#ifdef CONFIG_DRM_AMDGPU_SI
112MODULE_FIRMWARE(FIRMWARE_TAHITI);
113MODULE_FIRMWARE(FIRMWARE_VERDE);
114MODULE_FIRMWARE(FIRMWARE_PITCAIRN);
115MODULE_FIRMWARE(FIRMWARE_OLAND);
116#endif
117#ifdef CONFIG_DRM_AMDGPU_CIK
118MODULE_FIRMWARE(FIRMWARE_BONAIRE);
119MODULE_FIRMWARE(FIRMWARE_KABINI);
120MODULE_FIRMWARE(FIRMWARE_KAVERI);
121MODULE_FIRMWARE(FIRMWARE_HAWAII);
122MODULE_FIRMWARE(FIRMWARE_MULLINS);
123#endif
124MODULE_FIRMWARE(FIRMWARE_TONGA);
125MODULE_FIRMWARE(FIRMWARE_CARRIZO);
126MODULE_FIRMWARE(FIRMWARE_FIJI);
127MODULE_FIRMWARE(FIRMWARE_STONEY);
128MODULE_FIRMWARE(FIRMWARE_POLARIS10);
129MODULE_FIRMWARE(FIRMWARE_POLARIS11);
130MODULE_FIRMWARE(FIRMWARE_POLARIS12);
131MODULE_FIRMWARE(FIRMWARE_VEGAM);
132
133MODULE_FIRMWARE(FIRMWARE_VEGA10);
134MODULE_FIRMWARE(FIRMWARE_VEGA12);
135MODULE_FIRMWARE(FIRMWARE_VEGA20);
136
137static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
138static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
139
140static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
141 uint32_t size,
142 struct amdgpu_bo **bo_ptr)
143{
144 struct ttm_operation_ctx ctx = { true, false };
145 struct amdgpu_bo *bo = NULL;
146 void *addr;
147 int r;
148
149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
150 AMDGPU_GEM_DOMAIN_GTT,
151 &bo, NULL, &addr);
152 if (r)
153 return r;
154
155 if (adev->uvd.address_64_bit)
156 goto succ;
157
158 amdgpu_bo_kunmap(bo);
159 amdgpu_bo_unpin(bo);
160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
161 amdgpu_uvd_force_into_uvd_segment(bo);
162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
163 if (r)
164 goto err;
165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
166 if (r)
167 goto err_pin;
168 r = amdgpu_bo_kmap(bo, &addr);
169 if (r)
170 goto err_kmap;
171succ:
172 amdgpu_bo_unreserve(bo);
173 *bo_ptr = bo;
174 return 0;
175err_kmap:
176 amdgpu_bo_unpin(bo);
177err_pin:
178err:
179 amdgpu_bo_unreserve(bo);
180 amdgpu_bo_unref(&bo);
181 return r;
182}
183
184int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
185{
186 unsigned long bo_size;
187 const char *fw_name;
188 const struct common_firmware_header *hdr;
189 unsigned int family_id;
190 int i, j, r;
191
192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
193
194 switch (adev->asic_type) {
195#ifdef CONFIG_DRM_AMDGPU_SI
196 case CHIP_TAHITI:
197 fw_name = FIRMWARE_TAHITI;
198 break;
199 case CHIP_VERDE:
200 fw_name = FIRMWARE_VERDE;
201 break;
202 case CHIP_PITCAIRN:
203 fw_name = FIRMWARE_PITCAIRN;
204 break;
205 case CHIP_OLAND:
206 fw_name = FIRMWARE_OLAND;
207 break;
208#endif
209#ifdef CONFIG_DRM_AMDGPU_CIK
210 case CHIP_BONAIRE:
211 fw_name = FIRMWARE_BONAIRE;
212 break;
213 case CHIP_KABINI:
214 fw_name = FIRMWARE_KABINI;
215 break;
216 case CHIP_KAVERI:
217 fw_name = FIRMWARE_KAVERI;
218 break;
219 case CHIP_HAWAII:
220 fw_name = FIRMWARE_HAWAII;
221 break;
222 case CHIP_MULLINS:
223 fw_name = FIRMWARE_MULLINS;
224 break;
225#endif
226 case CHIP_TONGA:
227 fw_name = FIRMWARE_TONGA;
228 break;
229 case CHIP_FIJI:
230 fw_name = FIRMWARE_FIJI;
231 break;
232 case CHIP_CARRIZO:
233 fw_name = FIRMWARE_CARRIZO;
234 break;
235 case CHIP_STONEY:
236 fw_name = FIRMWARE_STONEY;
237 break;
238 case CHIP_POLARIS10:
239 fw_name = FIRMWARE_POLARIS10;
240 break;
241 case CHIP_POLARIS11:
242 fw_name = FIRMWARE_POLARIS11;
243 break;
244 case CHIP_POLARIS12:
245 fw_name = FIRMWARE_POLARIS12;
246 break;
247 case CHIP_VEGA10:
248 fw_name = FIRMWARE_VEGA10;
249 break;
250 case CHIP_VEGA12:
251 fw_name = FIRMWARE_VEGA12;
252 break;
253 case CHIP_VEGAM:
254 fw_name = FIRMWARE_VEGAM;
255 break;
256 case CHIP_VEGA20:
257 fw_name = FIRMWARE_VEGA20;
258 break;
259 default:
260 return -EINVAL;
261 }
262
263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, "%s", fw_name);
264 if (r) {
265 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
266 fw_name);
267 amdgpu_ucode_release(&adev->uvd.fw);
268 return r;
269 }
270
271 /* Set the default UVD handles that the firmware can handle */
272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
273
274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
275 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
276
277 if (adev->asic_type < CHIP_VEGA20) {
278 unsigned int version_major, version_minor;
279
280 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
281 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
282 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",
283 version_major, version_minor, family_id);
284
285 /*
286 * Limit the number of UVD handles depending on microcode major
287 * and minor versions. The firmware version which has 40 UVD
288 * instances support is 1.80. So all subsequent versions should
289 * also have the same support.
290 */
291 if ((version_major > 0x01) ||
292 ((version_major == 0x01) && (version_minor >= 0x50)))
293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
294
295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
296 (family_id << 8));
297
298 if ((adev->asic_type == CHIP_POLARIS10 ||
299 adev->asic_type == CHIP_POLARIS11) &&
300 (adev->uvd.fw_version < FW_1_66_16))
301 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",
302 version_major, version_minor);
303 } else {
304 unsigned int enc_major, enc_minor, dec_minor;
305
306 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
307 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
308 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
309 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n",
310 enc_major, enc_minor, dec_minor, family_id);
311
312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
313
314 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
315 }
316
317 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
318 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
319 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
321
322 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
323 if (adev->uvd.harvest_config & (1 << j))
324 continue;
325 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
326 AMDGPU_GEM_DOMAIN_VRAM |
327 AMDGPU_GEM_DOMAIN_GTT,
328 &adev->uvd.inst[j].vcpu_bo,
329 &adev->uvd.inst[j].gpu_addr,
330 &adev->uvd.inst[j].cpu_addr);
331 if (r) {
332 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
333 return r;
334 }
335 }
336
337 for (i = 0; i < adev->uvd.max_handles; ++i) {
338 atomic_set(&adev->uvd.handles[i], 0);
339 adev->uvd.filp[i] = NULL;
340 }
341
342 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
343 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
344 adev->uvd.address_64_bit = true;
345
346 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
347 if (r)
348 return r;
349
350 switch (adev->asic_type) {
351 case CHIP_TONGA:
352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
353 break;
354 case CHIP_CARRIZO:
355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
356 break;
357 case CHIP_FIJI:
358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
359 break;
360 case CHIP_STONEY:
361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
362 break;
363 default:
364 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
365 }
366
367 return 0;
368}
369
370int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
371{
372 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
373 int i, j;
374
375 drm_sched_entity_destroy(&adev->uvd.entity);
376
377 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
378 if (adev->uvd.harvest_config & (1 << j))
379 continue;
380 kvfree(adev->uvd.inst[j].saved_bo);
381
382 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
383 &adev->uvd.inst[j].gpu_addr,
384 (void **)&adev->uvd.inst[j].cpu_addr);
385
386 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
387
388 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
390 }
391 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
392 amdgpu_ucode_release(&adev->uvd.fw);
393
394 return 0;
395}
396
397/**
398 * amdgpu_uvd_entity_init - init entity
399 *
400 * @adev: amdgpu_device pointer
401 * @ring: amdgpu_ring pointer to check
402 *
403 * Initialize the entity used for handle management in the kernel driver.
404 */
405int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)
406{
407 if (ring == &adev->uvd.inst[0].ring) {
408 struct drm_gpu_scheduler *sched = &ring->sched;
409 int r;
410
411 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
412 &sched, 1, NULL);
413 if (r) {
414 DRM_ERROR("Failed setting up UVD kernel entity.\n");
415 return r;
416 }
417 }
418
419 return 0;
420}
421
422int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev)
423{
424 unsigned int size;
425 void *ptr;
426 int i, j, idx;
427
428 cancel_delayed_work_sync(&adev->uvd.idle_work);
429
430 /* only valid for physical mode */
431 if (adev->asic_type < CHIP_POLARIS10) {
432 for (i = 0; i < adev->uvd.max_handles; ++i)
433 if (atomic_read(&adev->uvd.handles[i]))
434 break;
435
436 if (i == adev->uvd.max_handles)
437 return 0;
438 }
439
440 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
441 if (adev->uvd.harvest_config & (1 << j))
442 continue;
443 if (adev->uvd.inst[j].vcpu_bo == NULL)
444 continue;
445
446 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
447 ptr = adev->uvd.inst[j].cpu_addr;
448
449 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
450 if (!adev->uvd.inst[j].saved_bo)
451 return -ENOMEM;
452
453 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
454 /* re-write 0 since err_event_athub will corrupt VCPU buffer */
455 if (amdgpu_ras_intr_triggered())
456 memset(adev->uvd.inst[j].saved_bo, 0, size);
457 else
458 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
459
460 drm_dev_exit(idx);
461 }
462 }
463
464 return 0;
465}
466
467int amdgpu_uvd_suspend(struct amdgpu_device *adev)
468{
469 if (amdgpu_ras_intr_triggered())
470 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
471
472 return 0;
473}
474
475int amdgpu_uvd_resume(struct amdgpu_device *adev)
476{
477 unsigned int size;
478 void *ptr;
479 int i, idx;
480
481 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
482 if (adev->uvd.harvest_config & (1 << i))
483 continue;
484 if (adev->uvd.inst[i].vcpu_bo == NULL)
485 return -EINVAL;
486
487 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
488 ptr = adev->uvd.inst[i].cpu_addr;
489
490 if (adev->uvd.inst[i].saved_bo != NULL) {
491 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
492 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
493 drm_dev_exit(idx);
494 }
495 kvfree(adev->uvd.inst[i].saved_bo);
496 adev->uvd.inst[i].saved_bo = NULL;
497 } else {
498 const struct common_firmware_header *hdr;
499 unsigned int offset;
500
501 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
502 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
503 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
504 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
505 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
506 le32_to_cpu(hdr->ucode_size_bytes));
507 drm_dev_exit(idx);
508 }
509 size -= le32_to_cpu(hdr->ucode_size_bytes);
510 ptr += le32_to_cpu(hdr->ucode_size_bytes);
511 }
512 memset_io(ptr, 0, size);
513 /* to restore uvd fence seq */
514 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
515 }
516 }
517 return 0;
518}
519
520void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
521{
522 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
523 int i, r;
524
525 for (i = 0; i < adev->uvd.max_handles; ++i) {
526 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
527
528 if (handle != 0 && adev->uvd.filp[i] == filp) {
529 struct dma_fence *fence;
530
531 r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
532 &fence);
533 if (r) {
534 DRM_ERROR("Error destroying UVD %d!\n", r);
535 continue;
536 }
537
538 dma_fence_wait(fence, false);
539 dma_fence_put(fence);
540
541 adev->uvd.filp[i] = NULL;
542 atomic_set(&adev->uvd.handles[i], 0);
543 }
544 }
545}
546
547static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
548{
549 int i;
550
551 for (i = 0; i < abo->placement.num_placement; ++i) {
552 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
553 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
554 if (abo->placements[i].mem_type == TTM_PL_VRAM)
555 abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
556 }
557}
558
559static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
560{
561 uint32_t lo, hi;
562 uint64_t addr;
563
564 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0);
565 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1);
566 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
567
568 return addr;
569}
570
571/**
572 * amdgpu_uvd_cs_pass1 - first parsing round
573 *
574 * @ctx: UVD parser context
575 *
576 * Make sure UVD message and feedback buffers are in VRAM and
577 * nobody is violating an 256MB boundary.
578 */
579static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
580{
581 struct ttm_operation_ctx tctx = { false, false };
582 struct amdgpu_bo_va_mapping *mapping;
583 struct amdgpu_bo *bo;
584 uint32_t cmd;
585 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
586 int r = 0;
587
588 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
589 if (r) {
590 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
591 return r;
592 }
593
594 if (!ctx->parser->adev->uvd.address_64_bit) {
595 /* check if it's a message or feedback command */
596 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
597 if (cmd == 0x0 || cmd == 0x3) {
598 /* yes, force it into VRAM */
599 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
600
601 amdgpu_bo_placement_from_domain(bo, domain);
602 }
603 amdgpu_uvd_force_into_uvd_segment(bo);
604
605 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
606 }
607
608 return r;
609}
610
611/**
612 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
613 *
614 * @adev: amdgpu_device pointer
615 * @msg: pointer to message structure
616 * @buf_sizes: placeholder to put the different buffer lengths
617 *
618 * Peek into the decode message and calculate the necessary buffer sizes.
619 */
620static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
621 unsigned int buf_sizes[])
622{
623 unsigned int stream_type = msg[4];
624 unsigned int width = msg[6];
625 unsigned int height = msg[7];
626 unsigned int dpb_size = msg[9];
627 unsigned int pitch = msg[28];
628 unsigned int level = msg[57];
629
630 unsigned int width_in_mb = width / 16;
631 unsigned int height_in_mb = ALIGN(height / 16, 2);
632 unsigned int fs_in_mb = width_in_mb * height_in_mb;
633
634 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer;
635 unsigned int min_ctx_size = ~0;
636
637 image_size = width * height;
638 image_size += image_size / 2;
639 image_size = ALIGN(image_size, 1024);
640
641 switch (stream_type) {
642 case 0: /* H264 */
643 switch (level) {
644 case 30:
645 num_dpb_buffer = 8100 / fs_in_mb;
646 break;
647 case 31:
648 num_dpb_buffer = 18000 / fs_in_mb;
649 break;
650 case 32:
651 num_dpb_buffer = 20480 / fs_in_mb;
652 break;
653 case 41:
654 num_dpb_buffer = 32768 / fs_in_mb;
655 break;
656 case 42:
657 num_dpb_buffer = 34816 / fs_in_mb;
658 break;
659 case 50:
660 num_dpb_buffer = 110400 / fs_in_mb;
661 break;
662 case 51:
663 num_dpb_buffer = 184320 / fs_in_mb;
664 break;
665 default:
666 num_dpb_buffer = 184320 / fs_in_mb;
667 break;
668 }
669 num_dpb_buffer++;
670 if (num_dpb_buffer > 17)
671 num_dpb_buffer = 17;
672
673 /* reference picture buffer */
674 min_dpb_size = image_size * num_dpb_buffer;
675
676 /* macroblock context buffer */
677 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
678
679 /* IT surface buffer */
680 min_dpb_size += width_in_mb * height_in_mb * 32;
681 break;
682
683 case 1: /* VC1 */
684
685 /* reference picture buffer */
686 min_dpb_size = image_size * 3;
687
688 /* CONTEXT_BUFFER */
689 min_dpb_size += width_in_mb * height_in_mb * 128;
690
691 /* IT surface buffer */
692 min_dpb_size += width_in_mb * 64;
693
694 /* DB surface buffer */
695 min_dpb_size += width_in_mb * 128;
696
697 /* BP */
698 tmp = max(width_in_mb, height_in_mb);
699 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
700 break;
701
702 case 3: /* MPEG2 */
703
704 /* reference picture buffer */
705 min_dpb_size = image_size * 3;
706 break;
707
708 case 4: /* MPEG4 */
709
710 /* reference picture buffer */
711 min_dpb_size = image_size * 3;
712
713 /* CM */
714 min_dpb_size += width_in_mb * height_in_mb * 64;
715
716 /* IT surface buffer */
717 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
718 break;
719
720 case 7: /* H264 Perf */
721 switch (level) {
722 case 30:
723 num_dpb_buffer = 8100 / fs_in_mb;
724 break;
725 case 31:
726 num_dpb_buffer = 18000 / fs_in_mb;
727 break;
728 case 32:
729 num_dpb_buffer = 20480 / fs_in_mb;
730 break;
731 case 41:
732 num_dpb_buffer = 32768 / fs_in_mb;
733 break;
734 case 42:
735 num_dpb_buffer = 34816 / fs_in_mb;
736 break;
737 case 50:
738 num_dpb_buffer = 110400 / fs_in_mb;
739 break;
740 case 51:
741 num_dpb_buffer = 184320 / fs_in_mb;
742 break;
743 default:
744 num_dpb_buffer = 184320 / fs_in_mb;
745 break;
746 }
747 num_dpb_buffer++;
748 if (num_dpb_buffer > 17)
749 num_dpb_buffer = 17;
750
751 /* reference picture buffer */
752 min_dpb_size = image_size * num_dpb_buffer;
753
754 if (!adev->uvd.use_ctx_buf) {
755 /* macroblock context buffer */
756 min_dpb_size +=
757 width_in_mb * height_in_mb * num_dpb_buffer * 192;
758
759 /* IT surface buffer */
760 min_dpb_size += width_in_mb * height_in_mb * 32;
761 } else {
762 /* macroblock context buffer */
763 min_ctx_size =
764 width_in_mb * height_in_mb * num_dpb_buffer * 192;
765 }
766 break;
767
768 case 8: /* MJPEG */
769 min_dpb_size = 0;
770 break;
771
772 case 16: /* H265 */
773 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
774 image_size = ALIGN(image_size, 256);
775
776 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
777 min_dpb_size = image_size * num_dpb_buffer;
778 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
779 * 16 * num_dpb_buffer + 52 * 1024;
780 break;
781
782 default:
783 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
784 return -EINVAL;
785 }
786
787 if (width > pitch) {
788 DRM_ERROR("Invalid UVD decoding target pitch!\n");
789 return -EINVAL;
790 }
791
792 if (dpb_size < min_dpb_size) {
793 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
794 dpb_size, min_dpb_size);
795 return -EINVAL;
796 }
797
798 buf_sizes[0x1] = dpb_size;
799 buf_sizes[0x2] = image_size;
800 buf_sizes[0x4] = min_ctx_size;
801 /* store image width to adjust nb memory pstate */
802 adev->uvd.decode_image_width = width;
803 return 0;
804}
805
806/**
807 * amdgpu_uvd_cs_msg - handle UVD message
808 *
809 * @ctx: UVD parser context
810 * @bo: buffer object containing the message
811 * @offset: offset into the buffer object
812 *
813 * Peek into the UVD message and extract the session id.
814 * Make sure that we don't open up to many sessions.
815 */
816static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
817 struct amdgpu_bo *bo, unsigned int offset)
818{
819 struct amdgpu_device *adev = ctx->parser->adev;
820 int32_t *msg, msg_type, handle;
821 void *ptr;
822 long r;
823 int i;
824
825 if (offset & 0x3F) {
826 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
827 return -EINVAL;
828 }
829
830 r = amdgpu_bo_kmap(bo, &ptr);
831 if (r) {
832 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
833 return r;
834 }
835
836 msg = ptr + offset;
837
838 msg_type = msg[1];
839 handle = msg[2];
840
841 if (handle == 0) {
842 amdgpu_bo_kunmap(bo);
843 DRM_ERROR("Invalid UVD handle!\n");
844 return -EINVAL;
845 }
846
847 switch (msg_type) {
848 case 0:
849 /* it's a create msg, calc image size (width * height) */
850 amdgpu_bo_kunmap(bo);
851
852 /* try to alloc a new handle */
853 for (i = 0; i < adev->uvd.max_handles; ++i) {
854 if (atomic_read(&adev->uvd.handles[i]) == handle) {
855 DRM_ERROR(")Handle 0x%x already in use!\n",
856 handle);
857 return -EINVAL;
858 }
859
860 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
861 adev->uvd.filp[i] = ctx->parser->filp;
862 return 0;
863 }
864 }
865
866 DRM_ERROR("No more free UVD handles!\n");
867 return -ENOSPC;
868
869 case 1:
870 /* it's a decode msg, calc buffer sizes */
871 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
872 amdgpu_bo_kunmap(bo);
873 if (r)
874 return r;
875
876 /* validate the handle */
877 for (i = 0; i < adev->uvd.max_handles; ++i) {
878 if (atomic_read(&adev->uvd.handles[i]) == handle) {
879 if (adev->uvd.filp[i] != ctx->parser->filp) {
880 DRM_ERROR("UVD handle collision detected!\n");
881 return -EINVAL;
882 }
883 return 0;
884 }
885 }
886
887 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
888 return -ENOENT;
889
890 case 2:
891 /* it's a destroy msg, free the handle */
892 for (i = 0; i < adev->uvd.max_handles; ++i)
893 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
894 amdgpu_bo_kunmap(bo);
895 return 0;
896
897 default:
898 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
899 }
900
901 amdgpu_bo_kunmap(bo);
902 return -EINVAL;
903}
904
905/**
906 * amdgpu_uvd_cs_pass2 - second parsing round
907 *
908 * @ctx: UVD parser context
909 *
910 * Patch buffer addresses, make sure buffer sizes are correct.
911 */
912static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
913{
914 struct amdgpu_bo_va_mapping *mapping;
915 struct amdgpu_bo *bo;
916 uint32_t cmd;
917 uint64_t start, end;
918 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
919 int r;
920
921 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
922 if (r) {
923 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
924 return r;
925 }
926
927 start = amdgpu_bo_gpu_offset(bo);
928
929 end = (mapping->last + 1 - mapping->start);
930 end = end * AMDGPU_GPU_PAGE_SIZE + start;
931
932 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
933 start += addr;
934
935 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start));
936 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start));
937
938 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
939 if (cmd < 0x4) {
940 if ((end - start) < ctx->buf_sizes[cmd]) {
941 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
942 (unsigned int)(end - start),
943 ctx->buf_sizes[cmd]);
944 return -EINVAL;
945 }
946
947 } else if (cmd == 0x206) {
948 if ((end - start) < ctx->buf_sizes[4]) {
949 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
950 (unsigned int)(end - start),
951 ctx->buf_sizes[4]);
952 return -EINVAL;
953 }
954 } else if ((cmd != 0x100) && (cmd != 0x204)) {
955 DRM_ERROR("invalid UVD command %X!\n", cmd);
956 return -EINVAL;
957 }
958
959 if (!ctx->parser->adev->uvd.address_64_bit) {
960 if ((start >> 28) != ((end - 1) >> 28)) {
961 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n",
962 start, end);
963 return -EINVAL;
964 }
965
966 if ((cmd == 0 || cmd == 0x3) &&
967 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
968 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n",
969 start, end);
970 return -EINVAL;
971 }
972 }
973
974 if (cmd == 0) {
975 ctx->has_msg_cmd = true;
976 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
977 if (r)
978 return r;
979 } else if (!ctx->has_msg_cmd) {
980 DRM_ERROR("Message needed before other commands are send!\n");
981 return -EINVAL;
982 }
983
984 return 0;
985}
986
987/**
988 * amdgpu_uvd_cs_reg - parse register writes
989 *
990 * @ctx: UVD parser context
991 * @cb: callback function
992 *
993 * Parse the register writes, call cb on each complete command.
994 */
995static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
996 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
997{
998 int i, r;
999
1000 ctx->idx++;
1001 for (i = 0; i <= ctx->count; ++i) {
1002 unsigned int reg = ctx->reg + i;
1003
1004 if (ctx->idx >= ctx->ib->length_dw) {
1005 DRM_ERROR("Register command after end of CS!\n");
1006 return -EINVAL;
1007 }
1008
1009 switch (reg) {
1010 case mmUVD_GPCOM_VCPU_DATA0:
1011 ctx->data0 = ctx->idx;
1012 break;
1013 case mmUVD_GPCOM_VCPU_DATA1:
1014 ctx->data1 = ctx->idx;
1015 break;
1016 case mmUVD_GPCOM_VCPU_CMD:
1017 r = cb(ctx);
1018 if (r)
1019 return r;
1020 break;
1021 case mmUVD_ENGINE_CNTL:
1022 case mmUVD_NO_OP:
1023 break;
1024 default:
1025 DRM_ERROR("Invalid reg 0x%X!\n", reg);
1026 return -EINVAL;
1027 }
1028 ctx->idx++;
1029 }
1030 return 0;
1031}
1032
1033/**
1034 * amdgpu_uvd_cs_packets - parse UVD packets
1035 *
1036 * @ctx: UVD parser context
1037 * @cb: callback function
1038 *
1039 * Parse the command stream packets.
1040 */
1041static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
1042 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
1043{
1044 int r;
1045
1046 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) {
1047 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx);
1048 unsigned int type = CP_PACKET_GET_TYPE(cmd);
1049
1050 switch (type) {
1051 case PACKET_TYPE0:
1052 ctx->reg = CP_PACKET0_GET_REG(cmd);
1053 ctx->count = CP_PACKET_GET_COUNT(cmd);
1054 r = amdgpu_uvd_cs_reg(ctx, cb);
1055 if (r)
1056 return r;
1057 break;
1058 case PACKET_TYPE2:
1059 ++ctx->idx;
1060 break;
1061 default:
1062 DRM_ERROR("Unknown packet type %d !\n", type);
1063 return -EINVAL;
1064 }
1065 }
1066 return 0;
1067}
1068
1069/**
1070 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
1071 *
1072 * @parser: Command submission parser context
1073 * @job: the job to parse
1074 * @ib: the IB to patch
1075 *
1076 * Parse the command stream, patch in addresses as necessary.
1077 */
1078int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,
1079 struct amdgpu_job *job,
1080 struct amdgpu_ib *ib)
1081{
1082 struct amdgpu_uvd_cs_ctx ctx = {};
1083 unsigned int buf_sizes[] = {
1084 [0x00000000] = 2048,
1085 [0x00000001] = 0xFFFFFFFF,
1086 [0x00000002] = 0xFFFFFFFF,
1087 [0x00000003] = 2048,
1088 [0x00000004] = 0xFFFFFFFF,
1089 };
1090 int r;
1091
1092 job->vm = NULL;
1093
1094 if (ib->length_dw % 16) {
1095 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
1096 ib->length_dw);
1097 return -EINVAL;
1098 }
1099
1100 ctx.parser = parser;
1101 ctx.buf_sizes = buf_sizes;
1102 ctx.ib = ib;
1103
1104 /* first round only required on chips without UVD 64 bit address support */
1105 if (!parser->adev->uvd.address_64_bit) {
1106 /* first round, make sure the buffers are actually in the UVD segment */
1107 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
1108 if (r)
1109 return r;
1110 }
1111
1112 /* second round, patch buffer addresses into the command stream */
1113 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
1114 if (r)
1115 return r;
1116
1117 if (!ctx.has_msg_cmd) {
1118 DRM_ERROR("UVD-IBs need a msg command!\n");
1119 return -EINVAL;
1120 }
1121
1122 return 0;
1123}
1124
1125static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1126 bool direct, struct dma_fence **fence)
1127{
1128 struct amdgpu_device *adev = ring->adev;
1129 struct dma_fence *f = NULL;
1130 uint32_t offset, data[4];
1131 struct amdgpu_job *job;
1132 struct amdgpu_ib *ib;
1133 uint64_t addr;
1134 int i, r;
1135
1136 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,
1137 AMDGPU_FENCE_OWNER_UNDEFINED,
1138 64, direct ? AMDGPU_IB_POOL_DIRECT :
1139 AMDGPU_IB_POOL_DELAYED, &job);
1140 if (r)
1141 return r;
1142
1143 if (adev->asic_type >= CHIP_VEGA10)
1144 offset = adev->reg_offset[UVD_HWIP][ring->me][1];
1145 else
1146 offset = UVD_BASE_SI;
1147
1148 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0);
1149 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0);
1150 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0);
1151 data[3] = PACKET0(offset + UVD_NO_OP, 0);
1152
1153 ib = &job->ibs[0];
1154 addr = amdgpu_bo_gpu_offset(bo);
1155 ib->ptr[0] = data[0];
1156 ib->ptr[1] = addr;
1157 ib->ptr[2] = data[1];
1158 ib->ptr[3] = addr >> 32;
1159 ib->ptr[4] = data[2];
1160 ib->ptr[5] = 0;
1161 for (i = 6; i < 16; i += 2) {
1162 ib->ptr[i] = data[3];
1163 ib->ptr[i+1] = 0;
1164 }
1165 ib->length_dw = 16;
1166
1167 if (direct) {
1168 r = amdgpu_job_submit_direct(job, ring, &f);
1169 if (r)
1170 goto err_free;
1171 } else {
1172 r = drm_sched_job_add_resv_dependencies(&job->base,
1173 bo->tbo.base.resv,
1174 DMA_RESV_USAGE_KERNEL);
1175 if (r)
1176 goto err_free;
1177
1178 f = amdgpu_job_submit(job);
1179 }
1180
1181 amdgpu_bo_reserve(bo, true);
1182 amdgpu_bo_fence(bo, f, false);
1183 amdgpu_bo_unreserve(bo);
1184
1185 if (fence)
1186 *fence = dma_fence_get(f);
1187 dma_fence_put(f);
1188
1189 return 0;
1190
1191err_free:
1192 amdgpu_job_free(job);
1193 return r;
1194}
1195
1196/* multiple fence commands without any stream commands in between can
1197 * crash the vcpu so just try to emmit a dummy create/destroy msg to
1198 * avoid this
1199 */
1200int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1201 struct dma_fence **fence)
1202{
1203 struct amdgpu_device *adev = ring->adev;
1204 struct amdgpu_bo *bo = adev->uvd.ib_bo;
1205 uint32_t *msg;
1206 int i;
1207
1208 msg = amdgpu_bo_kptr(bo);
1209 /* stitch together an UVD create msg */
1210 msg[0] = cpu_to_le32(0x00000de4);
1211 msg[1] = cpu_to_le32(0x00000000);
1212 msg[2] = cpu_to_le32(handle);
1213 msg[3] = cpu_to_le32(0x00000000);
1214 msg[4] = cpu_to_le32(0x00000000);
1215 msg[5] = cpu_to_le32(0x00000000);
1216 msg[6] = cpu_to_le32(0x00000000);
1217 msg[7] = cpu_to_le32(0x00000780);
1218 msg[8] = cpu_to_le32(0x00000440);
1219 msg[9] = cpu_to_le32(0x00000000);
1220 msg[10] = cpu_to_le32(0x01b37000);
1221 for (i = 11; i < 1024; ++i)
1222 msg[i] = cpu_to_le32(0x0);
1223
1224 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1225
1226}
1227
1228int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1229 bool direct, struct dma_fence **fence)
1230{
1231 struct amdgpu_device *adev = ring->adev;
1232 struct amdgpu_bo *bo = NULL;
1233 uint32_t *msg;
1234 int r, i;
1235
1236 if (direct) {
1237 bo = adev->uvd.ib_bo;
1238 } else {
1239 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
1240 if (r)
1241 return r;
1242 }
1243
1244 msg = amdgpu_bo_kptr(bo);
1245 /* stitch together an UVD destroy msg */
1246 msg[0] = cpu_to_le32(0x00000de4);
1247 msg[1] = cpu_to_le32(0x00000002);
1248 msg[2] = cpu_to_le32(handle);
1249 msg[3] = cpu_to_le32(0x00000000);
1250 for (i = 4; i < 1024; ++i)
1251 msg[i] = cpu_to_le32(0x0);
1252
1253 r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
1254
1255 if (!direct)
1256 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
1257
1258 return r;
1259}
1260
1261static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1262{
1263 struct amdgpu_device *adev =
1264 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1265 unsigned int fences = 0, i, j;
1266
1267 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1268 if (adev->uvd.harvest_config & (1 << i))
1269 continue;
1270 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1271 for (j = 0; j < adev->uvd.num_enc_rings; ++j)
1272 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1273 }
1274
1275 if (fences == 0) {
1276 if (adev->pm.dpm_enabled) {
1277 amdgpu_dpm_enable_uvd(adev, false);
1278 } else {
1279 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1280 /* shutdown the UVD block */
1281 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1282 AMD_PG_STATE_GATE);
1283 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1284 AMD_CG_STATE_GATE);
1285 }
1286 } else {
1287 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1288 }
1289}
1290
1291void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1292{
1293 struct amdgpu_device *adev = ring->adev;
1294 bool set_clocks;
1295
1296 if (amdgpu_sriov_vf(adev))
1297 return;
1298
1299 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1300 if (set_clocks) {
1301 if (adev->pm.dpm_enabled) {
1302 amdgpu_dpm_enable_uvd(adev, true);
1303 } else {
1304 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1305 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1306 AMD_CG_STATE_UNGATE);
1307 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1308 AMD_PG_STATE_UNGATE);
1309 }
1310 }
1311}
1312
1313void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1314{
1315 if (!amdgpu_sriov_vf(ring->adev))
1316 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1317}
1318
1319/**
1320 * amdgpu_uvd_ring_test_ib - test ib execution
1321 *
1322 * @ring: amdgpu_ring pointer
1323 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1324 *
1325 * Test if we can successfully execute an IB
1326 */
1327int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1328{
1329 struct dma_fence *fence;
1330 long r;
1331
1332 r = amdgpu_uvd_get_create_msg(ring, 1, &fence);
1333 if (r)
1334 goto error;
1335
1336 r = dma_fence_wait_timeout(fence, false, timeout);
1337 dma_fence_put(fence);
1338 if (r == 0)
1339 r = -ETIMEDOUT;
1340 if (r < 0)
1341 goto error;
1342
1343 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1344 if (r)
1345 goto error;
1346
1347 r = dma_fence_wait_timeout(fence, false, timeout);
1348 if (r == 0)
1349 r = -ETIMEDOUT;
1350 else if (r > 0)
1351 r = 0;
1352
1353 dma_fence_put(fence);
1354
1355error:
1356 return r;
1357}
1358
1359/**
1360 * amdgpu_uvd_used_handles - returns used UVD handles
1361 *
1362 * @adev: amdgpu_device pointer
1363 *
1364 * Returns the number of UVD handles in use
1365 */
1366uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1367{
1368 unsigned int i;
1369 uint32_t used_handles = 0;
1370
1371 for (i = 0; i < adev->uvd.max_handles; ++i) {
1372 /*
1373 * Handles can be freed in any order, and not
1374 * necessarily linear. So we need to count
1375 * all non-zero handles.
1376 */
1377 if (atomic_read(&adev->uvd.handles[i]))
1378 used_handles++;
1379 }
1380
1381 return used_handles;
1382}
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "amdgpu.h"
37#include "amdgpu_pm.h"
38#include "amdgpu_uvd.h"
39#include "cikd.h"
40#include "uvd/uvd_4_2_d.h"
41
42/* 1 second timeout */
43#define UVD_IDLE_TIMEOUT_MS 1000
44
45/* Firmware Names */
46#ifdef CONFIG_DRM_AMDGPU_CIK
47#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48#define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51#define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
52#endif
53#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
55#define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
56#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
57
58/**
59 * amdgpu_uvd_cs_ctx - Command submission parser context
60 *
61 * Used for emulating virtual memory support on UVD 4.2.
62 */
63struct amdgpu_uvd_cs_ctx {
64 struct amdgpu_cs_parser *parser;
65 unsigned reg, count;
66 unsigned data0, data1;
67 unsigned idx;
68 unsigned ib_idx;
69
70 /* does the IB has a msg command */
71 bool has_msg_cmd;
72
73 /* minimum buffer sizes */
74 unsigned *buf_sizes;
75};
76
77#ifdef CONFIG_DRM_AMDGPU_CIK
78MODULE_FIRMWARE(FIRMWARE_BONAIRE);
79MODULE_FIRMWARE(FIRMWARE_KABINI);
80MODULE_FIRMWARE(FIRMWARE_KAVERI);
81MODULE_FIRMWARE(FIRMWARE_HAWAII);
82MODULE_FIRMWARE(FIRMWARE_MULLINS);
83#endif
84MODULE_FIRMWARE(FIRMWARE_TONGA);
85MODULE_FIRMWARE(FIRMWARE_CARRIZO);
86MODULE_FIRMWARE(FIRMWARE_FIJI);
87MODULE_FIRMWARE(FIRMWARE_STONEY);
88
89static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
90static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
91
92int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
93{
94 struct amdgpu_ring *ring;
95 struct amd_sched_rq *rq;
96 unsigned long bo_size;
97 const char *fw_name;
98 const struct common_firmware_header *hdr;
99 unsigned version_major, version_minor, family_id;
100 int i, r;
101
102 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
103
104 switch (adev->asic_type) {
105#ifdef CONFIG_DRM_AMDGPU_CIK
106 case CHIP_BONAIRE:
107 fw_name = FIRMWARE_BONAIRE;
108 break;
109 case CHIP_KABINI:
110 fw_name = FIRMWARE_KABINI;
111 break;
112 case CHIP_KAVERI:
113 fw_name = FIRMWARE_KAVERI;
114 break;
115 case CHIP_HAWAII:
116 fw_name = FIRMWARE_HAWAII;
117 break;
118 case CHIP_MULLINS:
119 fw_name = FIRMWARE_MULLINS;
120 break;
121#endif
122 case CHIP_TONGA:
123 fw_name = FIRMWARE_TONGA;
124 break;
125 case CHIP_FIJI:
126 fw_name = FIRMWARE_FIJI;
127 break;
128 case CHIP_CARRIZO:
129 fw_name = FIRMWARE_CARRIZO;
130 break;
131 case CHIP_STONEY:
132 fw_name = FIRMWARE_STONEY;
133 break;
134 default:
135 return -EINVAL;
136 }
137
138 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
139 if (r) {
140 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
141 fw_name);
142 return r;
143 }
144
145 r = amdgpu_ucode_validate(adev->uvd.fw);
146 if (r) {
147 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
148 fw_name);
149 release_firmware(adev->uvd.fw);
150 adev->uvd.fw = NULL;
151 return r;
152 }
153
154 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
155 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
156 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
157 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
159 version_major, version_minor, family_id);
160
161 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
162 (family_id << 8));
163
164 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
165 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
166 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
167 AMDGPU_GEM_DOMAIN_VRAM,
168 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
169 NULL, NULL, &adev->uvd.vcpu_bo);
170 if (r) {
171 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
172 return r;
173 }
174
175 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
176 if (r) {
177 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
178 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
179 return r;
180 }
181
182 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
183 &adev->uvd.gpu_addr);
184 if (r) {
185 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
186 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
187 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
188 return r;
189 }
190
191 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
192 if (r) {
193 dev_err(adev->dev, "(%d) UVD map failed\n", r);
194 return r;
195 }
196
197 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
198
199 ring = &adev->uvd.ring;
200 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
201 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
202 rq, amdgpu_sched_jobs);
203 if (r != 0) {
204 DRM_ERROR("Failed setting up UVD run queue.\n");
205 return r;
206 }
207
208 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
209 atomic_set(&adev->uvd.handles[i], 0);
210 adev->uvd.filp[i] = NULL;
211 }
212
213 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
214 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
215 adev->uvd.address_64_bit = true;
216
217 return 0;
218}
219
220int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
221{
222 int r;
223
224 if (adev->uvd.vcpu_bo == NULL)
225 return 0;
226
227 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
228
229 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
230 if (!r) {
231 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
232 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
233 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
234 }
235
236 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
237
238 amdgpu_ring_fini(&adev->uvd.ring);
239
240 release_firmware(adev->uvd.fw);
241
242 return 0;
243}
244
245int amdgpu_uvd_suspend(struct amdgpu_device *adev)
246{
247 unsigned size;
248 void *ptr;
249 int i;
250
251 if (adev->uvd.vcpu_bo == NULL)
252 return 0;
253
254 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
255 if (atomic_read(&adev->uvd.handles[i]))
256 break;
257
258 if (i == AMDGPU_MAX_UVD_HANDLES)
259 return 0;
260
261 cancel_delayed_work_sync(&adev->uvd.idle_work);
262
263 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
264 ptr = adev->uvd.cpu_addr;
265
266 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
267 if (!adev->uvd.saved_bo)
268 return -ENOMEM;
269
270 memcpy(adev->uvd.saved_bo, ptr, size);
271
272 return 0;
273}
274
275int amdgpu_uvd_resume(struct amdgpu_device *adev)
276{
277 unsigned size;
278 void *ptr;
279
280 if (adev->uvd.vcpu_bo == NULL)
281 return -EINVAL;
282
283 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
284 ptr = adev->uvd.cpu_addr;
285
286 if (adev->uvd.saved_bo != NULL) {
287 memcpy(ptr, adev->uvd.saved_bo, size);
288 kfree(adev->uvd.saved_bo);
289 adev->uvd.saved_bo = NULL;
290 } else {
291 const struct common_firmware_header *hdr;
292 unsigned offset;
293
294 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
295 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
296 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
297 (adev->uvd.fw->size) - offset);
298 size -= le32_to_cpu(hdr->ucode_size_bytes);
299 ptr += le32_to_cpu(hdr->ucode_size_bytes);
300 memset(ptr, 0, size);
301 }
302
303 return 0;
304}
305
306void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
307{
308 struct amdgpu_ring *ring = &adev->uvd.ring;
309 int i, r;
310
311 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
312 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
313 if (handle != 0 && adev->uvd.filp[i] == filp) {
314 struct fence *fence;
315
316 amdgpu_uvd_note_usage(adev);
317
318 r = amdgpu_uvd_get_destroy_msg(ring, handle,
319 false, &fence);
320 if (r) {
321 DRM_ERROR("Error destroying UVD (%d)!\n", r);
322 continue;
323 }
324
325 fence_wait(fence, false);
326 fence_put(fence);
327
328 adev->uvd.filp[i] = NULL;
329 atomic_set(&adev->uvd.handles[i], 0);
330 }
331 }
332}
333
334static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
335{
336 int i;
337 for (i = 0; i < rbo->placement.num_placement; ++i) {
338 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
339 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
340 }
341}
342
343/**
344 * amdgpu_uvd_cs_pass1 - first parsing round
345 *
346 * @ctx: UVD parser context
347 *
348 * Make sure UVD message and feedback buffers are in VRAM and
349 * nobody is violating an 256MB boundary.
350 */
351static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
352{
353 struct amdgpu_bo_va_mapping *mapping;
354 struct amdgpu_bo *bo;
355 uint32_t cmd, lo, hi;
356 uint64_t addr;
357 int r = 0;
358
359 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
360 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
361 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
362
363 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
364 if (mapping == NULL) {
365 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
366 return -EINVAL;
367 }
368
369 if (!ctx->parser->adev->uvd.address_64_bit) {
370 /* check if it's a message or feedback command */
371 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
372 if (cmd == 0x0 || cmd == 0x3) {
373 /* yes, force it into VRAM */
374 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
375 amdgpu_ttm_placement_from_domain(bo, domain);
376 }
377 amdgpu_uvd_force_into_uvd_segment(bo);
378
379 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
380 }
381
382 return r;
383}
384
385/**
386 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
387 *
388 * @msg: pointer to message structure
389 * @buf_sizes: returned buffer sizes
390 *
391 * Peek into the decode message and calculate the necessary buffer sizes.
392 */
393static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
394{
395 unsigned stream_type = msg[4];
396 unsigned width = msg[6];
397 unsigned height = msg[7];
398 unsigned dpb_size = msg[9];
399 unsigned pitch = msg[28];
400 unsigned level = msg[57];
401
402 unsigned width_in_mb = width / 16;
403 unsigned height_in_mb = ALIGN(height / 16, 2);
404 unsigned fs_in_mb = width_in_mb * height_in_mb;
405
406 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
407 unsigned min_ctx_size = 0;
408
409 image_size = width * height;
410 image_size += image_size / 2;
411 image_size = ALIGN(image_size, 1024);
412
413 switch (stream_type) {
414 case 0: /* H264 */
415 case 7: /* H264 Perf */
416 switch(level) {
417 case 30:
418 num_dpb_buffer = 8100 / fs_in_mb;
419 break;
420 case 31:
421 num_dpb_buffer = 18000 / fs_in_mb;
422 break;
423 case 32:
424 num_dpb_buffer = 20480 / fs_in_mb;
425 break;
426 case 41:
427 num_dpb_buffer = 32768 / fs_in_mb;
428 break;
429 case 42:
430 num_dpb_buffer = 34816 / fs_in_mb;
431 break;
432 case 50:
433 num_dpb_buffer = 110400 / fs_in_mb;
434 break;
435 case 51:
436 num_dpb_buffer = 184320 / fs_in_mb;
437 break;
438 default:
439 num_dpb_buffer = 184320 / fs_in_mb;
440 break;
441 }
442 num_dpb_buffer++;
443 if (num_dpb_buffer > 17)
444 num_dpb_buffer = 17;
445
446 /* reference picture buffer */
447 min_dpb_size = image_size * num_dpb_buffer;
448
449 /* macroblock context buffer */
450 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
451
452 /* IT surface buffer */
453 min_dpb_size += width_in_mb * height_in_mb * 32;
454 break;
455
456 case 1: /* VC1 */
457
458 /* reference picture buffer */
459 min_dpb_size = image_size * 3;
460
461 /* CONTEXT_BUFFER */
462 min_dpb_size += width_in_mb * height_in_mb * 128;
463
464 /* IT surface buffer */
465 min_dpb_size += width_in_mb * 64;
466
467 /* DB surface buffer */
468 min_dpb_size += width_in_mb * 128;
469
470 /* BP */
471 tmp = max(width_in_mb, height_in_mb);
472 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
473 break;
474
475 case 3: /* MPEG2 */
476
477 /* reference picture buffer */
478 min_dpb_size = image_size * 3;
479 break;
480
481 case 4: /* MPEG4 */
482
483 /* reference picture buffer */
484 min_dpb_size = image_size * 3;
485
486 /* CM */
487 min_dpb_size += width_in_mb * height_in_mb * 64;
488
489 /* IT surface buffer */
490 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
491 break;
492
493 case 16: /* H265 */
494 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
495 image_size = ALIGN(image_size, 256);
496
497 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
498 min_dpb_size = image_size * num_dpb_buffer;
499 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
500 * 16 * num_dpb_buffer + 52 * 1024;
501 break;
502
503 default:
504 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
505 return -EINVAL;
506 }
507
508 if (width > pitch) {
509 DRM_ERROR("Invalid UVD decoding target pitch!\n");
510 return -EINVAL;
511 }
512
513 if (dpb_size < min_dpb_size) {
514 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
515 dpb_size, min_dpb_size);
516 return -EINVAL;
517 }
518
519 buf_sizes[0x1] = dpb_size;
520 buf_sizes[0x2] = image_size;
521 buf_sizes[0x4] = min_ctx_size;
522 return 0;
523}
524
525/**
526 * amdgpu_uvd_cs_msg - handle UVD message
527 *
528 * @ctx: UVD parser context
529 * @bo: buffer object containing the message
530 * @offset: offset into the buffer object
531 *
532 * Peek into the UVD message and extract the session id.
533 * Make sure that we don't open up to many sessions.
534 */
535static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
536 struct amdgpu_bo *bo, unsigned offset)
537{
538 struct amdgpu_device *adev = ctx->parser->adev;
539 int32_t *msg, msg_type, handle;
540 void *ptr;
541 long r;
542 int i;
543
544 if (offset & 0x3F) {
545 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
546 return -EINVAL;
547 }
548
549 r = amdgpu_bo_kmap(bo, &ptr);
550 if (r) {
551 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
552 return r;
553 }
554
555 msg = ptr + offset;
556
557 msg_type = msg[1];
558 handle = msg[2];
559
560 if (handle == 0) {
561 DRM_ERROR("Invalid UVD handle!\n");
562 return -EINVAL;
563 }
564
565 switch (msg_type) {
566 case 0:
567 /* it's a create msg, calc image size (width * height) */
568 amdgpu_bo_kunmap(bo);
569
570 /* try to alloc a new handle */
571 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
572 if (atomic_read(&adev->uvd.handles[i]) == handle) {
573 DRM_ERROR("Handle 0x%x already in use!\n", handle);
574 return -EINVAL;
575 }
576
577 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
578 adev->uvd.filp[i] = ctx->parser->filp;
579 return 0;
580 }
581 }
582
583 DRM_ERROR("No more free UVD handles!\n");
584 return -EINVAL;
585
586 case 1:
587 /* it's a decode msg, calc buffer sizes */
588 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
589 amdgpu_bo_kunmap(bo);
590 if (r)
591 return r;
592
593 /* validate the handle */
594 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
595 if (atomic_read(&adev->uvd.handles[i]) == handle) {
596 if (adev->uvd.filp[i] != ctx->parser->filp) {
597 DRM_ERROR("UVD handle collision detected!\n");
598 return -EINVAL;
599 }
600 return 0;
601 }
602 }
603
604 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
605 return -ENOENT;
606
607 case 2:
608 /* it's a destroy msg, free the handle */
609 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
610 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
611 amdgpu_bo_kunmap(bo);
612 return 0;
613
614 default:
615 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
616 return -EINVAL;
617 }
618 BUG();
619 return -EINVAL;
620}
621
622/**
623 * amdgpu_uvd_cs_pass2 - second parsing round
624 *
625 * @ctx: UVD parser context
626 *
627 * Patch buffer addresses, make sure buffer sizes are correct.
628 */
629static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
630{
631 struct amdgpu_bo_va_mapping *mapping;
632 struct amdgpu_bo *bo;
633 uint32_t cmd, lo, hi;
634 uint64_t start, end;
635 uint64_t addr;
636 int r;
637
638 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
639 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
640 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
641
642 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
643 if (mapping == NULL)
644 return -EINVAL;
645
646 start = amdgpu_bo_gpu_offset(bo);
647
648 end = (mapping->it.last + 1 - mapping->it.start);
649 end = end * AMDGPU_GPU_PAGE_SIZE + start;
650
651 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
652 start += addr;
653
654 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
655 lower_32_bits(start));
656 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
657 upper_32_bits(start));
658
659 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
660 if (cmd < 0x4) {
661 if ((end - start) < ctx->buf_sizes[cmd]) {
662 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
663 (unsigned)(end - start),
664 ctx->buf_sizes[cmd]);
665 return -EINVAL;
666 }
667
668 } else if (cmd == 0x206) {
669 if ((end - start) < ctx->buf_sizes[4]) {
670 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
671 (unsigned)(end - start),
672 ctx->buf_sizes[4]);
673 return -EINVAL;
674 }
675 } else if ((cmd != 0x100) && (cmd != 0x204)) {
676 DRM_ERROR("invalid UVD command %X!\n", cmd);
677 return -EINVAL;
678 }
679
680 if (!ctx->parser->adev->uvd.address_64_bit) {
681 if ((start >> 28) != ((end - 1) >> 28)) {
682 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
683 start, end);
684 return -EINVAL;
685 }
686
687 if ((cmd == 0 || cmd == 0x3) &&
688 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
689 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
690 start, end);
691 return -EINVAL;
692 }
693 }
694
695 if (cmd == 0) {
696 ctx->has_msg_cmd = true;
697 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
698 if (r)
699 return r;
700 } else if (!ctx->has_msg_cmd) {
701 DRM_ERROR("Message needed before other commands are send!\n");
702 return -EINVAL;
703 }
704
705 return 0;
706}
707
708/**
709 * amdgpu_uvd_cs_reg - parse register writes
710 *
711 * @ctx: UVD parser context
712 * @cb: callback function
713 *
714 * Parse the register writes, call cb on each complete command.
715 */
716static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
717 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
718{
719 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
720 int i, r;
721
722 ctx->idx++;
723 for (i = 0; i <= ctx->count; ++i) {
724 unsigned reg = ctx->reg + i;
725
726 if (ctx->idx >= ib->length_dw) {
727 DRM_ERROR("Register command after end of CS!\n");
728 return -EINVAL;
729 }
730
731 switch (reg) {
732 case mmUVD_GPCOM_VCPU_DATA0:
733 ctx->data0 = ctx->idx;
734 break;
735 case mmUVD_GPCOM_VCPU_DATA1:
736 ctx->data1 = ctx->idx;
737 break;
738 case mmUVD_GPCOM_VCPU_CMD:
739 r = cb(ctx);
740 if (r)
741 return r;
742 break;
743 case mmUVD_ENGINE_CNTL:
744 break;
745 default:
746 DRM_ERROR("Invalid reg 0x%X!\n", reg);
747 return -EINVAL;
748 }
749 ctx->idx++;
750 }
751 return 0;
752}
753
754/**
755 * amdgpu_uvd_cs_packets - parse UVD packets
756 *
757 * @ctx: UVD parser context
758 * @cb: callback function
759 *
760 * Parse the command stream packets.
761 */
762static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
763 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
764{
765 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
766 int r;
767
768 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
769 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
770 unsigned type = CP_PACKET_GET_TYPE(cmd);
771 switch (type) {
772 case PACKET_TYPE0:
773 ctx->reg = CP_PACKET0_GET_REG(cmd);
774 ctx->count = CP_PACKET_GET_COUNT(cmd);
775 r = amdgpu_uvd_cs_reg(ctx, cb);
776 if (r)
777 return r;
778 break;
779 case PACKET_TYPE2:
780 ++ctx->idx;
781 break;
782 default:
783 DRM_ERROR("Unknown packet type %d !\n", type);
784 return -EINVAL;
785 }
786 }
787 return 0;
788}
789
790/**
791 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
792 *
793 * @parser: Command submission parser context
794 *
795 * Parse the command stream, patch in addresses as necessary.
796 */
797int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
798{
799 struct amdgpu_uvd_cs_ctx ctx = {};
800 unsigned buf_sizes[] = {
801 [0x00000000] = 2048,
802 [0x00000001] = 0xFFFFFFFF,
803 [0x00000002] = 0xFFFFFFFF,
804 [0x00000003] = 2048,
805 [0x00000004] = 0xFFFFFFFF,
806 };
807 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
808 int r;
809
810 if (ib->length_dw % 16) {
811 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
812 ib->length_dw);
813 return -EINVAL;
814 }
815
816 ctx.parser = parser;
817 ctx.buf_sizes = buf_sizes;
818 ctx.ib_idx = ib_idx;
819
820 /* first round, make sure the buffers are actually in the UVD segment */
821 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
822 if (r)
823 return r;
824
825 /* second round, patch buffer addresses into the command stream */
826 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
827 if (r)
828 return r;
829
830 if (!ctx.has_msg_cmd) {
831 DRM_ERROR("UVD-IBs need a msg command!\n");
832 return -EINVAL;
833 }
834
835 amdgpu_uvd_note_usage(ctx.parser->adev);
836
837 return 0;
838}
839
840static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
841 bool direct, struct fence **fence)
842{
843 struct ttm_validate_buffer tv;
844 struct ww_acquire_ctx ticket;
845 struct list_head head;
846 struct amdgpu_job *job;
847 struct amdgpu_ib *ib;
848 struct fence *f = NULL;
849 struct amdgpu_device *adev = ring->adev;
850 uint64_t addr;
851 int i, r;
852
853 memset(&tv, 0, sizeof(tv));
854 tv.bo = &bo->tbo;
855
856 INIT_LIST_HEAD(&head);
857 list_add(&tv.head, &head);
858
859 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
860 if (r)
861 return r;
862
863 if (!bo->adev->uvd.address_64_bit) {
864 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
865 amdgpu_uvd_force_into_uvd_segment(bo);
866 }
867
868 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
869 if (r)
870 goto err;
871
872 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
873 if (r)
874 goto err;
875
876 ib = &job->ibs[0];
877 addr = amdgpu_bo_gpu_offset(bo);
878 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
879 ib->ptr[1] = addr;
880 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
881 ib->ptr[3] = addr >> 32;
882 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
883 ib->ptr[5] = 0;
884 for (i = 6; i < 16; ++i)
885 ib->ptr[i] = PACKET2(0);
886 ib->length_dw = 16;
887
888 if (direct) {
889 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
890 job->fence = f;
891 if (r)
892 goto err_free;
893
894 amdgpu_job_free(job);
895 } else {
896 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
897 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
898 if (r)
899 goto err_free;
900 }
901
902 ttm_eu_fence_buffer_objects(&ticket, &head, f);
903
904 if (fence)
905 *fence = fence_get(f);
906 amdgpu_bo_unref(&bo);
907 fence_put(f);
908
909 return 0;
910
911err_free:
912 amdgpu_job_free(job);
913
914err:
915 ttm_eu_backoff_reservation(&ticket, &head);
916 return r;
917}
918
919/* multiple fence commands without any stream commands in between can
920 crash the vcpu so just try to emmit a dummy create/destroy msg to
921 avoid this */
922int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
923 struct fence **fence)
924{
925 struct amdgpu_device *adev = ring->adev;
926 struct amdgpu_bo *bo;
927 uint32_t *msg;
928 int r, i;
929
930 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
931 AMDGPU_GEM_DOMAIN_VRAM,
932 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
933 NULL, NULL, &bo);
934 if (r)
935 return r;
936
937 r = amdgpu_bo_reserve(bo, false);
938 if (r) {
939 amdgpu_bo_unref(&bo);
940 return r;
941 }
942
943 r = amdgpu_bo_kmap(bo, (void **)&msg);
944 if (r) {
945 amdgpu_bo_unreserve(bo);
946 amdgpu_bo_unref(&bo);
947 return r;
948 }
949
950 /* stitch together an UVD create msg */
951 msg[0] = cpu_to_le32(0x00000de4);
952 msg[1] = cpu_to_le32(0x00000000);
953 msg[2] = cpu_to_le32(handle);
954 msg[3] = cpu_to_le32(0x00000000);
955 msg[4] = cpu_to_le32(0x00000000);
956 msg[5] = cpu_to_le32(0x00000000);
957 msg[6] = cpu_to_le32(0x00000000);
958 msg[7] = cpu_to_le32(0x00000780);
959 msg[8] = cpu_to_le32(0x00000440);
960 msg[9] = cpu_to_le32(0x00000000);
961 msg[10] = cpu_to_le32(0x01b37000);
962 for (i = 11; i < 1024; ++i)
963 msg[i] = cpu_to_le32(0x0);
964
965 amdgpu_bo_kunmap(bo);
966 amdgpu_bo_unreserve(bo);
967
968 return amdgpu_uvd_send_msg(ring, bo, true, fence);
969}
970
971int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
972 bool direct, struct fence **fence)
973{
974 struct amdgpu_device *adev = ring->adev;
975 struct amdgpu_bo *bo;
976 uint32_t *msg;
977 int r, i;
978
979 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
980 AMDGPU_GEM_DOMAIN_VRAM,
981 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
982 NULL, NULL, &bo);
983 if (r)
984 return r;
985
986 r = amdgpu_bo_reserve(bo, false);
987 if (r) {
988 amdgpu_bo_unref(&bo);
989 return r;
990 }
991
992 r = amdgpu_bo_kmap(bo, (void **)&msg);
993 if (r) {
994 amdgpu_bo_unreserve(bo);
995 amdgpu_bo_unref(&bo);
996 return r;
997 }
998
999 /* stitch together an UVD destroy msg */
1000 msg[0] = cpu_to_le32(0x00000de4);
1001 msg[1] = cpu_to_le32(0x00000002);
1002 msg[2] = cpu_to_le32(handle);
1003 msg[3] = cpu_to_le32(0x00000000);
1004 for (i = 4; i < 1024; ++i)
1005 msg[i] = cpu_to_le32(0x0);
1006
1007 amdgpu_bo_kunmap(bo);
1008 amdgpu_bo_unreserve(bo);
1009
1010 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1011}
1012
1013static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1014{
1015 struct amdgpu_device *adev =
1016 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1017 unsigned i, fences, handles = 0;
1018
1019 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1020
1021 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
1022 if (atomic_read(&adev->uvd.handles[i]))
1023 ++handles;
1024
1025 if (fences == 0 && handles == 0) {
1026 if (adev->pm.dpm_enabled) {
1027 amdgpu_dpm_enable_uvd(adev, false);
1028 } else {
1029 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1030 }
1031 } else {
1032 schedule_delayed_work(&adev->uvd.idle_work,
1033 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1034 }
1035}
1036
1037static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1038{
1039 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1040 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1041 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1042
1043 if (set_clocks) {
1044 if (adev->pm.dpm_enabled) {
1045 amdgpu_dpm_enable_uvd(adev, true);
1046 } else {
1047 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1048 }
1049 }
1050}