Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
4 *
5 * Copyright (C) 2007 David Brownell
6 */
7
8#include <linux/gpio/driver.h>
9#include <linux/i2c.h>
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/kernel.h>
14#include <linux/mod_devicetable.h>
15#include <linux/module.h>
16#include <linux/property.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19
20static const struct i2c_device_id pcf857x_id[] = {
21 { "pcf8574", 8 },
22 { "pcf8574a", 8 },
23 { "pca8574", 8 },
24 { "pca9670", 8 },
25 { "pca9672", 8 },
26 { "pca9674", 8 },
27 { "pcf8575", 16 },
28 { "pca8575", 16 },
29 { "pca9671", 16 },
30 { "pca9673", 16 },
31 { "pca9675", 16 },
32 { "max7328", 8 },
33 { "max7329", 8 },
34 { }
35};
36MODULE_DEVICE_TABLE(i2c, pcf857x_id);
37
38static const struct of_device_id pcf857x_of_table[] = {
39 { .compatible = "nxp,pcf8574", (void *)8 },
40 { .compatible = "nxp,pcf8574a", (void *)8 },
41 { .compatible = "nxp,pca8574", (void *)8 },
42 { .compatible = "nxp,pca9670", (void *)8 },
43 { .compatible = "nxp,pca9672", (void *)8 },
44 { .compatible = "nxp,pca9674", (void *)8 },
45 { .compatible = "nxp,pcf8575", (void *)16 },
46 { .compatible = "nxp,pca8575", (void *)16 },
47 { .compatible = "nxp,pca9671", (void *)16 },
48 { .compatible = "nxp,pca9673", (void *)16 },
49 { .compatible = "nxp,pca9675", (void *)16 },
50 { .compatible = "maxim,max7328", (void *)8 },
51 { .compatible = "maxim,max7329", (void *)8 },
52 { }
53};
54MODULE_DEVICE_TABLE(of, pcf857x_of_table);
55
56/*
57 * The pcf857x, pca857x, and pca967x chips only expose one read and one
58 * write register. Writing a "one" bit (to match the reset state) lets
59 * that pin be used as an input; it's not an open-drain model, but acts
60 * a bit like one. This is described as "quasi-bidirectional"; read the
61 * chip documentation for details.
62 *
63 * Many other I2C GPIO expander chips (like the pca953x models) have
64 * more complex register models and more conventional circuitry using
65 * push/pull drivers. They often use the same 0x20..0x27 addresses as
66 * pcf857x parts, making the "legacy" I2C driver model problematic.
67 */
68struct pcf857x {
69 struct gpio_chip chip;
70 struct i2c_client *client;
71 struct mutex lock; /* protect 'out' */
72 unsigned int out; /* software latch */
73 unsigned int status; /* current status */
74 unsigned int irq_enabled; /* enabled irqs */
75
76 int (*write)(struct i2c_client *client, unsigned int data);
77 int (*read)(struct i2c_client *client);
78};
79
80/*-------------------------------------------------------------------------*/
81
82/* Talk to 8-bit I/O expander */
83
84static int i2c_write_le8(struct i2c_client *client, unsigned int data)
85{
86 return i2c_smbus_write_byte(client, data);
87}
88
89static int i2c_read_le8(struct i2c_client *client)
90{
91 return i2c_smbus_read_byte(client);
92}
93
94/* Talk to 16-bit I/O expander */
95
96static int i2c_write_le16(struct i2c_client *client, unsigned int word)
97{
98 u8 buf[2] = { word & 0xff, word >> 8, };
99 int status;
100
101 status = i2c_master_send(client, buf, 2);
102 return (status < 0) ? status : 0;
103}
104
105static int i2c_read_le16(struct i2c_client *client)
106{
107 u8 buf[2];
108 int status;
109
110 status = i2c_master_recv(client, buf, 2);
111 if (status < 0)
112 return status;
113 return (buf[1] << 8) | buf[0];
114}
115
116/*-------------------------------------------------------------------------*/
117
118static int pcf857x_input(struct gpio_chip *chip, unsigned int offset)
119{
120 struct pcf857x *gpio = gpiochip_get_data(chip);
121 int status;
122
123 mutex_lock(&gpio->lock);
124 gpio->out |= (1 << offset);
125 status = gpio->write(gpio->client, gpio->out);
126 mutex_unlock(&gpio->lock);
127
128 return status;
129}
130
131static int pcf857x_get(struct gpio_chip *chip, unsigned int offset)
132{
133 struct pcf857x *gpio = gpiochip_get_data(chip);
134 int value;
135
136 value = gpio->read(gpio->client);
137 return (value < 0) ? value : !!(value & (1 << offset));
138}
139
140static int pcf857x_get_multiple(struct gpio_chip *chip, unsigned long *mask,
141 unsigned long *bits)
142{
143 struct pcf857x *gpio = gpiochip_get_data(chip);
144 int value = gpio->read(gpio->client);
145
146 if (value < 0)
147 return value;
148
149 *bits &= ~*mask;
150 *bits |= value & *mask;
151
152 return 0;
153}
154
155static int pcf857x_output(struct gpio_chip *chip, unsigned int offset, int value)
156{
157 struct pcf857x *gpio = gpiochip_get_data(chip);
158 unsigned int bit = 1 << offset;
159 int status;
160
161 mutex_lock(&gpio->lock);
162 if (value)
163 gpio->out |= bit;
164 else
165 gpio->out &= ~bit;
166 status = gpio->write(gpio->client, gpio->out);
167 mutex_unlock(&gpio->lock);
168
169 return status;
170}
171
172static void pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value)
173{
174 pcf857x_output(chip, offset, value);
175}
176
177static void pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask,
178 unsigned long *bits)
179{
180 struct pcf857x *gpio = gpiochip_get_data(chip);
181
182 mutex_lock(&gpio->lock);
183 gpio->out &= ~*mask;
184 gpio->out |= *bits & *mask;
185 gpio->write(gpio->client, gpio->out);
186 mutex_unlock(&gpio->lock);
187}
188
189/*-------------------------------------------------------------------------*/
190
191static irqreturn_t pcf857x_irq(int irq, void *data)
192{
193 struct pcf857x *gpio = data;
194 unsigned long change, i, status;
195
196 status = gpio->read(gpio->client);
197
198 /*
199 * call the interrupt handler iff gpio is used as
200 * interrupt source, just to avoid bad irqs
201 */
202 mutex_lock(&gpio->lock);
203 change = (gpio->status ^ status) & gpio->irq_enabled;
204 gpio->status = status;
205 mutex_unlock(&gpio->lock);
206
207 for_each_set_bit(i, &change, gpio->chip.ngpio)
208 handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i));
209
210 return IRQ_HANDLED;
211}
212
213/*
214 * NOP functions
215 */
216static void noop(struct irq_data *data) { }
217
218static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
219{
220 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
221
222 return irq_set_irq_wake(gpio->client->irq, on);
223}
224
225static void pcf857x_irq_enable(struct irq_data *data)
226{
227 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
228 irq_hw_number_t hwirq = irqd_to_hwirq(data);
229
230 gpiochip_enable_irq(&gpio->chip, hwirq);
231 gpio->irq_enabled |= (1 << hwirq);
232}
233
234static void pcf857x_irq_disable(struct irq_data *data)
235{
236 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
237 irq_hw_number_t hwirq = irqd_to_hwirq(data);
238
239 gpio->irq_enabled &= ~(1 << hwirq);
240 gpiochip_disable_irq(&gpio->chip, hwirq);
241}
242
243static void pcf857x_irq_bus_lock(struct irq_data *data)
244{
245 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
246
247 mutex_lock(&gpio->lock);
248}
249
250static void pcf857x_irq_bus_sync_unlock(struct irq_data *data)
251{
252 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
253
254 mutex_unlock(&gpio->lock);
255}
256
257static const struct irq_chip pcf857x_irq_chip = {
258 .name = "pcf857x",
259 .irq_enable = pcf857x_irq_enable,
260 .irq_disable = pcf857x_irq_disable,
261 .irq_ack = noop,
262 .irq_mask = noop,
263 .irq_unmask = noop,
264 .irq_set_wake = pcf857x_irq_set_wake,
265 .irq_bus_lock = pcf857x_irq_bus_lock,
266 .irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock,
267 .flags = IRQCHIP_IMMUTABLE,
268 GPIOCHIP_IRQ_RESOURCE_HELPERS,
269};
270
271/*-------------------------------------------------------------------------*/
272
273static int pcf857x_probe(struct i2c_client *client)
274{
275 struct pcf857x *gpio;
276 unsigned int n_latch = 0;
277 int status;
278
279 device_property_read_u32(&client->dev, "lines-initial-states", &n_latch);
280
281 /* Allocate, initialize, and register this gpio_chip. */
282 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
283 if (!gpio)
284 return -ENOMEM;
285
286 mutex_init(&gpio->lock);
287
288 gpio->chip.base = -1;
289 gpio->chip.can_sleep = true;
290 gpio->chip.parent = &client->dev;
291 gpio->chip.owner = THIS_MODULE;
292 gpio->chip.get = pcf857x_get;
293 gpio->chip.get_multiple = pcf857x_get_multiple;
294 gpio->chip.set = pcf857x_set;
295 gpio->chip.set_multiple = pcf857x_set_multiple;
296 gpio->chip.direction_input = pcf857x_input;
297 gpio->chip.direction_output = pcf857x_output;
298 gpio->chip.ngpio = (uintptr_t)i2c_get_match_data(client);
299
300 /* NOTE: the OnSemi jlc1562b is also largely compatible with
301 * these parts, notably for output. It has a low-resolution
302 * DAC instead of pin change IRQs; and its inputs can be the
303 * result of comparators.
304 */
305
306 /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
307 * 9670, 9672, 9764, and 9764a use quite a variety.
308 *
309 * NOTE: we don't distinguish here between *4 and *4a parts.
310 */
311 if (gpio->chip.ngpio == 8) {
312 gpio->write = i2c_write_le8;
313 gpio->read = i2c_read_le8;
314
315 if (!i2c_check_functionality(client->adapter,
316 I2C_FUNC_SMBUS_BYTE))
317 status = -EIO;
318
319 /* fail if there's no chip present */
320 else
321 status = i2c_smbus_read_byte(client);
322
323 /* '75/'75c addresses are 0x20..0x27, just like the '74;
324 * the '75c doesn't have a current source pulling high.
325 * 9671, 9673, and 9765 use quite a variety of addresses.
326 *
327 * NOTE: we don't distinguish here between '75 and '75c parts.
328 */
329 } else if (gpio->chip.ngpio == 16) {
330 gpio->write = i2c_write_le16;
331 gpio->read = i2c_read_le16;
332
333 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
334 status = -EIO;
335
336 /* fail if there's no chip present */
337 else
338 status = i2c_read_le16(client);
339
340 } else {
341 dev_dbg(&client->dev, "unsupported number of gpios\n");
342 status = -EINVAL;
343 }
344
345 if (status < 0)
346 goto fail;
347
348 gpio->chip.label = client->name;
349
350 gpio->client = client;
351 i2c_set_clientdata(client, gpio);
352
353 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
354 * We can't actually know whether a pin is configured (a) as output
355 * and driving the signal low, or (b) as input and reporting a low
356 * value ... without knowing the last value written since the chip
357 * came out of reset (if any). We can't read the latched output.
358 *
359 * In short, the only reliable solution for setting up pin direction
360 * is to do it explicitly. The setup() method can do that, but it
361 * may cause transient glitching since it can't know the last value
362 * written (some pins may need to be driven low).
363 *
364 * Using n_latch avoids that trouble. When left initialized to zero,
365 * our software copy of the "latch" then matches the chip's all-ones
366 * reset state. Otherwise it flags pins to be driven low.
367 */
368 gpio->out = ~n_latch;
369 gpio->status = gpio->read(gpio->client);
370
371 /* Enable irqchip if we have an interrupt */
372 if (client->irq) {
373 struct gpio_irq_chip *girq;
374
375 status = devm_request_threaded_irq(&client->dev, client->irq,
376 NULL, pcf857x_irq, IRQF_ONESHOT |
377 IRQF_TRIGGER_FALLING | IRQF_SHARED,
378 dev_name(&client->dev), gpio);
379 if (status)
380 goto fail;
381
382 girq = &gpio->chip.irq;
383 gpio_irq_chip_set_chip(girq, &pcf857x_irq_chip);
384 /* This will let us handle the parent IRQ in the driver */
385 girq->parent_handler = NULL;
386 girq->num_parents = 0;
387 girq->parents = NULL;
388 girq->default_type = IRQ_TYPE_NONE;
389 girq->handler = handle_level_irq;
390 girq->threaded = true;
391 }
392
393 status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio);
394 if (status < 0)
395 goto fail;
396
397 dev_info(&client->dev, "probed\n");
398
399 return 0;
400
401fail:
402 dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
403 client->name);
404
405 return status;
406}
407
408static void pcf857x_shutdown(struct i2c_client *client)
409{
410 struct pcf857x *gpio = i2c_get_clientdata(client);
411
412 /* Drive all the I/O lines high */
413 gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1);
414}
415
416static struct i2c_driver pcf857x_driver = {
417 .driver = {
418 .name = "pcf857x",
419 .of_match_table = pcf857x_of_table,
420 },
421 .probe = pcf857x_probe,
422 .shutdown = pcf857x_shutdown,
423 .id_table = pcf857x_id,
424};
425
426static int __init pcf857x_init(void)
427{
428 return i2c_add_driver(&pcf857x_driver);
429}
430/* register after i2c postcore initcall and before
431 * subsys initcalls that may rely on these GPIOs
432 */
433subsys_initcall(pcf857x_init);
434
435static void __exit pcf857x_exit(void)
436{
437 i2c_del_driver(&pcf857x_driver);
438}
439module_exit(pcf857x_exit);
440
441MODULE_DESCRIPTION("Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders");
442MODULE_LICENSE("GPL");
443MODULE_AUTHOR("David Brownell");
1/*
2 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
3 *
4 * Copyright (C) 2007 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/gpio.h>
22#include <linux/i2c.h>
23#include <linux/i2c/pcf857x.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/irqdomain.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/slab.h>
32#include <linux/spinlock.h>
33
34
35static const struct i2c_device_id pcf857x_id[] = {
36 { "pcf8574", 8 },
37 { "pcf8574a", 8 },
38 { "pca8574", 8 },
39 { "pca9670", 8 },
40 { "pca9672", 8 },
41 { "pca9674", 8 },
42 { "pcf8575", 16 },
43 { "pca8575", 16 },
44 { "pca9671", 16 },
45 { "pca9673", 16 },
46 { "pca9675", 16 },
47 { "max7328", 8 },
48 { "max7329", 8 },
49 { "tca9554", 8 },
50 { }
51};
52MODULE_DEVICE_TABLE(i2c, pcf857x_id);
53
54#ifdef CONFIG_OF
55static const struct of_device_id pcf857x_of_table[] = {
56 { .compatible = "nxp,pcf8574" },
57 { .compatible = "nxp,pcf8574a" },
58 { .compatible = "nxp,pca8574" },
59 { .compatible = "nxp,pca9670" },
60 { .compatible = "nxp,pca9672" },
61 { .compatible = "nxp,pca9674" },
62 { .compatible = "nxp,pcf8575" },
63 { .compatible = "nxp,pca8575" },
64 { .compatible = "nxp,pca9671" },
65 { .compatible = "nxp,pca9673" },
66 { .compatible = "nxp,pca9675" },
67 { .compatible = "maxim,max7328" },
68 { .compatible = "maxim,max7329" },
69 { .compatible = "ti,tca9554" },
70 { }
71};
72MODULE_DEVICE_TABLE(of, pcf857x_of_table);
73#endif
74
75/*
76 * The pcf857x, pca857x, and pca967x chips only expose one read and one
77 * write register. Writing a "one" bit (to match the reset state) lets
78 * that pin be used as an input; it's not an open-drain model, but acts
79 * a bit like one. This is described as "quasi-bidirectional"; read the
80 * chip documentation for details.
81 *
82 * Many other I2C GPIO expander chips (like the pca953x models) have
83 * more complex register models and more conventional circuitry using
84 * push/pull drivers. They often use the same 0x20..0x27 addresses as
85 * pcf857x parts, making the "legacy" I2C driver model problematic.
86 */
87struct pcf857x {
88 struct gpio_chip chip;
89 struct i2c_client *client;
90 struct mutex lock; /* protect 'out' */
91 unsigned out; /* software latch */
92 unsigned status; /* current status */
93 unsigned int irq_parent;
94 unsigned irq_enabled; /* enabled irqs */
95
96 int (*write)(struct i2c_client *client, unsigned data);
97 int (*read)(struct i2c_client *client);
98};
99
100/*-------------------------------------------------------------------------*/
101
102/* Talk to 8-bit I/O expander */
103
104static int i2c_write_le8(struct i2c_client *client, unsigned data)
105{
106 return i2c_smbus_write_byte(client, data);
107}
108
109static int i2c_read_le8(struct i2c_client *client)
110{
111 return (int)i2c_smbus_read_byte(client);
112}
113
114/* Talk to 16-bit I/O expander */
115
116static int i2c_write_le16(struct i2c_client *client, unsigned word)
117{
118 u8 buf[2] = { word & 0xff, word >> 8, };
119 int status;
120
121 status = i2c_master_send(client, buf, 2);
122 return (status < 0) ? status : 0;
123}
124
125static int i2c_read_le16(struct i2c_client *client)
126{
127 u8 buf[2];
128 int status;
129
130 status = i2c_master_recv(client, buf, 2);
131 if (status < 0)
132 return status;
133 return (buf[1] << 8) | buf[0];
134}
135
136/*-------------------------------------------------------------------------*/
137
138static int pcf857x_input(struct gpio_chip *chip, unsigned offset)
139{
140 struct pcf857x *gpio = gpiochip_get_data(chip);
141 int status;
142
143 mutex_lock(&gpio->lock);
144 gpio->out |= (1 << offset);
145 status = gpio->write(gpio->client, gpio->out);
146 mutex_unlock(&gpio->lock);
147
148 return status;
149}
150
151static int pcf857x_get(struct gpio_chip *chip, unsigned offset)
152{
153 struct pcf857x *gpio = gpiochip_get_data(chip);
154 int value;
155
156 value = gpio->read(gpio->client);
157 return (value < 0) ? value : !!(value & (1 << offset));
158}
159
160static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
161{
162 struct pcf857x *gpio = gpiochip_get_data(chip);
163 unsigned bit = 1 << offset;
164 int status;
165
166 mutex_lock(&gpio->lock);
167 if (value)
168 gpio->out |= bit;
169 else
170 gpio->out &= ~bit;
171 status = gpio->write(gpio->client, gpio->out);
172 mutex_unlock(&gpio->lock);
173
174 return status;
175}
176
177static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
178{
179 pcf857x_output(chip, offset, value);
180}
181
182/*-------------------------------------------------------------------------*/
183
184static irqreturn_t pcf857x_irq(int irq, void *data)
185{
186 struct pcf857x *gpio = data;
187 unsigned long change, i, status;
188
189 status = gpio->read(gpio->client);
190
191 /*
192 * call the interrupt handler iff gpio is used as
193 * interrupt source, just to avoid bad irqs
194 */
195 mutex_lock(&gpio->lock);
196 change = (gpio->status ^ status) & gpio->irq_enabled;
197 gpio->status = status;
198 mutex_unlock(&gpio->lock);
199
200 for_each_set_bit(i, &change, gpio->chip.ngpio)
201 handle_nested_irq(irq_find_mapping(gpio->chip.irqdomain, i));
202
203 return IRQ_HANDLED;
204}
205
206/*
207 * NOP functions
208 */
209static void noop(struct irq_data *data) { }
210
211static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
212{
213 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
214
215 int error = 0;
216
217 if (gpio->irq_parent) {
218 error = irq_set_irq_wake(gpio->irq_parent, on);
219 if (error) {
220 dev_dbg(&gpio->client->dev,
221 "irq %u doesn't support irq_set_wake\n",
222 gpio->irq_parent);
223 gpio->irq_parent = 0;
224 }
225 }
226 return error;
227}
228
229static void pcf857x_irq_enable(struct irq_data *data)
230{
231 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
232
233 gpio->irq_enabled |= (1 << data->hwirq);
234}
235
236static void pcf857x_irq_disable(struct irq_data *data)
237{
238 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
239
240 gpio->irq_enabled &= ~(1 << data->hwirq);
241}
242
243static void pcf857x_irq_bus_lock(struct irq_data *data)
244{
245 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
246
247 mutex_lock(&gpio->lock);
248}
249
250static void pcf857x_irq_bus_sync_unlock(struct irq_data *data)
251{
252 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
253
254 mutex_unlock(&gpio->lock);
255}
256
257static struct irq_chip pcf857x_irq_chip = {
258 .name = "pcf857x",
259 .irq_enable = pcf857x_irq_enable,
260 .irq_disable = pcf857x_irq_disable,
261 .irq_ack = noop,
262 .irq_mask = noop,
263 .irq_unmask = noop,
264 .irq_set_wake = pcf857x_irq_set_wake,
265 .irq_bus_lock = pcf857x_irq_bus_lock,
266 .irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock,
267};
268
269/*-------------------------------------------------------------------------*/
270
271static int pcf857x_probe(struct i2c_client *client,
272 const struct i2c_device_id *id)
273{
274 struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
275 struct device_node *np = client->dev.of_node;
276 struct pcf857x *gpio;
277 unsigned int n_latch = 0;
278 int status;
279
280 if (IS_ENABLED(CONFIG_OF) && np)
281 of_property_read_u32(np, "lines-initial-states", &n_latch);
282 else if (pdata)
283 n_latch = pdata->n_latch;
284 else
285 dev_dbg(&client->dev, "no platform data\n");
286
287 /* Allocate, initialize, and register this gpio_chip. */
288 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
289 if (!gpio)
290 return -ENOMEM;
291
292 mutex_init(&gpio->lock);
293
294 gpio->chip.base = pdata ? pdata->gpio_base : -1;
295 gpio->chip.can_sleep = true;
296 gpio->chip.parent = &client->dev;
297 gpio->chip.owner = THIS_MODULE;
298 gpio->chip.get = pcf857x_get;
299 gpio->chip.set = pcf857x_set;
300 gpio->chip.direction_input = pcf857x_input;
301 gpio->chip.direction_output = pcf857x_output;
302 gpio->chip.ngpio = id->driver_data;
303
304 /* NOTE: the OnSemi jlc1562b is also largely compatible with
305 * these parts, notably for output. It has a low-resolution
306 * DAC instead of pin change IRQs; and its inputs can be the
307 * result of comparators.
308 */
309
310 /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
311 * 9670, 9672, 9764, and 9764a use quite a variety.
312 *
313 * NOTE: we don't distinguish here between *4 and *4a parts.
314 */
315 if (gpio->chip.ngpio == 8) {
316 gpio->write = i2c_write_le8;
317 gpio->read = i2c_read_le8;
318
319 if (!i2c_check_functionality(client->adapter,
320 I2C_FUNC_SMBUS_BYTE))
321 status = -EIO;
322
323 /* fail if there's no chip present */
324 else
325 status = i2c_smbus_read_byte(client);
326
327 /* '75/'75c addresses are 0x20..0x27, just like the '74;
328 * the '75c doesn't have a current source pulling high.
329 * 9671, 9673, and 9765 use quite a variety of addresses.
330 *
331 * NOTE: we don't distinguish here between '75 and '75c parts.
332 */
333 } else if (gpio->chip.ngpio == 16) {
334 gpio->write = i2c_write_le16;
335 gpio->read = i2c_read_le16;
336
337 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
338 status = -EIO;
339
340 /* fail if there's no chip present */
341 else
342 status = i2c_read_le16(client);
343
344 } else {
345 dev_dbg(&client->dev, "unsupported number of gpios\n");
346 status = -EINVAL;
347 }
348
349 if (status < 0)
350 goto fail;
351
352 gpio->chip.label = client->name;
353
354 gpio->client = client;
355 i2c_set_clientdata(client, gpio);
356
357 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
358 * We can't actually know whether a pin is configured (a) as output
359 * and driving the signal low, or (b) as input and reporting a low
360 * value ... without knowing the last value written since the chip
361 * came out of reset (if any). We can't read the latched output.
362 *
363 * In short, the only reliable solution for setting up pin direction
364 * is to do it explicitly. The setup() method can do that, but it
365 * may cause transient glitching since it can't know the last value
366 * written (some pins may need to be driven low).
367 *
368 * Using n_latch avoids that trouble. When left initialized to zero,
369 * our software copy of the "latch" then matches the chip's all-ones
370 * reset state. Otherwise it flags pins to be driven low.
371 */
372 gpio->out = ~n_latch;
373 gpio->status = gpio->out;
374
375 status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio);
376 if (status < 0)
377 goto fail;
378
379 /* Enable irqchip if we have an interrupt */
380 if (client->irq) {
381 status = gpiochip_irqchip_add(&gpio->chip, &pcf857x_irq_chip,
382 0, handle_level_irq,
383 IRQ_TYPE_NONE);
384 if (status) {
385 dev_err(&client->dev, "cannot add irqchip\n");
386 goto fail;
387 }
388
389 status = devm_request_threaded_irq(&client->dev, client->irq,
390 NULL, pcf857x_irq, IRQF_ONESHOT |
391 IRQF_TRIGGER_FALLING | IRQF_SHARED,
392 dev_name(&client->dev), gpio);
393 if (status)
394 goto fail;
395
396 gpiochip_set_chained_irqchip(&gpio->chip, &pcf857x_irq_chip,
397 client->irq, NULL);
398 gpio->irq_parent = client->irq;
399 }
400
401 /* Let platform code set up the GPIOs and their users.
402 * Now is the first time anyone could use them.
403 */
404 if (pdata && pdata->setup) {
405 status = pdata->setup(client,
406 gpio->chip.base, gpio->chip.ngpio,
407 pdata->context);
408 if (status < 0)
409 dev_warn(&client->dev, "setup --> %d\n", status);
410 }
411
412 dev_info(&client->dev, "probed\n");
413
414 return 0;
415
416fail:
417 dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
418 client->name);
419
420 return status;
421}
422
423static int pcf857x_remove(struct i2c_client *client)
424{
425 struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
426 struct pcf857x *gpio = i2c_get_clientdata(client);
427 int status = 0;
428
429 if (pdata && pdata->teardown) {
430 status = pdata->teardown(client,
431 gpio->chip.base, gpio->chip.ngpio,
432 pdata->context);
433 if (status < 0) {
434 dev_err(&client->dev, "%s --> %d\n",
435 "teardown", status);
436 return status;
437 }
438 }
439
440 return status;
441}
442
443static struct i2c_driver pcf857x_driver = {
444 .driver = {
445 .name = "pcf857x",
446 .of_match_table = of_match_ptr(pcf857x_of_table),
447 },
448 .probe = pcf857x_probe,
449 .remove = pcf857x_remove,
450 .id_table = pcf857x_id,
451};
452
453static int __init pcf857x_init(void)
454{
455 return i2c_add_driver(&pcf857x_driver);
456}
457/* register after i2c postcore initcall and before
458 * subsys initcalls that may rely on these GPIOs
459 */
460subsys_initcall(pcf857x_init);
461
462static void __exit pcf857x_exit(void)
463{
464 i2c_del_driver(&pcf857x_driver);
465}
466module_exit(pcf857x_exit);
467
468MODULE_LICENSE("GPL");
469MODULE_AUTHOR("David Brownell");