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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/clocksource/arm_arch_timer.c
4 *
5 * Copyright (C) 2011 ARM Ltd.
6 * All Rights Reserved
7 */
8
9#define pr_fmt(fmt) "arch_timer: " fmt
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/cpu.h>
16#include <linux/cpu_pm.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/clocksource_ids.h>
20#include <linux/interrupt.h>
21#include <linux/kstrtox.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/sched/clock.h>
27#include <linux/sched_clock.h>
28#include <linux/acpi.h>
29#include <linux/arm-smccc.h>
30#include <linux/ptp_kvm.h>
31
32#include <asm/arch_timer.h>
33#include <asm/virt.h>
34
35#include <clocksource/arm_arch_timer.h>
36
37#define CNTTIDR 0x08
38#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
39
40#define CNTACR(n) (0x40 + ((n) * 4))
41#define CNTACR_RPCT BIT(0)
42#define CNTACR_RVCT BIT(1)
43#define CNTACR_RFRQ BIT(2)
44#define CNTACR_RVOFF BIT(3)
45#define CNTACR_RWVT BIT(4)
46#define CNTACR_RWPT BIT(5)
47
48#define CNTPCT_LO 0x00
49#define CNTVCT_LO 0x08
50#define CNTFRQ 0x10
51#define CNTP_CVAL_LO 0x20
52#define CNTP_CTL 0x2c
53#define CNTV_CVAL_LO 0x30
54#define CNTV_CTL 0x3c
55
56/*
57 * The minimum amount of time a generic counter is guaranteed to not roll over
58 * (40 years)
59 */
60#define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600)
61
62static unsigned arch_timers_present __initdata;
63
64struct arch_timer {
65 void __iomem *base;
66 struct clock_event_device evt;
67};
68
69static struct arch_timer *arch_timer_mem __ro_after_init;
70
71#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
72
73static u32 arch_timer_rate __ro_after_init;
74static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
75
76static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
78 [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
79 [ARCH_TIMER_VIRT_PPI] = "virt",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
82};
83
84static struct clock_event_device __percpu *arch_timer_evt;
85
86static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
87static bool arch_timer_c3stop __ro_after_init;
88static bool arch_timer_mem_use_virtual __ro_after_init;
89static bool arch_counter_suspend_stop __ro_after_init;
90#ifdef CONFIG_GENERIC_GETTIMEOFDAY
91static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
92#else
93static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
94#endif /* CONFIG_GENERIC_GETTIMEOFDAY */
95
96static cpumask_t evtstrm_available = CPU_MASK_NONE;
97static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
98
99static int __init early_evtstrm_cfg(char *buf)
100{
101 return kstrtobool(buf, &evtstrm_enable);
102}
103early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
104
105/*
106 * Makes an educated guess at a valid counter width based on the Generic Timer
107 * specification. Of note:
108 * 1) the system counter is at least 56 bits wide
109 * 2) a roll-over time of not less than 40 years
110 *
111 * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
112 */
113static int arch_counter_get_width(void)
114{
115 u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_rate;
116
117 /* guarantee the returned width is within the valid range */
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);
119}
120
121/*
122 * Architected system timer support.
123 */
124
125static __always_inline
126void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
127 struct clock_event_device *clk)
128{
129 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
130 struct arch_timer *timer = to_arch_timer(clk);
131 switch (reg) {
132 case ARCH_TIMER_REG_CTRL:
133 writel_relaxed((u32)val, timer->base + CNTP_CTL);
134 break;
135 case ARCH_TIMER_REG_CVAL:
136 /*
137 * Not guaranteed to be atomic, so the timer
138 * must be disabled at this point.
139 */
140 writeq_relaxed(val, timer->base + CNTP_CVAL_LO);
141 break;
142 default:
143 BUILD_BUG();
144 }
145 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
146 struct arch_timer *timer = to_arch_timer(clk);
147 switch (reg) {
148 case ARCH_TIMER_REG_CTRL:
149 writel_relaxed((u32)val, timer->base + CNTV_CTL);
150 break;
151 case ARCH_TIMER_REG_CVAL:
152 /* Same restriction as above */
153 writeq_relaxed(val, timer->base + CNTV_CVAL_LO);
154 break;
155 default:
156 BUILD_BUG();
157 }
158 } else {
159 arch_timer_reg_write_cp15(access, reg, val);
160 }
161}
162
163static __always_inline
164u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
165 struct clock_event_device *clk)
166{
167 u32 val;
168
169 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
170 struct arch_timer *timer = to_arch_timer(clk);
171 switch (reg) {
172 case ARCH_TIMER_REG_CTRL:
173 val = readl_relaxed(timer->base + CNTP_CTL);
174 break;
175 default:
176 BUILD_BUG();
177 }
178 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
179 struct arch_timer *timer = to_arch_timer(clk);
180 switch (reg) {
181 case ARCH_TIMER_REG_CTRL:
182 val = readl_relaxed(timer->base + CNTV_CTL);
183 break;
184 default:
185 BUILD_BUG();
186 }
187 } else {
188 val = arch_timer_reg_read_cp15(access, reg);
189 }
190
191 return val;
192}
193
194static noinstr u64 raw_counter_get_cntpct_stable(void)
195{
196 return __arch_counter_get_cntpct_stable();
197}
198
199static notrace u64 arch_counter_get_cntpct_stable(void)
200{
201 u64 val;
202 preempt_disable_notrace();
203 val = __arch_counter_get_cntpct_stable();
204 preempt_enable_notrace();
205 return val;
206}
207
208static noinstr u64 arch_counter_get_cntpct(void)
209{
210 return __arch_counter_get_cntpct();
211}
212
213static noinstr u64 raw_counter_get_cntvct_stable(void)
214{
215 return __arch_counter_get_cntvct_stable();
216}
217
218static notrace u64 arch_counter_get_cntvct_stable(void)
219{
220 u64 val;
221 preempt_disable_notrace();
222 val = __arch_counter_get_cntvct_stable();
223 preempt_enable_notrace();
224 return val;
225}
226
227static noinstr u64 arch_counter_get_cntvct(void)
228{
229 return __arch_counter_get_cntvct();
230}
231
232/*
233 * Default to cp15 based access because arm64 uses this function for
234 * sched_clock() before DT is probed and the cp15 method is guaranteed
235 * to exist on arm64. arm doesn't use this before DT is probed so even
236 * if we don't have the cp15 accessors we won't have a problem.
237 */
238u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
239EXPORT_SYMBOL_GPL(arch_timer_read_counter);
240
241static u64 arch_counter_read(struct clocksource *cs)
242{
243 return arch_timer_read_counter();
244}
245
246static u64 arch_counter_read_cc(const struct cyclecounter *cc)
247{
248 return arch_timer_read_counter();
249}
250
251static struct clocksource clocksource_counter = {
252 .name = "arch_sys_counter",
253 .id = CSID_ARM_ARCH_COUNTER,
254 .rating = 400,
255 .read = arch_counter_read,
256 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
257};
258
259static struct cyclecounter cyclecounter __ro_after_init = {
260 .read = arch_counter_read_cc,
261};
262
263struct ate_acpi_oem_info {
264 char oem_id[ACPI_OEM_ID_SIZE + 1];
265 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
266 u32 oem_revision;
267};
268
269#ifdef CONFIG_FSL_ERRATUM_A008585
270/*
271 * The number of retries is an arbitrary value well beyond the highest number
272 * of iterations the loop has been observed to take.
273 */
274#define __fsl_a008585_read_reg(reg) ({ \
275 u64 _old, _new; \
276 int _retries = 200; \
277 \
278 do { \
279 _old = read_sysreg(reg); \
280 _new = read_sysreg(reg); \
281 _retries--; \
282 } while (unlikely(_old != _new) && _retries); \
283 \
284 WARN_ON_ONCE(!_retries); \
285 _new; \
286})
287
288static u64 notrace fsl_a008585_read_cntpct_el0(void)
289{
290 return __fsl_a008585_read_reg(cntpct_el0);
291}
292
293static u64 notrace fsl_a008585_read_cntvct_el0(void)
294{
295 return __fsl_a008585_read_reg(cntvct_el0);
296}
297#endif
298
299#ifdef CONFIG_HISILICON_ERRATUM_161010101
300/*
301 * Verify whether the value of the second read is larger than the first by
302 * less than 32 is the only way to confirm the value is correct, so clear the
303 * lower 5 bits to check whether the difference is greater than 32 or not.
304 * Theoretically the erratum should not occur more than twice in succession
305 * when reading the system counter, but it is possible that some interrupts
306 * may lead to more than twice read errors, triggering the warning, so setting
307 * the number of retries far beyond the number of iterations the loop has been
308 * observed to take.
309 */
310#define __hisi_161010101_read_reg(reg) ({ \
311 u64 _old, _new; \
312 int _retries = 50; \
313 \
314 do { \
315 _old = read_sysreg(reg); \
316 _new = read_sysreg(reg); \
317 _retries--; \
318 } while (unlikely((_new - _old) >> 5) && _retries); \
319 \
320 WARN_ON_ONCE(!_retries); \
321 _new; \
322})
323
324static u64 notrace hisi_161010101_read_cntpct_el0(void)
325{
326 return __hisi_161010101_read_reg(cntpct_el0);
327}
328
329static u64 notrace hisi_161010101_read_cntvct_el0(void)
330{
331 return __hisi_161010101_read_reg(cntvct_el0);
332}
333
334static const struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
335 /*
336 * Note that trailing spaces are required to properly match
337 * the OEM table information.
338 */
339 {
340 .oem_id = "HISI ",
341 .oem_table_id = "HIP05 ",
342 .oem_revision = 0,
343 },
344 {
345 .oem_id = "HISI ",
346 .oem_table_id = "HIP06 ",
347 .oem_revision = 0,
348 },
349 {
350 .oem_id = "HISI ",
351 .oem_table_id = "HIP07 ",
352 .oem_revision = 0,
353 },
354 { /* Sentinel indicating the end of the OEM array */ },
355};
356#endif
357
358#ifdef CONFIG_ARM64_ERRATUM_858921
359static u64 notrace arm64_858921_read_cntpct_el0(void)
360{
361 u64 old, new;
362
363 old = read_sysreg(cntpct_el0);
364 new = read_sysreg(cntpct_el0);
365 return (((old ^ new) >> 32) & 1) ? old : new;
366}
367
368static u64 notrace arm64_858921_read_cntvct_el0(void)
369{
370 u64 old, new;
371
372 old = read_sysreg(cntvct_el0);
373 new = read_sysreg(cntvct_el0);
374 return (((old ^ new) >> 32) & 1) ? old : new;
375}
376#endif
377
378#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
379/*
380 * The low bits of the counter registers are indeterminate while bit 10 or
381 * greater is rolling over. Since the counter value can jump both backward
382 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
383 * with all ones or all zeros in the low bits. Bound the loop by the maximum
384 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
385 */
386#define __sun50i_a64_read_reg(reg) ({ \
387 u64 _val; \
388 int _retries = 150; \
389 \
390 do { \
391 _val = read_sysreg(reg); \
392 _retries--; \
393 } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \
394 \
395 WARN_ON_ONCE(!_retries); \
396 _val; \
397})
398
399static u64 notrace sun50i_a64_read_cntpct_el0(void)
400{
401 return __sun50i_a64_read_reg(cntpct_el0);
402}
403
404static u64 notrace sun50i_a64_read_cntvct_el0(void)
405{
406 return __sun50i_a64_read_reg(cntvct_el0);
407}
408#endif
409
410#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
411DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
412EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
413
414static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
415
416/*
417 * Force the inlining of this function so that the register accesses
418 * can be themselves correctly inlined.
419 */
420static __always_inline
421void erratum_set_next_event_generic(const int access, unsigned long evt,
422 struct clock_event_device *clk)
423{
424 unsigned long ctrl;
425 u64 cval;
426
427 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
428 ctrl |= ARCH_TIMER_CTRL_ENABLE;
429 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
430
431 if (access == ARCH_TIMER_PHYS_ACCESS) {
432 cval = evt + arch_counter_get_cntpct_stable();
433 write_sysreg(cval, cntp_cval_el0);
434 } else {
435 cval = evt + arch_counter_get_cntvct_stable();
436 write_sysreg(cval, cntv_cval_el0);
437 }
438
439 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
440}
441
442static __maybe_unused int erratum_set_next_event_virt(unsigned long evt,
443 struct clock_event_device *clk)
444{
445 erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
446 return 0;
447}
448
449static __maybe_unused int erratum_set_next_event_phys(unsigned long evt,
450 struct clock_event_device *clk)
451{
452 erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
453 return 0;
454}
455
456static const struct arch_timer_erratum_workaround ool_workarounds[] = {
457#ifdef CONFIG_FSL_ERRATUM_A008585
458 {
459 .match_type = ate_match_dt,
460 .id = "fsl,erratum-a008585",
461 .desc = "Freescale erratum a005858",
462 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
463 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
464 .set_next_event_phys = erratum_set_next_event_phys,
465 .set_next_event_virt = erratum_set_next_event_virt,
466 },
467#endif
468#ifdef CONFIG_HISILICON_ERRATUM_161010101
469 {
470 .match_type = ate_match_dt,
471 .id = "hisilicon,erratum-161010101",
472 .desc = "HiSilicon erratum 161010101",
473 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
474 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
475 .set_next_event_phys = erratum_set_next_event_phys,
476 .set_next_event_virt = erratum_set_next_event_virt,
477 },
478 {
479 .match_type = ate_match_acpi_oem_info,
480 .id = hisi_161010101_oem_info,
481 .desc = "HiSilicon erratum 161010101",
482 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
483 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
484 .set_next_event_phys = erratum_set_next_event_phys,
485 .set_next_event_virt = erratum_set_next_event_virt,
486 },
487#endif
488#ifdef CONFIG_ARM64_ERRATUM_858921
489 {
490 .match_type = ate_match_local_cap_id,
491 .id = (void *)ARM64_WORKAROUND_858921,
492 .desc = "ARM erratum 858921",
493 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
494 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
495 .set_next_event_phys = erratum_set_next_event_phys,
496 .set_next_event_virt = erratum_set_next_event_virt,
497 },
498#endif
499#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
500 {
501 .match_type = ate_match_dt,
502 .id = "allwinner,erratum-unknown1",
503 .desc = "Allwinner erratum UNKNOWN1",
504 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
505 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
506 .set_next_event_phys = erratum_set_next_event_phys,
507 .set_next_event_virt = erratum_set_next_event_virt,
508 },
509#endif
510#ifdef CONFIG_ARM64_ERRATUM_1418040
511 {
512 .match_type = ate_match_local_cap_id,
513 .id = (void *)ARM64_WORKAROUND_1418040,
514 .desc = "ARM erratum 1418040",
515 .disable_compat_vdso = true,
516 },
517#endif
518};
519
520typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
521 const void *);
522
523static
524bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
525 const void *arg)
526{
527 const struct device_node *np = arg;
528
529 return of_property_read_bool(np, wa->id);
530}
531
532static
533bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
534 const void *arg)
535{
536 return this_cpu_has_cap((uintptr_t)wa->id);
537}
538
539
540static
541bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
542 const void *arg)
543{
544 static const struct ate_acpi_oem_info empty_oem_info = {};
545 const struct ate_acpi_oem_info *info = wa->id;
546 const struct acpi_table_header *table = arg;
547
548 /* Iterate over the ACPI OEM info array, looking for a match */
549 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
550 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
551 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
552 info->oem_revision == table->oem_revision)
553 return true;
554
555 info++;
556 }
557
558 return false;
559}
560
561static const struct arch_timer_erratum_workaround *
562arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
563 ate_match_fn_t match_fn,
564 void *arg)
565{
566 int i;
567
568 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
569 if (ool_workarounds[i].match_type != type)
570 continue;
571
572 if (match_fn(&ool_workarounds[i], arg))
573 return &ool_workarounds[i];
574 }
575
576 return NULL;
577}
578
579static
580void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
581 bool local)
582{
583 int i;
584
585 if (local) {
586 __this_cpu_write(timer_unstable_counter_workaround, wa);
587 } else {
588 for_each_possible_cpu(i)
589 per_cpu(timer_unstable_counter_workaround, i) = wa;
590 }
591
592 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
593 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
594
595 /*
596 * Don't use the vdso fastpath if errata require using the
597 * out-of-line counter accessor. We may change our mind pretty
598 * late in the game (with a per-CPU erratum, for example), so
599 * change both the default value and the vdso itself.
600 */
601 if (wa->read_cntvct_el0) {
602 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
603 vdso_default = VDSO_CLOCKMODE_NONE;
604 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
605 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
606 clocksource_counter.vdso_clock_mode = vdso_default;
607 }
608}
609
610static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
611 void *arg)
612{
613 const struct arch_timer_erratum_workaround *wa, *__wa;
614 ate_match_fn_t match_fn = NULL;
615 bool local = false;
616
617 switch (type) {
618 case ate_match_dt:
619 match_fn = arch_timer_check_dt_erratum;
620 break;
621 case ate_match_local_cap_id:
622 match_fn = arch_timer_check_local_cap_erratum;
623 local = true;
624 break;
625 case ate_match_acpi_oem_info:
626 match_fn = arch_timer_check_acpi_oem_erratum;
627 break;
628 default:
629 WARN_ON(1);
630 return;
631 }
632
633 wa = arch_timer_iterate_errata(type, match_fn, arg);
634 if (!wa)
635 return;
636
637 __wa = __this_cpu_read(timer_unstable_counter_workaround);
638 if (__wa && wa != __wa)
639 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
640 wa->desc, __wa->desc);
641
642 if (__wa)
643 return;
644
645 arch_timer_enable_workaround(wa, local);
646 pr_info("Enabling %s workaround for %s\n",
647 local ? "local" : "global", wa->desc);
648}
649
650static bool arch_timer_this_cpu_has_cntvct_wa(void)
651{
652 return has_erratum_handler(read_cntvct_el0);
653}
654
655static bool arch_timer_counter_has_wa(void)
656{
657 return atomic_read(&timer_unstable_counter_workaround_in_use);
658}
659#else
660#define arch_timer_check_ool_workaround(t,a) do { } while(0)
661#define arch_timer_this_cpu_has_cntvct_wa() ({false;})
662#define arch_timer_counter_has_wa() ({false;})
663#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
664
665static __always_inline irqreturn_t timer_handler(const int access,
666 struct clock_event_device *evt)
667{
668 unsigned long ctrl;
669
670 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
671 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
672 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
673 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
674 evt->event_handler(evt);
675 return IRQ_HANDLED;
676 }
677
678 return IRQ_NONE;
679}
680
681static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
682{
683 struct clock_event_device *evt = dev_id;
684
685 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
686}
687
688static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
689{
690 struct clock_event_device *evt = dev_id;
691
692 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
693}
694
695static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
696{
697 struct clock_event_device *evt = dev_id;
698
699 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
700}
701
702static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
703{
704 struct clock_event_device *evt = dev_id;
705
706 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
707}
708
709static __always_inline int arch_timer_shutdown(const int access,
710 struct clock_event_device *clk)
711{
712 unsigned long ctrl;
713
714 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
715 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
716 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
717
718 return 0;
719}
720
721static int arch_timer_shutdown_virt(struct clock_event_device *clk)
722{
723 return arch_timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
724}
725
726static int arch_timer_shutdown_phys(struct clock_event_device *clk)
727{
728 return arch_timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
729}
730
731static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
732{
733 return arch_timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
734}
735
736static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
737{
738 return arch_timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
739}
740
741static __always_inline void set_next_event(const int access, unsigned long evt,
742 struct clock_event_device *clk)
743{
744 unsigned long ctrl;
745 u64 cnt;
746
747 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
748 ctrl |= ARCH_TIMER_CTRL_ENABLE;
749 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
750
751 if (access == ARCH_TIMER_PHYS_ACCESS)
752 cnt = __arch_counter_get_cntpct();
753 else
754 cnt = __arch_counter_get_cntvct();
755
756 arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
757 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
758}
759
760static int arch_timer_set_next_event_virt(unsigned long evt,
761 struct clock_event_device *clk)
762{
763 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
764 return 0;
765}
766
767static int arch_timer_set_next_event_phys(unsigned long evt,
768 struct clock_event_device *clk)
769{
770 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
771 return 0;
772}
773
774static noinstr u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo)
775{
776 u32 cnt_lo, cnt_hi, tmp_hi;
777
778 do {
779 cnt_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4));
780 cnt_lo = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo));
781 tmp_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4));
782 } while (cnt_hi != tmp_hi);
783
784 return ((u64) cnt_hi << 32) | cnt_lo;
785}
786
787static __always_inline void set_next_event_mem(const int access, unsigned long evt,
788 struct clock_event_device *clk)
789{
790 struct arch_timer *timer = to_arch_timer(clk);
791 unsigned long ctrl;
792 u64 cnt;
793
794 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
795
796 /* Timer must be disabled before programming CVAL */
797 if (ctrl & ARCH_TIMER_CTRL_ENABLE) {
798 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
799 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
800 }
801
802 ctrl |= ARCH_TIMER_CTRL_ENABLE;
803 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
804
805 if (access == ARCH_TIMER_MEM_VIRT_ACCESS)
806 cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO);
807 else
808 cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO);
809
810 arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
811 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
812}
813
814static int arch_timer_set_next_event_virt_mem(unsigned long evt,
815 struct clock_event_device *clk)
816{
817 set_next_event_mem(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
818 return 0;
819}
820
821static int arch_timer_set_next_event_phys_mem(unsigned long evt,
822 struct clock_event_device *clk)
823{
824 set_next_event_mem(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
825 return 0;
826}
827
828static u64 __arch_timer_check_delta(void)
829{
830#ifdef CONFIG_ARM64
831 const struct midr_range broken_cval_midrs[] = {
832 /*
833 * XGene-1 implements CVAL in terms of TVAL, meaning
834 * that the maximum timer range is 32bit. Shame on them.
835 *
836 * Note that TVAL is signed, thus has only 31 of its
837 * 32 bits to express magnitude.
838 */
839 MIDR_REV_RANGE(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
840 APM_CPU_PART_XGENE),
841 APM_CPU_VAR_POTENZA, 0x0, 0xf),
842 {},
843 };
844
845 if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
846 pr_warn_once("Broken CNTx_CVAL_EL1, using 31 bit TVAL instead.\n");
847 return CLOCKSOURCE_MASK(31);
848 }
849#endif
850 return CLOCKSOURCE_MASK(arch_counter_get_width());
851}
852
853static void __arch_timer_setup(unsigned type,
854 struct clock_event_device *clk)
855{
856 u64 max_delta;
857
858 clk->features = CLOCK_EVT_FEAT_ONESHOT;
859
860 if (type == ARCH_TIMER_TYPE_CP15) {
861 typeof(clk->set_next_event) sne;
862
863 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
864
865 if (arch_timer_c3stop)
866 clk->features |= CLOCK_EVT_FEAT_C3STOP;
867 clk->name = "arch_sys_timer";
868 clk->rating = 450;
869 clk->cpumask = cpumask_of(smp_processor_id());
870 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
871 switch (arch_timer_uses_ppi) {
872 case ARCH_TIMER_VIRT_PPI:
873 clk->set_state_shutdown = arch_timer_shutdown_virt;
874 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
875 sne = erratum_handler(set_next_event_virt);
876 break;
877 case ARCH_TIMER_PHYS_SECURE_PPI:
878 case ARCH_TIMER_PHYS_NONSECURE_PPI:
879 case ARCH_TIMER_HYP_PPI:
880 clk->set_state_shutdown = arch_timer_shutdown_phys;
881 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
882 sne = erratum_handler(set_next_event_phys);
883 break;
884 default:
885 BUG();
886 }
887
888 clk->set_next_event = sne;
889 max_delta = __arch_timer_check_delta();
890 } else {
891 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
892 clk->name = "arch_mem_timer";
893 clk->rating = 400;
894 clk->cpumask = cpu_possible_mask;
895 if (arch_timer_mem_use_virtual) {
896 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
897 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
898 clk->set_next_event =
899 arch_timer_set_next_event_virt_mem;
900 } else {
901 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
902 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
903 clk->set_next_event =
904 arch_timer_set_next_event_phys_mem;
905 }
906
907 max_delta = CLOCKSOURCE_MASK(56);
908 }
909
910 clk->set_state_shutdown(clk);
911
912 clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
913}
914
915static void arch_timer_evtstrm_enable(unsigned int divider)
916{
917 u32 cntkctl = arch_timer_get_cntkctl();
918
919#ifdef CONFIG_ARM64
920 /* ECV is likely to require a large divider. Use the EVNTIS flag. */
921 if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) {
922 cntkctl |= ARCH_TIMER_EVT_INTERVAL_SCALE;
923 divider -= 8;
924 }
925#endif
926
927 divider = min(divider, 15U);
928 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
929 /* Set the divider and enable virtual event stream */
930 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
931 | ARCH_TIMER_VIRT_EVT_EN;
932 arch_timer_set_cntkctl(cntkctl);
933 arch_timer_set_evtstrm_feature();
934 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
935}
936
937static void arch_timer_configure_evtstream(void)
938{
939 int evt_stream_div, lsb;
940
941 /*
942 * As the event stream can at most be generated at half the frequency
943 * of the counter, use half the frequency when computing the divider.
944 */
945 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
946
947 /*
948 * Find the closest power of two to the divisor. If the adjacent bit
949 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
950 */
951 lsb = fls(evt_stream_div) - 1;
952 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
953 lsb++;
954
955 /* enable event stream */
956 arch_timer_evtstrm_enable(max(0, lsb));
957}
958
959static int arch_timer_evtstrm_starting_cpu(unsigned int cpu)
960{
961 arch_timer_configure_evtstream();
962 return 0;
963}
964
965static int arch_timer_evtstrm_dying_cpu(unsigned int cpu)
966{
967 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
968 return 0;
969}
970
971static int __init arch_timer_evtstrm_register(void)
972{
973 if (!arch_timer_evt || !evtstrm_enable)
974 return 0;
975
976 return cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING,
977 "clockevents/arm/arch_timer_evtstrm:starting",
978 arch_timer_evtstrm_starting_cpu,
979 arch_timer_evtstrm_dying_cpu);
980}
981core_initcall(arch_timer_evtstrm_register);
982
983static void arch_counter_set_user_access(void)
984{
985 u32 cntkctl = arch_timer_get_cntkctl();
986
987 /* Disable user access to the timers and both counters */
988 /* Also disable virtual event stream */
989 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
990 | ARCH_TIMER_USR_VT_ACCESS_EN
991 | ARCH_TIMER_USR_VCT_ACCESS_EN
992 | ARCH_TIMER_VIRT_EVT_EN
993 | ARCH_TIMER_USR_PCT_ACCESS_EN);
994
995 /*
996 * Enable user access to the virtual counter if it doesn't
997 * need to be workaround. The vdso may have been already
998 * disabled though.
999 */
1000 if (arch_timer_this_cpu_has_cntvct_wa())
1001 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
1002 else
1003 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
1004
1005 arch_timer_set_cntkctl(cntkctl);
1006}
1007
1008static bool arch_timer_has_nonsecure_ppi(void)
1009{
1010 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
1011 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1012}
1013
1014static u32 check_ppi_trigger(int irq)
1015{
1016 u32 flags = irq_get_trigger_type(irq);
1017
1018 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
1019 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
1020 pr_warn("WARNING: Please fix your firmware\n");
1021 flags = IRQF_TRIGGER_LOW;
1022 }
1023
1024 return flags;
1025}
1026
1027static int arch_timer_starting_cpu(unsigned int cpu)
1028{
1029 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1030 u32 flags;
1031
1032 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
1033
1034 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
1035 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
1036
1037 if (arch_timer_has_nonsecure_ppi()) {
1038 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1039 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1040 flags);
1041 }
1042
1043 arch_counter_set_user_access();
1044
1045 return 0;
1046}
1047
1048static int validate_timer_rate(void)
1049{
1050 if (!arch_timer_rate)
1051 return -EINVAL;
1052
1053 /* Arch timer frequency < 1MHz can cause trouble */
1054 WARN_ON(arch_timer_rate < 1000000);
1055
1056 return 0;
1057}
1058
1059/*
1060 * For historical reasons, when probing with DT we use whichever (non-zero)
1061 * rate was probed first, and don't verify that others match. If the first node
1062 * probed has a clock-frequency property, this overrides the HW register.
1063 */
1064static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
1065{
1066 /* Who has more than one independent system counter? */
1067 if (arch_timer_rate)
1068 return;
1069
1070 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
1071 arch_timer_rate = rate;
1072
1073 /* Check the timer frequency. */
1074 if (validate_timer_rate())
1075 pr_warn("frequency not available\n");
1076}
1077
1078static void __init arch_timer_banner(unsigned type)
1079{
1080 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
1081 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
1082 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
1083 " and " : "",
1084 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
1085 (unsigned long)arch_timer_rate / 1000000,
1086 (unsigned long)(arch_timer_rate / 10000) % 100,
1087 type & ARCH_TIMER_TYPE_CP15 ?
1088 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
1089 "",
1090 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
1091 type & ARCH_TIMER_TYPE_MEM ?
1092 arch_timer_mem_use_virtual ? "virt" : "phys" :
1093 "");
1094}
1095
1096u32 arch_timer_get_rate(void)
1097{
1098 return arch_timer_rate;
1099}
1100
1101bool arch_timer_evtstrm_available(void)
1102{
1103 /*
1104 * We might get called from a preemptible context. This is fine
1105 * because availability of the event stream should be always the same
1106 * for a preemptible context and context where we might resume a task.
1107 */
1108 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
1109}
1110
1111static noinstr u64 arch_counter_get_cntvct_mem(void)
1112{
1113 return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO);
1114}
1115
1116static struct arch_timer_kvm_info arch_timer_kvm_info;
1117
1118struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
1119{
1120 return &arch_timer_kvm_info;
1121}
1122
1123static void __init arch_counter_register(unsigned type)
1124{
1125 u64 (*scr)(void);
1126 u64 start_count;
1127 int width;
1128
1129 /* Register the CP15 based counter if we have one */
1130 if (type & ARCH_TIMER_TYPE_CP15) {
1131 u64 (*rd)(void);
1132
1133 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
1134 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
1135 if (arch_timer_counter_has_wa()) {
1136 rd = arch_counter_get_cntvct_stable;
1137 scr = raw_counter_get_cntvct_stable;
1138 } else {
1139 rd = arch_counter_get_cntvct;
1140 scr = arch_counter_get_cntvct;
1141 }
1142 } else {
1143 if (arch_timer_counter_has_wa()) {
1144 rd = arch_counter_get_cntpct_stable;
1145 scr = raw_counter_get_cntpct_stable;
1146 } else {
1147 rd = arch_counter_get_cntpct;
1148 scr = arch_counter_get_cntpct;
1149 }
1150 }
1151
1152 arch_timer_read_counter = rd;
1153 clocksource_counter.vdso_clock_mode = vdso_default;
1154 } else {
1155 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1156 scr = arch_counter_get_cntvct_mem;
1157 }
1158
1159 width = arch_counter_get_width();
1160 clocksource_counter.mask = CLOCKSOURCE_MASK(width);
1161 cyclecounter.mask = CLOCKSOURCE_MASK(width);
1162
1163 if (!arch_counter_suspend_stop)
1164 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1165 start_count = arch_timer_read_counter();
1166 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1167 cyclecounter.mult = clocksource_counter.mult;
1168 cyclecounter.shift = clocksource_counter.shift;
1169 timecounter_init(&arch_timer_kvm_info.timecounter,
1170 &cyclecounter, start_count);
1171
1172 sched_clock_register(scr, width, arch_timer_rate);
1173}
1174
1175static void arch_timer_stop(struct clock_event_device *clk)
1176{
1177 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1178
1179 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1180 if (arch_timer_has_nonsecure_ppi())
1181 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1182}
1183
1184static int arch_timer_dying_cpu(unsigned int cpu)
1185{
1186 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1187
1188 arch_timer_stop(clk);
1189 return 0;
1190}
1191
1192#ifdef CONFIG_CPU_PM
1193static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1194static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1195 unsigned long action, void *hcpu)
1196{
1197 if (action == CPU_PM_ENTER) {
1198 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1199
1200 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1201 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1202 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1203
1204 if (arch_timer_have_evtstrm_feature())
1205 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1206 }
1207 return NOTIFY_OK;
1208}
1209
1210static struct notifier_block arch_timer_cpu_pm_notifier = {
1211 .notifier_call = arch_timer_cpu_pm_notify,
1212};
1213
1214static int __init arch_timer_cpu_pm_init(void)
1215{
1216 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1217}
1218
1219static void __init arch_timer_cpu_pm_deinit(void)
1220{
1221 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1222}
1223
1224#else
1225static int __init arch_timer_cpu_pm_init(void)
1226{
1227 return 0;
1228}
1229
1230static void __init arch_timer_cpu_pm_deinit(void)
1231{
1232}
1233#endif
1234
1235static int __init arch_timer_register(void)
1236{
1237 int err;
1238 int ppi;
1239
1240 arch_timer_evt = alloc_percpu(struct clock_event_device);
1241 if (!arch_timer_evt) {
1242 err = -ENOMEM;
1243 goto out;
1244 }
1245
1246 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1247 switch (arch_timer_uses_ppi) {
1248 case ARCH_TIMER_VIRT_PPI:
1249 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1250 "arch_timer", arch_timer_evt);
1251 break;
1252 case ARCH_TIMER_PHYS_SECURE_PPI:
1253 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1254 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1255 "arch_timer", arch_timer_evt);
1256 if (!err && arch_timer_has_nonsecure_ppi()) {
1257 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1258 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1259 "arch_timer", arch_timer_evt);
1260 if (err)
1261 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1262 arch_timer_evt);
1263 }
1264 break;
1265 case ARCH_TIMER_HYP_PPI:
1266 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1267 "arch_timer", arch_timer_evt);
1268 break;
1269 default:
1270 BUG();
1271 }
1272
1273 if (err) {
1274 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1275 goto out_free;
1276 }
1277
1278 err = arch_timer_cpu_pm_init();
1279 if (err)
1280 goto out_unreg_notify;
1281
1282 /* Register and immediately configure the timer on the boot CPU */
1283 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1284 "clockevents/arm/arch_timer:starting",
1285 arch_timer_starting_cpu, arch_timer_dying_cpu);
1286 if (err)
1287 goto out_unreg_cpupm;
1288 return 0;
1289
1290out_unreg_cpupm:
1291 arch_timer_cpu_pm_deinit();
1292
1293out_unreg_notify:
1294 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1295 if (arch_timer_has_nonsecure_ppi())
1296 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1297 arch_timer_evt);
1298
1299out_free:
1300 free_percpu(arch_timer_evt);
1301 arch_timer_evt = NULL;
1302out:
1303 return err;
1304}
1305
1306static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1307{
1308 int ret;
1309 irq_handler_t func;
1310
1311 arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL);
1312 if (!arch_timer_mem)
1313 return -ENOMEM;
1314
1315 arch_timer_mem->base = base;
1316 arch_timer_mem->evt.irq = irq;
1317 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt);
1318
1319 if (arch_timer_mem_use_virtual)
1320 func = arch_timer_handler_virt_mem;
1321 else
1322 func = arch_timer_handler_phys_mem;
1323
1324 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt);
1325 if (ret) {
1326 pr_err("Failed to request mem timer irq\n");
1327 kfree(arch_timer_mem);
1328 arch_timer_mem = NULL;
1329 }
1330
1331 return ret;
1332}
1333
1334static const struct of_device_id arch_timer_of_match[] __initconst = {
1335 { .compatible = "arm,armv7-timer", },
1336 { .compatible = "arm,armv8-timer", },
1337 {},
1338};
1339
1340static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1341 { .compatible = "arm,armv7-timer-mem", },
1342 {},
1343};
1344
1345static bool __init arch_timer_needs_of_probing(void)
1346{
1347 struct device_node *dn;
1348 bool needs_probing = false;
1349 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1350
1351 /* We have two timers, and both device-tree nodes are probed. */
1352 if ((arch_timers_present & mask) == mask)
1353 return false;
1354
1355 /*
1356 * Only one type of timer is probed,
1357 * check if we have another type of timer node in device-tree.
1358 */
1359 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1360 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1361 else
1362 dn = of_find_matching_node(NULL, arch_timer_of_match);
1363
1364 if (dn && of_device_is_available(dn))
1365 needs_probing = true;
1366
1367 of_node_put(dn);
1368
1369 return needs_probing;
1370}
1371
1372static int __init arch_timer_common_init(void)
1373{
1374 arch_timer_banner(arch_timers_present);
1375 arch_counter_register(arch_timers_present);
1376 return arch_timer_arch_init();
1377}
1378
1379/**
1380 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1381 *
1382 * If HYP mode is available, we know that the physical timer
1383 * has been configured to be accessible from PL1. Use it, so
1384 * that a guest can use the virtual timer instead.
1385 *
1386 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1387 * accesses to CNTP_*_EL1 registers are silently redirected to
1388 * their CNTHP_*_EL2 counterparts, and use a different PPI
1389 * number.
1390 *
1391 * If no interrupt provided for virtual timer, we'll have to
1392 * stick to the physical timer. It'd better be accessible...
1393 * For arm64 we never use the secure interrupt.
1394 *
1395 * Return: a suitable PPI type for the current system.
1396 */
1397static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1398{
1399 if (is_kernel_in_hyp_mode())
1400 return ARCH_TIMER_HYP_PPI;
1401
1402 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1403 return ARCH_TIMER_VIRT_PPI;
1404
1405 if (IS_ENABLED(CONFIG_ARM64))
1406 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1407
1408 return ARCH_TIMER_PHYS_SECURE_PPI;
1409}
1410
1411static void __init arch_timer_populate_kvm_info(void)
1412{
1413 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1414 if (is_kernel_in_hyp_mode())
1415 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1416}
1417
1418static int __init arch_timer_of_init(struct device_node *np)
1419{
1420 int i, irq, ret;
1421 u32 rate;
1422 bool has_names;
1423
1424 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1425 pr_warn("multiple nodes in dt, skipping\n");
1426 return 0;
1427 }
1428
1429 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1430
1431 has_names = of_property_present(np, "interrupt-names");
1432
1433 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1434 if (has_names)
1435 irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1436 else
1437 irq = of_irq_get(np, i);
1438 if (irq > 0)
1439 arch_timer_ppi[i] = irq;
1440 }
1441
1442 arch_timer_populate_kvm_info();
1443
1444 rate = arch_timer_get_cntfrq();
1445 arch_timer_of_configure_rate(rate, np);
1446
1447 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1448
1449 /* Check for globally applicable workarounds */
1450 arch_timer_check_ool_workaround(ate_match_dt, np);
1451
1452 /*
1453 * If we cannot rely on firmware initializing the timer registers then
1454 * we should use the physical timers instead.
1455 */
1456 if (IS_ENABLED(CONFIG_ARM) &&
1457 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1458 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1459 else
1460 arch_timer_uses_ppi = arch_timer_select_ppi();
1461
1462 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1463 pr_err("No interrupt available, giving up\n");
1464 return -EINVAL;
1465 }
1466
1467 /* On some systems, the counter stops ticking when in suspend. */
1468 arch_counter_suspend_stop = of_property_read_bool(np,
1469 "arm,no-tick-in-suspend");
1470
1471 ret = arch_timer_register();
1472 if (ret)
1473 return ret;
1474
1475 if (arch_timer_needs_of_probing())
1476 return 0;
1477
1478 return arch_timer_common_init();
1479}
1480TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1481TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1482
1483static u32 __init
1484arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1485{
1486 void __iomem *base;
1487 u32 rate;
1488
1489 base = ioremap(frame->cntbase, frame->size);
1490 if (!base) {
1491 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1492 return 0;
1493 }
1494
1495 rate = readl_relaxed(base + CNTFRQ);
1496
1497 iounmap(base);
1498
1499 return rate;
1500}
1501
1502static struct arch_timer_mem_frame * __init
1503arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1504{
1505 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1506 void __iomem *cntctlbase;
1507 u32 cnttidr;
1508 int i;
1509
1510 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1511 if (!cntctlbase) {
1512 pr_err("Can't map CNTCTLBase @ %pa\n",
1513 &timer_mem->cntctlbase);
1514 return NULL;
1515 }
1516
1517 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1518
1519 /*
1520 * Try to find a virtual capable frame. Otherwise fall back to a
1521 * physical capable frame.
1522 */
1523 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1524 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1525 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1526
1527 frame = &timer_mem->frame[i];
1528 if (!frame->valid)
1529 continue;
1530
1531 /* Try enabling everything, and see what sticks */
1532 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1533 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1534
1535 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1536 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1537 best_frame = frame;
1538 arch_timer_mem_use_virtual = true;
1539 break;
1540 }
1541
1542 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1543 continue;
1544
1545 best_frame = frame;
1546 }
1547
1548 iounmap(cntctlbase);
1549
1550 return best_frame;
1551}
1552
1553static int __init
1554arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1555{
1556 void __iomem *base;
1557 int ret, irq;
1558
1559 if (arch_timer_mem_use_virtual)
1560 irq = frame->virt_irq;
1561 else
1562 irq = frame->phys_irq;
1563
1564 if (!irq) {
1565 pr_err("Frame missing %s irq.\n",
1566 arch_timer_mem_use_virtual ? "virt" : "phys");
1567 return -EINVAL;
1568 }
1569
1570 if (!request_mem_region(frame->cntbase, frame->size,
1571 "arch_mem_timer"))
1572 return -EBUSY;
1573
1574 base = ioremap(frame->cntbase, frame->size);
1575 if (!base) {
1576 pr_err("Can't map frame's registers\n");
1577 return -ENXIO;
1578 }
1579
1580 ret = arch_timer_mem_register(base, irq);
1581 if (ret) {
1582 iounmap(base);
1583 return ret;
1584 }
1585
1586 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1587
1588 return 0;
1589}
1590
1591static int __init arch_timer_mem_of_init(struct device_node *np)
1592{
1593 struct arch_timer_mem *timer_mem;
1594 struct arch_timer_mem_frame *frame;
1595 struct resource res;
1596 int ret = -EINVAL;
1597 u32 rate;
1598
1599 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1600 if (!timer_mem)
1601 return -ENOMEM;
1602
1603 if (of_address_to_resource(np, 0, &res))
1604 goto out;
1605 timer_mem->cntctlbase = res.start;
1606 timer_mem->size = resource_size(&res);
1607
1608 for_each_available_child_of_node_scoped(np, frame_node) {
1609 u32 n;
1610 struct arch_timer_mem_frame *frame;
1611
1612 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1613 pr_err(FW_BUG "Missing frame-number.\n");
1614 goto out;
1615 }
1616 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1617 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1618 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1619 goto out;
1620 }
1621 frame = &timer_mem->frame[n];
1622
1623 if (frame->valid) {
1624 pr_err(FW_BUG "Duplicated frame-number.\n");
1625 goto out;
1626 }
1627
1628 if (of_address_to_resource(frame_node, 0, &res))
1629 goto out;
1630
1631 frame->cntbase = res.start;
1632 frame->size = resource_size(&res);
1633
1634 frame->virt_irq = irq_of_parse_and_map(frame_node,
1635 ARCH_TIMER_VIRT_SPI);
1636 frame->phys_irq = irq_of_parse_and_map(frame_node,
1637 ARCH_TIMER_PHYS_SPI);
1638
1639 frame->valid = true;
1640 }
1641
1642 frame = arch_timer_mem_find_best_frame(timer_mem);
1643 if (!frame) {
1644 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1645 &timer_mem->cntctlbase);
1646 ret = -EINVAL;
1647 goto out;
1648 }
1649
1650 rate = arch_timer_mem_frame_get_cntfrq(frame);
1651 arch_timer_of_configure_rate(rate, np);
1652
1653 ret = arch_timer_mem_frame_register(frame);
1654 if (!ret && !arch_timer_needs_of_probing())
1655 ret = arch_timer_common_init();
1656out:
1657 kfree(timer_mem);
1658 return ret;
1659}
1660TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1661 arch_timer_mem_of_init);
1662
1663#ifdef CONFIG_ACPI_GTDT
1664static int __init
1665arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1666{
1667 struct arch_timer_mem_frame *frame;
1668 u32 rate;
1669 int i;
1670
1671 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1672 frame = &timer_mem->frame[i];
1673
1674 if (!frame->valid)
1675 continue;
1676
1677 rate = arch_timer_mem_frame_get_cntfrq(frame);
1678 if (rate == arch_timer_rate)
1679 continue;
1680
1681 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1682 &frame->cntbase,
1683 (unsigned long)rate, (unsigned long)arch_timer_rate);
1684
1685 return -EINVAL;
1686 }
1687
1688 return 0;
1689}
1690
1691static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1692{
1693 struct arch_timer_mem *timers, *timer;
1694 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1695 int timer_count, i, ret = 0;
1696
1697 timers = kcalloc(platform_timer_count, sizeof(*timers),
1698 GFP_KERNEL);
1699 if (!timers)
1700 return -ENOMEM;
1701
1702 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1703 if (ret || !timer_count)
1704 goto out;
1705
1706 /*
1707 * While unlikely, it's theoretically possible that none of the frames
1708 * in a timer expose the combination of feature we want.
1709 */
1710 for (i = 0; i < timer_count; i++) {
1711 timer = &timers[i];
1712
1713 frame = arch_timer_mem_find_best_frame(timer);
1714 if (!best_frame)
1715 best_frame = frame;
1716
1717 ret = arch_timer_mem_verify_cntfrq(timer);
1718 if (ret) {
1719 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1720 goto out;
1721 }
1722
1723 if (!best_frame) /* implies !frame */
1724 /*
1725 * Only complain about missing suitable frames if we
1726 * haven't already found one in a previous iteration.
1727 */
1728 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1729 &timer->cntctlbase);
1730 }
1731
1732 if (best_frame)
1733 ret = arch_timer_mem_frame_register(best_frame);
1734out:
1735 kfree(timers);
1736 return ret;
1737}
1738
1739/* Initialize per-processor generic timer and memory-mapped timer(if present) */
1740static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1741{
1742 int ret, platform_timer_count;
1743
1744 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1745 pr_warn("already initialized, skipping\n");
1746 return -EINVAL;
1747 }
1748
1749 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1750
1751 ret = acpi_gtdt_init(table, &platform_timer_count);
1752 if (ret)
1753 return ret;
1754
1755 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1756 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1757
1758 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1759 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1760
1761 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1762 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1763
1764 arch_timer_populate_kvm_info();
1765
1766 /*
1767 * When probing via ACPI, we have no mechanism to override the sysreg
1768 * CNTFRQ value. This *must* be correct.
1769 */
1770 arch_timer_rate = arch_timer_get_cntfrq();
1771 ret = validate_timer_rate();
1772 if (ret) {
1773 pr_err(FW_BUG "frequency not available.\n");
1774 return ret;
1775 }
1776
1777 arch_timer_uses_ppi = arch_timer_select_ppi();
1778 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1779 pr_err("No interrupt available, giving up\n");
1780 return -EINVAL;
1781 }
1782
1783 /* Always-on capability */
1784 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1785
1786 /* Check for globally applicable workarounds */
1787 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1788
1789 ret = arch_timer_register();
1790 if (ret)
1791 return ret;
1792
1793 if (platform_timer_count &&
1794 arch_timer_mem_acpi_init(platform_timer_count))
1795 pr_err("Failed to initialize memory-mapped timer.\n");
1796
1797 return arch_timer_common_init();
1798}
1799TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1800#endif
1801
1802int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1803 enum clocksource_ids *cs_id)
1804{
1805 struct arm_smccc_res hvc_res;
1806 u32 ptp_counter;
1807 ktime_t ktime;
1808
1809 if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1810 return -EOPNOTSUPP;
1811
1812 if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1813 ptp_counter = KVM_PTP_VIRT_COUNTER;
1814 else
1815 ptp_counter = KVM_PTP_PHYS_COUNTER;
1816
1817 arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1818 ptp_counter, &hvc_res);
1819
1820 if ((int)(hvc_res.a0) < 0)
1821 return -EOPNOTSUPP;
1822
1823 ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1824 *ts = ktime_to_timespec64(ktime);
1825 if (cycle)
1826 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1827 if (cs_id)
1828 *cs_id = CSID_ARM_ARCH_COUNTER;
1829
1830 return 0;
1831}
1832EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);
1/*
2 * linux/drivers/clocksource/arm_arch_timer.c
3 *
4 * Copyright (C) 2011 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/cpu.h>
16#include <linux/cpu_pm.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/interrupt.h>
20#include <linux/of_irq.h>
21#include <linux/of_address.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24#include <linux/sched_clock.h>
25#include <linux/acpi.h>
26
27#include <asm/arch_timer.h>
28#include <asm/virt.h>
29
30#include <clocksource/arm_arch_timer.h>
31
32#define CNTTIDR 0x08
33#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
34
35#define CNTACR(n) (0x40 + ((n) * 4))
36#define CNTACR_RPCT BIT(0)
37#define CNTACR_RVCT BIT(1)
38#define CNTACR_RFRQ BIT(2)
39#define CNTACR_RVOFF BIT(3)
40#define CNTACR_RWVT BIT(4)
41#define CNTACR_RWPT BIT(5)
42
43#define CNTVCT_LO 0x08
44#define CNTVCT_HI 0x0c
45#define CNTFRQ 0x10
46#define CNTP_TVAL 0x28
47#define CNTP_CTL 0x2c
48#define CNTV_TVAL 0x38
49#define CNTV_CTL 0x3c
50
51#define ARCH_CP15_TIMER BIT(0)
52#define ARCH_MEM_TIMER BIT(1)
53static unsigned arch_timers_present __initdata;
54
55static void __iomem *arch_counter_base;
56
57struct arch_timer {
58 void __iomem *base;
59 struct clock_event_device evt;
60};
61
62#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
63
64static u32 arch_timer_rate;
65
66enum ppi_nr {
67 PHYS_SECURE_PPI,
68 PHYS_NONSECURE_PPI,
69 VIRT_PPI,
70 HYP_PPI,
71 MAX_TIMER_PPI
72};
73
74static int arch_timer_ppi[MAX_TIMER_PPI];
75
76static struct clock_event_device __percpu *arch_timer_evt;
77
78static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
79static bool arch_timer_c3stop;
80static bool arch_timer_mem_use_virtual;
81
82/*
83 * Architected system timer support.
84 */
85
86static __always_inline
87void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
88 struct clock_event_device *clk)
89{
90 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
91 struct arch_timer *timer = to_arch_timer(clk);
92 switch (reg) {
93 case ARCH_TIMER_REG_CTRL:
94 writel_relaxed(val, timer->base + CNTP_CTL);
95 break;
96 case ARCH_TIMER_REG_TVAL:
97 writel_relaxed(val, timer->base + CNTP_TVAL);
98 break;
99 }
100 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
101 struct arch_timer *timer = to_arch_timer(clk);
102 switch (reg) {
103 case ARCH_TIMER_REG_CTRL:
104 writel_relaxed(val, timer->base + CNTV_CTL);
105 break;
106 case ARCH_TIMER_REG_TVAL:
107 writel_relaxed(val, timer->base + CNTV_TVAL);
108 break;
109 }
110 } else {
111 arch_timer_reg_write_cp15(access, reg, val);
112 }
113}
114
115static __always_inline
116u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
117 struct clock_event_device *clk)
118{
119 u32 val;
120
121 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
122 struct arch_timer *timer = to_arch_timer(clk);
123 switch (reg) {
124 case ARCH_TIMER_REG_CTRL:
125 val = readl_relaxed(timer->base + CNTP_CTL);
126 break;
127 case ARCH_TIMER_REG_TVAL:
128 val = readl_relaxed(timer->base + CNTP_TVAL);
129 break;
130 }
131 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
132 struct arch_timer *timer = to_arch_timer(clk);
133 switch (reg) {
134 case ARCH_TIMER_REG_CTRL:
135 val = readl_relaxed(timer->base + CNTV_CTL);
136 break;
137 case ARCH_TIMER_REG_TVAL:
138 val = readl_relaxed(timer->base + CNTV_TVAL);
139 break;
140 }
141 } else {
142 val = arch_timer_reg_read_cp15(access, reg);
143 }
144
145 return val;
146}
147
148static __always_inline irqreturn_t timer_handler(const int access,
149 struct clock_event_device *evt)
150{
151 unsigned long ctrl;
152
153 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
154 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
155 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
156 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
157 evt->event_handler(evt);
158 return IRQ_HANDLED;
159 }
160
161 return IRQ_NONE;
162}
163
164static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
165{
166 struct clock_event_device *evt = dev_id;
167
168 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
169}
170
171static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
172{
173 struct clock_event_device *evt = dev_id;
174
175 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
176}
177
178static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
179{
180 struct clock_event_device *evt = dev_id;
181
182 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
183}
184
185static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
186{
187 struct clock_event_device *evt = dev_id;
188
189 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
190}
191
192static __always_inline int timer_shutdown(const int access,
193 struct clock_event_device *clk)
194{
195 unsigned long ctrl;
196
197 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
198 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
199 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
200
201 return 0;
202}
203
204static int arch_timer_shutdown_virt(struct clock_event_device *clk)
205{
206 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
207}
208
209static int arch_timer_shutdown_phys(struct clock_event_device *clk)
210{
211 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
212}
213
214static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
215{
216 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
217}
218
219static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
220{
221 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
222}
223
224static __always_inline void set_next_event(const int access, unsigned long evt,
225 struct clock_event_device *clk)
226{
227 unsigned long ctrl;
228 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
229 ctrl |= ARCH_TIMER_CTRL_ENABLE;
230 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
231 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
232 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
233}
234
235static int arch_timer_set_next_event_virt(unsigned long evt,
236 struct clock_event_device *clk)
237{
238 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
239 return 0;
240}
241
242static int arch_timer_set_next_event_phys(unsigned long evt,
243 struct clock_event_device *clk)
244{
245 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
246 return 0;
247}
248
249static int arch_timer_set_next_event_virt_mem(unsigned long evt,
250 struct clock_event_device *clk)
251{
252 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
253 return 0;
254}
255
256static int arch_timer_set_next_event_phys_mem(unsigned long evt,
257 struct clock_event_device *clk)
258{
259 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
260 return 0;
261}
262
263static void __arch_timer_setup(unsigned type,
264 struct clock_event_device *clk)
265{
266 clk->features = CLOCK_EVT_FEAT_ONESHOT;
267
268 if (type == ARCH_CP15_TIMER) {
269 if (arch_timer_c3stop)
270 clk->features |= CLOCK_EVT_FEAT_C3STOP;
271 clk->name = "arch_sys_timer";
272 clk->rating = 450;
273 clk->cpumask = cpumask_of(smp_processor_id());
274 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
275 switch (arch_timer_uses_ppi) {
276 case VIRT_PPI:
277 clk->set_state_shutdown = arch_timer_shutdown_virt;
278 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
279 clk->set_next_event = arch_timer_set_next_event_virt;
280 break;
281 case PHYS_SECURE_PPI:
282 case PHYS_NONSECURE_PPI:
283 case HYP_PPI:
284 clk->set_state_shutdown = arch_timer_shutdown_phys;
285 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
286 clk->set_next_event = arch_timer_set_next_event_phys;
287 break;
288 default:
289 BUG();
290 }
291 } else {
292 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
293 clk->name = "arch_mem_timer";
294 clk->rating = 400;
295 clk->cpumask = cpu_all_mask;
296 if (arch_timer_mem_use_virtual) {
297 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
298 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
299 clk->set_next_event =
300 arch_timer_set_next_event_virt_mem;
301 } else {
302 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
303 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
304 clk->set_next_event =
305 arch_timer_set_next_event_phys_mem;
306 }
307 }
308
309 clk->set_state_shutdown(clk);
310
311 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
312}
313
314static void arch_timer_evtstrm_enable(int divider)
315{
316 u32 cntkctl = arch_timer_get_cntkctl();
317
318 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
319 /* Set the divider and enable virtual event stream */
320 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
321 | ARCH_TIMER_VIRT_EVT_EN;
322 arch_timer_set_cntkctl(cntkctl);
323 elf_hwcap |= HWCAP_EVTSTRM;
324#ifdef CONFIG_COMPAT
325 compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
326#endif
327}
328
329static void arch_timer_configure_evtstream(void)
330{
331 int evt_stream_div, pos;
332
333 /* Find the closest power of two to the divisor */
334 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
335 pos = fls(evt_stream_div);
336 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
337 pos--;
338 /* enable event stream */
339 arch_timer_evtstrm_enable(min(pos, 15));
340}
341
342static void arch_counter_set_user_access(void)
343{
344 u32 cntkctl = arch_timer_get_cntkctl();
345
346 /* Disable user access to the timers and the physical counter */
347 /* Also disable virtual event stream */
348 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
349 | ARCH_TIMER_USR_VT_ACCESS_EN
350 | ARCH_TIMER_VIRT_EVT_EN
351 | ARCH_TIMER_USR_PCT_ACCESS_EN);
352
353 /* Enable user access to the virtual counter */
354 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
355
356 arch_timer_set_cntkctl(cntkctl);
357}
358
359static bool arch_timer_has_nonsecure_ppi(void)
360{
361 return (arch_timer_uses_ppi == PHYS_SECURE_PPI &&
362 arch_timer_ppi[PHYS_NONSECURE_PPI]);
363}
364
365static int arch_timer_setup(struct clock_event_device *clk)
366{
367 __arch_timer_setup(ARCH_CP15_TIMER, clk);
368
369 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], 0);
370
371 if (arch_timer_has_nonsecure_ppi())
372 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
373
374 arch_counter_set_user_access();
375 if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
376 arch_timer_configure_evtstream();
377
378 return 0;
379}
380
381static void
382arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
383{
384 /* Who has more than one independent system counter? */
385 if (arch_timer_rate)
386 return;
387
388 /*
389 * Try to determine the frequency from the device tree or CNTFRQ,
390 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
391 */
392 if (!acpi_disabled ||
393 of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
394 if (cntbase)
395 arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
396 else
397 arch_timer_rate = arch_timer_get_cntfrq();
398 }
399
400 /* Check the timer frequency. */
401 if (arch_timer_rate == 0)
402 pr_warn("Architected timer frequency not available\n");
403}
404
405static void arch_timer_banner(unsigned type)
406{
407 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
408 type & ARCH_CP15_TIMER ? "cp15" : "",
409 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
410 type & ARCH_MEM_TIMER ? "mmio" : "",
411 (unsigned long)arch_timer_rate / 1000000,
412 (unsigned long)(arch_timer_rate / 10000) % 100,
413 type & ARCH_CP15_TIMER ?
414 (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
415 "",
416 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
417 type & ARCH_MEM_TIMER ?
418 arch_timer_mem_use_virtual ? "virt" : "phys" :
419 "");
420}
421
422u32 arch_timer_get_rate(void)
423{
424 return arch_timer_rate;
425}
426
427static u64 arch_counter_get_cntvct_mem(void)
428{
429 u32 vct_lo, vct_hi, tmp_hi;
430
431 do {
432 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
433 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
434 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
435 } while (vct_hi != tmp_hi);
436
437 return ((u64) vct_hi << 32) | vct_lo;
438}
439
440/*
441 * Default to cp15 based access because arm64 uses this function for
442 * sched_clock() before DT is probed and the cp15 method is guaranteed
443 * to exist on arm64. arm doesn't use this before DT is probed so even
444 * if we don't have the cp15 accessors we won't have a problem.
445 */
446u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
447
448static cycle_t arch_counter_read(struct clocksource *cs)
449{
450 return arch_timer_read_counter();
451}
452
453static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
454{
455 return arch_timer_read_counter();
456}
457
458static struct clocksource clocksource_counter = {
459 .name = "arch_sys_counter",
460 .rating = 400,
461 .read = arch_counter_read,
462 .mask = CLOCKSOURCE_MASK(56),
463 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
464};
465
466static struct cyclecounter cyclecounter = {
467 .read = arch_counter_read_cc,
468 .mask = CLOCKSOURCE_MASK(56),
469};
470
471static struct timecounter timecounter;
472
473struct timecounter *arch_timer_get_timecounter(void)
474{
475 return &timecounter;
476}
477
478static void __init arch_counter_register(unsigned type)
479{
480 u64 start_count;
481
482 /* Register the CP15 based counter if we have one */
483 if (type & ARCH_CP15_TIMER) {
484 if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI)
485 arch_timer_read_counter = arch_counter_get_cntvct;
486 else
487 arch_timer_read_counter = arch_counter_get_cntpct;
488 } else {
489 arch_timer_read_counter = arch_counter_get_cntvct_mem;
490
491 /* If the clocksource name is "arch_sys_counter" the
492 * VDSO will attempt to read the CP15-based counter.
493 * Ensure this does not happen when CP15-based
494 * counter is not available.
495 */
496 clocksource_counter.name = "arch_mem_counter";
497 }
498
499 start_count = arch_timer_read_counter();
500 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
501 cyclecounter.mult = clocksource_counter.mult;
502 cyclecounter.shift = clocksource_counter.shift;
503 timecounter_init(&timecounter, &cyclecounter, start_count);
504
505 /* 56 bits minimum, so we assume worst case rollover */
506 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
507}
508
509static void arch_timer_stop(struct clock_event_device *clk)
510{
511 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
512 clk->irq, smp_processor_id());
513
514 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
515 if (arch_timer_has_nonsecure_ppi())
516 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
517
518 clk->set_state_shutdown(clk);
519}
520
521static int arch_timer_cpu_notify(struct notifier_block *self,
522 unsigned long action, void *hcpu)
523{
524 /*
525 * Grab cpu pointer in each case to avoid spurious
526 * preemptible warnings
527 */
528 switch (action & ~CPU_TASKS_FROZEN) {
529 case CPU_STARTING:
530 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
531 break;
532 case CPU_DYING:
533 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
534 break;
535 }
536
537 return NOTIFY_OK;
538}
539
540static struct notifier_block arch_timer_cpu_nb = {
541 .notifier_call = arch_timer_cpu_notify,
542};
543
544#ifdef CONFIG_CPU_PM
545static unsigned int saved_cntkctl;
546static int arch_timer_cpu_pm_notify(struct notifier_block *self,
547 unsigned long action, void *hcpu)
548{
549 if (action == CPU_PM_ENTER)
550 saved_cntkctl = arch_timer_get_cntkctl();
551 else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
552 arch_timer_set_cntkctl(saved_cntkctl);
553 return NOTIFY_OK;
554}
555
556static struct notifier_block arch_timer_cpu_pm_notifier = {
557 .notifier_call = arch_timer_cpu_pm_notify,
558};
559
560static int __init arch_timer_cpu_pm_init(void)
561{
562 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
563}
564#else
565static int __init arch_timer_cpu_pm_init(void)
566{
567 return 0;
568}
569#endif
570
571static int __init arch_timer_register(void)
572{
573 int err;
574 int ppi;
575
576 arch_timer_evt = alloc_percpu(struct clock_event_device);
577 if (!arch_timer_evt) {
578 err = -ENOMEM;
579 goto out;
580 }
581
582 ppi = arch_timer_ppi[arch_timer_uses_ppi];
583 switch (arch_timer_uses_ppi) {
584 case VIRT_PPI:
585 err = request_percpu_irq(ppi, arch_timer_handler_virt,
586 "arch_timer", arch_timer_evt);
587 break;
588 case PHYS_SECURE_PPI:
589 case PHYS_NONSECURE_PPI:
590 err = request_percpu_irq(ppi, arch_timer_handler_phys,
591 "arch_timer", arch_timer_evt);
592 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
593 ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
594 err = request_percpu_irq(ppi, arch_timer_handler_phys,
595 "arch_timer", arch_timer_evt);
596 if (err)
597 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
598 arch_timer_evt);
599 }
600 break;
601 case HYP_PPI:
602 err = request_percpu_irq(ppi, arch_timer_handler_phys,
603 "arch_timer", arch_timer_evt);
604 break;
605 default:
606 BUG();
607 }
608
609 if (err) {
610 pr_err("arch_timer: can't register interrupt %d (%d)\n",
611 ppi, err);
612 goto out_free;
613 }
614
615 err = register_cpu_notifier(&arch_timer_cpu_nb);
616 if (err)
617 goto out_free_irq;
618
619 err = arch_timer_cpu_pm_init();
620 if (err)
621 goto out_unreg_notify;
622
623 /* Immediately configure the timer on the boot CPU */
624 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
625
626 return 0;
627
628out_unreg_notify:
629 unregister_cpu_notifier(&arch_timer_cpu_nb);
630out_free_irq:
631 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
632 if (arch_timer_has_nonsecure_ppi())
633 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
634 arch_timer_evt);
635
636out_free:
637 free_percpu(arch_timer_evt);
638out:
639 return err;
640}
641
642static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
643{
644 int ret;
645 irq_handler_t func;
646 struct arch_timer *t;
647
648 t = kzalloc(sizeof(*t), GFP_KERNEL);
649 if (!t)
650 return -ENOMEM;
651
652 t->base = base;
653 t->evt.irq = irq;
654 __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
655
656 if (arch_timer_mem_use_virtual)
657 func = arch_timer_handler_virt_mem;
658 else
659 func = arch_timer_handler_phys_mem;
660
661 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
662 if (ret) {
663 pr_err("arch_timer: Failed to request mem timer irq\n");
664 kfree(t);
665 }
666
667 return ret;
668}
669
670static const struct of_device_id arch_timer_of_match[] __initconst = {
671 { .compatible = "arm,armv7-timer", },
672 { .compatible = "arm,armv8-timer", },
673 {},
674};
675
676static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
677 { .compatible = "arm,armv7-timer-mem", },
678 {},
679};
680
681static bool __init
682arch_timer_needs_probing(int type, const struct of_device_id *matches)
683{
684 struct device_node *dn;
685 bool needs_probing = false;
686
687 dn = of_find_matching_node(NULL, matches);
688 if (dn && of_device_is_available(dn) && !(arch_timers_present & type))
689 needs_probing = true;
690 of_node_put(dn);
691
692 return needs_probing;
693}
694
695static void __init arch_timer_common_init(void)
696{
697 unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
698
699 /* Wait until both nodes are probed if we have two timers */
700 if ((arch_timers_present & mask) != mask) {
701 if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
702 return;
703 if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
704 return;
705 }
706
707 arch_timer_banner(arch_timers_present);
708 arch_counter_register(arch_timers_present);
709 arch_timer_arch_init();
710}
711
712static void __init arch_timer_init(void)
713{
714 /*
715 * If HYP mode is available, we know that the physical timer
716 * has been configured to be accessible from PL1. Use it, so
717 * that a guest can use the virtual timer instead.
718 *
719 * If no interrupt provided for virtual timer, we'll have to
720 * stick to the physical timer. It'd better be accessible...
721 *
722 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
723 * accesses to CNTP_*_EL1 registers are silently redirected to
724 * their CNTHP_*_EL2 counterparts, and use a different PPI
725 * number.
726 */
727 if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
728 bool has_ppi;
729
730 if (is_kernel_in_hyp_mode()) {
731 arch_timer_uses_ppi = HYP_PPI;
732 has_ppi = !!arch_timer_ppi[HYP_PPI];
733 } else {
734 arch_timer_uses_ppi = PHYS_SECURE_PPI;
735 has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] ||
736 !!arch_timer_ppi[PHYS_NONSECURE_PPI]);
737 }
738
739 if (!has_ppi) {
740 pr_warn("arch_timer: No interrupt available, giving up\n");
741 return;
742 }
743 }
744
745 arch_timer_register();
746 arch_timer_common_init();
747}
748
749static void __init arch_timer_of_init(struct device_node *np)
750{
751 int i;
752
753 if (arch_timers_present & ARCH_CP15_TIMER) {
754 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
755 return;
756 }
757
758 arch_timers_present |= ARCH_CP15_TIMER;
759 for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
760 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
761
762 arch_timer_detect_rate(NULL, np);
763
764 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
765
766 /*
767 * If we cannot rely on firmware initializing the timer registers then
768 * we should use the physical timers instead.
769 */
770 if (IS_ENABLED(CONFIG_ARM) &&
771 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
772 arch_timer_uses_ppi = PHYS_SECURE_PPI;
773
774 arch_timer_init();
775}
776CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
777CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
778
779static void __init arch_timer_mem_init(struct device_node *np)
780{
781 struct device_node *frame, *best_frame = NULL;
782 void __iomem *cntctlbase, *base;
783 unsigned int irq;
784 u32 cnttidr;
785
786 arch_timers_present |= ARCH_MEM_TIMER;
787 cntctlbase = of_iomap(np, 0);
788 if (!cntctlbase) {
789 pr_err("arch_timer: Can't find CNTCTLBase\n");
790 return;
791 }
792
793 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
794
795 /*
796 * Try to find a virtual capable frame. Otherwise fall back to a
797 * physical capable frame.
798 */
799 for_each_available_child_of_node(np, frame) {
800 int n;
801 u32 cntacr;
802
803 if (of_property_read_u32(frame, "frame-number", &n)) {
804 pr_err("arch_timer: Missing frame-number\n");
805 of_node_put(frame);
806 goto out;
807 }
808
809 /* Try enabling everything, and see what sticks */
810 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
811 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
812 writel_relaxed(cntacr, cntctlbase + CNTACR(n));
813 cntacr = readl_relaxed(cntctlbase + CNTACR(n));
814
815 if ((cnttidr & CNTTIDR_VIRT(n)) &&
816 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
817 of_node_put(best_frame);
818 best_frame = frame;
819 arch_timer_mem_use_virtual = true;
820 break;
821 }
822
823 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
824 continue;
825
826 of_node_put(best_frame);
827 best_frame = of_node_get(frame);
828 }
829
830 base = arch_counter_base = of_iomap(best_frame, 0);
831 if (!base) {
832 pr_err("arch_timer: Can't map frame's registers\n");
833 goto out;
834 }
835
836 if (arch_timer_mem_use_virtual)
837 irq = irq_of_parse_and_map(best_frame, 1);
838 else
839 irq = irq_of_parse_and_map(best_frame, 0);
840
841 if (!irq) {
842 pr_err("arch_timer: Frame missing %s irq",
843 arch_timer_mem_use_virtual ? "virt" : "phys");
844 goto out;
845 }
846
847 arch_timer_detect_rate(base, np);
848 arch_timer_mem_register(base, irq);
849 arch_timer_common_init();
850out:
851 iounmap(cntctlbase);
852 of_node_put(best_frame);
853}
854CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
855 arch_timer_mem_init);
856
857#ifdef CONFIG_ACPI
858static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
859{
860 int trigger, polarity;
861
862 if (!interrupt)
863 return 0;
864
865 trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
866 : ACPI_LEVEL_SENSITIVE;
867
868 polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
869 : ACPI_ACTIVE_HIGH;
870
871 return acpi_register_gsi(NULL, interrupt, trigger, polarity);
872}
873
874/* Initialize per-processor generic timer */
875static int __init arch_timer_acpi_init(struct acpi_table_header *table)
876{
877 struct acpi_table_gtdt *gtdt;
878
879 if (arch_timers_present & ARCH_CP15_TIMER) {
880 pr_warn("arch_timer: already initialized, skipping\n");
881 return -EINVAL;
882 }
883
884 gtdt = container_of(table, struct acpi_table_gtdt, header);
885
886 arch_timers_present |= ARCH_CP15_TIMER;
887
888 arch_timer_ppi[PHYS_SECURE_PPI] =
889 map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
890 gtdt->secure_el1_flags);
891
892 arch_timer_ppi[PHYS_NONSECURE_PPI] =
893 map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
894 gtdt->non_secure_el1_flags);
895
896 arch_timer_ppi[VIRT_PPI] =
897 map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
898 gtdt->virtual_timer_flags);
899
900 arch_timer_ppi[HYP_PPI] =
901 map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
902 gtdt->non_secure_el2_flags);
903
904 /* Get the frequency from CNTFRQ */
905 arch_timer_detect_rate(NULL, NULL);
906
907 /* Always-on capability */
908 arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
909
910 arch_timer_init();
911 return 0;
912}
913CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
914#endif