1/*
  2 * linux/arch/arm/mach-pxa/cm-x255.c
  3 *
  4 * Copyright (C) 2007, 2008 CompuLab, Ltd.
  5 * Mike Rapoport <mike@compulab.co.il>
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License version 2 as
  9 * published by the Free Software Foundation.
 10 */
 11
 12#include <linux/platform_device.h>
 13#include <linux/irq.h>
 14#include <linux/mtd/partitions.h>
 15#include <linux/mtd/physmap.h>
 16#include <linux/mtd/nand-gpio.h>
 17
 18#include <linux/spi/spi.h>
 19#include <linux/spi/pxa2xx_spi.h>
 20
 21#include <asm/mach/arch.h>
 22#include <asm/mach-types.h>
 23#include <asm/mach/map.h>
 24
 25#include "pxa25x.h"
 26
 27#include "generic.h"
 28
 29#define GPIO_NAND_CS	(5)
 30#define GPIO_NAND_ALE	(4)
 31#define GPIO_NAND_CLE	(3)
 32#define GPIO_NAND_RB	(10)
 33
 34static unsigned long cmx255_pin_config[] = {
 35	/* AC'97 */
 36	GPIO28_AC97_BITCLK,
 37	GPIO29_AC97_SDATA_IN_0,
 38	GPIO30_AC97_SDATA_OUT,
 39	GPIO31_AC97_SYNC,
 40
 41	/* BTUART */
 42	GPIO42_BTUART_RXD,
 43	GPIO43_BTUART_TXD,
 44	GPIO44_BTUART_CTS,
 45	GPIO45_BTUART_RTS,
 46
 47	/* STUART */
 48	GPIO46_STUART_RXD,
 49	GPIO47_STUART_TXD,
 50
 51	/* LCD */
 52	GPIOxx_LCD_TFT_16BPP,
 53
 54	/* SSP1 */
 55	GPIO23_SSP1_SCLK,
 56	GPIO24_SSP1_SFRM,
 57	GPIO25_SSP1_TXD,
 58	GPIO26_SSP1_RXD,
 59
 60	/* SSP2 */
 61	GPIO81_SSP2_CLK_OUT,
 62	GPIO82_SSP2_FRM_OUT,
 63	GPIO83_SSP2_TXD,
 64	GPIO84_SSP2_RXD,
 65
 66	/* PC Card */
 67	GPIO48_nPOE,
 68	GPIO49_nPWE,
 69	GPIO50_nPIOR,
 70	GPIO51_nPIOW,
 71	GPIO52_nPCE_1,
 72	GPIO53_nPCE_2,
 73	GPIO54_nPSKTSEL,
 74	GPIO55_nPREG,
 75	GPIO56_nPWAIT,
 76	GPIO57_nIOIS16,
 77
 78	/* SDRAM and local bus */
 79	GPIO15_nCS_1,
 80	GPIO78_nCS_2,
 81	GPIO79_nCS_3,
 82	GPIO80_nCS_4,
 83	GPIO33_nCS_5,
 84	GPIO18_RDY,
 85
 86	/* GPIO */
 87	GPIO0_GPIO	| WAKEUP_ON_EDGE_BOTH,
 88	GPIO9_GPIO,				/* PC card reset */
 89
 90	/* NAND controls */
 91	GPIO5_GPIO	| MFP_LPM_DRIVE_HIGH,	/* NAND CE# */
 92	GPIO4_GPIO	| MFP_LPM_DRIVE_LOW,	/* NAND ALE */
 93	GPIO3_GPIO	| MFP_LPM_DRIVE_LOW,	/* NAND CLE */
 94	GPIO10_GPIO,				/* NAND Ready/Busy */
 95
 96	/* interrupts */
 97	GPIO22_GPIO,	/* DM9000 interrupt */
 98};
 99
100#if defined(CONFIG_SPI_PXA2XX)
101static struct pxa2xx_spi_master pxa_ssp_master_info = {
102	.num_chipselect	= 1,
103};
104
105static struct spi_board_info spi_board_info[] __initdata = {
106	[0] = {
107		.modalias	= "rtc-max6902",
108		.max_speed_hz	= 1000000,
109		.bus_num	= 1,
110		.chip_select	= 0,
111	},
112};
113
114static void __init cmx255_init_rtc(void)
115{
116	pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
117	spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
118}
119#else
120static inline void cmx255_init_rtc(void) {}
121#endif
122
123#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
124static struct mtd_partition cmx255_nor_partitions[] = {
125	{
126		.name		= "ARMmon",
127		.size		= 0x00030000,
128		.offset		= 0,
129		.mask_flags	= MTD_WRITEABLE  /* force read-only */
130	} , {
131		.name		= "ARMmon setup block",
132		.size		= 0x00010000,
133		.offset		= MTDPART_OFS_APPEND,
134		.mask_flags	= MTD_WRITEABLE  /* force read-only */
135	} , {
136		.name		= "kernel",
137		.size		= 0x00160000,
138		.offset		= MTDPART_OFS_APPEND,
139	} , {
140		.name		= "ramdisk",
141		.size		= MTDPART_SIZ_FULL,
142		.offset		= MTDPART_OFS_APPEND
143	}
144};
145
146static struct physmap_flash_data cmx255_nor_flash_data[] = {
147	{
148		.width		= 2,	/* bankwidth in bytes */
149		.parts		= cmx255_nor_partitions,
150		.nr_parts	= ARRAY_SIZE(cmx255_nor_partitions)
151	}
152};
153
154static struct resource cmx255_nor_resource = {
155	.start	= PXA_CS0_PHYS,
156	.end	= PXA_CS0_PHYS + SZ_8M - 1,
157	.flags	= IORESOURCE_MEM,
158};
159
160static struct platform_device cmx255_nor = {
161	.name	= "physmap-flash",
162	.id	= -1,
163	.dev	= {
164		.platform_data = cmx255_nor_flash_data,
165	},
166	.resource = &cmx255_nor_resource,
167	.num_resources = 1,
168};
169
170static void __init cmx255_init_nor(void)
171{
172	platform_device_register(&cmx255_nor);
173}
174#else
175static inline void cmx255_init_nor(void) {}
176#endif
177
178#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
179static struct resource cmx255_nand_resource[] = {
180	[0] = {
181		.start = PXA_CS1_PHYS,
182		.end   = PXA_CS1_PHYS + 11,
183		.flags = IORESOURCE_MEM,
184	},
185	[1] = {
186		.start = PXA_CS5_PHYS,
187		.end   = PXA_CS5_PHYS + 3,
188		.flags = IORESOURCE_MEM,
189	},
190};
191
192static struct mtd_partition cmx255_nand_parts[] = {
193	[0] = {
194		.name	= "cmx255-nand",
195		.size	= MTDPART_SIZ_FULL,
196		.offset	= 0,
197	},
198};
199
200static struct gpio_nand_platdata cmx255_nand_platdata = {
201	.gpio_nce = GPIO_NAND_CS,
202	.gpio_cle = GPIO_NAND_CLE,
203	.gpio_ale = GPIO_NAND_ALE,
204	.gpio_rdy = GPIO_NAND_RB,
205	.gpio_nwp = -1,
206	.parts = cmx255_nand_parts,
207	.num_parts = ARRAY_SIZE(cmx255_nand_parts),
208	.chip_delay = 25,
209};
210
211static struct platform_device cmx255_nand = {
212	.name		= "gpio-nand",
213	.num_resources	= ARRAY_SIZE(cmx255_nand_resource),
214	.resource	= cmx255_nand_resource,
215	.id		= -1,
216	.dev		= {
217		.platform_data = &cmx255_nand_platdata,
218	}
219};
220
221static void __init cmx255_init_nand(void)
222{
223	platform_device_register(&cmx255_nand);
224}
225#else
226static inline void cmx255_init_nand(void) {}
227#endif
228
229void __init cmx255_init(void)
230{
231	pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
232
233	cmx255_init_rtc();
234	cmx255_init_nor();
235	cmx255_init_nand();
236}