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1/*
2 * linux/arch/arm/mach-omap1/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/suspend.h>
39#include <linux/sched.h>
40#include <linux/debugfs.h>
41#include <linux/seq_file.h>
42#include <linux/interrupt.h>
43#include <linux/sysfs.h>
44#include <linux/module.h>
45#include <linux/io.h>
46#include <linux/atomic.h>
47#include <linux/cpu.h>
48
49#include <asm/fncpy.h>
50#include <asm/system_misc.h>
51#include <asm/irq.h>
52#include <asm/mach/time.h>
53#include <asm/mach/irq.h>
54
55#include <linux/soc/ti/omap1-io.h>
56#include "tc.h"
57#include <linux/omap-dma.h>
58#include <clocksource/timer-ti-dm.h>
59
60#include "hardware.h"
61#include "mux.h"
62#include "irqs.h"
63#include "iomap.h"
64#include "clock.h"
65#include "pm.h"
66#include "soc.h"
67#include "sram.h"
68
69static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
70static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
71static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
72static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
73static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
74
75static unsigned short enable_dyn_sleep;
76
77static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
78 char *buf)
79{
80 return sprintf(buf, "%hu\n", enable_dyn_sleep);
81}
82
83static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
84 const char * buf, size_t n)
85{
86 unsigned short value;
87 if (sscanf(buf, "%hu", &value) != 1 ||
88 (value != 0 && value != 1) ||
89 (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
90 pr_err("idle_sleep_store: Invalid value\n");
91 return -EINVAL;
92 }
93 enable_dyn_sleep = value;
94 return n;
95}
96
97static struct kobj_attribute sleep_while_idle_attr =
98 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
99
100
101static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
102
103/*
104 * Let's power down on idle, but only if we are really
105 * idle, because once we start down the path of
106 * going idle we continue to do idle even if we get
107 * a clock tick interrupt . .
108 */
109void omap1_pm_idle(void)
110{
111 extern __u32 arm_idlect1_mask;
112 __u32 use_idlect1 = arm_idlect1_mask;
113
114 local_fiq_disable();
115
116#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
117 use_idlect1 = use_idlect1 & ~(1 << 9);
118#endif
119
120#ifdef CONFIG_OMAP_DM_TIMER
121 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
122#endif
123
124 if (omap_dma_running())
125 use_idlect1 &= ~(1 << 6);
126
127 /*
128 * We should be able to remove the do_sleep variable and multiple
129 * tests above as soon as drivers, timer and DMA code have been fixed.
130 * Even the sleep block count should become obsolete.
131 */
132 if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
133
134 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
135 if (cpu_is_omap15xx())
136 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
137 else
138 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
139 omap_writel(use_idlect1, ARM_IDLECT1);
140 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
141 omap_writel(saved_idlect1, ARM_IDLECT1);
142
143 local_fiq_enable();
144 return;
145 }
146 omap_sram_suspend(omap_readl(ARM_IDLECT1),
147 omap_readl(ARM_IDLECT2));
148
149 local_fiq_enable();
150}
151
152/*
153 * Configuration of the wakeup event is board specific. For the
154 * moment we put it into this helper function. Later it may move
155 * to board specific files.
156 */
157static void omap_pm_wakeup_setup(void)
158{
159 u32 level1_wake = 0;
160 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
161
162 /*
163 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
164 * and the L2 wakeup interrupts: keypad and UART2. Note that the
165 * drivers must still separately call omap_set_gpio_wakeup() to
166 * wake up to a GPIO interrupt.
167 */
168 if (cpu_is_omap15xx())
169 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
170 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
171 else if (cpu_is_omap16xx())
172 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
173 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
174
175 omap_writel(~level1_wake, OMAP_IH1_MIR);
176
177 if (cpu_is_omap15xx()) {
178 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
179 omap_writel(~level2_wake, OMAP_IH2_MIR);
180 } else if (cpu_is_omap16xx()) {
181 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
182 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
183
184 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
185 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
186 OMAP_IH2_1_MIR);
187 omap_writel(~0x0, OMAP_IH2_2_MIR);
188 omap_writel(~0x0, OMAP_IH2_3_MIR);
189 }
190
191 /* New IRQ agreement, recalculate in cascade order */
192 omap_writel(1, OMAP_IH2_CONTROL);
193 omap_writel(1, OMAP_IH1_CONTROL);
194}
195
196#define EN_DSPCK 13 /* ARM_CKCTL */
197#define EN_APICK 6 /* ARM_IDLECT2 */
198#define DSP_EN 1 /* ARM_RSTCT1 */
199
200void omap1_pm_suspend(void)
201{
202 unsigned long arg0 = 0, arg1 = 0;
203
204 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
205 omap_rev());
206
207 omap_serial_wake_trigger(1);
208
209 if (!cpu_is_omap15xx())
210 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
211
212 /*
213 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
214 */
215
216 local_irq_disable();
217 local_fiq_disable();
218
219 /*
220 * Step 2: save registers
221 *
222 * The omap is a strange/beautiful device. The caches, memory
223 * and register state are preserved across power saves.
224 * We have to save and restore very little register state to
225 * idle the omap.
226 *
227 * Save interrupt, MPUI, ARM and UPLD control registers.
228 */
229
230 if (cpu_is_omap15xx()) {
231 MPUI1510_SAVE(OMAP_IH1_MIR);
232 MPUI1510_SAVE(OMAP_IH2_MIR);
233 MPUI1510_SAVE(MPUI_CTRL);
234 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
235 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
236 MPUI1510_SAVE(EMIFS_CONFIG);
237 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
238 } else if (cpu_is_omap16xx()) {
239 MPUI1610_SAVE(OMAP_IH1_MIR);
240 MPUI1610_SAVE(OMAP_IH2_0_MIR);
241 MPUI1610_SAVE(OMAP_IH2_1_MIR);
242 MPUI1610_SAVE(OMAP_IH2_2_MIR);
243 MPUI1610_SAVE(OMAP_IH2_3_MIR);
244 MPUI1610_SAVE(MPUI_CTRL);
245 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
246 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
247 MPUI1610_SAVE(EMIFS_CONFIG);
248 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
249 }
250
251 ARM_SAVE(ARM_CKCTL);
252 ARM_SAVE(ARM_IDLECT1);
253 ARM_SAVE(ARM_IDLECT2);
254 if (!(cpu_is_omap15xx()))
255 ARM_SAVE(ARM_IDLECT3);
256 ARM_SAVE(ARM_EWUPCT);
257 ARM_SAVE(ARM_RSTCT1);
258 ARM_SAVE(ARM_RSTCT2);
259 ARM_SAVE(ARM_SYSST);
260 ULPD_SAVE(ULPD_CLOCK_CTRL);
261 ULPD_SAVE(ULPD_STATUS_REQ);
262
263 /* (Step 3 removed - we now allow deep sleep by default) */
264
265 /*
266 * Step 4: OMAP DSP Shutdown
267 */
268
269 /* stop DSP */
270 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
271
272 /* shut down dsp_ck */
273 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
274
275 /* temporarily enabling api_ck to access DSP registers */
276 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
277
278 /* save DSP registers */
279 DSP_SAVE(DSP_IDLECT2);
280
281 /* Stop all DSP domain clocks */
282 __raw_writew(0, DSP_IDLECT2);
283
284 /*
285 * Step 5: Wakeup Event Setup
286 */
287
288 omap_pm_wakeup_setup();
289
290 /*
291 * Step 6: ARM and Traffic controller shutdown
292 */
293
294 /* disable ARM watchdog */
295 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
296 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
297
298 /*
299 * Step 6b: ARM and Traffic controller shutdown
300 *
301 * Step 6 continues here. Prepare jump to power management
302 * assembly code in internal SRAM.
303 *
304 * Since the omap_cpu_suspend routine has been copied to
305 * SRAM, we'll do an indirect procedure call to it and pass the
306 * contents of arm_idlect1 and arm_idlect2 so it can restore
307 * them when it wakes up and it will return.
308 */
309
310 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
311 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
312
313 /*
314 * Step 6c: ARM and Traffic controller shutdown
315 *
316 * Jump to assembly code. The processor will stay there
317 * until wake up.
318 */
319 omap_sram_suspend(arg0, arg1);
320
321 /*
322 * If we are here, processor is woken up!
323 */
324
325 /*
326 * Restore DSP clocks
327 */
328
329 /* again temporarily enabling api_ck to access DSP registers */
330 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
331
332 /* Restore DSP domain clocks */
333 DSP_RESTORE(DSP_IDLECT2);
334
335 /*
336 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
337 */
338
339 if (!(cpu_is_omap15xx()))
340 ARM_RESTORE(ARM_IDLECT3);
341 ARM_RESTORE(ARM_CKCTL);
342 ARM_RESTORE(ARM_EWUPCT);
343 ARM_RESTORE(ARM_RSTCT1);
344 ARM_RESTORE(ARM_RSTCT2);
345 ARM_RESTORE(ARM_SYSST);
346 ULPD_RESTORE(ULPD_CLOCK_CTRL);
347 ULPD_RESTORE(ULPD_STATUS_REQ);
348
349 if (cpu_is_omap15xx()) {
350 MPUI1510_RESTORE(MPUI_CTRL);
351 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
352 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
353 MPUI1510_RESTORE(EMIFS_CONFIG);
354 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
355 MPUI1510_RESTORE(OMAP_IH1_MIR);
356 MPUI1510_RESTORE(OMAP_IH2_MIR);
357 } else if (cpu_is_omap16xx()) {
358 MPUI1610_RESTORE(MPUI_CTRL);
359 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
360 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
361 MPUI1610_RESTORE(EMIFS_CONFIG);
362 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
363
364 MPUI1610_RESTORE(OMAP_IH1_MIR);
365 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
366 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
367 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
368 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
369 }
370
371 if (!cpu_is_omap15xx())
372 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
373
374 /*
375 * Re-enable interrupts
376 */
377
378 local_irq_enable();
379 local_fiq_enable();
380
381 omap_serial_wake_trigger(0);
382
383 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
384 omap_rev());
385}
386
387#ifdef CONFIG_DEBUG_FS
388/*
389 * Read system PM registers for debugging
390 */
391static int omap_pm_debug_show(struct seq_file *m, void *v)
392{
393 ARM_SAVE(ARM_CKCTL);
394 ARM_SAVE(ARM_IDLECT1);
395 ARM_SAVE(ARM_IDLECT2);
396 if (!(cpu_is_omap15xx()))
397 ARM_SAVE(ARM_IDLECT3);
398 ARM_SAVE(ARM_EWUPCT);
399 ARM_SAVE(ARM_RSTCT1);
400 ARM_SAVE(ARM_RSTCT2);
401 ARM_SAVE(ARM_SYSST);
402
403 ULPD_SAVE(ULPD_IT_STATUS);
404 ULPD_SAVE(ULPD_CLOCK_CTRL);
405 ULPD_SAVE(ULPD_SOFT_REQ);
406 ULPD_SAVE(ULPD_STATUS_REQ);
407 ULPD_SAVE(ULPD_DPLL_CTRL);
408 ULPD_SAVE(ULPD_POWER_CTRL);
409
410 if (cpu_is_omap15xx()) {
411 MPUI1510_SAVE(MPUI_CTRL);
412 MPUI1510_SAVE(MPUI_DSP_STATUS);
413 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
414 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
415 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
416 MPUI1510_SAVE(EMIFS_CONFIG);
417 } else if (cpu_is_omap16xx()) {
418 MPUI1610_SAVE(MPUI_CTRL);
419 MPUI1610_SAVE(MPUI_DSP_STATUS);
420 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
421 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
422 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
423 MPUI1610_SAVE(EMIFS_CONFIG);
424 }
425
426 seq_printf(m,
427 "ARM_CKCTL_REG: 0x%-8x \n"
428 "ARM_IDLECT1_REG: 0x%-8x \n"
429 "ARM_IDLECT2_REG: 0x%-8x \n"
430 "ARM_IDLECT3_REG: 0x%-8x \n"
431 "ARM_EWUPCT_REG: 0x%-8x \n"
432 "ARM_RSTCT1_REG: 0x%-8x \n"
433 "ARM_RSTCT2_REG: 0x%-8x \n"
434 "ARM_SYSST_REG: 0x%-8x \n"
435 "ULPD_IT_STATUS_REG: 0x%-4x \n"
436 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
437 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
438 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
439 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
440 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
441 ARM_SHOW(ARM_CKCTL),
442 ARM_SHOW(ARM_IDLECT1),
443 ARM_SHOW(ARM_IDLECT2),
444 ARM_SHOW(ARM_IDLECT3),
445 ARM_SHOW(ARM_EWUPCT),
446 ARM_SHOW(ARM_RSTCT1),
447 ARM_SHOW(ARM_RSTCT2),
448 ARM_SHOW(ARM_SYSST),
449 ULPD_SHOW(ULPD_IT_STATUS),
450 ULPD_SHOW(ULPD_CLOCK_CTRL),
451 ULPD_SHOW(ULPD_SOFT_REQ),
452 ULPD_SHOW(ULPD_DPLL_CTRL),
453 ULPD_SHOW(ULPD_STATUS_REQ),
454 ULPD_SHOW(ULPD_POWER_CTRL));
455
456 if (cpu_is_omap15xx()) {
457 seq_printf(m,
458 "MPUI1510_CTRL_REG 0x%-8x \n"
459 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
460 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
461 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
462 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
463 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
464 MPUI1510_SHOW(MPUI_CTRL),
465 MPUI1510_SHOW(MPUI_DSP_STATUS),
466 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
467 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
468 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
469 MPUI1510_SHOW(EMIFS_CONFIG));
470 } else if (cpu_is_omap16xx()) {
471 seq_printf(m,
472 "MPUI1610_CTRL_REG 0x%-8x \n"
473 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
474 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
475 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
476 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
477 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
478 MPUI1610_SHOW(MPUI_CTRL),
479 MPUI1610_SHOW(MPUI_DSP_STATUS),
480 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
481 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
482 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
483 MPUI1610_SHOW(EMIFS_CONFIG));
484 }
485
486 return 0;
487}
488
489DEFINE_SHOW_ATTRIBUTE(omap_pm_debug);
490
491static void omap_pm_init_debugfs(void)
492{
493 struct dentry *d;
494
495 d = debugfs_create_dir("pm_debug", NULL);
496 debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, d, NULL,
497 &omap_pm_debug_fops);
498}
499
500#endif /* CONFIG_DEBUG_FS */
501
502/*
503 * omap_pm_prepare - Do preliminary suspend work.
504 *
505 */
506static int omap_pm_prepare(void)
507{
508 /* We cannot sleep in idle until we have resumed */
509 cpu_idle_poll_ctrl(true);
510 return 0;
511}
512
513
514/*
515 * omap_pm_enter - Actually enter a sleep state.
516 * @state: State we're entering.
517 *
518 */
519
520static int omap_pm_enter(suspend_state_t state)
521{
522 switch (state)
523 {
524 case PM_SUSPEND_MEM:
525 omap1_pm_suspend();
526 break;
527 default:
528 return -EINVAL;
529 }
530
531 return 0;
532}
533
534
535/**
536 * omap_pm_finish - Finish up suspend sequence.
537 *
538 * This is called after we wake back up (or if entering the sleep state
539 * failed).
540 */
541
542static void omap_pm_finish(void)
543{
544 cpu_idle_poll_ctrl(false);
545}
546
547
548static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
549{
550 return IRQ_HANDLED;
551}
552
553
554
555static const struct platform_suspend_ops omap_pm_ops = {
556 .prepare = omap_pm_prepare,
557 .enter = omap_pm_enter,
558 .finish = omap_pm_finish,
559 .valid = suspend_valid_only_mem,
560};
561
562static int __init omap_pm_init(void)
563{
564 int error = 0;
565 int irq;
566
567 if (!cpu_class_is_omap1())
568 return -ENODEV;
569
570 pr_info("Power Management for TI OMAP.\n");
571
572 if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
573 pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
574
575 if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
576 pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
577
578 if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
579 IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
580 /* OMAP16xx only */
581 pr_info("OMAP1 PM: sleep states in idle enabled\n");
582 enable_dyn_sleep = 1;
583 }
584
585 /*
586 * We copy the assembler sleep/wakeup routines to SRAM.
587 * These routines need to be in SRAM as that's the only
588 * memory the MPU can see when it wakes up.
589 */
590 if (cpu_is_omap15xx()) {
591 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
592 omap1510_cpu_suspend_sz);
593 } else if (cpu_is_omap16xx()) {
594 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
595 omap1610_cpu_suspend_sz);
596 }
597
598 if (omap_sram_suspend == NULL) {
599 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
600 return -ENODEV;
601 }
602
603 arm_pm_idle = omap1_pm_idle;
604
605 if (cpu_is_omap16xx())
606 irq = INT_1610_WAKE_UP_REQ;
607 else
608 irq = -1;
609
610 if (irq >= 0) {
611 if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
612 pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
613 }
614
615 /* Program new power ramp-up time
616 * (0 for most boards since we don't lower voltage when in deep sleep)
617 */
618 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
619
620 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
621 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
622
623 /* Configure IDLECT3 */
624 if (cpu_is_omap16xx())
625 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
626
627 suspend_set_ops(&omap_pm_ops);
628
629#ifdef CONFIG_DEBUG_FS
630 omap_pm_init_debugfs();
631#endif
632
633 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
634 if (error)
635 pr_err("sysfs_create_file failed: %d\n", error);
636
637 if (cpu_is_omap16xx()) {
638 /* configure LOW_PWR pin */
639 omap_cfg_reg(T20_1610_LOW_PWR);
640 }
641
642 return error;
643}
644__initcall(omap_pm_init);
1/*
2 * linux/arch/arm/mach-omap1/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/suspend.h>
39#include <linux/sched.h>
40#include <linux/debugfs.h>
41#include <linux/seq_file.h>
42#include <linux/interrupt.h>
43#include <linux/sysfs.h>
44#include <linux/module.h>
45#include <linux/io.h>
46#include <linux/atomic.h>
47#include <linux/cpu.h>
48
49#include <asm/fncpy.h>
50#include <asm/system_misc.h>
51#include <asm/irq.h>
52#include <asm/mach/time.h>
53#include <asm/mach/irq.h>
54
55#include <mach/tc.h>
56#include <mach/mux.h>
57#include <linux/omap-dma.h>
58#include <plat/dmtimer.h>
59
60#include <mach/irqs.h>
61
62#include "iomap.h"
63#include "clock.h"
64#include "pm.h"
65#include "soc.h"
66#include "sram.h"
67
68static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
69static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
70static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
71static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
72static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
73static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
74
75static unsigned short enable_dyn_sleep;
76
77static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
78 char *buf)
79{
80 return sprintf(buf, "%hu\n", enable_dyn_sleep);
81}
82
83static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
84 const char * buf, size_t n)
85{
86 unsigned short value;
87 if (sscanf(buf, "%hu", &value) != 1 ||
88 (value != 0 && value != 1) ||
89 (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
90 pr_err("idle_sleep_store: Invalid value\n");
91 return -EINVAL;
92 }
93 enable_dyn_sleep = value;
94 return n;
95}
96
97static struct kobj_attribute sleep_while_idle_attr =
98 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
99
100
101static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
102
103/*
104 * Let's power down on idle, but only if we are really
105 * idle, because once we start down the path of
106 * going idle we continue to do idle even if we get
107 * a clock tick interrupt . .
108 */
109void omap1_pm_idle(void)
110{
111 extern __u32 arm_idlect1_mask;
112 __u32 use_idlect1 = arm_idlect1_mask;
113
114 local_fiq_disable();
115
116#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
117 use_idlect1 = use_idlect1 & ~(1 << 9);
118#endif
119
120#ifdef CONFIG_OMAP_DM_TIMER
121 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
122#endif
123
124 if (omap_dma_running())
125 use_idlect1 &= ~(1 << 6);
126
127 /*
128 * We should be able to remove the do_sleep variable and multiple
129 * tests above as soon as drivers, timer and DMA code have been fixed.
130 * Even the sleep block count should become obsolete.
131 */
132 if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
133
134 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
135 if (cpu_is_omap15xx())
136 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
137 else
138 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
139 omap_writel(use_idlect1, ARM_IDLECT1);
140 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
141 omap_writel(saved_idlect1, ARM_IDLECT1);
142
143 local_fiq_enable();
144 return;
145 }
146 omap_sram_suspend(omap_readl(ARM_IDLECT1),
147 omap_readl(ARM_IDLECT2));
148
149 local_fiq_enable();
150}
151
152/*
153 * Configuration of the wakeup event is board specific. For the
154 * moment we put it into this helper function. Later it may move
155 * to board specific files.
156 */
157static void omap_pm_wakeup_setup(void)
158{
159 u32 level1_wake = 0;
160 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
161
162 /*
163 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
164 * and the L2 wakeup interrupts: keypad and UART2. Note that the
165 * drivers must still separately call omap_set_gpio_wakeup() to
166 * wake up to a GPIO interrupt.
167 */
168 if (cpu_is_omap7xx())
169 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
170 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
171 else if (cpu_is_omap15xx())
172 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
173 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
174 else if (cpu_is_omap16xx())
175 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
176 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
177
178 omap_writel(~level1_wake, OMAP_IH1_MIR);
179
180 if (cpu_is_omap7xx()) {
181 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
182 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
183 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
184 OMAP_IH2_1_MIR);
185 } else if (cpu_is_omap15xx()) {
186 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
187 omap_writel(~level2_wake, OMAP_IH2_MIR);
188 } else if (cpu_is_omap16xx()) {
189 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
190 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
191
192 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
193 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
194 OMAP_IH2_1_MIR);
195 omap_writel(~0x0, OMAP_IH2_2_MIR);
196 omap_writel(~0x0, OMAP_IH2_3_MIR);
197 }
198
199 /* New IRQ agreement, recalculate in cascade order */
200 omap_writel(1, OMAP_IH2_CONTROL);
201 omap_writel(1, OMAP_IH1_CONTROL);
202}
203
204#define EN_DSPCK 13 /* ARM_CKCTL */
205#define EN_APICK 6 /* ARM_IDLECT2 */
206#define DSP_EN 1 /* ARM_RSTCT1 */
207
208void omap1_pm_suspend(void)
209{
210 unsigned long arg0 = 0, arg1 = 0;
211
212 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
213 omap_rev());
214
215 omap_serial_wake_trigger(1);
216
217 if (!cpu_is_omap15xx())
218 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
219
220 /*
221 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
222 */
223
224 local_irq_disable();
225 local_fiq_disable();
226
227 /*
228 * Step 2: save registers
229 *
230 * The omap is a strange/beautiful device. The caches, memory
231 * and register state are preserved across power saves.
232 * We have to save and restore very little register state to
233 * idle the omap.
234 *
235 * Save interrupt, MPUI, ARM and UPLD control registers.
236 */
237
238 if (cpu_is_omap7xx()) {
239 MPUI7XX_SAVE(OMAP_IH1_MIR);
240 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
241 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
242 MPUI7XX_SAVE(MPUI_CTRL);
243 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
244 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
245 MPUI7XX_SAVE(EMIFS_CONFIG);
246 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
247
248 } else if (cpu_is_omap15xx()) {
249 MPUI1510_SAVE(OMAP_IH1_MIR);
250 MPUI1510_SAVE(OMAP_IH2_MIR);
251 MPUI1510_SAVE(MPUI_CTRL);
252 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
253 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
254 MPUI1510_SAVE(EMIFS_CONFIG);
255 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
256 } else if (cpu_is_omap16xx()) {
257 MPUI1610_SAVE(OMAP_IH1_MIR);
258 MPUI1610_SAVE(OMAP_IH2_0_MIR);
259 MPUI1610_SAVE(OMAP_IH2_1_MIR);
260 MPUI1610_SAVE(OMAP_IH2_2_MIR);
261 MPUI1610_SAVE(OMAP_IH2_3_MIR);
262 MPUI1610_SAVE(MPUI_CTRL);
263 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
264 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
265 MPUI1610_SAVE(EMIFS_CONFIG);
266 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
267 }
268
269 ARM_SAVE(ARM_CKCTL);
270 ARM_SAVE(ARM_IDLECT1);
271 ARM_SAVE(ARM_IDLECT2);
272 if (!(cpu_is_omap15xx()))
273 ARM_SAVE(ARM_IDLECT3);
274 ARM_SAVE(ARM_EWUPCT);
275 ARM_SAVE(ARM_RSTCT1);
276 ARM_SAVE(ARM_RSTCT2);
277 ARM_SAVE(ARM_SYSST);
278 ULPD_SAVE(ULPD_CLOCK_CTRL);
279 ULPD_SAVE(ULPD_STATUS_REQ);
280
281 /* (Step 3 removed - we now allow deep sleep by default) */
282
283 /*
284 * Step 4: OMAP DSP Shutdown
285 */
286
287 /* stop DSP */
288 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
289
290 /* shut down dsp_ck */
291 if (!cpu_is_omap7xx())
292 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
293
294 /* temporarily enabling api_ck to access DSP registers */
295 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
296
297 /* save DSP registers */
298 DSP_SAVE(DSP_IDLECT2);
299
300 /* Stop all DSP domain clocks */
301 __raw_writew(0, DSP_IDLECT2);
302
303 /*
304 * Step 5: Wakeup Event Setup
305 */
306
307 omap_pm_wakeup_setup();
308
309 /*
310 * Step 6: ARM and Traffic controller shutdown
311 */
312
313 /* disable ARM watchdog */
314 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
315 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
316
317 /*
318 * Step 6b: ARM and Traffic controller shutdown
319 *
320 * Step 6 continues here. Prepare jump to power management
321 * assembly code in internal SRAM.
322 *
323 * Since the omap_cpu_suspend routine has been copied to
324 * SRAM, we'll do an indirect procedure call to it and pass the
325 * contents of arm_idlect1 and arm_idlect2 so it can restore
326 * them when it wakes up and it will return.
327 */
328
329 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
330 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
331
332 /*
333 * Step 6c: ARM and Traffic controller shutdown
334 *
335 * Jump to assembly code. The processor will stay there
336 * until wake up.
337 */
338 omap_sram_suspend(arg0, arg1);
339
340 /*
341 * If we are here, processor is woken up!
342 */
343
344 /*
345 * Restore DSP clocks
346 */
347
348 /* again temporarily enabling api_ck to access DSP registers */
349 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
350
351 /* Restore DSP domain clocks */
352 DSP_RESTORE(DSP_IDLECT2);
353
354 /*
355 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
356 */
357
358 if (!(cpu_is_omap15xx()))
359 ARM_RESTORE(ARM_IDLECT3);
360 ARM_RESTORE(ARM_CKCTL);
361 ARM_RESTORE(ARM_EWUPCT);
362 ARM_RESTORE(ARM_RSTCT1);
363 ARM_RESTORE(ARM_RSTCT2);
364 ARM_RESTORE(ARM_SYSST);
365 ULPD_RESTORE(ULPD_CLOCK_CTRL);
366 ULPD_RESTORE(ULPD_STATUS_REQ);
367
368 if (cpu_is_omap7xx()) {
369 MPUI7XX_RESTORE(EMIFS_CONFIG);
370 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
371 MPUI7XX_RESTORE(OMAP_IH1_MIR);
372 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
373 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
374 } else if (cpu_is_omap15xx()) {
375 MPUI1510_RESTORE(MPUI_CTRL);
376 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
377 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
378 MPUI1510_RESTORE(EMIFS_CONFIG);
379 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
380 MPUI1510_RESTORE(OMAP_IH1_MIR);
381 MPUI1510_RESTORE(OMAP_IH2_MIR);
382 } else if (cpu_is_omap16xx()) {
383 MPUI1610_RESTORE(MPUI_CTRL);
384 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
385 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
386 MPUI1610_RESTORE(EMIFS_CONFIG);
387 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
388
389 MPUI1610_RESTORE(OMAP_IH1_MIR);
390 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
391 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
392 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
393 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
394 }
395
396 if (!cpu_is_omap15xx())
397 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
398
399 /*
400 * Re-enable interrupts
401 */
402
403 local_irq_enable();
404 local_fiq_enable();
405
406 omap_serial_wake_trigger(0);
407
408 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
409 omap_rev());
410}
411
412#ifdef CONFIG_DEBUG_FS
413/*
414 * Read system PM registers for debugging
415 */
416static int omap_pm_debug_show(struct seq_file *m, void *v)
417{
418 ARM_SAVE(ARM_CKCTL);
419 ARM_SAVE(ARM_IDLECT1);
420 ARM_SAVE(ARM_IDLECT2);
421 if (!(cpu_is_omap15xx()))
422 ARM_SAVE(ARM_IDLECT3);
423 ARM_SAVE(ARM_EWUPCT);
424 ARM_SAVE(ARM_RSTCT1);
425 ARM_SAVE(ARM_RSTCT2);
426 ARM_SAVE(ARM_SYSST);
427
428 ULPD_SAVE(ULPD_IT_STATUS);
429 ULPD_SAVE(ULPD_CLOCK_CTRL);
430 ULPD_SAVE(ULPD_SOFT_REQ);
431 ULPD_SAVE(ULPD_STATUS_REQ);
432 ULPD_SAVE(ULPD_DPLL_CTRL);
433 ULPD_SAVE(ULPD_POWER_CTRL);
434
435 if (cpu_is_omap7xx()) {
436 MPUI7XX_SAVE(MPUI_CTRL);
437 MPUI7XX_SAVE(MPUI_DSP_STATUS);
438 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
439 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
440 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
441 MPUI7XX_SAVE(EMIFS_CONFIG);
442 } else if (cpu_is_omap15xx()) {
443 MPUI1510_SAVE(MPUI_CTRL);
444 MPUI1510_SAVE(MPUI_DSP_STATUS);
445 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
446 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
447 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
448 MPUI1510_SAVE(EMIFS_CONFIG);
449 } else if (cpu_is_omap16xx()) {
450 MPUI1610_SAVE(MPUI_CTRL);
451 MPUI1610_SAVE(MPUI_DSP_STATUS);
452 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
453 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
454 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
455 MPUI1610_SAVE(EMIFS_CONFIG);
456 }
457
458 seq_printf(m,
459 "ARM_CKCTL_REG: 0x%-8x \n"
460 "ARM_IDLECT1_REG: 0x%-8x \n"
461 "ARM_IDLECT2_REG: 0x%-8x \n"
462 "ARM_IDLECT3_REG: 0x%-8x \n"
463 "ARM_EWUPCT_REG: 0x%-8x \n"
464 "ARM_RSTCT1_REG: 0x%-8x \n"
465 "ARM_RSTCT2_REG: 0x%-8x \n"
466 "ARM_SYSST_REG: 0x%-8x \n"
467 "ULPD_IT_STATUS_REG: 0x%-4x \n"
468 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
469 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
470 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
471 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
472 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
473 ARM_SHOW(ARM_CKCTL),
474 ARM_SHOW(ARM_IDLECT1),
475 ARM_SHOW(ARM_IDLECT2),
476 ARM_SHOW(ARM_IDLECT3),
477 ARM_SHOW(ARM_EWUPCT),
478 ARM_SHOW(ARM_RSTCT1),
479 ARM_SHOW(ARM_RSTCT2),
480 ARM_SHOW(ARM_SYSST),
481 ULPD_SHOW(ULPD_IT_STATUS),
482 ULPD_SHOW(ULPD_CLOCK_CTRL),
483 ULPD_SHOW(ULPD_SOFT_REQ),
484 ULPD_SHOW(ULPD_DPLL_CTRL),
485 ULPD_SHOW(ULPD_STATUS_REQ),
486 ULPD_SHOW(ULPD_POWER_CTRL));
487
488 if (cpu_is_omap7xx()) {
489 seq_printf(m,
490 "MPUI7XX_CTRL_REG 0x%-8x \n"
491 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
492 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
493 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
494 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
495 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
496 MPUI7XX_SHOW(MPUI_CTRL),
497 MPUI7XX_SHOW(MPUI_DSP_STATUS),
498 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
499 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
500 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
501 MPUI7XX_SHOW(EMIFS_CONFIG));
502 } else if (cpu_is_omap15xx()) {
503 seq_printf(m,
504 "MPUI1510_CTRL_REG 0x%-8x \n"
505 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
506 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
507 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
508 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
509 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
510 MPUI1510_SHOW(MPUI_CTRL),
511 MPUI1510_SHOW(MPUI_DSP_STATUS),
512 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
513 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
514 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
515 MPUI1510_SHOW(EMIFS_CONFIG));
516 } else if (cpu_is_omap16xx()) {
517 seq_printf(m,
518 "MPUI1610_CTRL_REG 0x%-8x \n"
519 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
520 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
521 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
522 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
523 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
524 MPUI1610_SHOW(MPUI_CTRL),
525 MPUI1610_SHOW(MPUI_DSP_STATUS),
526 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
527 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
528 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
529 MPUI1610_SHOW(EMIFS_CONFIG));
530 }
531
532 return 0;
533}
534
535static int omap_pm_debug_open(struct inode *inode, struct file *file)
536{
537 return single_open(file, omap_pm_debug_show,
538 &inode->i_private);
539}
540
541static const struct file_operations omap_pm_debug_fops = {
542 .open = omap_pm_debug_open,
543 .read = seq_read,
544 .llseek = seq_lseek,
545 .release = single_release,
546};
547
548static void omap_pm_init_debugfs(void)
549{
550 struct dentry *d;
551
552 d = debugfs_create_dir("pm_debug", NULL);
553 if (!d)
554 return;
555
556 (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
557 d, NULL, &omap_pm_debug_fops);
558}
559
560#endif /* CONFIG_DEBUG_FS */
561
562/*
563 * omap_pm_prepare - Do preliminary suspend work.
564 *
565 */
566static int omap_pm_prepare(void)
567{
568 /* We cannot sleep in idle until we have resumed */
569 cpu_idle_poll_ctrl(true);
570 return 0;
571}
572
573
574/*
575 * omap_pm_enter - Actually enter a sleep state.
576 * @state: State we're entering.
577 *
578 */
579
580static int omap_pm_enter(suspend_state_t state)
581{
582 switch (state)
583 {
584 case PM_SUSPEND_STANDBY:
585 case PM_SUSPEND_MEM:
586 omap1_pm_suspend();
587 break;
588 default:
589 return -EINVAL;
590 }
591
592 return 0;
593}
594
595
596/**
597 * omap_pm_finish - Finish up suspend sequence.
598 *
599 * This is called after we wake back up (or if entering the sleep state
600 * failed).
601 */
602
603static void omap_pm_finish(void)
604{
605 cpu_idle_poll_ctrl(false);
606}
607
608
609static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
610{
611 return IRQ_HANDLED;
612}
613
614static struct irqaction omap_wakeup_irq = {
615 .name = "peripheral wakeup",
616 .handler = omap_wakeup_interrupt
617};
618
619
620
621static const struct platform_suspend_ops omap_pm_ops = {
622 .prepare = omap_pm_prepare,
623 .enter = omap_pm_enter,
624 .finish = omap_pm_finish,
625 .valid = suspend_valid_only_mem,
626};
627
628static int __init omap_pm_init(void)
629{
630 int error = 0;
631
632 if (!cpu_class_is_omap1())
633 return -ENODEV;
634
635 pr_info("Power Management for TI OMAP.\n");
636
637 if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
638 pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
639
640 if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
641 pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
642
643 if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
644 IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
645 /* OMAP16xx only */
646 pr_info("OMAP1 PM: sleep states in idle enabled\n");
647 enable_dyn_sleep = 1;
648 }
649
650 /*
651 * We copy the assembler sleep/wakeup routines to SRAM.
652 * These routines need to be in SRAM as that's the only
653 * memory the MPU can see when it wakes up.
654 */
655 if (cpu_is_omap7xx()) {
656 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
657 omap7xx_cpu_suspend_sz);
658 } else if (cpu_is_omap15xx()) {
659 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
660 omap1510_cpu_suspend_sz);
661 } else if (cpu_is_omap16xx()) {
662 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
663 omap1610_cpu_suspend_sz);
664 }
665
666 if (omap_sram_suspend == NULL) {
667 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
668 return -ENODEV;
669 }
670
671 arm_pm_idle = omap1_pm_idle;
672
673 if (cpu_is_omap7xx())
674 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
675 else if (cpu_is_omap16xx())
676 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
677
678 /* Program new power ramp-up time
679 * (0 for most boards since we don't lower voltage when in deep sleep)
680 */
681 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
682
683 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
684 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
685
686 /* Configure IDLECT3 */
687 if (cpu_is_omap7xx())
688 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
689 else if (cpu_is_omap16xx())
690 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
691
692 suspend_set_ops(&omap_pm_ops);
693
694#ifdef CONFIG_DEBUG_FS
695 omap_pm_init_debugfs();
696#endif
697
698 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
699 if (error)
700 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
701
702 if (cpu_is_omap16xx()) {
703 /* configure LOW_PWR pin */
704 omap_cfg_reg(T20_1610_LOW_PWR);
705 }
706
707 return error;
708}
709__initcall(omap_pm_init);