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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2009, 2010 ARM Limited
5 *
6 * Author: Will Deacon <will.deacon@arm.com>
7 */
8
9/*
10 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
11 * using the CPU's debug registers.
12 */
13#define pr_fmt(fmt) "hw-breakpoint: " fmt
14
15#include <linux/errno.h>
16#include <linux/hardirq.h>
17#include <linux/perf_event.h>
18#include <linux/hw_breakpoint.h>
19#include <linux/smp.h>
20#include <linux/cfi.h>
21#include <linux/cpu_pm.h>
22#include <linux/coresight.h>
23
24#include <asm/cacheflush.h>
25#include <asm/cputype.h>
26#include <asm/current.h>
27#include <asm/hw_breakpoint.h>
28#include <asm/traps.h>
29
30/* Breakpoint currently in use for each BRP. */
31static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
32
33/* Watchpoint currently in use for each WRP. */
34static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
35
36/* Number of BRP/WRP registers on this CPU. */
37static int core_num_brps __ro_after_init;
38static int core_num_wrps __ro_after_init;
39
40/* Debug architecture version. */
41static u8 debug_arch __ro_after_init;
42
43/* Does debug architecture support OS Save and Restore? */
44static bool has_ossr __ro_after_init;
45
46/* Maximum supported watchpoint length. */
47static u8 max_watchpoint_len __ro_after_init;
48
49#define READ_WB_REG_CASE(OP2, M, VAL) \
50 case ((OP2 << 4) + M): \
51 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
52 break
53
54#define WRITE_WB_REG_CASE(OP2, M, VAL) \
55 case ((OP2 << 4) + M): \
56 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
57 break
58
59#define GEN_READ_WB_REG_CASES(OP2, VAL) \
60 READ_WB_REG_CASE(OP2, 0, VAL); \
61 READ_WB_REG_CASE(OP2, 1, VAL); \
62 READ_WB_REG_CASE(OP2, 2, VAL); \
63 READ_WB_REG_CASE(OP2, 3, VAL); \
64 READ_WB_REG_CASE(OP2, 4, VAL); \
65 READ_WB_REG_CASE(OP2, 5, VAL); \
66 READ_WB_REG_CASE(OP2, 6, VAL); \
67 READ_WB_REG_CASE(OP2, 7, VAL); \
68 READ_WB_REG_CASE(OP2, 8, VAL); \
69 READ_WB_REG_CASE(OP2, 9, VAL); \
70 READ_WB_REG_CASE(OP2, 10, VAL); \
71 READ_WB_REG_CASE(OP2, 11, VAL); \
72 READ_WB_REG_CASE(OP2, 12, VAL); \
73 READ_WB_REG_CASE(OP2, 13, VAL); \
74 READ_WB_REG_CASE(OP2, 14, VAL); \
75 READ_WB_REG_CASE(OP2, 15, VAL)
76
77#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
78 WRITE_WB_REG_CASE(OP2, 0, VAL); \
79 WRITE_WB_REG_CASE(OP2, 1, VAL); \
80 WRITE_WB_REG_CASE(OP2, 2, VAL); \
81 WRITE_WB_REG_CASE(OP2, 3, VAL); \
82 WRITE_WB_REG_CASE(OP2, 4, VAL); \
83 WRITE_WB_REG_CASE(OP2, 5, VAL); \
84 WRITE_WB_REG_CASE(OP2, 6, VAL); \
85 WRITE_WB_REG_CASE(OP2, 7, VAL); \
86 WRITE_WB_REG_CASE(OP2, 8, VAL); \
87 WRITE_WB_REG_CASE(OP2, 9, VAL); \
88 WRITE_WB_REG_CASE(OP2, 10, VAL); \
89 WRITE_WB_REG_CASE(OP2, 11, VAL); \
90 WRITE_WB_REG_CASE(OP2, 12, VAL); \
91 WRITE_WB_REG_CASE(OP2, 13, VAL); \
92 WRITE_WB_REG_CASE(OP2, 14, VAL); \
93 WRITE_WB_REG_CASE(OP2, 15, VAL)
94
95static u32 read_wb_reg(int n)
96{
97 u32 val = 0;
98
99 switch (n) {
100 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
101 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
102 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
103 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
104 default:
105 pr_warn("attempt to read from unknown breakpoint register %d\n",
106 n);
107 }
108
109 return val;
110}
111
112static void write_wb_reg(int n, u32 val)
113{
114 switch (n) {
115 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
116 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
117 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
118 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
119 default:
120 pr_warn("attempt to write to unknown breakpoint register %d\n",
121 n);
122 }
123 isb();
124}
125
126/* Determine debug architecture. */
127static u8 get_debug_arch(void)
128{
129 u32 didr;
130
131 /* Do we implement the extended CPUID interface? */
132 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
133 pr_warn_once("CPUID feature registers not supported. "
134 "Assuming v6 debug is present.\n");
135 return ARM_DEBUG_ARCH_V6;
136 }
137
138 ARM_DBG_READ(c0, c0, 0, didr);
139 return (didr >> 16) & 0xf;
140}
141
142u8 arch_get_debug_arch(void)
143{
144 return debug_arch;
145}
146
147static int debug_arch_supported(void)
148{
149 u8 arch = get_debug_arch();
150
151 /* We don't support the memory-mapped interface. */
152 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
153 arch >= ARM_DEBUG_ARCH_V7_1;
154}
155
156/* Can we determine the watchpoint access type from the fsr? */
157static int debug_exception_updates_fsr(void)
158{
159 return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
160}
161
162/* Determine number of WRP registers available. */
163static int get_num_wrp_resources(void)
164{
165 u32 didr;
166 ARM_DBG_READ(c0, c0, 0, didr);
167 return ((didr >> 28) & 0xf) + 1;
168}
169
170/* Determine number of BRP registers available. */
171static int get_num_brp_resources(void)
172{
173 u32 didr;
174 ARM_DBG_READ(c0, c0, 0, didr);
175 return ((didr >> 24) & 0xf) + 1;
176}
177
178/* Does this core support mismatch breakpoints? */
179static int core_has_mismatch_brps(void)
180{
181 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
182 get_num_brp_resources() > 1);
183}
184
185/* Determine number of usable WRPs available. */
186static int get_num_wrps(void)
187{
188 /*
189 * On debug architectures prior to 7.1, when a watchpoint fires, the
190 * only way to work out which watchpoint it was is by disassembling
191 * the faulting instruction and working out the address of the memory
192 * access.
193 *
194 * Furthermore, we can only do this if the watchpoint was precise
195 * since imprecise watchpoints prevent us from calculating register
196 * based addresses.
197 *
198 * Providing we have more than 1 breakpoint register, we only report
199 * a single watchpoint register for the time being. This way, we always
200 * know which watchpoint fired. In the future we can either add a
201 * disassembler and address generation emulator, or we can insert a
202 * check to see if the DFAR is set on watchpoint exception entry
203 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
204 * that it is set on some implementations].
205 */
206 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
207 return 1;
208
209 return get_num_wrp_resources();
210}
211
212/* Determine number of usable BRPs available. */
213static int get_num_brps(void)
214{
215 int brps = get_num_brp_resources();
216 return core_has_mismatch_brps() ? brps - 1 : brps;
217}
218
219/*
220 * In order to access the breakpoint/watchpoint control registers,
221 * we must be running in debug monitor mode. Unfortunately, we can
222 * be put into halting debug mode at any time by an external debugger
223 * but there is nothing we can do to prevent that.
224 */
225static int monitor_mode_enabled(void)
226{
227 u32 dscr;
228 ARM_DBG_READ(c0, c1, 0, dscr);
229 return !!(dscr & ARM_DSCR_MDBGEN);
230}
231
232static int enable_monitor_mode(void)
233{
234 u32 dscr;
235 ARM_DBG_READ(c0, c1, 0, dscr);
236
237 /* If monitor mode is already enabled, just return. */
238 if (dscr & ARM_DSCR_MDBGEN)
239 goto out;
240
241 /* Write to the corresponding DSCR. */
242 switch (get_debug_arch()) {
243 case ARM_DEBUG_ARCH_V6:
244 case ARM_DEBUG_ARCH_V6_1:
245 ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
246 break;
247 case ARM_DEBUG_ARCH_V7_ECP14:
248 case ARM_DEBUG_ARCH_V7_1:
249 case ARM_DEBUG_ARCH_V8:
250 case ARM_DEBUG_ARCH_V8_1:
251 case ARM_DEBUG_ARCH_V8_2:
252 case ARM_DEBUG_ARCH_V8_4:
253 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
254 isb();
255 break;
256 default:
257 return -ENODEV;
258 }
259
260 /* Check that the write made it through. */
261 ARM_DBG_READ(c0, c1, 0, dscr);
262 if (!(dscr & ARM_DSCR_MDBGEN)) {
263 pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
264 smp_processor_id());
265 return -EPERM;
266 }
267
268out:
269 return 0;
270}
271
272int hw_breakpoint_slots(int type)
273{
274 if (!debug_arch_supported())
275 return 0;
276
277 /*
278 * We can be called early, so don't rely on
279 * our static variables being initialised.
280 */
281 switch (type) {
282 case TYPE_INST:
283 return get_num_brps();
284 case TYPE_DATA:
285 return get_num_wrps();
286 default:
287 pr_warn("unknown slot type: %d\n", type);
288 return 0;
289 }
290}
291
292/*
293 * Check if 8-bit byte-address select is available.
294 * This clobbers WRP 0.
295 */
296static u8 get_max_wp_len(void)
297{
298 u32 ctrl_reg;
299 struct arch_hw_breakpoint_ctrl ctrl;
300 u8 size = 4;
301
302 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
303 goto out;
304
305 memset(&ctrl, 0, sizeof(ctrl));
306 ctrl.len = ARM_BREAKPOINT_LEN_8;
307 ctrl_reg = encode_ctrl_reg(ctrl);
308
309 write_wb_reg(ARM_BASE_WVR, 0);
310 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
311 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
312 size = 8;
313
314out:
315 return size;
316}
317
318u8 arch_get_max_wp_len(void)
319{
320 return max_watchpoint_len;
321}
322
323/*
324 * Install a perf counter breakpoint.
325 */
326int arch_install_hw_breakpoint(struct perf_event *bp)
327{
328 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
329 struct perf_event **slot, **slots;
330 int i, max_slots, ctrl_base, val_base;
331 u32 addr, ctrl;
332
333 addr = info->address;
334 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
335
336 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
337 /* Breakpoint */
338 ctrl_base = ARM_BASE_BCR;
339 val_base = ARM_BASE_BVR;
340 slots = this_cpu_ptr(bp_on_reg);
341 max_slots = core_num_brps;
342 } else {
343 /* Watchpoint */
344 ctrl_base = ARM_BASE_WCR;
345 val_base = ARM_BASE_WVR;
346 slots = this_cpu_ptr(wp_on_reg);
347 max_slots = core_num_wrps;
348 }
349
350 for (i = 0; i < max_slots; ++i) {
351 slot = &slots[i];
352
353 if (!*slot) {
354 *slot = bp;
355 break;
356 }
357 }
358
359 if (i == max_slots) {
360 pr_warn("Can't find any breakpoint slot\n");
361 return -EBUSY;
362 }
363
364 /* Override the breakpoint data with the step data. */
365 if (info->step_ctrl.enabled) {
366 addr = info->trigger & ~0x3;
367 ctrl = encode_ctrl_reg(info->step_ctrl);
368 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
369 i = 0;
370 ctrl_base = ARM_BASE_BCR + core_num_brps;
371 val_base = ARM_BASE_BVR + core_num_brps;
372 }
373 }
374
375 /* Setup the address register. */
376 write_wb_reg(val_base + i, addr);
377
378 /* Setup the control register. */
379 write_wb_reg(ctrl_base + i, ctrl);
380 return 0;
381}
382
383void arch_uninstall_hw_breakpoint(struct perf_event *bp)
384{
385 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
386 struct perf_event **slot, **slots;
387 int i, max_slots, base;
388
389 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
390 /* Breakpoint */
391 base = ARM_BASE_BCR;
392 slots = this_cpu_ptr(bp_on_reg);
393 max_slots = core_num_brps;
394 } else {
395 /* Watchpoint */
396 base = ARM_BASE_WCR;
397 slots = this_cpu_ptr(wp_on_reg);
398 max_slots = core_num_wrps;
399 }
400
401 /* Remove the breakpoint. */
402 for (i = 0; i < max_slots; ++i) {
403 slot = &slots[i];
404
405 if (*slot == bp) {
406 *slot = NULL;
407 break;
408 }
409 }
410
411 if (i == max_slots) {
412 pr_warn("Can't find any breakpoint slot\n");
413 return;
414 }
415
416 /* Ensure that we disable the mismatch breakpoint. */
417 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
418 info->step_ctrl.enabled) {
419 i = 0;
420 base = ARM_BASE_BCR + core_num_brps;
421 }
422
423 /* Reset the control register. */
424 write_wb_reg(base + i, 0);
425}
426
427static int get_hbp_len(u8 hbp_len)
428{
429 unsigned int len_in_bytes = 0;
430
431 switch (hbp_len) {
432 case ARM_BREAKPOINT_LEN_1:
433 len_in_bytes = 1;
434 break;
435 case ARM_BREAKPOINT_LEN_2:
436 len_in_bytes = 2;
437 break;
438 case ARM_BREAKPOINT_LEN_4:
439 len_in_bytes = 4;
440 break;
441 case ARM_BREAKPOINT_LEN_8:
442 len_in_bytes = 8;
443 break;
444 }
445
446 return len_in_bytes;
447}
448
449/*
450 * Check whether bp virtual address is in kernel space.
451 */
452int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
453{
454 unsigned int len;
455 unsigned long va;
456
457 va = hw->address;
458 len = get_hbp_len(hw->ctrl.len);
459
460 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
461}
462
463/*
464 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
465 * Hopefully this will disappear when ptrace can bypass the conversion
466 * to generic breakpoint descriptions.
467 */
468int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
469 int *gen_len, int *gen_type)
470{
471 /* Type */
472 switch (ctrl.type) {
473 case ARM_BREAKPOINT_EXECUTE:
474 *gen_type = HW_BREAKPOINT_X;
475 break;
476 case ARM_BREAKPOINT_LOAD:
477 *gen_type = HW_BREAKPOINT_R;
478 break;
479 case ARM_BREAKPOINT_STORE:
480 *gen_type = HW_BREAKPOINT_W;
481 break;
482 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
483 *gen_type = HW_BREAKPOINT_RW;
484 break;
485 default:
486 return -EINVAL;
487 }
488
489 /* Len */
490 switch (ctrl.len) {
491 case ARM_BREAKPOINT_LEN_1:
492 *gen_len = HW_BREAKPOINT_LEN_1;
493 break;
494 case ARM_BREAKPOINT_LEN_2:
495 *gen_len = HW_BREAKPOINT_LEN_2;
496 break;
497 case ARM_BREAKPOINT_LEN_4:
498 *gen_len = HW_BREAKPOINT_LEN_4;
499 break;
500 case ARM_BREAKPOINT_LEN_8:
501 *gen_len = HW_BREAKPOINT_LEN_8;
502 break;
503 default:
504 return -EINVAL;
505 }
506
507 return 0;
508}
509
510/*
511 * Construct an arch_hw_breakpoint from a perf_event.
512 */
513static int arch_build_bp_info(struct perf_event *bp,
514 const struct perf_event_attr *attr,
515 struct arch_hw_breakpoint *hw)
516{
517 /* Type */
518 switch (attr->bp_type) {
519 case HW_BREAKPOINT_X:
520 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE;
521 break;
522 case HW_BREAKPOINT_R:
523 hw->ctrl.type = ARM_BREAKPOINT_LOAD;
524 break;
525 case HW_BREAKPOINT_W:
526 hw->ctrl.type = ARM_BREAKPOINT_STORE;
527 break;
528 case HW_BREAKPOINT_RW:
529 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
530 break;
531 default:
532 return -EINVAL;
533 }
534
535 /* Len */
536 switch (attr->bp_len) {
537 case HW_BREAKPOINT_LEN_1:
538 hw->ctrl.len = ARM_BREAKPOINT_LEN_1;
539 break;
540 case HW_BREAKPOINT_LEN_2:
541 hw->ctrl.len = ARM_BREAKPOINT_LEN_2;
542 break;
543 case HW_BREAKPOINT_LEN_4:
544 hw->ctrl.len = ARM_BREAKPOINT_LEN_4;
545 break;
546 case HW_BREAKPOINT_LEN_8:
547 hw->ctrl.len = ARM_BREAKPOINT_LEN_8;
548 if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
549 && max_watchpoint_len >= 8)
550 break;
551 fallthrough;
552 default:
553 return -EINVAL;
554 }
555
556 /*
557 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
558 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
559 * by the hardware and must be aligned to the appropriate number of
560 * bytes.
561 */
562 if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
563 hw->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
564 hw->ctrl.len != ARM_BREAKPOINT_LEN_4)
565 return -EINVAL;
566
567 /* Address */
568 hw->address = attr->bp_addr;
569
570 /* Privilege */
571 hw->ctrl.privilege = ARM_BREAKPOINT_USER;
572 if (arch_check_bp_in_kernelspace(hw))
573 hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
574
575 /* Enabled? */
576 hw->ctrl.enabled = !attr->disabled;
577
578 /* Mismatch */
579 hw->ctrl.mismatch = 0;
580
581 return 0;
582}
583
584/*
585 * Validate the arch-specific HW Breakpoint register settings.
586 */
587int hw_breakpoint_arch_parse(struct perf_event *bp,
588 const struct perf_event_attr *attr,
589 struct arch_hw_breakpoint *hw)
590{
591 int ret = 0;
592 u32 offset, alignment_mask = 0x3;
593
594 /* Ensure that we are in monitor debug mode. */
595 if (!monitor_mode_enabled())
596 return -ENODEV;
597
598 /* Build the arch_hw_breakpoint. */
599 ret = arch_build_bp_info(bp, attr, hw);
600 if (ret)
601 goto out;
602
603 /* Check address alignment. */
604 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8)
605 alignment_mask = 0x7;
606 offset = hw->address & alignment_mask;
607 switch (offset) {
608 case 0:
609 /* Aligned */
610 break;
611 case 1:
612 case 2:
613 /* Allow halfword watchpoints and breakpoints. */
614 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
615 break;
616 fallthrough;
617 case 3:
618 /* Allow single byte watchpoint. */
619 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
620 break;
621 fallthrough;
622 default:
623 ret = -EINVAL;
624 goto out;
625 }
626
627 hw->address &= ~alignment_mask;
628 hw->ctrl.len <<= offset;
629
630 if (is_default_overflow_handler(bp)) {
631 /*
632 * Mismatch breakpoints are required for single-stepping
633 * breakpoints.
634 */
635 if (!core_has_mismatch_brps())
636 return -EINVAL;
637
638 /* We don't allow mismatch breakpoints in kernel space. */
639 if (arch_check_bp_in_kernelspace(hw))
640 return -EPERM;
641
642 /*
643 * Per-cpu breakpoints are not supported by our stepping
644 * mechanism.
645 */
646 if (!bp->hw.target)
647 return -EINVAL;
648
649 /*
650 * We only support specific access types if the fsr
651 * reports them.
652 */
653 if (!debug_exception_updates_fsr() &&
654 (hw->ctrl.type == ARM_BREAKPOINT_LOAD ||
655 hw->ctrl.type == ARM_BREAKPOINT_STORE))
656 return -EINVAL;
657 }
658
659out:
660 return ret;
661}
662
663/*
664 * Enable/disable single-stepping over the breakpoint bp at address addr.
665 */
666static void enable_single_step(struct perf_event *bp, u32 addr)
667{
668 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
669
670 arch_uninstall_hw_breakpoint(bp);
671 info->step_ctrl.mismatch = 1;
672 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
673 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
674 info->step_ctrl.privilege = info->ctrl.privilege;
675 info->step_ctrl.enabled = 1;
676 info->trigger = addr;
677 arch_install_hw_breakpoint(bp);
678}
679
680static void disable_single_step(struct perf_event *bp)
681{
682 arch_uninstall_hw_breakpoint(bp);
683 counter_arch_bp(bp)->step_ctrl.enabled = 0;
684 arch_install_hw_breakpoint(bp);
685}
686
687/*
688 * Arm32 hardware does not always report a watchpoint hit address that matches
689 * one of the watchpoints set. It can also report an address "near" the
690 * watchpoint if a single instruction access both watched and unwatched
691 * addresses. There is no straight-forward way, short of disassembling the
692 * offending instruction, to map that address back to the watchpoint. This
693 * function computes the distance of the memory access from the watchpoint as a
694 * heuristic for the likelyhood that a given access triggered the watchpoint.
695 *
696 * See this same function in the arm64 platform code, which has the same
697 * problem.
698 *
699 * The function returns the distance of the address from the bytes watched by
700 * the watchpoint. In case of an exact match, it returns 0.
701 */
702static u32 get_distance_from_watchpoint(unsigned long addr, u32 val,
703 struct arch_hw_breakpoint_ctrl *ctrl)
704{
705 u32 wp_low, wp_high;
706 u32 lens, lene;
707
708 lens = __ffs(ctrl->len);
709 lene = __fls(ctrl->len);
710
711 wp_low = val + lens;
712 wp_high = val + lene;
713 if (addr < wp_low)
714 return wp_low - addr;
715 else if (addr > wp_high)
716 return addr - wp_high;
717 else
718 return 0;
719}
720
721static int watchpoint_fault_on_uaccess(struct pt_regs *regs,
722 struct arch_hw_breakpoint *info)
723{
724 return !user_mode(regs) && info->ctrl.privilege == ARM_BREAKPOINT_USER;
725}
726
727static void watchpoint_handler(unsigned long addr, unsigned int fsr,
728 struct pt_regs *regs)
729{
730 int i, access, closest_match = 0;
731 u32 min_dist = -1, dist;
732 u32 val, ctrl_reg;
733 struct perf_event *wp, **slots;
734 struct arch_hw_breakpoint *info;
735 struct arch_hw_breakpoint_ctrl ctrl;
736
737 slots = this_cpu_ptr(wp_on_reg);
738
739 /*
740 * Find all watchpoints that match the reported address. If no exact
741 * match is found. Attribute the hit to the closest watchpoint.
742 */
743 rcu_read_lock();
744 for (i = 0; i < core_num_wrps; ++i) {
745 wp = slots[i];
746 if (wp == NULL)
747 continue;
748
749 /*
750 * The DFAR is an unknown value on debug architectures prior
751 * to 7.1. Since we only allow a single watchpoint on these
752 * older CPUs, we can set the trigger to the lowest possible
753 * faulting address.
754 */
755 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
756 BUG_ON(i > 0);
757 info = counter_arch_bp(wp);
758 info->trigger = wp->attr.bp_addr;
759 } else {
760 /* Check that the access type matches. */
761 if (debug_exception_updates_fsr()) {
762 access = (fsr & ARM_FSR_ACCESS_MASK) ?
763 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
764 if (!(access & hw_breakpoint_type(wp)))
765 continue;
766 }
767
768 val = read_wb_reg(ARM_BASE_WVR + i);
769 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
770 decode_ctrl_reg(ctrl_reg, &ctrl);
771 dist = get_distance_from_watchpoint(addr, val, &ctrl);
772 if (dist < min_dist) {
773 min_dist = dist;
774 closest_match = i;
775 }
776 /* Is this an exact match? */
777 if (dist != 0)
778 continue;
779
780 /* We have a winner. */
781 info = counter_arch_bp(wp);
782 info->trigger = addr;
783 }
784
785 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
786
787 /*
788 * If we triggered a user watchpoint from a uaccess routine,
789 * then handle the stepping ourselves since userspace really
790 * can't help us with this.
791 */
792 if (watchpoint_fault_on_uaccess(regs, info))
793 goto step;
794
795 perf_bp_event(wp, regs);
796
797 /*
798 * Defer stepping to the overflow handler if one is installed.
799 * Otherwise, insert a temporary mismatch breakpoint so that
800 * we can single-step over the watchpoint trigger.
801 */
802 if (!is_default_overflow_handler(wp))
803 continue;
804step:
805 enable_single_step(wp, instruction_pointer(regs));
806 }
807
808 if (min_dist > 0 && min_dist != -1) {
809 /* No exact match found. */
810 wp = slots[closest_match];
811 info = counter_arch_bp(wp);
812 info->trigger = addr;
813 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
814 perf_bp_event(wp, regs);
815 if (is_default_overflow_handler(wp))
816 enable_single_step(wp, instruction_pointer(regs));
817 }
818
819 rcu_read_unlock();
820}
821
822static void watchpoint_single_step_handler(unsigned long pc)
823{
824 int i;
825 struct perf_event *wp, **slots;
826 struct arch_hw_breakpoint *info;
827
828 slots = this_cpu_ptr(wp_on_reg);
829
830 for (i = 0; i < core_num_wrps; ++i) {
831 rcu_read_lock();
832
833 wp = slots[i];
834
835 if (wp == NULL)
836 goto unlock;
837
838 info = counter_arch_bp(wp);
839 if (!info->step_ctrl.enabled)
840 goto unlock;
841
842 /*
843 * Restore the original watchpoint if we've completed the
844 * single-step.
845 */
846 if (info->trigger != pc)
847 disable_single_step(wp);
848
849unlock:
850 rcu_read_unlock();
851 }
852}
853
854static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
855{
856 int i;
857 u32 ctrl_reg, val, addr;
858 struct perf_event *bp, **slots;
859 struct arch_hw_breakpoint *info;
860 struct arch_hw_breakpoint_ctrl ctrl;
861
862 slots = this_cpu_ptr(bp_on_reg);
863
864 /* The exception entry code places the amended lr in the PC. */
865 addr = regs->ARM_pc;
866
867 /* Check the currently installed breakpoints first. */
868 for (i = 0; i < core_num_brps; ++i) {
869 rcu_read_lock();
870
871 bp = slots[i];
872
873 if (bp == NULL)
874 goto unlock;
875
876 info = counter_arch_bp(bp);
877
878 /* Check if the breakpoint value matches. */
879 val = read_wb_reg(ARM_BASE_BVR + i);
880 if (val != (addr & ~0x3))
881 goto mismatch;
882
883 /* Possible match, check the byte address select to confirm. */
884 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
885 decode_ctrl_reg(ctrl_reg, &ctrl);
886 if ((1 << (addr & 0x3)) & ctrl.len) {
887 info->trigger = addr;
888 pr_debug("breakpoint fired: address = 0x%x\n", addr);
889 perf_bp_event(bp, regs);
890 if (is_default_overflow_handler(bp))
891 enable_single_step(bp, addr);
892 goto unlock;
893 }
894
895mismatch:
896 /* If we're stepping a breakpoint, it can now be restored. */
897 if (info->step_ctrl.enabled)
898 disable_single_step(bp);
899unlock:
900 rcu_read_unlock();
901 }
902
903 /* Handle any pending watchpoint single-step breakpoints. */
904 watchpoint_single_step_handler(addr);
905}
906
907#ifdef CONFIG_CFI_CLANG
908static void hw_breakpoint_cfi_handler(struct pt_regs *regs)
909{
910 /*
911 * TODO: implementing target and type to pass to CFI using the more
912 * elaborate report_cfi_failure() requires compiler work. To be able
913 * to properly extract target information the compiler needs to
914 * emit a stable instructions sequence for the CFI checks so we can
915 * decode the instructions preceding the trap and figure out which
916 * registers were used.
917 */
918
919 switch (report_cfi_failure_noaddr(regs, instruction_pointer(regs))) {
920 case BUG_TRAP_TYPE_BUG:
921 die("Oops - CFI", regs, 0);
922 break;
923 case BUG_TRAP_TYPE_WARN:
924 /* Skip the breaking instruction */
925 instruction_pointer(regs) += 4;
926 break;
927 default:
928 die("Unknown CFI error", regs, 0);
929 break;
930 }
931}
932#else
933static void hw_breakpoint_cfi_handler(struct pt_regs *regs)
934{
935}
936#endif
937
938/*
939 * Called from either the Data Abort Handler [watchpoint] or the
940 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
941 */
942static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
943 struct pt_regs *regs)
944{
945 int ret = 0;
946 u32 dscr;
947
948 preempt_disable();
949
950 if (interrupts_enabled(regs))
951 local_irq_enable();
952
953 /* We only handle watchpoints and hardware breakpoints. */
954 ARM_DBG_READ(c0, c1, 0, dscr);
955
956 /* Perform perf callbacks. */
957 switch (ARM_DSCR_MOE(dscr)) {
958 case ARM_ENTRY_BREAKPOINT:
959 breakpoint_handler(addr, regs);
960 break;
961 case ARM_ENTRY_ASYNC_WATCHPOINT:
962 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
963 fallthrough;
964 case ARM_ENTRY_SYNC_WATCHPOINT:
965 watchpoint_handler(addr, fsr, regs);
966 break;
967 case ARM_ENTRY_CFI_BREAKPOINT:
968 hw_breakpoint_cfi_handler(regs);
969 break;
970 default:
971 ret = 1; /* Unhandled fault. */
972 }
973
974 preempt_enable();
975
976 return ret;
977}
978
979#ifdef CONFIG_ARM_ERRATA_764319
980static int oslsr_fault;
981
982static int debug_oslsr_trap(struct pt_regs *regs, unsigned int instr)
983{
984 oslsr_fault = 1;
985 instruction_pointer(regs) += 4;
986 return 0;
987}
988
989static struct undef_hook debug_oslsr_hook = {
990 .instr_mask = 0xffffffff,
991 .instr_val = 0xee115e91,
992 .fn = debug_oslsr_trap,
993};
994#endif
995
996/*
997 * One-time initialisation.
998 */
999static cpumask_t debug_err_mask;
1000
1001static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
1002{
1003 int cpu = smp_processor_id();
1004
1005 pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
1006 instr, cpu);
1007
1008 /* Set the error flag for this CPU and skip the faulting instruction. */
1009 cpumask_set_cpu(cpu, &debug_err_mask);
1010 instruction_pointer(regs) += 4;
1011 return 0;
1012}
1013
1014static struct undef_hook debug_reg_hook = {
1015 .instr_mask = 0x0fe80f10,
1016 .instr_val = 0x0e000e10,
1017 .fn = debug_reg_trap,
1018};
1019
1020/* Does this core support OS Save and Restore? */
1021static bool core_has_os_save_restore(void)
1022{
1023 u32 oslsr;
1024
1025 switch (get_debug_arch()) {
1026 case ARM_DEBUG_ARCH_V7_1:
1027 return true;
1028 case ARM_DEBUG_ARCH_V7_ECP14:
1029#ifdef CONFIG_ARM_ERRATA_764319
1030 oslsr_fault = 0;
1031 register_undef_hook(&debug_oslsr_hook);
1032 ARM_DBG_READ(c1, c1, 4, oslsr);
1033 unregister_undef_hook(&debug_oslsr_hook);
1034 if (oslsr_fault)
1035 return false;
1036#else
1037 ARM_DBG_READ(c1, c1, 4, oslsr);
1038#endif
1039 if (oslsr & ARM_OSLSR_OSLM0)
1040 return true;
1041 fallthrough;
1042 default:
1043 return false;
1044 }
1045}
1046
1047static void reset_ctrl_regs(unsigned int cpu)
1048{
1049 int i, raw_num_brps, err = 0;
1050 u32 val;
1051
1052 /*
1053 * v7 debug contains save and restore registers so that debug state
1054 * can be maintained across low-power modes without leaving the debug
1055 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
1056 * the debug registers out of reset, so we must unlock the OS Lock
1057 * Access Register to avoid taking undefined instruction exceptions
1058 * later on.
1059 */
1060 switch (debug_arch) {
1061 case ARM_DEBUG_ARCH_V6:
1062 case ARM_DEBUG_ARCH_V6_1:
1063 /* ARMv6 cores clear the registers out of reset. */
1064 goto out_mdbgen;
1065 case ARM_DEBUG_ARCH_V7_ECP14:
1066 /*
1067 * Ensure sticky power-down is clear (i.e. debug logic is
1068 * powered up).
1069 */
1070 ARM_DBG_READ(c1, c5, 4, val);
1071 if ((val & 0x1) == 0)
1072 err = -EPERM;
1073
1074 if (!has_ossr)
1075 goto clear_vcr;
1076 break;
1077 case ARM_DEBUG_ARCH_V7_1:
1078 /*
1079 * Ensure the OS double lock is clear.
1080 */
1081 ARM_DBG_READ(c1, c3, 4, val);
1082 if ((val & 0x1) == 1)
1083 err = -EPERM;
1084 break;
1085 }
1086
1087 if (err) {
1088 pr_warn_once("CPU %d debug is powered down!\n", cpu);
1089 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1090 return;
1091 }
1092
1093 /*
1094 * Unconditionally clear the OS lock by writing a value
1095 * other than CS_LAR_KEY to the access register.
1096 */
1097 ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK);
1098 isb();
1099
1100 /*
1101 * Clear any configured vector-catch events before
1102 * enabling monitor mode.
1103 */
1104clear_vcr:
1105 ARM_DBG_WRITE(c0, c7, 0, 0);
1106 isb();
1107
1108 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1109 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
1110 return;
1111 }
1112
1113 /*
1114 * The control/value register pairs are UNKNOWN out of reset so
1115 * clear them to avoid spurious debug events.
1116 */
1117 raw_num_brps = get_num_brp_resources();
1118 for (i = 0; i < raw_num_brps; ++i) {
1119 write_wb_reg(ARM_BASE_BCR + i, 0UL);
1120 write_wb_reg(ARM_BASE_BVR + i, 0UL);
1121 }
1122
1123 for (i = 0; i < core_num_wrps; ++i) {
1124 write_wb_reg(ARM_BASE_WCR + i, 0UL);
1125 write_wb_reg(ARM_BASE_WVR + i, 0UL);
1126 }
1127
1128 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1129 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1130 return;
1131 }
1132
1133 /*
1134 * Have a crack at enabling monitor mode. We don't actually need
1135 * it yet, but reporting an error early is useful if it fails.
1136 */
1137out_mdbgen:
1138 if (enable_monitor_mode())
1139 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1140}
1141
1142static int dbg_reset_online(unsigned int cpu)
1143{
1144 local_irq_disable();
1145 reset_ctrl_regs(cpu);
1146 local_irq_enable();
1147 return 0;
1148}
1149
1150#ifdef CONFIG_CPU_PM
1151static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
1152 void *v)
1153{
1154 if (action == CPU_PM_EXIT)
1155 reset_ctrl_regs(smp_processor_id());
1156
1157 return NOTIFY_OK;
1158}
1159
1160static struct notifier_block dbg_cpu_pm_nb = {
1161 .notifier_call = dbg_cpu_pm_notify,
1162};
1163
1164static void __init pm_init(void)
1165{
1166 cpu_pm_register_notifier(&dbg_cpu_pm_nb);
1167}
1168#else
1169static inline void pm_init(void)
1170{
1171}
1172#endif
1173
1174static int __init arch_hw_breakpoint_init(void)
1175{
1176 int ret;
1177
1178 debug_arch = get_debug_arch();
1179
1180 if (!debug_arch_supported()) {
1181 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1182 return 0;
1183 }
1184
1185 /*
1186 * Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD
1187 * whenever a WFI is issued, even if the core is not powered down, in
1188 * violation of the architecture. When DBGPRSR.SPD is set, accesses to
1189 * breakpoint and watchpoint registers are treated as undefined, so
1190 * this results in boot time and runtime failures when these are
1191 * accessed and we unexpectedly take a trap.
1192 *
1193 * It's not clear if/how this can be worked around, so we blacklist
1194 * Scorpion CPUs to avoid these issues.
1195 */
1196 if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
1197 pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
1198 return 0;
1199 }
1200
1201 has_ossr = core_has_os_save_restore();
1202
1203 /* Determine how many BRPs/WRPs are available. */
1204 core_num_brps = get_num_brps();
1205 core_num_wrps = get_num_wrps();
1206
1207 /*
1208 * We need to tread carefully here because DBGSWENABLE may be
1209 * driven low on this core and there isn't an architected way to
1210 * determine that.
1211 */
1212 cpus_read_lock();
1213 register_undef_hook(&debug_reg_hook);
1214
1215 /*
1216 * Register CPU notifier which resets the breakpoint resources. We
1217 * assume that a halting debugger will leave the world in a nice state
1218 * for us.
1219 */
1220 ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN,
1221 "arm/hw_breakpoint:online",
1222 dbg_reset_online, NULL);
1223 unregister_undef_hook(&debug_reg_hook);
1224 if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) {
1225 core_num_brps = 0;
1226 core_num_wrps = 0;
1227 if (ret > 0)
1228 cpuhp_remove_state_nocalls_cpuslocked(ret);
1229 cpus_read_unlock();
1230 return 0;
1231 }
1232
1233 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1234 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1235 "", core_num_wrps);
1236
1237 /* Work out the maximum supported watchpoint length. */
1238 max_watchpoint_len = get_max_wp_len();
1239 pr_info("maximum watchpoint size is %u bytes.\n",
1240 max_watchpoint_len);
1241
1242 /* Register debug fault handler. */
1243 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1244 TRAP_HWBKPT, "watchpoint debug exception");
1245 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1246 TRAP_HWBKPT, "breakpoint debug exception");
1247 cpus_read_unlock();
1248
1249 /* Register PM notifiers. */
1250 pm_init();
1251 return 0;
1252}
1253arch_initcall(arch_hw_breakpoint_init);
1254
1255void hw_breakpoint_pmu_read(struct perf_event *bp)
1256{
1257}
1258
1259/*
1260 * Dummy function to register with die_notifier.
1261 */
1262int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1263 unsigned long val, void *data)
1264{
1265 return NOTIFY_DONE;
1266}
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009, 2010 ARM Limited
16 *
17 * Author: Will Deacon <will.deacon@arm.com>
18 */
19
20/*
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
23 */
24#define pr_fmt(fmt) "hw-breakpoint: " fmt
25
26#include <linux/errno.h>
27#include <linux/hardirq.h>
28#include <linux/perf_event.h>
29#include <linux/hw_breakpoint.h>
30#include <linux/smp.h>
31#include <linux/cpu_pm.h>
32#include <linux/coresight.h>
33
34#include <asm/cacheflush.h>
35#include <asm/cputype.h>
36#include <asm/current.h>
37#include <asm/hw_breakpoint.h>
38#include <asm/traps.h>
39
40/* Breakpoint currently in use for each BRP. */
41static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
42
43/* Watchpoint currently in use for each WRP. */
44static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
45
46/* Number of BRP/WRP registers on this CPU. */
47static int core_num_brps;
48static int core_num_wrps;
49
50/* Debug architecture version. */
51static u8 debug_arch;
52
53/* Does debug architecture support OS Save and Restore? */
54static bool has_ossr;
55
56/* Maximum supported watchpoint length. */
57static u8 max_watchpoint_len;
58
59#define READ_WB_REG_CASE(OP2, M, VAL) \
60 case ((OP2 << 4) + M): \
61 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
62 break
63
64#define WRITE_WB_REG_CASE(OP2, M, VAL) \
65 case ((OP2 << 4) + M): \
66 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
67 break
68
69#define GEN_READ_WB_REG_CASES(OP2, VAL) \
70 READ_WB_REG_CASE(OP2, 0, VAL); \
71 READ_WB_REG_CASE(OP2, 1, VAL); \
72 READ_WB_REG_CASE(OP2, 2, VAL); \
73 READ_WB_REG_CASE(OP2, 3, VAL); \
74 READ_WB_REG_CASE(OP2, 4, VAL); \
75 READ_WB_REG_CASE(OP2, 5, VAL); \
76 READ_WB_REG_CASE(OP2, 6, VAL); \
77 READ_WB_REG_CASE(OP2, 7, VAL); \
78 READ_WB_REG_CASE(OP2, 8, VAL); \
79 READ_WB_REG_CASE(OP2, 9, VAL); \
80 READ_WB_REG_CASE(OP2, 10, VAL); \
81 READ_WB_REG_CASE(OP2, 11, VAL); \
82 READ_WB_REG_CASE(OP2, 12, VAL); \
83 READ_WB_REG_CASE(OP2, 13, VAL); \
84 READ_WB_REG_CASE(OP2, 14, VAL); \
85 READ_WB_REG_CASE(OP2, 15, VAL)
86
87#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
88 WRITE_WB_REG_CASE(OP2, 0, VAL); \
89 WRITE_WB_REG_CASE(OP2, 1, VAL); \
90 WRITE_WB_REG_CASE(OP2, 2, VAL); \
91 WRITE_WB_REG_CASE(OP2, 3, VAL); \
92 WRITE_WB_REG_CASE(OP2, 4, VAL); \
93 WRITE_WB_REG_CASE(OP2, 5, VAL); \
94 WRITE_WB_REG_CASE(OP2, 6, VAL); \
95 WRITE_WB_REG_CASE(OP2, 7, VAL); \
96 WRITE_WB_REG_CASE(OP2, 8, VAL); \
97 WRITE_WB_REG_CASE(OP2, 9, VAL); \
98 WRITE_WB_REG_CASE(OP2, 10, VAL); \
99 WRITE_WB_REG_CASE(OP2, 11, VAL); \
100 WRITE_WB_REG_CASE(OP2, 12, VAL); \
101 WRITE_WB_REG_CASE(OP2, 13, VAL); \
102 WRITE_WB_REG_CASE(OP2, 14, VAL); \
103 WRITE_WB_REG_CASE(OP2, 15, VAL)
104
105static u32 read_wb_reg(int n)
106{
107 u32 val = 0;
108
109 switch (n) {
110 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
111 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
112 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
113 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
114 default:
115 pr_warn("attempt to read from unknown breakpoint register %d\n",
116 n);
117 }
118
119 return val;
120}
121
122static void write_wb_reg(int n, u32 val)
123{
124 switch (n) {
125 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
126 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
127 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
128 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
129 default:
130 pr_warn("attempt to write to unknown breakpoint register %d\n",
131 n);
132 }
133 isb();
134}
135
136/* Determine debug architecture. */
137static u8 get_debug_arch(void)
138{
139 u32 didr;
140
141 /* Do we implement the extended CPUID interface? */
142 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
143 pr_warn_once("CPUID feature registers not supported. "
144 "Assuming v6 debug is present.\n");
145 return ARM_DEBUG_ARCH_V6;
146 }
147
148 ARM_DBG_READ(c0, c0, 0, didr);
149 return (didr >> 16) & 0xf;
150}
151
152u8 arch_get_debug_arch(void)
153{
154 return debug_arch;
155}
156
157static int debug_arch_supported(void)
158{
159 u8 arch = get_debug_arch();
160
161 /* We don't support the memory-mapped interface. */
162 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
163 arch >= ARM_DEBUG_ARCH_V7_1;
164}
165
166/* Can we determine the watchpoint access type from the fsr? */
167static int debug_exception_updates_fsr(void)
168{
169 return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
170}
171
172/* Determine number of WRP registers available. */
173static int get_num_wrp_resources(void)
174{
175 u32 didr;
176 ARM_DBG_READ(c0, c0, 0, didr);
177 return ((didr >> 28) & 0xf) + 1;
178}
179
180/* Determine number of BRP registers available. */
181static int get_num_brp_resources(void)
182{
183 u32 didr;
184 ARM_DBG_READ(c0, c0, 0, didr);
185 return ((didr >> 24) & 0xf) + 1;
186}
187
188/* Does this core support mismatch breakpoints? */
189static int core_has_mismatch_brps(void)
190{
191 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
192 get_num_brp_resources() > 1);
193}
194
195/* Determine number of usable WRPs available. */
196static int get_num_wrps(void)
197{
198 /*
199 * On debug architectures prior to 7.1, when a watchpoint fires, the
200 * only way to work out which watchpoint it was is by disassembling
201 * the faulting instruction and working out the address of the memory
202 * access.
203 *
204 * Furthermore, we can only do this if the watchpoint was precise
205 * since imprecise watchpoints prevent us from calculating register
206 * based addresses.
207 *
208 * Providing we have more than 1 breakpoint register, we only report
209 * a single watchpoint register for the time being. This way, we always
210 * know which watchpoint fired. In the future we can either add a
211 * disassembler and address generation emulator, or we can insert a
212 * check to see if the DFAR is set on watchpoint exception entry
213 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
214 * that it is set on some implementations].
215 */
216 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
217 return 1;
218
219 return get_num_wrp_resources();
220}
221
222/* Determine number of usable BRPs available. */
223static int get_num_brps(void)
224{
225 int brps = get_num_brp_resources();
226 return core_has_mismatch_brps() ? brps - 1 : brps;
227}
228
229/*
230 * In order to access the breakpoint/watchpoint control registers,
231 * we must be running in debug monitor mode. Unfortunately, we can
232 * be put into halting debug mode at any time by an external debugger
233 * but there is nothing we can do to prevent that.
234 */
235static int monitor_mode_enabled(void)
236{
237 u32 dscr;
238 ARM_DBG_READ(c0, c1, 0, dscr);
239 return !!(dscr & ARM_DSCR_MDBGEN);
240}
241
242static int enable_monitor_mode(void)
243{
244 u32 dscr;
245 ARM_DBG_READ(c0, c1, 0, dscr);
246
247 /* If monitor mode is already enabled, just return. */
248 if (dscr & ARM_DSCR_MDBGEN)
249 goto out;
250
251 /* Write to the corresponding DSCR. */
252 switch (get_debug_arch()) {
253 case ARM_DEBUG_ARCH_V6:
254 case ARM_DEBUG_ARCH_V6_1:
255 ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
256 break;
257 case ARM_DEBUG_ARCH_V7_ECP14:
258 case ARM_DEBUG_ARCH_V7_1:
259 case ARM_DEBUG_ARCH_V8:
260 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
261 isb();
262 break;
263 default:
264 return -ENODEV;
265 }
266
267 /* Check that the write made it through. */
268 ARM_DBG_READ(c0, c1, 0, dscr);
269 if (!(dscr & ARM_DSCR_MDBGEN)) {
270 pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
271 smp_processor_id());
272 return -EPERM;
273 }
274
275out:
276 return 0;
277}
278
279int hw_breakpoint_slots(int type)
280{
281 if (!debug_arch_supported())
282 return 0;
283
284 /*
285 * We can be called early, so don't rely on
286 * our static variables being initialised.
287 */
288 switch (type) {
289 case TYPE_INST:
290 return get_num_brps();
291 case TYPE_DATA:
292 return get_num_wrps();
293 default:
294 pr_warn("unknown slot type: %d\n", type);
295 return 0;
296 }
297}
298
299/*
300 * Check if 8-bit byte-address select is available.
301 * This clobbers WRP 0.
302 */
303static u8 get_max_wp_len(void)
304{
305 u32 ctrl_reg;
306 struct arch_hw_breakpoint_ctrl ctrl;
307 u8 size = 4;
308
309 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
310 goto out;
311
312 memset(&ctrl, 0, sizeof(ctrl));
313 ctrl.len = ARM_BREAKPOINT_LEN_8;
314 ctrl_reg = encode_ctrl_reg(ctrl);
315
316 write_wb_reg(ARM_BASE_WVR, 0);
317 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
318 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
319 size = 8;
320
321out:
322 return size;
323}
324
325u8 arch_get_max_wp_len(void)
326{
327 return max_watchpoint_len;
328}
329
330/*
331 * Install a perf counter breakpoint.
332 */
333int arch_install_hw_breakpoint(struct perf_event *bp)
334{
335 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
336 struct perf_event **slot, **slots;
337 int i, max_slots, ctrl_base, val_base;
338 u32 addr, ctrl;
339
340 addr = info->address;
341 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
342
343 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
344 /* Breakpoint */
345 ctrl_base = ARM_BASE_BCR;
346 val_base = ARM_BASE_BVR;
347 slots = this_cpu_ptr(bp_on_reg);
348 max_slots = core_num_brps;
349 } else {
350 /* Watchpoint */
351 ctrl_base = ARM_BASE_WCR;
352 val_base = ARM_BASE_WVR;
353 slots = this_cpu_ptr(wp_on_reg);
354 max_slots = core_num_wrps;
355 }
356
357 for (i = 0; i < max_slots; ++i) {
358 slot = &slots[i];
359
360 if (!*slot) {
361 *slot = bp;
362 break;
363 }
364 }
365
366 if (i == max_slots) {
367 pr_warn("Can't find any breakpoint slot\n");
368 return -EBUSY;
369 }
370
371 /* Override the breakpoint data with the step data. */
372 if (info->step_ctrl.enabled) {
373 addr = info->trigger & ~0x3;
374 ctrl = encode_ctrl_reg(info->step_ctrl);
375 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
376 i = 0;
377 ctrl_base = ARM_BASE_BCR + core_num_brps;
378 val_base = ARM_BASE_BVR + core_num_brps;
379 }
380 }
381
382 /* Setup the address register. */
383 write_wb_reg(val_base + i, addr);
384
385 /* Setup the control register. */
386 write_wb_reg(ctrl_base + i, ctrl);
387 return 0;
388}
389
390void arch_uninstall_hw_breakpoint(struct perf_event *bp)
391{
392 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
393 struct perf_event **slot, **slots;
394 int i, max_slots, base;
395
396 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
397 /* Breakpoint */
398 base = ARM_BASE_BCR;
399 slots = this_cpu_ptr(bp_on_reg);
400 max_slots = core_num_brps;
401 } else {
402 /* Watchpoint */
403 base = ARM_BASE_WCR;
404 slots = this_cpu_ptr(wp_on_reg);
405 max_slots = core_num_wrps;
406 }
407
408 /* Remove the breakpoint. */
409 for (i = 0; i < max_slots; ++i) {
410 slot = &slots[i];
411
412 if (*slot == bp) {
413 *slot = NULL;
414 break;
415 }
416 }
417
418 if (i == max_slots) {
419 pr_warn("Can't find any breakpoint slot\n");
420 return;
421 }
422
423 /* Ensure that we disable the mismatch breakpoint. */
424 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
425 info->step_ctrl.enabled) {
426 i = 0;
427 base = ARM_BASE_BCR + core_num_brps;
428 }
429
430 /* Reset the control register. */
431 write_wb_reg(base + i, 0);
432}
433
434static int get_hbp_len(u8 hbp_len)
435{
436 unsigned int len_in_bytes = 0;
437
438 switch (hbp_len) {
439 case ARM_BREAKPOINT_LEN_1:
440 len_in_bytes = 1;
441 break;
442 case ARM_BREAKPOINT_LEN_2:
443 len_in_bytes = 2;
444 break;
445 case ARM_BREAKPOINT_LEN_4:
446 len_in_bytes = 4;
447 break;
448 case ARM_BREAKPOINT_LEN_8:
449 len_in_bytes = 8;
450 break;
451 }
452
453 return len_in_bytes;
454}
455
456/*
457 * Check whether bp virtual address is in kernel space.
458 */
459int arch_check_bp_in_kernelspace(struct perf_event *bp)
460{
461 unsigned int len;
462 unsigned long va;
463 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
464
465 va = info->address;
466 len = get_hbp_len(info->ctrl.len);
467
468 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
469}
470
471/*
472 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
473 * Hopefully this will disappear when ptrace can bypass the conversion
474 * to generic breakpoint descriptions.
475 */
476int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
477 int *gen_len, int *gen_type)
478{
479 /* Type */
480 switch (ctrl.type) {
481 case ARM_BREAKPOINT_EXECUTE:
482 *gen_type = HW_BREAKPOINT_X;
483 break;
484 case ARM_BREAKPOINT_LOAD:
485 *gen_type = HW_BREAKPOINT_R;
486 break;
487 case ARM_BREAKPOINT_STORE:
488 *gen_type = HW_BREAKPOINT_W;
489 break;
490 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
491 *gen_type = HW_BREAKPOINT_RW;
492 break;
493 default:
494 return -EINVAL;
495 }
496
497 /* Len */
498 switch (ctrl.len) {
499 case ARM_BREAKPOINT_LEN_1:
500 *gen_len = HW_BREAKPOINT_LEN_1;
501 break;
502 case ARM_BREAKPOINT_LEN_2:
503 *gen_len = HW_BREAKPOINT_LEN_2;
504 break;
505 case ARM_BREAKPOINT_LEN_4:
506 *gen_len = HW_BREAKPOINT_LEN_4;
507 break;
508 case ARM_BREAKPOINT_LEN_8:
509 *gen_len = HW_BREAKPOINT_LEN_8;
510 break;
511 default:
512 return -EINVAL;
513 }
514
515 return 0;
516}
517
518/*
519 * Construct an arch_hw_breakpoint from a perf_event.
520 */
521static int arch_build_bp_info(struct perf_event *bp)
522{
523 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
524
525 /* Type */
526 switch (bp->attr.bp_type) {
527 case HW_BREAKPOINT_X:
528 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
529 break;
530 case HW_BREAKPOINT_R:
531 info->ctrl.type = ARM_BREAKPOINT_LOAD;
532 break;
533 case HW_BREAKPOINT_W:
534 info->ctrl.type = ARM_BREAKPOINT_STORE;
535 break;
536 case HW_BREAKPOINT_RW:
537 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 /* Len */
544 switch (bp->attr.bp_len) {
545 case HW_BREAKPOINT_LEN_1:
546 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
547 break;
548 case HW_BREAKPOINT_LEN_2:
549 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
550 break;
551 case HW_BREAKPOINT_LEN_4:
552 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
553 break;
554 case HW_BREAKPOINT_LEN_8:
555 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
556 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
557 && max_watchpoint_len >= 8)
558 break;
559 default:
560 return -EINVAL;
561 }
562
563 /*
564 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
565 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
566 * by the hardware and must be aligned to the appropriate number of
567 * bytes.
568 */
569 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
570 info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
571 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
572 return -EINVAL;
573
574 /* Address */
575 info->address = bp->attr.bp_addr;
576
577 /* Privilege */
578 info->ctrl.privilege = ARM_BREAKPOINT_USER;
579 if (arch_check_bp_in_kernelspace(bp))
580 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
581
582 /* Enabled? */
583 info->ctrl.enabled = !bp->attr.disabled;
584
585 /* Mismatch */
586 info->ctrl.mismatch = 0;
587
588 return 0;
589}
590
591/*
592 * Validate the arch-specific HW Breakpoint register settings.
593 */
594int arch_validate_hwbkpt_settings(struct perf_event *bp)
595{
596 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
597 int ret = 0;
598 u32 offset, alignment_mask = 0x3;
599
600 /* Ensure that we are in monitor debug mode. */
601 if (!monitor_mode_enabled())
602 return -ENODEV;
603
604 /* Build the arch_hw_breakpoint. */
605 ret = arch_build_bp_info(bp);
606 if (ret)
607 goto out;
608
609 /* Check address alignment. */
610 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
611 alignment_mask = 0x7;
612 offset = info->address & alignment_mask;
613 switch (offset) {
614 case 0:
615 /* Aligned */
616 break;
617 case 1:
618 case 2:
619 /* Allow halfword watchpoints and breakpoints. */
620 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
621 break;
622 case 3:
623 /* Allow single byte watchpoint. */
624 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
625 break;
626 default:
627 ret = -EINVAL;
628 goto out;
629 }
630
631 info->address &= ~alignment_mask;
632 info->ctrl.len <<= offset;
633
634 if (!bp->overflow_handler) {
635 /*
636 * Mismatch breakpoints are required for single-stepping
637 * breakpoints.
638 */
639 if (!core_has_mismatch_brps())
640 return -EINVAL;
641
642 /* We don't allow mismatch breakpoints in kernel space. */
643 if (arch_check_bp_in_kernelspace(bp))
644 return -EPERM;
645
646 /*
647 * Per-cpu breakpoints are not supported by our stepping
648 * mechanism.
649 */
650 if (!bp->hw.target)
651 return -EINVAL;
652
653 /*
654 * We only support specific access types if the fsr
655 * reports them.
656 */
657 if (!debug_exception_updates_fsr() &&
658 (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
659 info->ctrl.type == ARM_BREAKPOINT_STORE))
660 return -EINVAL;
661 }
662
663out:
664 return ret;
665}
666
667/*
668 * Enable/disable single-stepping over the breakpoint bp at address addr.
669 */
670static void enable_single_step(struct perf_event *bp, u32 addr)
671{
672 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
673
674 arch_uninstall_hw_breakpoint(bp);
675 info->step_ctrl.mismatch = 1;
676 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
677 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
678 info->step_ctrl.privilege = info->ctrl.privilege;
679 info->step_ctrl.enabled = 1;
680 info->trigger = addr;
681 arch_install_hw_breakpoint(bp);
682}
683
684static void disable_single_step(struct perf_event *bp)
685{
686 arch_uninstall_hw_breakpoint(bp);
687 counter_arch_bp(bp)->step_ctrl.enabled = 0;
688 arch_install_hw_breakpoint(bp);
689}
690
691static void watchpoint_handler(unsigned long addr, unsigned int fsr,
692 struct pt_regs *regs)
693{
694 int i, access;
695 u32 val, ctrl_reg, alignment_mask;
696 struct perf_event *wp, **slots;
697 struct arch_hw_breakpoint *info;
698 struct arch_hw_breakpoint_ctrl ctrl;
699
700 slots = this_cpu_ptr(wp_on_reg);
701
702 for (i = 0; i < core_num_wrps; ++i) {
703 rcu_read_lock();
704
705 wp = slots[i];
706
707 if (wp == NULL)
708 goto unlock;
709
710 info = counter_arch_bp(wp);
711 /*
712 * The DFAR is an unknown value on debug architectures prior
713 * to 7.1. Since we only allow a single watchpoint on these
714 * older CPUs, we can set the trigger to the lowest possible
715 * faulting address.
716 */
717 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
718 BUG_ON(i > 0);
719 info->trigger = wp->attr.bp_addr;
720 } else {
721 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
722 alignment_mask = 0x7;
723 else
724 alignment_mask = 0x3;
725
726 /* Check if the watchpoint value matches. */
727 val = read_wb_reg(ARM_BASE_WVR + i);
728 if (val != (addr & ~alignment_mask))
729 goto unlock;
730
731 /* Possible match, check the byte address select. */
732 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
733 decode_ctrl_reg(ctrl_reg, &ctrl);
734 if (!((1 << (addr & alignment_mask)) & ctrl.len))
735 goto unlock;
736
737 /* Check that the access type matches. */
738 if (debug_exception_updates_fsr()) {
739 access = (fsr & ARM_FSR_ACCESS_MASK) ?
740 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
741 if (!(access & hw_breakpoint_type(wp)))
742 goto unlock;
743 }
744
745 /* We have a winner. */
746 info->trigger = addr;
747 }
748
749 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
750 perf_bp_event(wp, regs);
751
752 /*
753 * If no overflow handler is present, insert a temporary
754 * mismatch breakpoint so we can single-step over the
755 * watchpoint trigger.
756 */
757 if (!wp->overflow_handler)
758 enable_single_step(wp, instruction_pointer(regs));
759
760unlock:
761 rcu_read_unlock();
762 }
763}
764
765static void watchpoint_single_step_handler(unsigned long pc)
766{
767 int i;
768 struct perf_event *wp, **slots;
769 struct arch_hw_breakpoint *info;
770
771 slots = this_cpu_ptr(wp_on_reg);
772
773 for (i = 0; i < core_num_wrps; ++i) {
774 rcu_read_lock();
775
776 wp = slots[i];
777
778 if (wp == NULL)
779 goto unlock;
780
781 info = counter_arch_bp(wp);
782 if (!info->step_ctrl.enabled)
783 goto unlock;
784
785 /*
786 * Restore the original watchpoint if we've completed the
787 * single-step.
788 */
789 if (info->trigger != pc)
790 disable_single_step(wp);
791
792unlock:
793 rcu_read_unlock();
794 }
795}
796
797static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
798{
799 int i;
800 u32 ctrl_reg, val, addr;
801 struct perf_event *bp, **slots;
802 struct arch_hw_breakpoint *info;
803 struct arch_hw_breakpoint_ctrl ctrl;
804
805 slots = this_cpu_ptr(bp_on_reg);
806
807 /* The exception entry code places the amended lr in the PC. */
808 addr = regs->ARM_pc;
809
810 /* Check the currently installed breakpoints first. */
811 for (i = 0; i < core_num_brps; ++i) {
812 rcu_read_lock();
813
814 bp = slots[i];
815
816 if (bp == NULL)
817 goto unlock;
818
819 info = counter_arch_bp(bp);
820
821 /* Check if the breakpoint value matches. */
822 val = read_wb_reg(ARM_BASE_BVR + i);
823 if (val != (addr & ~0x3))
824 goto mismatch;
825
826 /* Possible match, check the byte address select to confirm. */
827 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
828 decode_ctrl_reg(ctrl_reg, &ctrl);
829 if ((1 << (addr & 0x3)) & ctrl.len) {
830 info->trigger = addr;
831 pr_debug("breakpoint fired: address = 0x%x\n", addr);
832 perf_bp_event(bp, regs);
833 if (!bp->overflow_handler)
834 enable_single_step(bp, addr);
835 goto unlock;
836 }
837
838mismatch:
839 /* If we're stepping a breakpoint, it can now be restored. */
840 if (info->step_ctrl.enabled)
841 disable_single_step(bp);
842unlock:
843 rcu_read_unlock();
844 }
845
846 /* Handle any pending watchpoint single-step breakpoints. */
847 watchpoint_single_step_handler(addr);
848}
849
850/*
851 * Called from either the Data Abort Handler [watchpoint] or the
852 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
853 */
854static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
855 struct pt_regs *regs)
856{
857 int ret = 0;
858 u32 dscr;
859
860 preempt_disable();
861
862 if (interrupts_enabled(regs))
863 local_irq_enable();
864
865 /* We only handle watchpoints and hardware breakpoints. */
866 ARM_DBG_READ(c0, c1, 0, dscr);
867
868 /* Perform perf callbacks. */
869 switch (ARM_DSCR_MOE(dscr)) {
870 case ARM_ENTRY_BREAKPOINT:
871 breakpoint_handler(addr, regs);
872 break;
873 case ARM_ENTRY_ASYNC_WATCHPOINT:
874 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
875 case ARM_ENTRY_SYNC_WATCHPOINT:
876 watchpoint_handler(addr, fsr, regs);
877 break;
878 default:
879 ret = 1; /* Unhandled fault. */
880 }
881
882 preempt_enable();
883
884 return ret;
885}
886
887/*
888 * One-time initialisation.
889 */
890static cpumask_t debug_err_mask;
891
892static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
893{
894 int cpu = smp_processor_id();
895
896 pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
897 instr, cpu);
898
899 /* Set the error flag for this CPU and skip the faulting instruction. */
900 cpumask_set_cpu(cpu, &debug_err_mask);
901 instruction_pointer(regs) += 4;
902 return 0;
903}
904
905static struct undef_hook debug_reg_hook = {
906 .instr_mask = 0x0fe80f10,
907 .instr_val = 0x0e000e10,
908 .fn = debug_reg_trap,
909};
910
911/* Does this core support OS Save and Restore? */
912static bool core_has_os_save_restore(void)
913{
914 u32 oslsr;
915
916 switch (get_debug_arch()) {
917 case ARM_DEBUG_ARCH_V7_1:
918 return true;
919 case ARM_DEBUG_ARCH_V7_ECP14:
920 ARM_DBG_READ(c1, c1, 4, oslsr);
921 if (oslsr & ARM_OSLSR_OSLM0)
922 return true;
923 default:
924 return false;
925 }
926}
927
928static void reset_ctrl_regs(void *unused)
929{
930 int i, raw_num_brps, err = 0, cpu = smp_processor_id();
931 u32 val;
932
933 /*
934 * v7 debug contains save and restore registers so that debug state
935 * can be maintained across low-power modes without leaving the debug
936 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
937 * the debug registers out of reset, so we must unlock the OS Lock
938 * Access Register to avoid taking undefined instruction exceptions
939 * later on.
940 */
941 switch (debug_arch) {
942 case ARM_DEBUG_ARCH_V6:
943 case ARM_DEBUG_ARCH_V6_1:
944 /* ARMv6 cores clear the registers out of reset. */
945 goto out_mdbgen;
946 case ARM_DEBUG_ARCH_V7_ECP14:
947 /*
948 * Ensure sticky power-down is clear (i.e. debug logic is
949 * powered up).
950 */
951 ARM_DBG_READ(c1, c5, 4, val);
952 if ((val & 0x1) == 0)
953 err = -EPERM;
954
955 if (!has_ossr)
956 goto clear_vcr;
957 break;
958 case ARM_DEBUG_ARCH_V7_1:
959 /*
960 * Ensure the OS double lock is clear.
961 */
962 ARM_DBG_READ(c1, c3, 4, val);
963 if ((val & 0x1) == 1)
964 err = -EPERM;
965 break;
966 }
967
968 if (err) {
969 pr_warn_once("CPU %d debug is powered down!\n", cpu);
970 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
971 return;
972 }
973
974 /*
975 * Unconditionally clear the OS lock by writing a value
976 * other than CS_LAR_KEY to the access register.
977 */
978 ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK);
979 isb();
980
981 /*
982 * Clear any configured vector-catch events before
983 * enabling monitor mode.
984 */
985clear_vcr:
986 ARM_DBG_WRITE(c0, c7, 0, 0);
987 isb();
988
989 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
990 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
991 return;
992 }
993
994 /*
995 * The control/value register pairs are UNKNOWN out of reset so
996 * clear them to avoid spurious debug events.
997 */
998 raw_num_brps = get_num_brp_resources();
999 for (i = 0; i < raw_num_brps; ++i) {
1000 write_wb_reg(ARM_BASE_BCR + i, 0UL);
1001 write_wb_reg(ARM_BASE_BVR + i, 0UL);
1002 }
1003
1004 for (i = 0; i < core_num_wrps; ++i) {
1005 write_wb_reg(ARM_BASE_WCR + i, 0UL);
1006 write_wb_reg(ARM_BASE_WVR + i, 0UL);
1007 }
1008
1009 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1010 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1011 return;
1012 }
1013
1014 /*
1015 * Have a crack at enabling monitor mode. We don't actually need
1016 * it yet, but reporting an error early is useful if it fails.
1017 */
1018out_mdbgen:
1019 if (enable_monitor_mode())
1020 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1021}
1022
1023static int dbg_reset_notify(struct notifier_block *self,
1024 unsigned long action, void *cpu)
1025{
1026 if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
1027 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
1028
1029 return NOTIFY_OK;
1030}
1031
1032static struct notifier_block dbg_reset_nb = {
1033 .notifier_call = dbg_reset_notify,
1034};
1035
1036#ifdef CONFIG_CPU_PM
1037static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
1038 void *v)
1039{
1040 if (action == CPU_PM_EXIT)
1041 reset_ctrl_regs(NULL);
1042
1043 return NOTIFY_OK;
1044}
1045
1046static struct notifier_block dbg_cpu_pm_nb = {
1047 .notifier_call = dbg_cpu_pm_notify,
1048};
1049
1050static void __init pm_init(void)
1051{
1052 cpu_pm_register_notifier(&dbg_cpu_pm_nb);
1053}
1054#else
1055static inline void pm_init(void)
1056{
1057}
1058#endif
1059
1060static int __init arch_hw_breakpoint_init(void)
1061{
1062 debug_arch = get_debug_arch();
1063
1064 if (!debug_arch_supported()) {
1065 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1066 return 0;
1067 }
1068
1069 has_ossr = core_has_os_save_restore();
1070
1071 /* Determine how many BRPs/WRPs are available. */
1072 core_num_brps = get_num_brps();
1073 core_num_wrps = get_num_wrps();
1074
1075 cpu_notifier_register_begin();
1076
1077 /*
1078 * We need to tread carefully here because DBGSWENABLE may be
1079 * driven low on this core and there isn't an architected way to
1080 * determine that.
1081 */
1082 register_undef_hook(&debug_reg_hook);
1083
1084 /*
1085 * Reset the breakpoint resources. We assume that a halting
1086 * debugger will leave the world in a nice state for us.
1087 */
1088 on_each_cpu(reset_ctrl_regs, NULL, 1);
1089 unregister_undef_hook(&debug_reg_hook);
1090 if (!cpumask_empty(&debug_err_mask)) {
1091 core_num_brps = 0;
1092 core_num_wrps = 0;
1093 cpu_notifier_register_done();
1094 return 0;
1095 }
1096
1097 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1098 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1099 "", core_num_wrps);
1100
1101 /* Work out the maximum supported watchpoint length. */
1102 max_watchpoint_len = get_max_wp_len();
1103 pr_info("maximum watchpoint size is %u bytes.\n",
1104 max_watchpoint_len);
1105
1106 /* Register debug fault handler. */
1107 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1108 TRAP_HWBKPT, "watchpoint debug exception");
1109 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1110 TRAP_HWBKPT, "breakpoint debug exception");
1111
1112 /* Register hotplug and PM notifiers. */
1113 __register_cpu_notifier(&dbg_reset_nb);
1114
1115 cpu_notifier_register_done();
1116
1117 pm_init();
1118 return 0;
1119}
1120arch_initcall(arch_hw_breakpoint_init);
1121
1122void hw_breakpoint_pmu_read(struct perf_event *bp)
1123{
1124}
1125
1126/*
1127 * Dummy function to register with die_notifier.
1128 */
1129int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1130 unsigned long val, void *data)
1131{
1132 return NOTIFY_DONE;
1133}