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1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include "skeleton.dtsi"
14#include "imx28-pinfunc.h"
15
16/ {
17 interrupt-parent = <&icoll>;
18
19 aliases {
20 ethernet0 = &mac0;
21 ethernet1 = &mac1;
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 saif0 = &saif0;
28 saif1 = &saif1;
29 serial0 = &auart0;
30 serial1 = &auart1;
31 serial2 = &auart2;
32 serial3 = &auart3;
33 serial4 = &auart4;
34 spi0 = &ssp1;
35 spi1 = &ssp2;
36 usbphy0 = &usbphy0;
37 usbphy1 = &usbphy1;
38 };
39
40 cpus {
41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
47 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x3c900>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
65 compatible = "fsl,imx28-icoll", "fsl,icoll";
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
71 hsadc: hsadc@80002000 {
72 reg = <0x80002000 0x2000>;
73 interrupts = <13>;
74 dmas = <&dma_apbh 12>;
75 dma-names = "rx";
76 status = "disabled";
77 };
78
79 dma_apbh: dma-apbh@80004000 {
80 compatible = "fsl,imx28-dma-apbh";
81 reg = <0x80004000 0x2000>;
82 interrupts = <82 83 84 85
83 88 88 88 88
84 88 88 88 88
85 87 86 0 0>;
86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
87 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
88 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
89 "hsadc", "lcdif", "empty", "empty";
90 #dma-cells = <1>;
91 dma-channels = <16>;
92 clocks = <&clks 25>;
93 };
94
95 perfmon: perfmon@80006000 {
96 reg = <0x80006000 0x800>;
97 interrupts = <27>;
98 status = "disabled";
99 };
100
101 gpmi: gpmi-nand@8000c000 {
102 compatible = "fsl,imx28-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <41>;
108 interrupt-names = "bch";
109 clocks = <&clks 50>;
110 clock-names = "gpmi_io";
111 dmas = <&dma_apbh 4>;
112 dma-names = "rx-tx";
113 status = "disabled";
114 };
115
116 ssp0: ssp@80010000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0x80010000 0x2000>;
120 interrupts = <96>;
121 clocks = <&clks 46>;
122 dmas = <&dma_apbh 0>;
123 dma-names = "rx-tx";
124 status = "disabled";
125 };
126
127 ssp1: ssp@80012000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <0x80012000 0x2000>;
131 interrupts = <97>;
132 clocks = <&clks 47>;
133 dmas = <&dma_apbh 1>;
134 dma-names = "rx-tx";
135 status = "disabled";
136 };
137
138 ssp2: ssp@80014000 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <0x80014000 0x2000>;
142 interrupts = <98>;
143 clocks = <&clks 48>;
144 dmas = <&dma_apbh 2>;
145 dma-names = "rx-tx";
146 status = "disabled";
147 };
148
149 ssp3: ssp@80016000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0x80016000 0x2000>;
153 interrupts = <99>;
154 clocks = <&clks 49>;
155 dmas = <&dma_apbh 3>;
156 dma-names = "rx-tx";
157 status = "disabled";
158 };
159
160 pinctrl: pinctrl@80018000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx28-pinctrl", "simple-bus";
164 reg = <0x80018000 0x2000>;
165
166 gpio0: gpio@0 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <127>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio1: gpio@1 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <126>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
184 gpio2: gpio@2 {
185 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
186 interrupts = <125>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 };
192
193 gpio3: gpio@3 {
194 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
195 interrupts = <124>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio4: gpio@4 {
203 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupts = <123>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 };
210
211 duart_pins_a: duart@0 {
212 reg = <0>;
213 fsl,pinmux-ids = <
214 MX28_PAD_PWM0__DUART_RX
215 MX28_PAD_PWM1__DUART_TX
216 >;
217 fsl,drive-strength = <MXS_DRIVE_4mA>;
218 fsl,voltage = <MXS_VOLTAGE_HIGH>;
219 fsl,pull-up = <MXS_PULL_DISABLE>;
220 };
221
222 duart_pins_b: duart@1 {
223 reg = <1>;
224 fsl,pinmux-ids = <
225 MX28_PAD_AUART0_CTS__DUART_RX
226 MX28_PAD_AUART0_RTS__DUART_TX
227 >;
228 fsl,drive-strength = <MXS_DRIVE_4mA>;
229 fsl,voltage = <MXS_VOLTAGE_HIGH>;
230 fsl,pull-up = <MXS_PULL_DISABLE>;
231 };
232
233 duart_4pins_a: duart-4pins@0 {
234 reg = <0>;
235 fsl,pinmux-ids = <
236 MX28_PAD_AUART0_CTS__DUART_RX
237 MX28_PAD_AUART0_RTS__DUART_TX
238 MX28_PAD_AUART0_RX__DUART_CTS
239 MX28_PAD_AUART0_TX__DUART_RTS
240 >;
241 fsl,drive-strength = <MXS_DRIVE_4mA>;
242 fsl,voltage = <MXS_VOLTAGE_HIGH>;
243 fsl,pull-up = <MXS_PULL_DISABLE>;
244 };
245
246 gpmi_pins_a: gpmi-nand@0 {
247 reg = <0>;
248 fsl,pinmux-ids = <
249 MX28_PAD_GPMI_D00__GPMI_D0
250 MX28_PAD_GPMI_D01__GPMI_D1
251 MX28_PAD_GPMI_D02__GPMI_D2
252 MX28_PAD_GPMI_D03__GPMI_D3
253 MX28_PAD_GPMI_D04__GPMI_D4
254 MX28_PAD_GPMI_D05__GPMI_D5
255 MX28_PAD_GPMI_D06__GPMI_D6
256 MX28_PAD_GPMI_D07__GPMI_D7
257 MX28_PAD_GPMI_CE0N__GPMI_CE0N
258 MX28_PAD_GPMI_RDY0__GPMI_READY0
259 MX28_PAD_GPMI_RDN__GPMI_RDN
260 MX28_PAD_GPMI_WRN__GPMI_WRN
261 MX28_PAD_GPMI_ALE__GPMI_ALE
262 MX28_PAD_GPMI_CLE__GPMI_CLE
263 MX28_PAD_GPMI_RESETN__GPMI_RESETN
264 >;
265 fsl,drive-strength = <MXS_DRIVE_4mA>;
266 fsl,voltage = <MXS_VOLTAGE_HIGH>;
267 fsl,pull-up = <MXS_PULL_DISABLE>;
268 };
269
270 gpmi_status_cfg: gpmi-status-cfg {
271 fsl,pinmux-ids = <
272 MX28_PAD_GPMI_RDN__GPMI_RDN
273 MX28_PAD_GPMI_WRN__GPMI_WRN
274 MX28_PAD_GPMI_RESETN__GPMI_RESETN
275 >;
276 fsl,drive-strength = <MXS_DRIVE_12mA>;
277 };
278
279 auart0_pins_a: auart0@0 {
280 reg = <0>;
281 fsl,pinmux-ids = <
282 MX28_PAD_AUART0_RX__AUART0_RX
283 MX28_PAD_AUART0_TX__AUART0_TX
284 MX28_PAD_AUART0_CTS__AUART0_CTS
285 MX28_PAD_AUART0_RTS__AUART0_RTS
286 >;
287 fsl,drive-strength = <MXS_DRIVE_4mA>;
288 fsl,voltage = <MXS_VOLTAGE_HIGH>;
289 fsl,pull-up = <MXS_PULL_DISABLE>;
290 };
291
292 auart0_2pins_a: auart0-2pins@0 {
293 reg = <0>;
294 fsl,pinmux-ids = <
295 MX28_PAD_AUART0_RX__AUART0_RX
296 MX28_PAD_AUART0_TX__AUART0_TX
297 >;
298 fsl,drive-strength = <MXS_DRIVE_4mA>;
299 fsl,voltage = <MXS_VOLTAGE_HIGH>;
300 fsl,pull-up = <MXS_PULL_DISABLE>;
301 };
302
303 auart1_pins_a: auart1@0 {
304 reg = <0>;
305 fsl,pinmux-ids = <
306 MX28_PAD_AUART1_RX__AUART1_RX
307 MX28_PAD_AUART1_TX__AUART1_TX
308 MX28_PAD_AUART1_CTS__AUART1_CTS
309 MX28_PAD_AUART1_RTS__AUART1_RTS
310 >;
311 fsl,drive-strength = <MXS_DRIVE_4mA>;
312 fsl,voltage = <MXS_VOLTAGE_HIGH>;
313 fsl,pull-up = <MXS_PULL_DISABLE>;
314 };
315
316 auart1_2pins_a: auart1-2pins@0 {
317 reg = <0>;
318 fsl,pinmux-ids = <
319 MX28_PAD_AUART1_RX__AUART1_RX
320 MX28_PAD_AUART1_TX__AUART1_TX
321 >;
322 fsl,drive-strength = <MXS_DRIVE_4mA>;
323 fsl,voltage = <MXS_VOLTAGE_HIGH>;
324 fsl,pull-up = <MXS_PULL_DISABLE>;
325 };
326
327 auart2_2pins_a: auart2-2pins@0 {
328 reg = <0>;
329 fsl,pinmux-ids = <
330 MX28_PAD_SSP2_SCK__AUART2_RX
331 MX28_PAD_SSP2_MOSI__AUART2_TX
332 >;
333 fsl,drive-strength = <MXS_DRIVE_4mA>;
334 fsl,voltage = <MXS_VOLTAGE_HIGH>;
335 fsl,pull-up = <MXS_PULL_DISABLE>;
336 };
337
338 auart2_2pins_b: auart2-2pins@1 {
339 reg = <1>;
340 fsl,pinmux-ids = <
341 MX28_PAD_AUART2_RX__AUART2_RX
342 MX28_PAD_AUART2_TX__AUART2_TX
343 >;
344 fsl,drive-strength = <MXS_DRIVE_4mA>;
345 fsl,voltage = <MXS_VOLTAGE_HIGH>;
346 fsl,pull-up = <MXS_PULL_DISABLE>;
347 };
348
349 auart2_pins_a: auart2-pins@0 {
350 reg = <0>;
351 fsl,pinmux-ids = <
352 MX28_PAD_AUART2_RX__AUART2_RX
353 MX28_PAD_AUART2_TX__AUART2_TX
354 MX28_PAD_AUART2_CTS__AUART2_CTS
355 MX28_PAD_AUART2_RTS__AUART2_RTS
356 >;
357 fsl,drive-strength = <MXS_DRIVE_4mA>;
358 fsl,voltage = <MXS_VOLTAGE_HIGH>;
359 fsl,pull-up = <MXS_PULL_DISABLE>;
360 };
361
362 auart3_pins_a: auart3@0 {
363 reg = <0>;
364 fsl,pinmux-ids = <
365 MX28_PAD_AUART3_RX__AUART3_RX
366 MX28_PAD_AUART3_TX__AUART3_TX
367 MX28_PAD_AUART3_CTS__AUART3_CTS
368 MX28_PAD_AUART3_RTS__AUART3_RTS
369 >;
370 fsl,drive-strength = <MXS_DRIVE_4mA>;
371 fsl,voltage = <MXS_VOLTAGE_HIGH>;
372 fsl,pull-up = <MXS_PULL_DISABLE>;
373 };
374
375 auart3_2pins_a: auart3-2pins@0 {
376 reg = <0>;
377 fsl,pinmux-ids = <
378 MX28_PAD_SSP2_MISO__AUART3_RX
379 MX28_PAD_SSP2_SS0__AUART3_TX
380 >;
381 fsl,drive-strength = <MXS_DRIVE_4mA>;
382 fsl,voltage = <MXS_VOLTAGE_HIGH>;
383 fsl,pull-up = <MXS_PULL_DISABLE>;
384 };
385
386 auart3_2pins_b: auart3-2pins@1 {
387 reg = <1>;
388 fsl,pinmux-ids = <
389 MX28_PAD_AUART3_RX__AUART3_RX
390 MX28_PAD_AUART3_TX__AUART3_TX
391 >;
392 fsl,drive-strength = <MXS_DRIVE_4mA>;
393 fsl,voltage = <MXS_VOLTAGE_HIGH>;
394 fsl,pull-up = <MXS_PULL_DISABLE>;
395 };
396
397 auart4_2pins_a: auart4@0 {
398 reg = <0>;
399 fsl,pinmux-ids = <
400 MX28_PAD_SSP3_SCK__AUART4_TX
401 MX28_PAD_SSP3_MOSI__AUART4_RX
402 >;
403 fsl,drive-strength = <MXS_DRIVE_4mA>;
404 fsl,voltage = <MXS_VOLTAGE_HIGH>;
405 fsl,pull-up = <MXS_PULL_DISABLE>;
406 };
407
408 auart4_2pins_b: auart4@1 {
409 reg = <1>;
410 fsl,pinmux-ids = <
411 MX28_PAD_AUART0_CTS__AUART4_RX
412 MX28_PAD_AUART0_RTS__AUART4_TX
413 >;
414 fsl,drive-strength = <MXS_DRIVE_4mA>;
415 fsl,voltage = <MXS_VOLTAGE_HIGH>;
416 fsl,pull-up = <MXS_PULL_DISABLE>;
417 };
418
419 mac0_pins_a: mac0@0 {
420 reg = <0>;
421 fsl,pinmux-ids = <
422 MX28_PAD_ENET0_MDC__ENET0_MDC
423 MX28_PAD_ENET0_MDIO__ENET0_MDIO
424 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
425 MX28_PAD_ENET0_RXD0__ENET0_RXD0
426 MX28_PAD_ENET0_RXD1__ENET0_RXD1
427 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
428 MX28_PAD_ENET0_TXD0__ENET0_TXD0
429 MX28_PAD_ENET0_TXD1__ENET0_TXD1
430 MX28_PAD_ENET_CLK__CLKCTRL_ENET
431 >;
432 fsl,drive-strength = <MXS_DRIVE_8mA>;
433 fsl,voltage = <MXS_VOLTAGE_HIGH>;
434 fsl,pull-up = <MXS_PULL_ENABLE>;
435 };
436
437 mac1_pins_a: mac1@0 {
438 reg = <0>;
439 fsl,pinmux-ids = <
440 MX28_PAD_ENET0_CRS__ENET1_RX_EN
441 MX28_PAD_ENET0_RXD2__ENET1_RXD0
442 MX28_PAD_ENET0_RXD3__ENET1_RXD1
443 MX28_PAD_ENET0_COL__ENET1_TX_EN
444 MX28_PAD_ENET0_TXD2__ENET1_TXD0
445 MX28_PAD_ENET0_TXD3__ENET1_TXD1
446 >;
447 fsl,drive-strength = <MXS_DRIVE_8mA>;
448 fsl,voltage = <MXS_VOLTAGE_HIGH>;
449 fsl,pull-up = <MXS_PULL_ENABLE>;
450 };
451
452 mmc0_8bit_pins_a: mmc0-8bit@0 {
453 reg = <0>;
454 fsl,pinmux-ids = <
455 MX28_PAD_SSP0_DATA0__SSP0_D0
456 MX28_PAD_SSP0_DATA1__SSP0_D1
457 MX28_PAD_SSP0_DATA2__SSP0_D2
458 MX28_PAD_SSP0_DATA3__SSP0_D3
459 MX28_PAD_SSP0_DATA4__SSP0_D4
460 MX28_PAD_SSP0_DATA5__SSP0_D5
461 MX28_PAD_SSP0_DATA6__SSP0_D6
462 MX28_PAD_SSP0_DATA7__SSP0_D7
463 MX28_PAD_SSP0_CMD__SSP0_CMD
464 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
465 MX28_PAD_SSP0_SCK__SSP0_SCK
466 >;
467 fsl,drive-strength = <MXS_DRIVE_8mA>;
468 fsl,voltage = <MXS_VOLTAGE_HIGH>;
469 fsl,pull-up = <MXS_PULL_ENABLE>;
470 };
471
472 mmc0_4bit_pins_a: mmc0-4bit@0 {
473 reg = <0>;
474 fsl,pinmux-ids = <
475 MX28_PAD_SSP0_DATA0__SSP0_D0
476 MX28_PAD_SSP0_DATA1__SSP0_D1
477 MX28_PAD_SSP0_DATA2__SSP0_D2
478 MX28_PAD_SSP0_DATA3__SSP0_D3
479 MX28_PAD_SSP0_CMD__SSP0_CMD
480 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
481 MX28_PAD_SSP0_SCK__SSP0_SCK
482 >;
483 fsl,drive-strength = <MXS_DRIVE_8mA>;
484 fsl,voltage = <MXS_VOLTAGE_HIGH>;
485 fsl,pull-up = <MXS_PULL_ENABLE>;
486 };
487
488 mmc0_cd_cfg: mmc0-cd-cfg {
489 fsl,pinmux-ids = <
490 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
491 >;
492 fsl,pull-up = <MXS_PULL_DISABLE>;
493 };
494
495 mmc0_sck_cfg: mmc0-sck-cfg {
496 fsl,pinmux-ids = <
497 MX28_PAD_SSP0_SCK__SSP0_SCK
498 >;
499 fsl,drive-strength = <MXS_DRIVE_12mA>;
500 fsl,pull-up = <MXS_PULL_DISABLE>;
501 };
502
503 mmc1_4bit_pins_a: mmc1-4bit@0 {
504 reg = <0>;
505 fsl,pinmux-ids = <
506 MX28_PAD_GPMI_D00__SSP1_D0
507 MX28_PAD_GPMI_D01__SSP1_D1
508 MX28_PAD_GPMI_D02__SSP1_D2
509 MX28_PAD_GPMI_D03__SSP1_D3
510 MX28_PAD_GPMI_RDY1__SSP1_CMD
511 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
512 MX28_PAD_GPMI_WRN__SSP1_SCK
513 >;
514 fsl,drive-strength = <MXS_DRIVE_8mA>;
515 fsl,voltage = <MXS_VOLTAGE_HIGH>;
516 fsl,pull-up = <MXS_PULL_ENABLE>;
517 };
518
519 mmc1_cd_cfg: mmc1-cd-cfg {
520 fsl,pinmux-ids = <
521 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
522 >;
523 fsl,pull-up = <MXS_PULL_DISABLE>;
524 };
525
526 mmc1_sck_cfg: mmc1-sck-cfg {
527 fsl,pinmux-ids = <
528 MX28_PAD_GPMI_WRN__SSP1_SCK
529 >;
530 fsl,drive-strength = <MXS_DRIVE_12mA>;
531 fsl,pull-up = <MXS_PULL_DISABLE>;
532 };
533
534
535 mmc2_4bit_pins_a: mmc2-4bit@0 {
536 reg = <0>;
537 fsl,pinmux-ids = <
538 MX28_PAD_SSP0_DATA4__SSP2_D0
539 MX28_PAD_SSP1_SCK__SSP2_D1
540 MX28_PAD_SSP1_CMD__SSP2_D2
541 MX28_PAD_SSP0_DATA5__SSP2_D3
542 MX28_PAD_SSP0_DATA6__SSP2_CMD
543 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
544 MX28_PAD_SSP0_DATA7__SSP2_SCK
545 >;
546 fsl,drive-strength = <MXS_DRIVE_8mA>;
547 fsl,voltage = <MXS_VOLTAGE_HIGH>;
548 fsl,pull-up = <MXS_PULL_ENABLE>;
549 };
550
551 mmc2_cd_cfg: mmc2-cd-cfg {
552 fsl,pinmux-ids = <
553 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
554 >;
555 fsl,pull-up = <MXS_PULL_DISABLE>;
556 };
557
558 mmc2_sck_cfg: mmc2-sck-cfg {
559 fsl,pinmux-ids = <
560 MX28_PAD_SSP0_DATA7__SSP2_SCK
561 >;
562 fsl,drive-strength = <MXS_DRIVE_12mA>;
563 fsl,pull-up = <MXS_PULL_DISABLE>;
564 };
565
566 i2c0_pins_a: i2c0@0 {
567 reg = <0>;
568 fsl,pinmux-ids = <
569 MX28_PAD_I2C0_SCL__I2C0_SCL
570 MX28_PAD_I2C0_SDA__I2C0_SDA
571 >;
572 fsl,drive-strength = <MXS_DRIVE_8mA>;
573 fsl,voltage = <MXS_VOLTAGE_HIGH>;
574 fsl,pull-up = <MXS_PULL_ENABLE>;
575 };
576
577 i2c0_pins_b: i2c0@1 {
578 reg = <1>;
579 fsl,pinmux-ids = <
580 MX28_PAD_AUART0_RX__I2C0_SCL
581 MX28_PAD_AUART0_TX__I2C0_SDA
582 >;
583 fsl,drive-strength = <MXS_DRIVE_8mA>;
584 fsl,voltage = <MXS_VOLTAGE_HIGH>;
585 fsl,pull-up = <MXS_PULL_ENABLE>;
586 };
587
588 i2c1_pins_a: i2c1@0 {
589 reg = <0>;
590 fsl,pinmux-ids = <
591 MX28_PAD_PWM0__I2C1_SCL
592 MX28_PAD_PWM1__I2C1_SDA
593 >;
594 fsl,drive-strength = <MXS_DRIVE_8mA>;
595 fsl,voltage = <MXS_VOLTAGE_HIGH>;
596 fsl,pull-up = <MXS_PULL_ENABLE>;
597 };
598
599 i2c1_pins_b: i2c1@1 {
600 reg = <1>;
601 fsl,pinmux-ids = <
602 MX28_PAD_AUART2_CTS__I2C1_SCL
603 MX28_PAD_AUART2_RTS__I2C1_SDA
604 >;
605 fsl,drive-strength = <MXS_DRIVE_8mA>;
606 fsl,voltage = <MXS_VOLTAGE_HIGH>;
607 fsl,pull-up = <MXS_PULL_ENABLE>;
608 };
609
610 saif0_pins_a: saif0@0 {
611 reg = <0>;
612 fsl,pinmux-ids = <
613 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
614 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
615 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
616 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
617 >;
618 fsl,drive-strength = <MXS_DRIVE_12mA>;
619 fsl,voltage = <MXS_VOLTAGE_HIGH>;
620 fsl,pull-up = <MXS_PULL_ENABLE>;
621 };
622
623 saif0_pins_b: saif0@1 {
624 reg = <1>;
625 fsl,pinmux-ids = <
626 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
627 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
628 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
629 >;
630 fsl,drive-strength = <MXS_DRIVE_12mA>;
631 fsl,voltage = <MXS_VOLTAGE_HIGH>;
632 fsl,pull-up = <MXS_PULL_ENABLE>;
633 };
634
635 saif1_pins_a: saif1@0 {
636 reg = <0>;
637 fsl,pinmux-ids = <
638 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
639 >;
640 fsl,drive-strength = <MXS_DRIVE_12mA>;
641 fsl,voltage = <MXS_VOLTAGE_HIGH>;
642 fsl,pull-up = <MXS_PULL_ENABLE>;
643 };
644
645 pwm0_pins_a: pwm0@0 {
646 reg = <0>;
647 fsl,pinmux-ids = <
648 MX28_PAD_PWM0__PWM_0
649 >;
650 fsl,drive-strength = <MXS_DRIVE_4mA>;
651 fsl,voltage = <MXS_VOLTAGE_HIGH>;
652 fsl,pull-up = <MXS_PULL_DISABLE>;
653 };
654
655 pwm2_pins_a: pwm2@0 {
656 reg = <0>;
657 fsl,pinmux-ids = <
658 MX28_PAD_PWM2__PWM_2
659 >;
660 fsl,drive-strength = <MXS_DRIVE_4mA>;
661 fsl,voltage = <MXS_VOLTAGE_HIGH>;
662 fsl,pull-up = <MXS_PULL_DISABLE>;
663 };
664
665 pwm3_pins_a: pwm3@0 {
666 reg = <0>;
667 fsl,pinmux-ids = <
668 MX28_PAD_PWM3__PWM_3
669 >;
670 fsl,drive-strength = <MXS_DRIVE_4mA>;
671 fsl,voltage = <MXS_VOLTAGE_HIGH>;
672 fsl,pull-up = <MXS_PULL_DISABLE>;
673 };
674
675 pwm3_pins_b: pwm3@1 {
676 reg = <1>;
677 fsl,pinmux-ids = <
678 MX28_PAD_SAIF0_MCLK__PWM_3
679 >;
680 fsl,drive-strength = <MXS_DRIVE_4mA>;
681 fsl,voltage = <MXS_VOLTAGE_HIGH>;
682 fsl,pull-up = <MXS_PULL_DISABLE>;
683 };
684
685 pwm4_pins_a: pwm4@0 {
686 reg = <0>;
687 fsl,pinmux-ids = <
688 MX28_PAD_PWM4__PWM_4
689 >;
690 fsl,drive-strength = <MXS_DRIVE_4mA>;
691 fsl,voltage = <MXS_VOLTAGE_HIGH>;
692 fsl,pull-up = <MXS_PULL_DISABLE>;
693 };
694
695 lcdif_24bit_pins_a: lcdif-24bit@0 {
696 reg = <0>;
697 fsl,pinmux-ids = <
698 MX28_PAD_LCD_D00__LCD_D0
699 MX28_PAD_LCD_D01__LCD_D1
700 MX28_PAD_LCD_D02__LCD_D2
701 MX28_PAD_LCD_D03__LCD_D3
702 MX28_PAD_LCD_D04__LCD_D4
703 MX28_PAD_LCD_D05__LCD_D5
704 MX28_PAD_LCD_D06__LCD_D6
705 MX28_PAD_LCD_D07__LCD_D7
706 MX28_PAD_LCD_D08__LCD_D8
707 MX28_PAD_LCD_D09__LCD_D9
708 MX28_PAD_LCD_D10__LCD_D10
709 MX28_PAD_LCD_D11__LCD_D11
710 MX28_PAD_LCD_D12__LCD_D12
711 MX28_PAD_LCD_D13__LCD_D13
712 MX28_PAD_LCD_D14__LCD_D14
713 MX28_PAD_LCD_D15__LCD_D15
714 MX28_PAD_LCD_D16__LCD_D16
715 MX28_PAD_LCD_D17__LCD_D17
716 MX28_PAD_LCD_D18__LCD_D18
717 MX28_PAD_LCD_D19__LCD_D19
718 MX28_PAD_LCD_D20__LCD_D20
719 MX28_PAD_LCD_D21__LCD_D21
720 MX28_PAD_LCD_D22__LCD_D22
721 MX28_PAD_LCD_D23__LCD_D23
722 >;
723 fsl,drive-strength = <MXS_DRIVE_4mA>;
724 fsl,voltage = <MXS_VOLTAGE_HIGH>;
725 fsl,pull-up = <MXS_PULL_DISABLE>;
726 };
727
728 lcdif_18bit_pins_a: lcdif-18bit@0 {
729 reg = <0>;
730 fsl,pinmux-ids = <
731 MX28_PAD_LCD_D00__LCD_D0
732 MX28_PAD_LCD_D01__LCD_D1
733 MX28_PAD_LCD_D02__LCD_D2
734 MX28_PAD_LCD_D03__LCD_D3
735 MX28_PAD_LCD_D04__LCD_D4
736 MX28_PAD_LCD_D05__LCD_D5
737 MX28_PAD_LCD_D06__LCD_D6
738 MX28_PAD_LCD_D07__LCD_D7
739 MX28_PAD_LCD_D08__LCD_D8
740 MX28_PAD_LCD_D09__LCD_D9
741 MX28_PAD_LCD_D10__LCD_D10
742 MX28_PAD_LCD_D11__LCD_D11
743 MX28_PAD_LCD_D12__LCD_D12
744 MX28_PAD_LCD_D13__LCD_D13
745 MX28_PAD_LCD_D14__LCD_D14
746 MX28_PAD_LCD_D15__LCD_D15
747 MX28_PAD_LCD_D16__LCD_D16
748 MX28_PAD_LCD_D17__LCD_D17
749 >;
750 fsl,drive-strength = <MXS_DRIVE_4mA>;
751 fsl,voltage = <MXS_VOLTAGE_HIGH>;
752 fsl,pull-up = <MXS_PULL_DISABLE>;
753 };
754
755 lcdif_16bit_pins_a: lcdif-16bit@0 {
756 reg = <0>;
757 fsl,pinmux-ids = <
758 MX28_PAD_LCD_D00__LCD_D0
759 MX28_PAD_LCD_D01__LCD_D1
760 MX28_PAD_LCD_D02__LCD_D2
761 MX28_PAD_LCD_D03__LCD_D3
762 MX28_PAD_LCD_D04__LCD_D4
763 MX28_PAD_LCD_D05__LCD_D5
764 MX28_PAD_LCD_D06__LCD_D6
765 MX28_PAD_LCD_D07__LCD_D7
766 MX28_PAD_LCD_D08__LCD_D8
767 MX28_PAD_LCD_D09__LCD_D9
768 MX28_PAD_LCD_D10__LCD_D10
769 MX28_PAD_LCD_D11__LCD_D11
770 MX28_PAD_LCD_D12__LCD_D12
771 MX28_PAD_LCD_D13__LCD_D13
772 MX28_PAD_LCD_D14__LCD_D14
773 MX28_PAD_LCD_D15__LCD_D15
774 >;
775 fsl,drive-strength = <MXS_DRIVE_4mA>;
776 fsl,voltage = <MXS_VOLTAGE_HIGH>;
777 fsl,pull-up = <MXS_PULL_DISABLE>;
778 };
779
780 lcdif_sync_pins_a: lcdif-sync@0 {
781 reg = <0>;
782 fsl,pinmux-ids = <
783 MX28_PAD_LCD_RS__LCD_DOTCLK
784 MX28_PAD_LCD_CS__LCD_ENABLE
785 MX28_PAD_LCD_RD_E__LCD_VSYNC
786 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
787 >;
788 fsl,drive-strength = <MXS_DRIVE_4mA>;
789 fsl,voltage = <MXS_VOLTAGE_HIGH>;
790 fsl,pull-up = <MXS_PULL_DISABLE>;
791 };
792
793 can0_pins_a: can0@0 {
794 reg = <0>;
795 fsl,pinmux-ids = <
796 MX28_PAD_GPMI_RDY2__CAN0_TX
797 MX28_PAD_GPMI_RDY3__CAN0_RX
798 >;
799 fsl,drive-strength = <MXS_DRIVE_4mA>;
800 fsl,voltage = <MXS_VOLTAGE_HIGH>;
801 fsl,pull-up = <MXS_PULL_DISABLE>;
802 };
803
804 can1_pins_a: can1@0 {
805 reg = <0>;
806 fsl,pinmux-ids = <
807 MX28_PAD_GPMI_CE2N__CAN1_TX
808 MX28_PAD_GPMI_CE3N__CAN1_RX
809 >;
810 fsl,drive-strength = <MXS_DRIVE_4mA>;
811 fsl,voltage = <MXS_VOLTAGE_HIGH>;
812 fsl,pull-up = <MXS_PULL_DISABLE>;
813 };
814
815 spi2_pins_a: spi2@0 {
816 reg = <0>;
817 fsl,pinmux-ids = <
818 MX28_PAD_SSP2_SCK__SSP2_SCK
819 MX28_PAD_SSP2_MOSI__SSP2_CMD
820 MX28_PAD_SSP2_MISO__SSP2_D0
821 MX28_PAD_SSP2_SS0__SSP2_D3
822 >;
823 fsl,drive-strength = <MXS_DRIVE_8mA>;
824 fsl,voltage = <MXS_VOLTAGE_HIGH>;
825 fsl,pull-up = <MXS_PULL_ENABLE>;
826 };
827
828 spi3_pins_a: spi3@0 {
829 reg = <0>;
830 fsl,pinmux-ids = <
831 MX28_PAD_AUART2_RX__SSP3_D4
832 MX28_PAD_AUART2_TX__SSP3_D5
833 MX28_PAD_SSP3_SCK__SSP3_SCK
834 MX28_PAD_SSP3_MOSI__SSP3_CMD
835 MX28_PAD_SSP3_MISO__SSP3_D0
836 MX28_PAD_SSP3_SS0__SSP3_D3
837 >;
838 fsl,drive-strength = <MXS_DRIVE_8mA>;
839 fsl,voltage = <MXS_VOLTAGE_HIGH>;
840 fsl,pull-up = <MXS_PULL_DISABLE>;
841 };
842
843 spi3_pins_b: spi3@1 {
844 reg = <1>;
845 fsl,pinmux-ids = <
846 MX28_PAD_SSP3_SCK__SSP3_SCK
847 MX28_PAD_SSP3_MOSI__SSP3_CMD
848 MX28_PAD_SSP3_MISO__SSP3_D0
849 MX28_PAD_SSP3_SS0__SSP3_D3
850 >;
851 fsl,drive-strength = <MXS_DRIVE_8mA>;
852 fsl,voltage = <MXS_VOLTAGE_HIGH>;
853 fsl,pull-up = <MXS_PULL_ENABLE>;
854 };
855
856 usb0_pins_a: usb0@0 {
857 reg = <0>;
858 fsl,pinmux-ids = <
859 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
860 >;
861 fsl,drive-strength = <MXS_DRIVE_12mA>;
862 fsl,voltage = <MXS_VOLTAGE_HIGH>;
863 fsl,pull-up = <MXS_PULL_DISABLE>;
864 };
865
866 usb0_pins_b: usb0@1 {
867 reg = <1>;
868 fsl,pinmux-ids = <
869 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
870 >;
871 fsl,drive-strength = <MXS_DRIVE_12mA>;
872 fsl,voltage = <MXS_VOLTAGE_HIGH>;
873 fsl,pull-up = <MXS_PULL_DISABLE>;
874 };
875
876 usb1_pins_a: usb1@0 {
877 reg = <0>;
878 fsl,pinmux-ids = <
879 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
880 >;
881 fsl,drive-strength = <MXS_DRIVE_12mA>;
882 fsl,voltage = <MXS_VOLTAGE_HIGH>;
883 fsl,pull-up = <MXS_PULL_DISABLE>;
884 };
885
886 usb0_id_pins_a: usb0id@0 {
887 reg = <0>;
888 fsl,pinmux-ids = <
889 MX28_PAD_AUART1_RTS__USB0_ID
890 >;
891 fsl,drive-strength = <MXS_DRIVE_12mA>;
892 fsl,voltage = <MXS_VOLTAGE_HIGH>;
893 fsl,pull-up = <MXS_PULL_ENABLE>;
894 };
895
896 usb0_id_pins_b: usb0id1@0 {
897 reg = <0>;
898 fsl,pinmux-ids = <
899 MX28_PAD_PWM2__USB0_ID
900 >;
901 fsl,drive-strength = <MXS_DRIVE_12mA>;
902 fsl,voltage = <MXS_VOLTAGE_HIGH>;
903 fsl,pull-up = <MXS_PULL_ENABLE>;
904 };
905
906 };
907
908 digctl: digctl@8001c000 {
909 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
910 reg = <0x8001c000 0x2000>;
911 interrupts = <89>;
912 status = "disabled";
913 };
914
915 etm: etm@80022000 {
916 reg = <0x80022000 0x2000>;
917 status = "disabled";
918 };
919
920 dma_apbx: dma-apbx@80024000 {
921 compatible = "fsl,imx28-dma-apbx";
922 reg = <0x80024000 0x2000>;
923 interrupts = <78 79 66 0
924 80 81 68 69
925 70 71 72 73
926 74 75 76 77>;
927 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
928 "saif0", "saif1", "i2c0", "i2c1",
929 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
930 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
931 #dma-cells = <1>;
932 dma-channels = <16>;
933 clocks = <&clks 26>;
934 };
935
936 dcp: dcp@80028000 {
937 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
938 reg = <0x80028000 0x2000>;
939 interrupts = <52 53 54>;
940 status = "okay";
941 };
942
943 pxp: pxp@8002a000 {
944 reg = <0x8002a000 0x2000>;
945 interrupts = <39>;
946 status = "disabled";
947 };
948
949 ocotp: ocotp@8002c000 {
950 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
951 #address-cells = <1>;
952 #size-cells = <1>;
953 reg = <0x8002c000 0x2000>;
954 clocks = <&clks 25>;
955 };
956
957 axi-ahb@8002e000 {
958 reg = <0x8002e000 0x2000>;
959 status = "disabled";
960 };
961
962 lcdif: lcdif@80030000 {
963 compatible = "fsl,imx28-lcdif";
964 reg = <0x80030000 0x2000>;
965 interrupts = <38>;
966 clocks = <&clks 55>;
967 dmas = <&dma_apbh 13>;
968 dma-names = "rx";
969 status = "disabled";
970 };
971
972 can0: can@80032000 {
973 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
974 reg = <0x80032000 0x2000>;
975 interrupts = <8>;
976 clocks = <&clks 58>, <&clks 58>;
977 clock-names = "ipg", "per";
978 status = "disabled";
979 };
980
981 can1: can@80034000 {
982 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
983 reg = <0x80034000 0x2000>;
984 interrupts = <9>;
985 clocks = <&clks 59>, <&clks 59>;
986 clock-names = "ipg", "per";
987 status = "disabled";
988 };
989
990 simdbg: simdbg@8003c000 {
991 reg = <0x8003c000 0x200>;
992 status = "disabled";
993 };
994
995 simgpmisel: simgpmisel@8003c200 {
996 reg = <0x8003c200 0x100>;
997 status = "disabled";
998 };
999
1000 simsspsel: simsspsel@8003c300 {
1001 reg = <0x8003c300 0x100>;
1002 status = "disabled";
1003 };
1004
1005 simmemsel: simmemsel@8003c400 {
1006 reg = <0x8003c400 0x100>;
1007 status = "disabled";
1008 };
1009
1010 gpiomon: gpiomon@8003c500 {
1011 reg = <0x8003c500 0x100>;
1012 status = "disabled";
1013 };
1014
1015 simenet: simenet@8003c700 {
1016 reg = <0x8003c700 0x100>;
1017 status = "disabled";
1018 };
1019
1020 armjtag: armjtag@8003c800 {
1021 reg = <0x8003c800 0x100>;
1022 status = "disabled";
1023 };
1024 };
1025
1026 apbx@80040000 {
1027 compatible = "simple-bus";
1028 #address-cells = <1>;
1029 #size-cells = <1>;
1030 reg = <0x80040000 0x40000>;
1031 ranges;
1032
1033 clks: clkctrl@80040000 {
1034 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1035 reg = <0x80040000 0x2000>;
1036 #clock-cells = <1>;
1037 };
1038
1039 saif0: saif@80042000 {
1040 compatible = "fsl,imx28-saif";
1041 reg = <0x80042000 0x2000>;
1042 interrupts = <59>;
1043 #clock-cells = <0>;
1044 clocks = <&clks 53>;
1045 dmas = <&dma_apbx 4>;
1046 dma-names = "rx-tx";
1047 status = "disabled";
1048 };
1049
1050 power: power@80044000 {
1051 reg = <0x80044000 0x2000>;
1052 status = "disabled";
1053 };
1054
1055 saif1: saif@80046000 {
1056 compatible = "fsl,imx28-saif";
1057 reg = <0x80046000 0x2000>;
1058 interrupts = <58>;
1059 clocks = <&clks 54>;
1060 dmas = <&dma_apbx 5>;
1061 dma-names = "rx-tx";
1062 status = "disabled";
1063 };
1064
1065 lradc: lradc@80050000 {
1066 compatible = "fsl,imx28-lradc";
1067 reg = <0x80050000 0x2000>;
1068 interrupts = <10 14 15 16 17 18 19
1069 20 21 22 23 24 25>;
1070 status = "disabled";
1071 clocks = <&clks 41>;
1072 #io-channel-cells = <1>;
1073 };
1074
1075 spdif: spdif@80054000 {
1076 reg = <0x80054000 0x2000>;
1077 interrupts = <45>;
1078 dmas = <&dma_apbx 2>;
1079 dma-names = "tx";
1080 status = "disabled";
1081 };
1082
1083 mxs_rtc: rtc@80056000 {
1084 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1085 reg = <0x80056000 0x2000>;
1086 interrupts = <29>;
1087 };
1088
1089 i2c0: i2c@80058000 {
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 compatible = "fsl,imx28-i2c";
1093 reg = <0x80058000 0x2000>;
1094 interrupts = <111>;
1095 clock-frequency = <100000>;
1096 dmas = <&dma_apbx 6>;
1097 dma-names = "rx-tx";
1098 status = "disabled";
1099 };
1100
1101 i2c1: i2c@8005a000 {
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 compatible = "fsl,imx28-i2c";
1105 reg = <0x8005a000 0x2000>;
1106 interrupts = <110>;
1107 clock-frequency = <100000>;
1108 dmas = <&dma_apbx 7>;
1109 dma-names = "rx-tx";
1110 status = "disabled";
1111 };
1112
1113 pwm: pwm@80064000 {
1114 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1115 reg = <0x80064000 0x2000>;
1116 clocks = <&clks 44>;
1117 #pwm-cells = <2>;
1118 fsl,pwm-number = <8>;
1119 status = "disabled";
1120 };
1121
1122 timer: timrot@80068000 {
1123 compatible = "fsl,imx28-timrot", "fsl,timrot";
1124 reg = <0x80068000 0x2000>;
1125 interrupts = <48 49 50 51>;
1126 clocks = <&clks 26>;
1127 };
1128
1129 auart0: serial@8006a000 {
1130 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1131 reg = <0x8006a000 0x2000>;
1132 interrupts = <112>;
1133 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1134 dma-names = "rx", "tx";
1135 clocks = <&clks 45>;
1136 status = "disabled";
1137 };
1138
1139 auart1: serial@8006c000 {
1140 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1141 reg = <0x8006c000 0x2000>;
1142 interrupts = <113>;
1143 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1144 dma-names = "rx", "tx";
1145 clocks = <&clks 45>;
1146 status = "disabled";
1147 };
1148
1149 auart2: serial@8006e000 {
1150 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1151 reg = <0x8006e000 0x2000>;
1152 interrupts = <114>;
1153 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1154 dma-names = "rx", "tx";
1155 clocks = <&clks 45>;
1156 status = "disabled";
1157 };
1158
1159 auart3: serial@80070000 {
1160 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1161 reg = <0x80070000 0x2000>;
1162 interrupts = <115>;
1163 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1164 dma-names = "rx", "tx";
1165 clocks = <&clks 45>;
1166 status = "disabled";
1167 };
1168
1169 auart4: serial@80072000 {
1170 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1171 reg = <0x80072000 0x2000>;
1172 interrupts = <116>;
1173 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1174 dma-names = "rx", "tx";
1175 clocks = <&clks 45>;
1176 status = "disabled";
1177 };
1178
1179 duart: serial@80074000 {
1180 compatible = "arm,pl011", "arm,primecell";
1181 reg = <0x80074000 0x1000>;
1182 interrupts = <47>;
1183 clocks = <&clks 45>, <&clks 26>;
1184 clock-names = "uart", "apb_pclk";
1185 status = "disabled";
1186 };
1187
1188 usbphy0: usbphy@8007c000 {
1189 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1190 reg = <0x8007c000 0x2000>;
1191 clocks = <&clks 62>;
1192 status = "disabled";
1193 };
1194
1195 usbphy1: usbphy@8007e000 {
1196 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1197 reg = <0x8007e000 0x2000>;
1198 clocks = <&clks 63>;
1199 status = "disabled";
1200 };
1201 };
1202 };
1203
1204 ahb@80080000 {
1205 compatible = "simple-bus";
1206 #address-cells = <1>;
1207 #size-cells = <1>;
1208 reg = <0x80080000 0x80000>;
1209 ranges;
1210
1211 usb0: usb@80080000 {
1212 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1213 reg = <0x80080000 0x10000>;
1214 interrupts = <93>;
1215 clocks = <&clks 60>;
1216 fsl,usbphy = <&usbphy0>;
1217 status = "disabled";
1218 };
1219
1220 usb1: usb@80090000 {
1221 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1222 reg = <0x80090000 0x10000>;
1223 interrupts = <92>;
1224 clocks = <&clks 61>;
1225 fsl,usbphy = <&usbphy1>;
1226 dr_mode = "host";
1227 status = "disabled";
1228 };
1229
1230 dflpt: dflpt@800c0000 {
1231 reg = <0x800c0000 0x10000>;
1232 status = "disabled";
1233 };
1234
1235 mac0: ethernet@800f0000 {
1236 compatible = "fsl,imx28-fec";
1237 reg = <0x800f0000 0x4000>;
1238 interrupts = <101>;
1239 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1240 clock-names = "ipg", "ahb", "enet_out";
1241 status = "disabled";
1242 };
1243
1244 mac1: ethernet@800f4000 {
1245 compatible = "fsl,imx28-fec";
1246 reg = <0x800f4000 0x4000>;
1247 interrupts = <102>;
1248 clocks = <&clks 57>, <&clks 57>;
1249 clock-names = "ipg", "ahb";
1250 status = "disabled";
1251 };
1252
1253 etn_switch: switch@800f8000 {
1254 reg = <0x800f8000 0x8000>;
1255 status = "disabled";
1256 };
1257 };
1258
1259 iio-hwmon {
1260 compatible = "iio-hwmon";
1261 io-channels = <&lradc 8>;
1262 };
1263};