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1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34#include <dt-bindings/interrupt-controller/irq.h>
35#include <dt-bindings/clock/bcm-nsp.h>
36
37#include "skeleton.dtsi"
38
39/ {
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
52 reg = <0x0>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff042c>;
61 reg = <0x1>;
62 };
63 };
64
65 pmu {
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
70 };
71
72 mpcore {
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77
78 a9pll: arm_clk@00000 {
79 #clock-cells = <0>;
80 compatible = "brcm,nsp-armpll";
81 clocks = <&osc>;
82 reg = <0x00000 0x1000>;
83 };
84
85 timer@20200 {
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&periph_clk>;
90 };
91
92 twd-timer@20600 {
93 compatible = "arm,cortex-a9-twd-timer";
94 reg = <0x20600 0x20>;
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_HIGH)>;
97 clocks = <&periph_clk>;
98 };
99
100 twd-watchdog@20620 {
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
106 };
107
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
114 <0x20100 0x100>;
115 };
116
117 L2: l2-cache {
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
120 cache-unified;
121 cache-level = <2>;
122 };
123 };
124
125 clocks {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129
130 osc: oscillator {
131 #clock-cells = <0>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
134 };
135
136 iprocmed: iprocmed {
137 #clock-cells = <0>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
140 clock-div = <2>;
141 clock-mult = <1>;
142 };
143
144 iprocslow: iprocslow {
145 #clock-cells = <0>;
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
148 clock-div = <4>;
149 clock-mult = <1>;
150 };
151
152 periph_clk: periph_clk {
153 #clock-cells = <0>;
154 compatible = "fixed-factor-clock";
155 clocks = <&a9pll>;
156 clock-div = <2>;
157 clock-mult = <1>;
158 };
159 };
160
161 axi {
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011ba08>;
164 #address-cells = <1>;
165 #size-cells = <1>;
166
167 gpioa: gpio@0020 {
168 compatible = "brcm,nsp-gpio-a";
169 reg = <0x0020 0x70>,
170 <0x3f1c4 0x1c>;
171 #gpio-cells = <2>;
172 gpio-controller;
173 ngpios = <32>;
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
177 };
178
179 uart0: serial@0300 {
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&osc>;
184 status = "disabled";
185 };
186
187 uart1: serial@0400 {
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&osc>;
192 status = "disabled";
193 };
194
195 nand: nand@26000 {
196 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
197 reg = <0x026000 0x600>,
198 <0x11b408 0x600>,
199 <0x026f00 0x20>;
200 reg-names = "nand", "iproc-idm", "iproc-ext";
201 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
202
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 brcm,nand-has-wp;
207 };
208
209 ccbtimer0: timer@34000 {
210 compatible = "arm,sp804";
211 reg = <0x34000 0x1000>;
212 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&iprocslow>;
215 clock-names = "apb_pclk";
216 };
217
218 ccbtimer1: timer@35000 {
219 compatible = "arm,sp804";
220 reg = <0x35000 0x1000>;
221 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&iprocslow>;
224 clock-names = "apb_pclk";
225 };
226
227 i2c0: i2c@38000 {
228 compatible = "brcm,iproc-i2c";
229 reg = <0x38000 0x50>;
230 #address-cells = <1>;
231 #size-cells = <0>;
232 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
233 clock-frequency = <100000>;
234 };
235
236 watchdog@39000 {
237 compatible = "arm,sp805", "arm,primecell";
238 reg = <0x39000 0x1000>;
239 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&iprocslow>, <&iprocslow>;
241 clock-names = "wdogclk", "apb_pclk";
242 };
243
244 lcpll0: lcpll0@3f100 {
245 #clock-cells = <1>;
246 compatible = "brcm,nsp-lcpll0";
247 reg = <0x3f100 0x14>;
248 clocks = <&osc>;
249 clock-output-names = "lcpll0", "pcie_phy", "sdio",
250 "ddr_phy";
251 };
252
253 genpll: genpll@3f140 {
254 #clock-cells = <1>;
255 compatible = "brcm,nsp-genpll";
256 reg = <0x3f140 0x24>;
257 clocks = <&osc>;
258 clock-output-names = "genpll", "phy", "ethernetclk",
259 "usbclk", "iprocfast", "sata1",
260 "sata2";
261 };
262
263 pinctrl: pinctrl@3f1c0 {
264 compatible = "brcm,nsp-pinmux";
265 reg = <0x3f1c0 0x04>,
266 <0x30028 0x04>,
267 <0x3f408 0x04>;
268 };
269 };
270
271 pcie0: pcie@18012000 {
272 compatible = "brcm,iproc-pcie";
273 reg = <0x18012000 0x1000>;
274
275 #interrupt-cells = <1>;
276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
278
279 linux,pci-domain = <0>;
280
281 bus-range = <0x00 0xff>;
282
283 #address-cells = <3>;
284 #size-cells = <2>;
285 device_type = "pci";
286
287 /* Note: The HW does not support I/O resources. So,
288 * only the memory resource range is being specified.
289 */
290 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
291
292 status = "disabled";
293 };
294
295 pcie1: pcie@18013000 {
296 compatible = "brcm,iproc-pcie";
297 reg = <0x18013000 0x1000>;
298
299 #interrupt-cells = <1>;
300 interrupt-map-mask = <0 0 0 0>;
301 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
302
303 linux,pci-domain = <1>;
304
305 bus-range = <0x00 0xff>;
306
307 #address-cells = <3>;
308 #size-cells = <2>;
309 device_type = "pci";
310
311 /* Note: The HW does not support I/O resources. So,
312 * only the memory resource range is being specified.
313 */
314 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
315
316 status = "disabled";
317 };
318
319 pcie2: pcie@18014000 {
320 compatible = "brcm,iproc-pcie";
321 reg = <0x18014000 0x1000>;
322
323 #interrupt-cells = <1>;
324 interrupt-map-mask = <0 0 0 0>;
325 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
326
327 linux,pci-domain = <2>;
328
329 bus-range = <0x00 0xff>;
330
331 #address-cells = <3>;
332 #size-cells = <2>;
333 device_type = "pci";
334
335 /* Note: The HW does not support I/O resources. So,
336 * only the memory resource range is being specified.
337 */
338 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
339
340 status = "disabled";
341 };
342};