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1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/dma/at91.h>
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
18
19/ {
20 model = "Atmel AT91SAM9G45 family SoC";
21 compatible = "atmel,at91sam9g45";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 tcb1 = &tcb1;
37 i2c0 = &i2c0;
38 i2c1 = &i2c1;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <0>;
45 #size-cells = <0>;
46
47 cpu {
48 compatible = "arm,arm926ej-s";
49 device_type = "cpu";
50 };
51 };
52
53 memory {
54 reg = <0x70000000 0x10000000>;
55 };
56
57 clocks {
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 main_xtal: main_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 adc_op_clk: adc_op_clk{
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <300000>;
74 };
75 };
76
77 sram: sram@00300000 {
78 compatible = "mmio-sram";
79 reg = <0x00300000 0x10000>;
80 };
81
82 ahb {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
87
88 apb {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 aic: interrupt-controller@fffff000 {
95 #interrupt-cells = <3>;
96 compatible = "atmel,at91rm9200-aic";
97 interrupt-controller;
98 reg = <0xfffff000 0x200>;
99 atmel,external-irqs = <31>;
100 };
101
102 ramc0: ramc@ffffe400 {
103 compatible = "atmel,at91sam9g45-ddramc";
104 reg = <0xffffe400 0x200>;
105 clocks = <&ddrck>;
106 clock-names = "ddrck";
107 };
108
109 ramc1: ramc@ffffe600 {
110 compatible = "atmel,at91sam9g45-ddramc";
111 reg = <0xffffe600 0x200>;
112 clocks = <&ddrck>;
113 clock-names = "ddrck";
114 };
115
116 pmc: pmc@fffffc00 {
117 compatible = "atmel,at91sam9g45-pmc", "syscon";
118 reg = <0xfffffc00 0x100>;
119 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
120 interrupt-controller;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 #interrupt-cells = <1>;
124
125 main_osc: main_osc {
126 compatible = "atmel,at91rm9200-clk-main-osc";
127 #clock-cells = <0>;
128 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
129 clocks = <&main_xtal>;
130 };
131
132 main: mainck {
133 compatible = "atmel,at91rm9200-clk-main";
134 #clock-cells = <0>;
135 clocks = <&main_osc>;
136 };
137
138 plla: pllack {
139 compatible = "atmel,at91rm9200-clk-pll";
140 #clock-cells = <0>;
141 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
142 clocks = <&main>;
143 reg = <0>;
144 atmel,clk-input-range = <2000000 32000000>;
145 #atmel,pll-clk-output-range-cells = <4>;
146 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
147 695000000 750000000 1 0
148 645000000 700000000 2 0
149 595000000 650000000 3 0
150 545000000 600000000 0 1
151 495000000 555000000 1 1
152 445000000 500000000 2 1
153 400000000 450000000 3 1>;
154 };
155
156 plladiv: plladivck {
157 compatible = "atmel,at91sam9x5-clk-plldiv";
158 #clock-cells = <0>;
159 clocks = <&plla>;
160 };
161
162 utmi: utmick {
163 compatible = "atmel,at91sam9x5-clk-utmi";
164 #clock-cells = <0>;
165 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
166 clocks = <&main>;
167 };
168
169 mck: masterck {
170 compatible = "atmel,at91rm9200-clk-master";
171 #clock-cells = <0>;
172 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
174 atmel,clk-output-range = <0 133333333>;
175 atmel,clk-divisors = <1 2 4 3>;
176 };
177
178 usb: usbck {
179 compatible = "atmel,at91sam9x5-clk-usb";
180 #clock-cells = <0>;
181 clocks = <&plladiv>, <&utmi>;
182 };
183
184 prog: progck {
185 compatible = "atmel,at91sam9g45-clk-programmable";
186 #address-cells = <1>;
187 #size-cells = <0>;
188 interrupt-parent = <&pmc>;
189 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
190
191 prog0: prog0 {
192 #clock-cells = <0>;
193 reg = <0>;
194 interrupts = <AT91_PMC_PCKRDY(0)>;
195 };
196
197 prog1: prog1 {
198 #clock-cells = <0>;
199 reg = <1>;
200 interrupts = <AT91_PMC_PCKRDY(1)>;
201 };
202 };
203
204 systemck {
205 compatible = "atmel,at91rm9200-clk-system";
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 ddrck: ddrck {
210 #clock-cells = <0>;
211 reg = <2>;
212 clocks = <&mck>;
213 };
214
215 uhpck: uhpck {
216 #clock-cells = <0>;
217 reg = <6>;
218 clocks = <&usb>;
219 };
220
221 pck0: pck0 {
222 #clock-cells = <0>;
223 reg = <8>;
224 clocks = <&prog0>;
225 };
226
227 pck1: pck1 {
228 #clock-cells = <0>;
229 reg = <9>;
230 clocks = <&prog1>;
231 };
232 };
233
234 periphck {
235 compatible = "atmel,at91rm9200-clk-peripheral";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 clocks = <&mck>;
239
240 pioA_clk: pioA_clk {
241 #clock-cells = <0>;
242 reg = <2>;
243 };
244
245 pioB_clk: pioB_clk {
246 #clock-cells = <0>;
247 reg = <3>;
248 };
249
250 pioC_clk: pioC_clk {
251 #clock-cells = <0>;
252 reg = <4>;
253 };
254
255 pioDE_clk: pioDE_clk {
256 #clock-cells = <0>;
257 reg = <5>;
258 };
259
260 trng_clk: trng_clk {
261 #clock-cells = <0>;
262 reg = <6>;
263 };
264
265 usart0_clk: usart0_clk {
266 #clock-cells = <0>;
267 reg = <7>;
268 };
269
270 usart1_clk: usart1_clk {
271 #clock-cells = <0>;
272 reg = <8>;
273 };
274
275 usart2_clk: usart2_clk {
276 #clock-cells = <0>;
277 reg = <9>;
278 };
279
280 usart3_clk: usart3_clk {
281 #clock-cells = <0>;
282 reg = <10>;
283 };
284
285 mci0_clk: mci0_clk {
286 #clock-cells = <0>;
287 reg = <11>;
288 };
289
290 twi0_clk: twi0_clk {
291 #clock-cells = <0>;
292 reg = <12>;
293 };
294
295 twi1_clk: twi1_clk {
296 #clock-cells = <0>;
297 reg = <13>;
298 };
299
300 spi0_clk: spi0_clk {
301 #clock-cells = <0>;
302 reg = <14>;
303 };
304
305 spi1_clk: spi1_clk {
306 #clock-cells = <0>;
307 reg = <15>;
308 };
309
310 ssc0_clk: ssc0_clk {
311 #clock-cells = <0>;
312 reg = <16>;
313 };
314
315 ssc1_clk: ssc1_clk {
316 #clock-cells = <0>;
317 reg = <17>;
318 };
319
320 tcb0_clk: tcb0_clk {
321 #clock-cells = <0>;
322 reg = <18>;
323 };
324
325 pwm_clk: pwm_clk {
326 #clock-cells = <0>;
327 reg = <19>;
328 };
329
330 adc_clk: adc_clk {
331 #clock-cells = <0>;
332 reg = <20>;
333 };
334
335 dma0_clk: dma0_clk {
336 #clock-cells = <0>;
337 reg = <21>;
338 };
339
340 uhphs_clk: uhphs_clk {
341 #clock-cells = <0>;
342 reg = <22>;
343 };
344
345 lcd_clk: lcd_clk {
346 #clock-cells = <0>;
347 reg = <23>;
348 };
349
350 ac97_clk: ac97_clk {
351 #clock-cells = <0>;
352 reg = <24>;
353 };
354
355 macb0_clk: macb0_clk {
356 #clock-cells = <0>;
357 reg = <25>;
358 };
359
360 isi_clk: isi_clk {
361 #clock-cells = <0>;
362 reg = <26>;
363 };
364
365 udphs_clk: udphs_clk {
366 #clock-cells = <0>;
367 reg = <27>;
368 };
369
370 aestdessha_clk: aestdessha_clk {
371 #clock-cells = <0>;
372 reg = <28>;
373 };
374
375 mci1_clk: mci1_clk {
376 #clock-cells = <0>;
377 reg = <29>;
378 };
379
380 vdec_clk: vdec_clk {
381 #clock-cells = <0>;
382 reg = <30>;
383 };
384 };
385 };
386
387 rstc@fffffd00 {
388 compatible = "atmel,at91sam9g45-rstc";
389 reg = <0xfffffd00 0x10>;
390 clocks = <&clk32k>;
391 };
392
393 pit: timer@fffffd30 {
394 compatible = "atmel,at91sam9260-pit";
395 reg = <0xfffffd30 0xf>;
396 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
397 clocks = <&mck>;
398 };
399
400
401 shdwc@fffffd10 {
402 compatible = "atmel,at91sam9rl-shdwc";
403 reg = <0xfffffd10 0x10>;
404 clocks = <&clk32k>;
405 };
406
407 tcb0: timer@fff7c000 {
408 compatible = "atmel,at91rm9200-tcb";
409 reg = <0xfff7c000 0x100>;
410 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
411 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
412 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
413 };
414
415 tcb1: timer@fffd4000 {
416 compatible = "atmel,at91rm9200-tcb";
417 reg = <0xfffd4000 0x100>;
418 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
419 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
420 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
421 };
422
423 dma: dma-controller@ffffec00 {
424 compatible = "atmel,at91sam9g45-dma";
425 reg = <0xffffec00 0x200>;
426 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
427 #dma-cells = <2>;
428 clocks = <&dma0_clk>;
429 clock-names = "dma_clk";
430 };
431
432 pinctrl@fffff200 {
433 #address-cells = <1>;
434 #size-cells = <1>;
435 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
436 ranges = <0xfffff200 0xfffff200 0xa00>;
437
438 atmel,mux-mask = <
439 /* A B */
440 0xffffffff 0xffc003ff /* pioA */
441 0xffffffff 0x800f8f00 /* pioB */
442 0xffffffff 0x00000e00 /* pioC */
443 0xffffffff 0xff0c1381 /* pioD */
444 0xffffffff 0x81ffff81 /* pioE */
445 >;
446
447 /* shared pinctrl settings */
448 adc0 {
449 pinctrl_adc0_adtrg: adc0_adtrg {
450 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
451 };
452 pinctrl_adc0_ad0: adc0_ad0 {
453 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
454 };
455 pinctrl_adc0_ad1: adc0_ad1 {
456 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
457 };
458 pinctrl_adc0_ad2: adc0_ad2 {
459 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
460 };
461 pinctrl_adc0_ad3: adc0_ad3 {
462 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
463 };
464 pinctrl_adc0_ad4: adc0_ad4 {
465 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
466 };
467 pinctrl_adc0_ad5: adc0_ad5 {
468 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
469 };
470 pinctrl_adc0_ad6: adc0_ad6 {
471 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
472 };
473 pinctrl_adc0_ad7: adc0_ad7 {
474 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
475 };
476 };
477
478 dbgu {
479 pinctrl_dbgu: dbgu-0 {
480 atmel,pins =
481 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
482 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
483 };
484 };
485
486 i2c0 {
487 pinctrl_i2c0: i2c0-0 {
488 atmel,pins =
489 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
490 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
491 };
492 };
493
494 i2c1 {
495 pinctrl_i2c1: i2c1-0 {
496 atmel,pins =
497 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
498 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
499 };
500 };
501
502 isi {
503 pinctrl_isi_data_0_7: isi-0-data-0-7 {
504 atmel,pins =
505 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
506 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
507 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
508 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
509 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
510 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
511 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
512 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
513 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
514 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
515 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
516 };
517
518 pinctrl_isi_data_8_9: isi-0-data-8-9 {
519 atmel,pins =
520 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
521 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
522 };
523
524 pinctrl_isi_data_10_11: isi-0-data-10-11 {
525 atmel,pins =
526 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
527 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
528 };
529 };
530
531 usart0 {
532 pinctrl_usart0: usart0-0 {
533 atmel,pins =
534 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
535 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
536 };
537
538 pinctrl_usart0_rts: usart0_rts-0 {
539 atmel,pins =
540 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
541 };
542
543 pinctrl_usart0_cts: usart0_cts-0 {
544 atmel,pins =
545 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
546 };
547 };
548
549 uart1 {
550 pinctrl_usart1: usart1-0 {
551 atmel,pins =
552 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
553 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
554 };
555
556 pinctrl_usart1_rts: usart1_rts-0 {
557 atmel,pins =
558 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
559 };
560
561 pinctrl_usart1_cts: usart1_cts-0 {
562 atmel,pins =
563 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
564 };
565 };
566
567 usart2 {
568 pinctrl_usart2: usart2-0 {
569 atmel,pins =
570 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
571 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
572 };
573
574 pinctrl_usart2_rts: usart2_rts-0 {
575 atmel,pins =
576 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
577 };
578
579 pinctrl_usart2_cts: usart2_cts-0 {
580 atmel,pins =
581 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
582 };
583 };
584
585 usart3 {
586 pinctrl_usart3: usart3-0 {
587 atmel,pins =
588 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
589 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
590 };
591
592 pinctrl_usart3_rts: usart3_rts-0 {
593 atmel,pins =
594 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
595 };
596
597 pinctrl_usart3_cts: usart3_cts-0 {
598 atmel,pins =
599 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
600 };
601 };
602
603 nand {
604 pinctrl_nand: nand-0 {
605 atmel,pins =
606 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
607 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
608 };
609 };
610
611 macb {
612 pinctrl_macb_rmii: macb_rmii-0 {
613 atmel,pins =
614 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
615 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
616 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
617 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
618 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
619 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
620 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
621 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
622 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
623 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
624 };
625
626 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
627 atmel,pins =
628 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
629 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
630 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
631 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
632 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
633 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
634 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
635 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
636 };
637 };
638
639 mmc0 {
640 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
641 atmel,pins =
642 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
643 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
644 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
645 };
646
647 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
648 atmel,pins =
649 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
650 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
651 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
652 };
653
654 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
655 atmel,pins =
656 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
657 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
658 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
659 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
660 };
661 };
662
663 mmc1 {
664 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
665 atmel,pins =
666 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
667 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
668 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
669 };
670
671 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
672 atmel,pins =
673 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
674 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
675 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
676 };
677
678 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
679 atmel,pins =
680 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
681 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
682 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
683 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
684 };
685 };
686
687 ssc0 {
688 pinctrl_ssc0_tx: ssc0_tx-0 {
689 atmel,pins =
690 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
691 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
692 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
693 };
694
695 pinctrl_ssc0_rx: ssc0_rx-0 {
696 atmel,pins =
697 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
698 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
699 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
700 };
701 };
702
703 ssc1 {
704 pinctrl_ssc1_tx: ssc1_tx-0 {
705 atmel,pins =
706 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
707 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
708 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
709 };
710
711 pinctrl_ssc1_rx: ssc1_rx-0 {
712 atmel,pins =
713 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
714 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
715 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
716 };
717 };
718
719 spi0 {
720 pinctrl_spi0: spi0-0 {
721 atmel,pins =
722 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
723 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
724 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
725 };
726 };
727
728 spi1 {
729 pinctrl_spi1: spi1-0 {
730 atmel,pins =
731 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
732 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
733 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
734 };
735 };
736
737 tcb0 {
738 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
739 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
740 };
741
742 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
743 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
744 };
745
746 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
747 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
748 };
749
750 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
751 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
752 };
753
754 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
755 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
756 };
757
758 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
759 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
760 };
761
762 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
763 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
764 };
765
766 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
767 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
768 };
769
770 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
771 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
772 };
773 };
774
775 tcb1 {
776 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
777 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
778 };
779
780 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
781 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
782 };
783
784 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
785 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
786 };
787
788 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
789 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
790 };
791
792 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
793 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
794 };
795
796 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
797 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
798 };
799
800 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
801 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
802 };
803
804 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
805 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
806 };
807
808 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
809 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
810 };
811 };
812
813 fb {
814 pinctrl_fb: fb-0 {
815 atmel,pins =
816 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
817 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
818 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
819 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
820 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
821 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
822 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
823 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
824 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
825 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
826 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
827 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
828 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
829 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
830 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
831 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
832 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
833 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
834 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
835 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
836 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
837 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
838 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
839 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
840 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
841 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
842 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
843 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
844 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
845 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
846 };
847 };
848
849 pioA: gpio@fffff200 {
850 compatible = "atmel,at91rm9200-gpio";
851 reg = <0xfffff200 0x200>;
852 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
853 #gpio-cells = <2>;
854 gpio-controller;
855 interrupt-controller;
856 #interrupt-cells = <2>;
857 clocks = <&pioA_clk>;
858 };
859
860 pioB: gpio@fffff400 {
861 compatible = "atmel,at91rm9200-gpio";
862 reg = <0xfffff400 0x200>;
863 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
864 #gpio-cells = <2>;
865 gpio-controller;
866 interrupt-controller;
867 #interrupt-cells = <2>;
868 clocks = <&pioB_clk>;
869 };
870
871 pioC: gpio@fffff600 {
872 compatible = "atmel,at91rm9200-gpio";
873 reg = <0xfffff600 0x200>;
874 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
875 #gpio-cells = <2>;
876 gpio-controller;
877 interrupt-controller;
878 #interrupt-cells = <2>;
879 clocks = <&pioC_clk>;
880 };
881
882 pioD: gpio@fffff800 {
883 compatible = "atmel,at91rm9200-gpio";
884 reg = <0xfffff800 0x200>;
885 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
886 #gpio-cells = <2>;
887 gpio-controller;
888 interrupt-controller;
889 #interrupt-cells = <2>;
890 clocks = <&pioDE_clk>;
891 };
892
893 pioE: gpio@fffffa00 {
894 compatible = "atmel,at91rm9200-gpio";
895 reg = <0xfffffa00 0x200>;
896 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
897 #gpio-cells = <2>;
898 gpio-controller;
899 interrupt-controller;
900 #interrupt-cells = <2>;
901 clocks = <&pioDE_clk>;
902 };
903 };
904
905 dbgu: serial@ffffee00 {
906 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
907 reg = <0xffffee00 0x200>;
908 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
909 pinctrl-names = "default";
910 pinctrl-0 = <&pinctrl_dbgu>;
911 clocks = <&mck>;
912 clock-names = "usart";
913 status = "disabled";
914 };
915
916 usart0: serial@fff8c000 {
917 compatible = "atmel,at91sam9260-usart";
918 reg = <0xfff8c000 0x200>;
919 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
920 atmel,use-dma-rx;
921 atmel,use-dma-tx;
922 pinctrl-names = "default";
923 pinctrl-0 = <&pinctrl_usart0>;
924 clocks = <&usart0_clk>;
925 clock-names = "usart";
926 status = "disabled";
927 };
928
929 usart1: serial@fff90000 {
930 compatible = "atmel,at91sam9260-usart";
931 reg = <0xfff90000 0x200>;
932 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
933 atmel,use-dma-rx;
934 atmel,use-dma-tx;
935 pinctrl-names = "default";
936 pinctrl-0 = <&pinctrl_usart1>;
937 clocks = <&usart1_clk>;
938 clock-names = "usart";
939 status = "disabled";
940 };
941
942 usart2: serial@fff94000 {
943 compatible = "atmel,at91sam9260-usart";
944 reg = <0xfff94000 0x200>;
945 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
946 atmel,use-dma-rx;
947 atmel,use-dma-tx;
948 pinctrl-names = "default";
949 pinctrl-0 = <&pinctrl_usart2>;
950 clocks = <&usart2_clk>;
951 clock-names = "usart";
952 status = "disabled";
953 };
954
955 usart3: serial@fff98000 {
956 compatible = "atmel,at91sam9260-usart";
957 reg = <0xfff98000 0x200>;
958 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
959 atmel,use-dma-rx;
960 atmel,use-dma-tx;
961 pinctrl-names = "default";
962 pinctrl-0 = <&pinctrl_usart3>;
963 clocks = <&usart3_clk>;
964 clock-names = "usart";
965 status = "disabled";
966 };
967
968 macb0: ethernet@fffbc000 {
969 compatible = "cdns,at91sam9260-macb", "cdns,macb";
970 reg = <0xfffbc000 0x100>;
971 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
972 pinctrl-names = "default";
973 pinctrl-0 = <&pinctrl_macb_rmii>;
974 clocks = <&macb0_clk>, <&macb0_clk>;
975 clock-names = "hclk", "pclk";
976 status = "disabled";
977 };
978
979 trng@fffcc000 {
980 compatible = "atmel,at91sam9g45-trng";
981 reg = <0xfffcc000 0x4000>;
982 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
983 clocks = <&trng_clk>;
984 };
985
986 i2c0: i2c@fff84000 {
987 compatible = "atmel,at91sam9g10-i2c";
988 reg = <0xfff84000 0x100>;
989 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
990 pinctrl-names = "default";
991 pinctrl-0 = <&pinctrl_i2c0>;
992 #address-cells = <1>;
993 #size-cells = <0>;
994 clocks = <&twi0_clk>;
995 status = "disabled";
996 };
997
998 i2c1: i2c@fff88000 {
999 compatible = "atmel,at91sam9g10-i2c";
1000 reg = <0xfff88000 0x100>;
1001 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&pinctrl_i2c1>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1006 clocks = <&twi1_clk>;
1007 status = "disabled";
1008 };
1009
1010 ssc0: ssc@fff9c000 {
1011 compatible = "atmel,at91sam9g45-ssc";
1012 reg = <0xfff9c000 0x4000>;
1013 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1014 pinctrl-names = "default";
1015 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1016 clocks = <&ssc0_clk>;
1017 clock-names = "pclk";
1018 status = "disabled";
1019 };
1020
1021 ssc1: ssc@fffa0000 {
1022 compatible = "atmel,at91sam9g45-ssc";
1023 reg = <0xfffa0000 0x4000>;
1024 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1027 clocks = <&ssc1_clk>;
1028 clock-names = "pclk";
1029 status = "disabled";
1030 };
1031
1032 adc0: adc@fffb0000 {
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035 compatible = "atmel,at91sam9g45-adc";
1036 reg = <0xfffb0000 0x100>;
1037 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1038 clocks = <&adc_clk>, <&adc_op_clk>;
1039 clock-names = "adc_clk", "adc_op_clk";
1040 atmel,adc-channels-used = <0xff>;
1041 atmel,adc-vref = <3300>;
1042 atmel,adc-startup-time = <40>;
1043 atmel,adc-res = <8 10>;
1044 atmel,adc-res-names = "lowres", "highres";
1045 atmel,adc-use-res = "highres";
1046
1047 trigger@0 {
1048 reg = <0>;
1049 trigger-name = "external-rising";
1050 trigger-value = <0x1>;
1051 trigger-external;
1052 };
1053 trigger@1 {
1054 reg = <1>;
1055 trigger-name = "external-falling";
1056 trigger-value = <0x2>;
1057 trigger-external;
1058 };
1059
1060 trigger@2 {
1061 reg = <2>;
1062 trigger-name = "external-any";
1063 trigger-value = <0x3>;
1064 trigger-external;
1065 };
1066
1067 trigger@3 {
1068 reg = <3>;
1069 trigger-name = "continuous";
1070 trigger-value = <0x6>;
1071 };
1072 };
1073
1074 isi@fffb4000 {
1075 compatible = "atmel,at91sam9g45-isi";
1076 reg = <0xfffb4000 0x4000>;
1077 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
1078 clocks = <&isi_clk>;
1079 clock-names = "isi_clk";
1080 status = "disabled";
1081 port {
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 };
1085 };
1086
1087 pwm0: pwm@fffb8000 {
1088 compatible = "atmel,at91sam9rl-pwm";
1089 reg = <0xfffb8000 0x300>;
1090 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
1091 #pwm-cells = <3>;
1092 clocks = <&pwm_clk>;
1093 status = "disabled";
1094 };
1095
1096 mmc0: mmc@fff80000 {
1097 compatible = "atmel,hsmci";
1098 reg = <0xfff80000 0x600>;
1099 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1100 pinctrl-names = "default";
1101 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1102 dma-names = "rxtx";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 clocks = <&mci0_clk>;
1106 clock-names = "mci_clk";
1107 status = "disabled";
1108 };
1109
1110 mmc1: mmc@fffd0000 {
1111 compatible = "atmel,hsmci";
1112 reg = <0xfffd0000 0x600>;
1113 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1114 pinctrl-names = "default";
1115 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
1116 dma-names = "rxtx";
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 clocks = <&mci1_clk>;
1120 clock-names = "mci_clk";
1121 status = "disabled";
1122 };
1123
1124 watchdog@fffffd40 {
1125 compatible = "atmel,at91sam9260-wdt";
1126 reg = <0xfffffd40 0x10>;
1127 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1128 clocks = <&clk32k>;
1129 atmel,watchdog-type = "hardware";
1130 atmel,reset-type = "all";
1131 atmel,dbg-halt;
1132 status = "disabled";
1133 };
1134
1135 spi0: spi@fffa4000 {
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 compatible = "atmel,at91rm9200-spi";
1139 reg = <0xfffa4000 0x200>;
1140 interrupts = <14 4 3>;
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&pinctrl_spi0>;
1143 clocks = <&spi0_clk>;
1144 clock-names = "spi_clk";
1145 status = "disabled";
1146 };
1147
1148 spi1: spi@fffa8000 {
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 compatible = "atmel,at91rm9200-spi";
1152 reg = <0xfffa8000 0x200>;
1153 interrupts = <15 4 3>;
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&pinctrl_spi1>;
1156 clocks = <&spi1_clk>;
1157 clock-names = "spi_clk";
1158 status = "disabled";
1159 };
1160
1161 usb2: gadget@fff78000 {
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164 compatible = "atmel,at91sam9g45-udc";
1165 reg = <0x00600000 0x80000
1166 0xfff78000 0x400>;
1167 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1168 clocks = <&udphs_clk>, <&utmi>;
1169 clock-names = "pclk", "hclk";
1170 status = "disabled";
1171
1172 ep0 {
1173 reg = <0>;
1174 atmel,fifo-size = <64>;
1175 atmel,nb-banks = <1>;
1176 };
1177
1178 ep1 {
1179 reg = <1>;
1180 atmel,fifo-size = <1024>;
1181 atmel,nb-banks = <2>;
1182 atmel,can-dma;
1183 atmel,can-isoc;
1184 };
1185
1186 ep2 {
1187 reg = <2>;
1188 atmel,fifo-size = <1024>;
1189 atmel,nb-banks = <2>;
1190 atmel,can-dma;
1191 atmel,can-isoc;
1192 };
1193
1194 ep3 {
1195 reg = <3>;
1196 atmel,fifo-size = <1024>;
1197 atmel,nb-banks = <3>;
1198 atmel,can-dma;
1199 };
1200
1201 ep4 {
1202 reg = <4>;
1203 atmel,fifo-size = <1024>;
1204 atmel,nb-banks = <3>;
1205 atmel,can-dma;
1206 };
1207
1208 ep5 {
1209 reg = <5>;
1210 atmel,fifo-size = <1024>;
1211 atmel,nb-banks = <3>;
1212 atmel,can-dma;
1213 atmel,can-isoc;
1214 };
1215
1216 ep6 {
1217 reg = <6>;
1218 atmel,fifo-size = <1024>;
1219 atmel,nb-banks = <3>;
1220 atmel,can-dma;
1221 atmel,can-isoc;
1222 };
1223 };
1224
1225 sckc@fffffd50 {
1226 compatible = "atmel,at91sam9x5-sckc";
1227 reg = <0xfffffd50 0x4>;
1228
1229 slow_osc: slow_osc {
1230 compatible = "atmel,at91sam9x5-clk-slow-osc";
1231 #clock-cells = <0>;
1232 atmel,startup-time-usec = <1200000>;
1233 clocks = <&slow_xtal>;
1234 };
1235
1236 slow_rc_osc: slow_rc_osc {
1237 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1238 #clock-cells = <0>;
1239 atmel,startup-time-usec = <75>;
1240 clock-frequency = <32768>;
1241 clock-accuracy = <50000000>;
1242 };
1243
1244 clk32k: slck {
1245 compatible = "atmel,at91sam9x5-clk-slow";
1246 #clock-cells = <0>;
1247 clocks = <&slow_rc_osc &slow_osc>;
1248 };
1249 };
1250
1251 rtc@fffffd20 {
1252 compatible = "atmel,at91sam9260-rtt";
1253 reg = <0xfffffd20 0x10>;
1254 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1255 clocks = <&clk32k>;
1256 status = "disabled";
1257 };
1258
1259 rtc@fffffdb0 {
1260 compatible = "atmel,at91rm9200-rtc";
1261 reg = <0xfffffdb0 0x30>;
1262 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1263 clocks = <&clk32k>;
1264 status = "disabled";
1265 };
1266
1267 gpbr: syscon@fffffd60 {
1268 compatible = "atmel,at91sam9260-gpbr", "syscon";
1269 reg = <0xfffffd60 0x10>;
1270 status = "disabled";
1271 };
1272 };
1273
1274 fb0: fb@0x00500000 {
1275 compatible = "atmel,at91sam9g45-lcdc";
1276 reg = <0x00500000 0x1000>;
1277 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&pinctrl_fb>;
1280 clocks = <&lcd_clk>, <&lcd_clk>;
1281 clock-names = "hclk", "lcdc_clk";
1282 status = "disabled";
1283 };
1284
1285 nand0: nand@40000000 {
1286 compatible = "atmel,at91rm9200-nand";
1287 #address-cells = <1>;
1288 #size-cells = <1>;
1289 reg = <0x40000000 0x10000000
1290 0xffffe200 0x200
1291 >;
1292 atmel,nand-addr-offset = <21>;
1293 atmel,nand-cmd-offset = <22>;
1294 atmel,nand-has-dma;
1295 pinctrl-names = "default";
1296 pinctrl-0 = <&pinctrl_nand>;
1297 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
1298 &pioC 14 GPIO_ACTIVE_HIGH
1299 0
1300 >;
1301 status = "disabled";
1302 };
1303
1304 usb0: ohci@00700000 {
1305 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1306 reg = <0x00700000 0x100000>;
1307 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1308 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1309 clock-names = "ohci_clk", "hclk", "uhpck";
1310 status = "disabled";
1311 };
1312
1313 usb1: ehci@00800000 {
1314 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1315 reg = <0x00800000 0x100000>;
1316 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1317 clocks = <&utmi>, <&uhphs_clk>;
1318 clock-names = "usb_clk", "ehci_clk";
1319 status = "disabled";
1320 };
1321 };
1322
1323 i2c@0 {
1324 compatible = "i2c-gpio";
1325 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
1326 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1327 >;
1328 i2c-gpio,sda-open-drain;
1329 i2c-gpio,scl-open-drain;
1330 i2c-gpio,delay-us = <5>; /* ~100 kHz */
1331 #address-cells = <1>;
1332 #size-cells = <0>;
1333 status = "disabled";
1334 };
1335};