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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * ARC CPU startup Code
4 *
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 * Vineetg: Dec 2007
8 * -Check if we are running on Simulator or on real hardware
9 * to skip certain things during boot on simulator
10 */
11
12#include <linux/linkage.h>
13#include <asm/asm-offsets.h>
14#include <asm/entry.h>
15#include <asm/arcregs.h>
16#include <asm/cache.h>
17#include <asm/dsp-impl.h>
18#include <asm/irqflags.h>
19
20.macro CPU_EARLY_SETUP
21
22 ; Setting up Vectror Table (in case exception happens in early boot
23 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
24
25 ; Disable I-cache/D-cache if kernel so configured
26 lr r5, [ARC_REG_IC_BCR]
27 breq r5, 0, 1f ; I$ doesn't exist
28 lr r5, [ARC_REG_IC_CTRL]
29#ifdef CONFIG_ARC_HAS_ICACHE
30 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
31#else
32 bset r5, r5, 0 ; I$ exists, but is not used
33#endif
34 sr r5, [ARC_REG_IC_CTRL]
35
361:
37 lr r5, [ARC_REG_DC_BCR]
38 breq r5, 0, 1f ; D$ doesn't exist
39 lr r5, [ARC_REG_DC_CTRL]
40 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
41#ifdef CONFIG_ARC_HAS_DCACHE
42 bclr r5, r5, 0 ; Enable (+Inv)
43#else
44 bset r5, r5, 0 ; Disable (+Inv)
45#endif
46 sr r5, [ARC_REG_DC_CTRL]
47
481:
49
50#ifdef CONFIG_ISA_ARCV2
51 ; Unaligned access is disabled at reset, so re-enable early as
52 ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
53 ; by default
54 lr r5, [status32]
55#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
56 bset r5, r5, STATUS_AD_BIT
57#else
58 ; Although disabled at reset, bootloader might have enabled it
59 bclr r5, r5, STATUS_AD_BIT
60#endif
61 kflag r5
62
63#ifdef CONFIG_ARC_LPB_DISABLE
64 lr r5, [ARC_REG_LPB_BUILD]
65 breq r5, 0, 1f ; LPB doesn't exist
66 mov r5, 1
67 sr r5, [ARC_REG_LPB_CTRL]
681:
69#endif /* CONFIG_ARC_LPB_DISABLE */
70
71 /* On HSDK, CCMs need to remapped super early */
72#ifdef CONFIG_ARC_SOC_HSDK
73 mov r6, 0x60000000
74 lr r5, [ARC_REG_ICCM_BUILD]
75 breq r5, 0, 1f
76 sr r6, [ARC_REG_AUX_ICCM]
771:
78 lr r5, [ARC_REG_DCCM_BUILD]
79 breq r5, 0, 2f
80 sr r6, [ARC_REG_AUX_DCCM]
812:
82#endif /* CONFIG_ARC_SOC_HSDK */
83
84#endif /* CONFIG_ISA_ARCV2 */
85
86 ; Config DSP_CTRL properly, so kernel may use integer multiply,
87 ; multiply-accumulate, and divide operations
88 DSP_EARLY_INIT
89.endm
90
91 .section .init.text, "ax",@progbits
92
93;----------------------------------------------------------------
94; Default Reset Handler (jumped into from Reset vector)
95; - Don't clobber r0,r1,r2 as they might have u-boot provided args
96; - Platforms can override this weak version if needed
97;----------------------------------------------------------------
98WEAK(res_service)
99 j stext
100END(res_service)
101
102;----------------------------------------------------------------
103; Kernel Entry point
104;----------------------------------------------------------------
105ENTRY(stext)
106
107 CPU_EARLY_SETUP
108
109#ifdef CONFIG_SMP
110 GET_CPU_ID r5
111 cmp r5, 0
112 mov.nz r0, r5
113 bz .Lmaster_proceed
114
115 ; Non-Masters wait for Master to boot enough and bring them up
116 ; when they resume, tail-call to entry point
117 mov blink, @first_lines_of_secondary
118 j arc_platform_smp_wait_to_boot
119
120.Lmaster_proceed:
121#endif
122
123 ; Clear BSS before updating any globals
124 ; XXX: use ZOL here
125 mov r5, __bss_start
126 sub r6, __bss_stop, r5
127 lsr.f lp_count, r6, 2
128 lpnz 1f
129 st.ab 0, [r5, 4]
1301:
131
132 ; Uboot - kernel ABI
133 ; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
134 ; r1 = magic number (always zero as of now)
135 ; r2 = pointer to uboot provided cmdline or external DTB in mem
136 ; These are handled later in handle_uboot_args()
137 st r0, [@uboot_tag]
138 st r1, [@uboot_magic]
139 st r2, [@uboot_arg]
140
141 ; setup "current" tsk and optionally cache it in dedicated r25
142 mov r9, @init_task
143 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
144
145 ; setup stack (fp, sp)
146 mov fp, 0
147
148 ; tsk->thread_info is really a PAGE, whose bottom hoists stack
149 GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
150
151 j start_kernel ; "C" entry point
152END(stext)
153
154#ifdef CONFIG_SMP
155;----------------------------------------------------------------
156; First lines of code run by secondary before jumping to 'C'
157;----------------------------------------------------------------
158 .section .text, "ax",@progbits
159ENTRY(first_lines_of_secondary)
160
161 ; setup per-cpu idle task as "current" on this CPU
162 ld r0, [@secondary_idle_tsk]
163 SET_CURR_TASK_ON_CPU r0, r1
164
165 ; setup stack (fp, sp)
166 mov fp, 0
167
168 ; set its stack base to tsk->thread_info bottom
169 GET_TSK_STACK_BASE r0, sp
170
171 j start_kernel_secondary
172END(first_lines_of_secondary)
173#endif
1/*
2 * ARC CPU startup Code
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Vineetg: Dec 2007
11 * -Check if we are running on Simulator or on real hardware
12 * to skip certain things during boot on simulator
13 */
14
15#include <linux/linkage.h>
16#include <asm/asm-offsets.h>
17#include <asm/entry.h>
18#include <asm/arcregs.h>
19#include <asm/cache.h>
20
21.macro CPU_EARLY_SETUP
22
23 ; Setting up Vectror Table (in case exception happens in early boot
24 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
25
26 ; Disable I-cache/D-cache if kernel so configured
27 lr r5, [ARC_REG_IC_BCR]
28 breq r5, 0, 1f ; I$ doesn't exist
29 lr r5, [ARC_REG_IC_CTRL]
30#ifdef CONFIG_ARC_HAS_ICACHE
31 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
32#else
33 bset r5, r5, 0 ; I$ exists, but is not used
34#endif
35 sr r5, [ARC_REG_IC_CTRL]
36
371:
38 lr r5, [ARC_REG_DC_BCR]
39 breq r5, 0, 1f ; D$ doesn't exist
40 lr r5, [ARC_REG_DC_CTRL]
41 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
42#ifdef CONFIG_ARC_HAS_DCACHE
43 bclr r5, r5, 0 ; Enable (+Inv)
44#else
45 bset r5, r5, 0 ; Disable (+Inv)
46#endif
47 sr r5, [ARC_REG_DC_CTRL]
48
491:
50.endm
51
52 .section .init.text, "ax",@progbits
53
54;----------------------------------------------------------------
55; Default Reset Handler (jumped into from Reset vector)
56; - Don't clobber r0,r1,r2 as they might have u-boot provided args
57; - Platforms can override this weak version if needed
58;----------------------------------------------------------------
59WEAK(res_service)
60 j stext
61END(res_service)
62
63;----------------------------------------------------------------
64; Kernel Entry point
65;----------------------------------------------------------------
66ENTRY(stext)
67
68 CPU_EARLY_SETUP
69
70#ifdef CONFIG_SMP
71 GET_CPU_ID r5
72 cmp r5, 0
73 mov.nz r0, r5
74#ifdef CONFIG_ARC_SMP_HALT_ON_RESET
75 ; Non-Master can proceed as system would be booted sufficiently
76 jnz first_lines_of_secondary
77#else
78 ; Non-Masters wait for Master to boot enough and bring them up
79 jnz arc_platform_smp_wait_to_boot
80#endif
81 ; Master falls thru
82#endif
83
84 ; Clear BSS before updating any globals
85 ; XXX: use ZOL here
86 mov r5, __bss_start
87 sub r6, __bss_stop, r5
88 lsr.f lp_count, r6, 2
89 lpnz 1f
90 st.ab 0, [r5, 4]
911:
92
93#ifdef CONFIG_ARC_UBOOT_SUPPORT
94 ; Uboot - kernel ABI
95 ; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
96 ; r1 = magic number (board identity, unused as of now
97 ; r2 = pointer to uboot provided cmdline or external DTB in mem
98 ; These are handled later in setup_arch()
99 st r0, [@uboot_tag]
100 st r2, [@uboot_arg]
101#endif
102
103 ; setup "current" tsk and optionally cache it in dedicated r25
104 mov r9, @init_task
105 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
106
107 ; setup stack (fp, sp)
108 mov fp, 0
109
110 ; tsk->thread_info is really a PAGE, whose bottom hoists stack
111 GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
112
113 j start_kernel ; "C" entry point
114END(stext)
115
116#ifdef CONFIG_SMP
117;----------------------------------------------------------------
118; First lines of code run by secondary before jumping to 'C'
119;----------------------------------------------------------------
120 .section .text, "ax",@progbits
121ENTRY(first_lines_of_secondary)
122
123 ; setup per-cpu idle task as "current" on this CPU
124 ld r0, [@secondary_idle_tsk]
125 SET_CURR_TASK_ON_CPU r0, r1
126
127 ; setup stack (fp, sp)
128 mov fp, 0
129
130 ; set it's stack base to tsk->thread_info bottom
131 GET_TSK_STACK_BASE r0, sp
132
133 j start_kernel_secondary
134END(first_lines_of_secondary)
135#endif