Loading...
Note: File does not exist in v6.13.7.
1/*
2 * Copyright (C) 2015 Linaro
3 *
4 * Author: Jun Nie <jun.nie@linaro.org>
5 *
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9#include <linux/clk.h>
10#include <linux/device.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18#include <sound/soc-dai.h>
19
20#include <sound/core.h>
21#include <sound/dmaengine_pcm.h>
22#include <sound/initval.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26
27#define ZX_I2S_PROCESS_CTRL 0x04
28#define ZX_I2S_TIMING_CTRL 0x08
29#define ZX_I2S_FIFO_CTRL 0x0C
30#define ZX_I2S_FIFO_STATUS 0x10
31#define ZX_I2S_INT_EN 0x14
32#define ZX_I2S_INT_STATUS 0x18
33#define ZX_I2S_DATA 0x1C
34#define ZX_I2S_FRAME_CNTR 0x20
35
36#define I2S_DEAGULT_FIFO_THRES (0x10)
37#define I2S_MAX_FIFO_THRES (0x20)
38
39#define ZX_I2S_PROCESS_TX_EN (1 << 0)
40#define ZX_I2S_PROCESS_TX_DIS (0 << 0)
41#define ZX_I2S_PROCESS_RX_EN (1 << 1)
42#define ZX_I2S_PROCESS_RX_DIS (0 << 1)
43#define ZX_I2S_PROCESS_I2S_EN (1 << 2)
44#define ZX_I2S_PROCESS_I2S_DIS (0 << 2)
45
46#define ZX_I2S_TIMING_MAST (1 << 0)
47#define ZX_I2S_TIMING_SLAVE (0 << 0)
48#define ZX_I2S_TIMING_MS_MASK (1 << 0)
49#define ZX_I2S_TIMING_LOOP (1 << 1)
50#define ZX_I2S_TIMING_NOR (0 << 1)
51#define ZX_I2S_TIMING_LOOP_MASK (1 << 1)
52#define ZX_I2S_TIMING_PTNR (1 << 2)
53#define ZX_I2S_TIMING_NTPR (0 << 2)
54#define ZX_I2S_TIMING_PHASE_MASK (1 << 2)
55#define ZX_I2S_TIMING_TDM (1 << 3)
56#define ZX_I2S_TIMING_I2S (0 << 3)
57#define ZX_I2S_TIMING_TIMING_MASK (1 << 3)
58#define ZX_I2S_TIMING_LONG_SYNC (1 << 4)
59#define ZX_I2S_TIMING_SHORT_SYNC (0 << 4)
60#define ZX_I2S_TIMING_SYNC_MASK (1 << 4)
61#define ZX_I2S_TIMING_TEAK_EN (1 << 5)
62#define ZX_I2S_TIMING_TEAK_DIS (0 << 5)
63#define ZX_I2S_TIMING_TEAK_MASK (1 << 5)
64#define ZX_I2S_TIMING_STD_I2S (0 << 6)
65#define ZX_I2S_TIMING_MSB_JUSTIF (1 << 6)
66#define ZX_I2S_TIMING_LSB_JUSTIF (2 << 6)
67#define ZX_I2S_TIMING_ALIGN_MASK (3 << 6)
68#define ZX_I2S_TIMING_CHN_MASK (7 << 8)
69#define ZX_I2S_TIMING_CHN(x) ((x - 1) << 8)
70#define ZX_I2S_TIMING_LANE_MASK (3 << 11)
71#define ZX_I2S_TIMING_LANE(x) ((x - 1) << 11)
72#define ZX_I2S_TIMING_TSCFG_MASK (7 << 13)
73#define ZX_I2S_TIMING_TSCFG(x) (x << 13)
74#define ZX_I2S_TIMING_TS_WIDTH_MASK (0x1f << 16)
75#define ZX_I2S_TIMING_TS_WIDTH(x) ((x - 1) << 16)
76#define ZX_I2S_TIMING_DATA_SIZE_MASK (0x1f << 21)
77#define ZX_I2S_TIMING_DATA_SIZE(x) ((x - 1) << 21)
78#define ZX_I2S_TIMING_CFG_ERR_MASK (1 << 31)
79
80#define ZX_I2S_FIFO_CTRL_TX_RST (1 << 0)
81#define ZX_I2S_FIFO_CTRL_TX_RST_MASK (1 << 0)
82#define ZX_I2S_FIFO_CTRL_RX_RST (1 << 1)
83#define ZX_I2S_FIFO_CTRL_RX_RST_MASK (1 << 1)
84#define ZX_I2S_FIFO_CTRL_TX_DMA_EN (1 << 4)
85#define ZX_I2S_FIFO_CTRL_TX_DMA_DIS (0 << 4)
86#define ZX_I2S_FIFO_CTRL_TX_DMA_MASK (1 << 4)
87#define ZX_I2S_FIFO_CTRL_RX_DMA_EN (1 << 5)
88#define ZX_I2S_FIFO_CTRL_RX_DMA_DIS (0 << 5)
89#define ZX_I2S_FIFO_CTRL_RX_DMA_MASK (1 << 5)
90#define ZX_I2S_FIFO_CTRL_TX_THRES_MASK (0x1F << 8)
91#define ZX_I2S_FIFO_CTRL_RX_THRES_MASK (0x1F << 16)
92
93#define CLK_RAT (32 * 4)
94
95struct zx_i2s_info {
96 struct snd_dmaengine_dai_dma_data dma_playback;
97 struct snd_dmaengine_dai_dma_data dma_capture;
98 struct clk *dai_wclk;
99 struct clk *dai_pclk;
100 void __iomem *reg_base;
101 int master;
102 resource_size_t mapbase;
103};
104
105static void zx_i2s_tx_en(void __iomem *base, bool on)
106{
107 unsigned long val;
108
109 val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
110 if (on)
111 val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;
112 else
113 val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);
114 writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
115}
116
117static void zx_i2s_rx_en(void __iomem *base, bool on)
118{
119 unsigned long val;
120
121 val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
122 if (on)
123 val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;
124 else
125 val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);
126 writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
127}
128
129static void zx_i2s_tx_dma_en(void __iomem *base, bool on)
130{
131 unsigned long val;
132
133 val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
134 val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);
135 if (on)
136 val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;
137 else
138 val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;
139 writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
140}
141
142static void zx_i2s_rx_dma_en(void __iomem *base, bool on)
143{
144 unsigned long val;
145
146 val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
147 val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);
148 if (on)
149 val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;
150 else
151 val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;
152 writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
153}
154
155#define ZX_I2S_RATES \
156 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
157 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
158 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000| \
159 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
160
161#define ZX_I2S_FMTBIT \
162 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
163 SNDRV_PCM_FMTBIT_S32_LE)
164
165static int zx_i2s_dai_probe(struct snd_soc_dai *dai)
166{
167 struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
168
169 snd_soc_dai_set_drvdata(dai, zx_i2s);
170 zx_i2s->dma_playback.addr = zx_i2s->mapbase + ZX_I2S_DATA;
171 zx_i2s->dma_playback.maxburst = 16;
172 zx_i2s->dma_capture.addr = zx_i2s->mapbase + ZX_I2S_DATA;
173 zx_i2s->dma_capture.maxburst = 16;
174 snd_soc_dai_init_dma_data(dai, &zx_i2s->dma_playback,
175 &zx_i2s->dma_capture);
176 return 0;
177}
178
179static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
180{
181 struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
182 unsigned long val;
183
184 val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
185 val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |
186 ZX_I2S_TIMING_TEAK_MASK | ZX_I2S_TIMING_SYNC_MASK |
187 ZX_I2S_TIMING_MS_MASK);
188
189 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
190 case SND_SOC_DAIFMT_I2S:
191 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);
192 break;
193 case SND_SOC_DAIFMT_LEFT_J:
194 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);
195 break;
196 case SND_SOC_DAIFMT_RIGHT_J:
197 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);
198 break;
199 default:
200 dev_err(cpu_dai->dev, "Unknown i2s timeing\n");
201 return -EINVAL;
202 }
203
204 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
205 case SND_SOC_DAIFMT_CBM_CFM:
206 /* Codec is master, and I2S is slave. */
207 i2s->master = 0;
208 val |= ZX_I2S_TIMING_SLAVE;
209 break;
210 case SND_SOC_DAIFMT_CBS_CFS:
211 /* Codec is slave, and I2S is master. */
212 i2s->master = 1;
213 val |= ZX_I2S_TIMING_MAST;
214 break;
215 default:
216 dev_err(cpu_dai->dev, "Unknown master/slave format\n");
217 return -EINVAL;
218 }
219
220 writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
221 return 0;
222}
223
224static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *socdai)
227{
228 struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(socdai);
229 struct snd_dmaengine_dai_dma_data *dma_data;
230 unsigned int lane, ch_num, len, ret = 0;
231 unsigned int ts_width = 32;
232 unsigned long val;
233 unsigned long chn_cfg;
234
235 dma_data = snd_soc_dai_get_dma_data(socdai, substream);
236 dma_data->addr_width = ts_width >> 3;
237
238 val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
239 val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |
240 ZX_I2S_TIMING_LANE_MASK | ZX_I2S_TIMING_CHN_MASK |
241 ZX_I2S_TIMING_TSCFG_MASK);
242
243 switch (params_format(params)) {
244 case SNDRV_PCM_FORMAT_S16_LE:
245 len = 16;
246 break;
247 case SNDRV_PCM_FORMAT_S24_LE:
248 len = 24;
249 break;
250 case SNDRV_PCM_FORMAT_S32_LE:
251 len = 32;
252 break;
253 default:
254 dev_err(socdai->dev, "Unknown data format\n");
255 return -EINVAL;
256 }
257 val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);
258
259 ch_num = params_channels(params);
260 switch (ch_num) {
261 case 1:
262 lane = 1;
263 chn_cfg = 2;
264 break;
265 case 2:
266 case 4:
267 case 6:
268 case 8:
269 lane = ch_num / 2;
270 chn_cfg = 3;
271 break;
272 default:
273 dev_err(socdai->dev, "Not support channel num %d\n", ch_num);
274 return -EINVAL;
275 }
276 val |= ZX_I2S_TIMING_LANE(lane);
277 val |= ZX_I2S_TIMING_TSCFG(chn_cfg);
278 val |= ZX_I2S_TIMING_CHN(ch_num);
279 writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
280
281 if (i2s->master)
282 ret = clk_set_rate(i2s->dai_wclk,
283 params_rate(params) * ch_num * CLK_RAT);
284
285 return ret;
286}
287
288static int zx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
289 struct snd_soc_dai *dai)
290{
291 struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
292 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
293 int ret = 0;
294
295 switch (cmd) {
296 case SNDRV_PCM_TRIGGER_START:
297 if (capture)
298 zx_i2s_rx_dma_en(zx_i2s->reg_base, true);
299 else
300 zx_i2s_tx_dma_en(zx_i2s->reg_base, true);
301 /* fall thru */
302 case SNDRV_PCM_TRIGGER_RESUME:
303 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
304 if (capture)
305 zx_i2s_rx_en(zx_i2s->reg_base, true);
306 else
307 zx_i2s_tx_en(zx_i2s->reg_base, true);
308 break;
309
310 case SNDRV_PCM_TRIGGER_STOP:
311 if (capture)
312 zx_i2s_rx_dma_en(zx_i2s->reg_base, false);
313 else
314 zx_i2s_tx_dma_en(zx_i2s->reg_base, false);
315 /* fall thru */
316 case SNDRV_PCM_TRIGGER_SUSPEND:
317 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
318 if (capture)
319 zx_i2s_rx_en(zx_i2s->reg_base, false);
320 else
321 zx_i2s_tx_en(zx_i2s->reg_base, false);
322 break;
323
324 default:
325 ret = -EINVAL;
326 break;
327 }
328
329 return ret;
330}
331
332static int zx_i2s_startup(struct snd_pcm_substream *substream,
333 struct snd_soc_dai *dai)
334{
335 struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
336 int ret;
337
338 ret = clk_prepare_enable(zx_i2s->dai_wclk);
339 if (ret)
340 return ret;
341
342 ret = clk_prepare_enable(zx_i2s->dai_pclk);
343 if (ret) {
344 clk_disable_unprepare(zx_i2s->dai_wclk);
345 return ret;
346 }
347
348 return ret;
349}
350
351static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
352 struct snd_soc_dai *dai)
353{
354 struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
355
356 clk_disable_unprepare(zx_i2s->dai_wclk);
357 clk_disable_unprepare(zx_i2s->dai_pclk);
358}
359
360static const struct snd_soc_dai_ops zx_i2s_dai_ops = {
361 .trigger = zx_i2s_trigger,
362 .hw_params = zx_i2s_hw_params,
363 .set_fmt = zx_i2s_set_fmt,
364 .startup = zx_i2s_startup,
365 .shutdown = zx_i2s_shutdown,
366};
367
368static const struct snd_soc_component_driver zx_i2s_component = {
369 .name = "zx-i2s",
370};
371
372static struct snd_soc_dai_driver zx_i2s_dai = {
373 .name = "zx-i2s-dai",
374 .id = 0,
375 .probe = zx_i2s_dai_probe,
376 .playback = {
377 .channels_min = 1,
378 .channels_max = 8,
379 .rates = ZX_I2S_RATES,
380 .formats = ZX_I2S_FMTBIT,
381 },
382 .capture = {
383 .channels_min = 1,
384 .channels_max = 2,
385 .rates = ZX_I2S_RATES,
386 .formats = ZX_I2S_FMTBIT,
387 },
388 .ops = &zx_i2s_dai_ops,
389};
390
391static int zx_i2s_probe(struct platform_device *pdev)
392{
393 struct resource *res;
394 struct zx_i2s_info *zx_i2s;
395 int ret;
396
397 zx_i2s = devm_kzalloc(&pdev->dev, sizeof(*zx_i2s), GFP_KERNEL);
398 if (!zx_i2s)
399 return -ENOMEM;
400
401 zx_i2s->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
402 if (IS_ERR(zx_i2s->dai_wclk)) {
403 dev_err(&pdev->dev, "Fail to get wclk\n");
404 return PTR_ERR(zx_i2s->dai_wclk);
405 }
406
407 zx_i2s->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
408 if (IS_ERR(zx_i2s->dai_pclk)) {
409 dev_err(&pdev->dev, "Fail to get pclk\n");
410 return PTR_ERR(zx_i2s->dai_pclk);
411 }
412
413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
414 zx_i2s->mapbase = res->start;
415 zx_i2s->reg_base = devm_ioremap_resource(&pdev->dev, res);
416 if (IS_ERR(zx_i2s->reg_base)) {
417 dev_err(&pdev->dev, "ioremap failed!\n");
418 return PTR_ERR(zx_i2s->reg_base);
419 }
420
421 writel_relaxed(0, zx_i2s->reg_base + ZX_I2S_FIFO_CTRL);
422 platform_set_drvdata(pdev, zx_i2s);
423
424 ret = devm_snd_soc_register_component(&pdev->dev, &zx_i2s_component,
425 &zx_i2s_dai, 1);
426 if (ret) {
427 dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
428 return ret;
429 }
430
431 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
432 if (ret)
433 dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
434
435 return ret;
436}
437
438static const struct of_device_id zx_i2s_dt_ids[] = {
439 { .compatible = "zte,zx296702-i2s", },
440 {}
441};
442MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
443
444static struct platform_driver i2s_driver = {
445 .probe = zx_i2s_probe,
446 .driver = {
447 .name = "zx-i2s",
448 .of_match_table = zx_i2s_dt_ids,
449 },
450};
451
452module_platform_driver(i2s_driver);
453
454MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
455MODULE_DESCRIPTION("ZTE I2S SoC DAI");
456MODULE_LICENSE("GPL");