1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Functions and macros to control the flowcontroller
 4 *
 5 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
 
 
 
 
 
 
 
 
 
 
 
 
 6 */
 7
 8#ifndef __SOC_TEGRA_FLOWCTRL_H__
 9#define __SOC_TEGRA_FLOWCTRL_H__
10
11#define FLOW_CTRL_HALT_CPU0_EVENTS	0x0
12#define FLOW_CTRL_WAITEVENT		(2 << 29)
13#define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
14#define FLOW_CTRL_JTAG_RESUME		(1 << 28)
15#define FLOW_CTRL_SCLK_RESUME		(1 << 27)
16#define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
17#define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
18#define FLOW_CTRL_HALT_LIC_IRQ		(1 << 11)
19#define FLOW_CTRL_HALT_LIC_FIQ		(1 << 10)
20#define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
21#define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
22#define FLOW_CTRL_CPU0_CSR		0x8
23#define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
24#define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
25#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL	(1 << 13)
26#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU	(1 << 12)
27#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
28		FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
29		FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
30#define FLOW_CTRL_CSR_ENABLE		(1 << 0)
31#define FLOW_CTRL_HALT_CPU1_EVENTS	0x14
32#define FLOW_CTRL_CPU1_CSR		0x18
33
34#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)
35#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)
36#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP	0
37
38#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0		(1 << 8)
39#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP	(0xF << 4)
40#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP	(0xF << 8)
41
42#ifndef __ASSEMBLY__
43#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
44u32 flowctrl_read_cpu_csr(unsigned int cpuid);
45void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
46void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
47
48void flowctrl_cpu_suspend_enter(unsigned int cpuid);
49void flowctrl_cpu_suspend_exit(unsigned int cpuid);
50#else
51static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
52{
53	return 0;
54}
55
56static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
57{
58}
59
60static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
61
62static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
63{
64}
65
66static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
67{
68}
69#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
70#endif /* __ASSEMBLY */
71#endif /* __SOC_TEGRA_FLOWCTRL_H__ */

 
 1/*
 2 * Functions and macros to control the flowcontroller
 3 *
 4 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
 5 *
 6 * This program is free software; you can redistribute it and/or modify it
 7 * under the terms and conditions of the GNU General Public License,
 8 * version 2, as published by the Free Software Foundation.
 9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __SOC_TEGRA_FLOWCTRL_H__
20#define __SOC_TEGRA_FLOWCTRL_H__
21
22#define FLOW_CTRL_HALT_CPU0_EVENTS	0x0
23#define FLOW_CTRL_WAITEVENT		(2 << 29)
24#define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
25#define FLOW_CTRL_JTAG_RESUME		(1 << 28)
26#define FLOW_CTRL_SCLK_RESUME		(1 << 27)
27#define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
28#define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
29#define FLOW_CTRL_HALT_LIC_IRQ		(1 << 11)
30#define FLOW_CTRL_HALT_LIC_FIQ		(1 << 10)
31#define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
32#define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
33#define FLOW_CTRL_CPU0_CSR		0x8
34#define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
35#define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
36#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL	(1 << 13)
37#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU	(1 << 12)
38#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
39		FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
40		FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
41#define FLOW_CTRL_CSR_ENABLE		(1 << 0)
42#define FLOW_CTRL_HALT_CPU1_EVENTS	0x14
43#define FLOW_CTRL_CPU1_CSR		0x18
44
45#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)
46#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)
47#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP	0
48
49#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0		(1 << 8)
50#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP	(0xF << 4)
51#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP	(0xF << 8)
52
53#ifndef __ASSEMBLY__
54#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
55u32 flowctrl_read_cpu_csr(unsigned int cpuid);
56void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
57void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
58
59void flowctrl_cpu_suspend_enter(unsigned int cpuid);
60void flowctrl_cpu_suspend_exit(unsigned int cpuid);
61#else
62static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
63{
64	return 0;
65}
66
67static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
68{
69}
70
71static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
72
73static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
74{
75}
76
77static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
78{
79}
80#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
81#endif /* __ASSEMBLY */
82#endif /* __SOC_TEGRA_FLOWCTRL_H__ */