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1/* SPDX-License-Identifier: GPL-2.0 */
2
3#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
4#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
5
6/* core clocks */
7#define PLL_APLL 1
8#define PLL_DPLL 2
9#define PLL_CPLL 3
10#define PLL_NPLL 4
11#define APLL_BOOST_H 5
12#define APLL_BOOST_L 6
13#define ARMCLK 7
14
15/* sclk gates (special clocks) */
16#define USB480M 14
17#define SCLK_PDM 15
18#define SCLK_I2S0_TX 16
19#define SCLK_I2S0_TX_OUT 17
20#define SCLK_I2S0_RX 18
21#define SCLK_I2S0_RX_OUT 19
22#define SCLK_I2S1 20
23#define SCLK_I2S1_OUT 21
24#define SCLK_I2S2 22
25#define SCLK_I2S2_OUT 23
26#define SCLK_UART1 24
27#define SCLK_UART2 25
28#define SCLK_UART3 26
29#define SCLK_UART4 27
30#define SCLK_UART5 28
31#define SCLK_I2C0 29
32#define SCLK_I2C1 30
33#define SCLK_I2C2 31
34#define SCLK_I2C3 32
35#define SCLK_I2C4 33
36#define SCLK_PWM0 34
37#define SCLK_PWM1 35
38#define SCLK_SPI0 36
39#define SCLK_SPI1 37
40#define SCLK_TIMER0 38
41#define SCLK_TIMER1 39
42#define SCLK_TIMER2 40
43#define SCLK_TIMER3 41
44#define SCLK_TIMER4 42
45#define SCLK_TIMER5 43
46#define SCLK_TSADC 44
47#define SCLK_SARADC 45
48#define SCLK_OTP 46
49#define SCLK_OTP_USR 47
50#define SCLK_CRYPTO 48
51#define SCLK_CRYPTO_APK 49
52#define SCLK_DDRC 50
53#define SCLK_ISP 51
54#define SCLK_CIF_OUT 52
55#define SCLK_RGA_CORE 53
56#define SCLK_VOPB_PWM 54
57#define SCLK_NANDC 55
58#define SCLK_SDIO 56
59#define SCLK_EMMC 57
60#define SCLK_SFC 58
61#define SCLK_SDMMC 59
62#define SCLK_OTG_ADP 60
63#define SCLK_GMAC_SRC 61
64#define SCLK_GMAC 62
65#define SCLK_GMAC_RX_TX 63
66#define SCLK_MAC_REF 64
67#define SCLK_MAC_REFOUT 65
68#define SCLK_MAC_OUT 66
69#define SCLK_SDMMC_DRV 67
70#define SCLK_SDMMC_SAMPLE 68
71#define SCLK_SDIO_DRV 69
72#define SCLK_SDIO_SAMPLE 70
73#define SCLK_EMMC_DRV 71
74#define SCLK_EMMC_SAMPLE 72
75#define SCLK_GPU 73
76#define SCLK_PVTM 74
77#define SCLK_CORE_VPU 75
78#define SCLK_GMAC_RMII 76
79#define SCLK_UART2_SRC 77
80#define SCLK_NANDC_DIV 78
81#define SCLK_NANDC_DIV50 79
82#define SCLK_SDIO_DIV 80
83#define SCLK_SDIO_DIV50 81
84#define SCLK_EMMC_DIV 82
85#define SCLK_EMMC_DIV50 83
86#define SCLK_DDRCLK 84
87#define SCLK_UART1_SRC 85
88#define SCLK_SDMMC_DIV 86
89#define SCLK_SDMMC_DIV50 87
90
91/* dclk gates */
92#define DCLK_VOPB 150
93#define DCLK_VOPL 151
94
95/* aclk gates */
96#define ACLK_GPU 170
97#define ACLK_BUS_PRE 171
98#define ACLK_CRYPTO 172
99#define ACLK_VI_PRE 173
100#define ACLK_VO_PRE 174
101#define ACLK_VPU 175
102#define ACLK_PERI_PRE 176
103#define ACLK_GMAC 178
104#define ACLK_CIF 179
105#define ACLK_ISP 180
106#define ACLK_VOPB 181
107#define ACLK_VOPL 182
108#define ACLK_RGA 183
109#define ACLK_GIC 184
110#define ACLK_DCF 186
111#define ACLK_DMAC 187
112#define ACLK_BUS_SRC 188
113#define ACLK_PERI_SRC 189
114
115/* hclk gates */
116#define HCLK_BUS_PRE 240
117#define HCLK_CRYPTO 241
118#define HCLK_VI_PRE 242
119#define HCLK_VO_PRE 243
120#define HCLK_VPU 244
121#define HCLK_PERI_PRE 245
122#define HCLK_MMC_NAND 246
123#define HCLK_SDMMC 247
124#define HCLK_USB 248
125#define HCLK_CIF 249
126#define HCLK_ISP 250
127#define HCLK_VOPB 251
128#define HCLK_VOPL 252
129#define HCLK_RGA 253
130#define HCLK_NANDC 254
131#define HCLK_SDIO 255
132#define HCLK_EMMC 256
133#define HCLK_SFC 257
134#define HCLK_OTG 258
135#define HCLK_HOST 259
136#define HCLK_HOST_ARB 260
137#define HCLK_PDM 261
138#define HCLK_I2S0 262
139#define HCLK_I2S1 263
140#define HCLK_I2S2 264
141
142/* pclk gates */
143#define PCLK_BUS_PRE 320
144#define PCLK_DDR 321
145#define PCLK_VO_PRE 322
146#define PCLK_GMAC 323
147#define PCLK_MIPI_DSI 324
148#define PCLK_MIPIDSIPHY 325
149#define PCLK_MIPICSIPHY 326
150#define PCLK_USB_GRF 327
151#define PCLK_DCF 328
152#define PCLK_UART1 329
153#define PCLK_UART2 330
154#define PCLK_UART3 331
155#define PCLK_UART4 332
156#define PCLK_UART5 333
157#define PCLK_I2C0 334
158#define PCLK_I2C1 335
159#define PCLK_I2C2 336
160#define PCLK_I2C3 337
161#define PCLK_I2C4 338
162#define PCLK_PWM0 339
163#define PCLK_PWM1 340
164#define PCLK_SPI0 341
165#define PCLK_SPI1 342
166#define PCLK_SARADC 343
167#define PCLK_TSADC 344
168#define PCLK_TIMER 345
169#define PCLK_OTP_NS 346
170#define PCLK_WDT_NS 347
171#define PCLK_GPIO1 348
172#define PCLK_GPIO2 349
173#define PCLK_GPIO3 350
174#define PCLK_ISP 351
175#define PCLK_CIF 352
176#define PCLK_OTP_PHY 353
177
178/* pmu-clocks indices */
179
180#define PLL_GPLL 1
181
182#define SCLK_RTC32K_PMU 4
183#define SCLK_WIFI_PMU 5
184#define SCLK_UART0_PMU 6
185#define SCLK_PVTM_PMU 7
186#define PCLK_PMU_PRE 8
187#define SCLK_REF24M_PMU 9
188#define SCLK_USBPHY_REF 10
189#define SCLK_MIPIDSIPHY_REF 11
190
191#define XIN24M_DIV 12
192
193#define PCLK_GPIO0_PMU 20
194#define PCLK_UART0_PMU 21
195
196/* soft-reset indices */
197#define SRST_CORE0_PO 0
198#define SRST_CORE1_PO 1
199#define SRST_CORE2_PO 2
200#define SRST_CORE3_PO 3
201#define SRST_CORE0 4
202#define SRST_CORE1 5
203#define SRST_CORE2 6
204#define SRST_CORE3 7
205#define SRST_CORE0_DBG 8
206#define SRST_CORE1_DBG 9
207#define SRST_CORE2_DBG 10
208#define SRST_CORE3_DBG 11
209#define SRST_TOPDBG 12
210#define SRST_CORE_NOC 13
211#define SRST_STRC_A 14
212#define SRST_L2C 15
213
214#define SRST_DAP 16
215#define SRST_CORE_PVTM 17
216#define SRST_GPU 18
217#define SRST_GPU_NIU 19
218#define SRST_UPCTL2 20
219#define SRST_UPCTL2_A 21
220#define SRST_UPCTL2_P 22
221#define SRST_MSCH 23
222#define SRST_MSCH_P 24
223#define SRST_DDRMON_P 25
224#define SRST_DDRSTDBY_P 26
225#define SRST_DDRSTDBY 27
226#define SRST_DDRGRF_p 28
227#define SRST_AXI_SPLIT_A 29
228#define SRST_AXI_CMD_A 30
229#define SRST_AXI_CMD_P 31
230
231#define SRST_DDRPHY 32
232#define SRST_DDRPHYDIV 33
233#define SRST_DDRPHY_P 34
234#define SRST_VPU_A 36
235#define SRST_VPU_NIU_A 37
236#define SRST_VPU_H 38
237#define SRST_VPU_NIU_H 39
238#define SRST_VI_NIU_A 40
239#define SRST_VI_NIU_H 41
240#define SRST_ISP_H 42
241#define SRST_ISP 43
242#define SRST_CIF_A 44
243#define SRST_CIF_H 45
244#define SRST_CIF_PCLKIN 46
245#define SRST_MIPICSIPHY_P 47
246
247#define SRST_VO_NIU_A 48
248#define SRST_VO_NIU_H 49
249#define SRST_VO_NIU_P 50
250#define SRST_VOPB_A 51
251#define SRST_VOPB_H 52
252#define SRST_VOPB 53
253#define SRST_PWM_VOPB 54
254#define SRST_VOPL_A 55
255#define SRST_VOPL_H 56
256#define SRST_VOPL 57
257#define SRST_RGA_A 58
258#define SRST_RGA_H 59
259#define SRST_RGA 60
260#define SRST_MIPIDSI_HOST_P 61
261#define SRST_MIPIDSIPHY_P 62
262#define SRST_VPU_CORE 63
263
264#define SRST_PERI_NIU_A 64
265#define SRST_USB_NIU_H 65
266#define SRST_USB2OTG_H 66
267#define SRST_USB2OTG 67
268#define SRST_USB2OTG_ADP 68
269#define SRST_USB2HOST_H 69
270#define SRST_USB2HOST_ARB_H 70
271#define SRST_USB2HOST_AUX_H 71
272#define SRST_USB2HOST_EHCI 72
273#define SRST_USB2HOST 73
274#define SRST_USBPHYPOR 74
275#define SRST_USBPHY_OTG_PORT 75
276#define SRST_USBPHY_HOST_PORT 76
277#define SRST_USBPHY_GRF 77
278#define SRST_CPU_BOOST_P 78
279#define SRST_CPU_BOOST 79
280
281#define SRST_MMC_NAND_NIU_H 80
282#define SRST_SDIO_H 81
283#define SRST_EMMC_H 82
284#define SRST_SFC_H 83
285#define SRST_SFC 84
286#define SRST_SDCARD_NIU_H 85
287#define SRST_SDMMC_H 86
288#define SRST_NANDC_H 89
289#define SRST_NANDC 90
290#define SRST_GMAC_NIU_A 92
291#define SRST_GMAC_NIU_P 93
292#define SRST_GMAC_A 94
293
294#define SRST_PMU_NIU_P 96
295#define SRST_PMU_SGRF_P 97
296#define SRST_PMU_GRF_P 98
297#define SRST_PMU 99
298#define SRST_PMU_MEM_P 100
299#define SRST_PMU_GPIO0_P 101
300#define SRST_PMU_UART0_P 102
301#define SRST_PMU_CRU_P 103
302#define SRST_PMU_PVTM 104
303#define SRST_PMU_UART 105
304#define SRST_PMU_NIU_H 106
305#define SRST_PMU_DDR_FAIL_SAVE 107
306#define SRST_PMU_CORE_PERF_A 108
307#define SRST_PMU_CORE_GRF_P 109
308#define SRST_PMU_GPU_PERF_A 110
309#define SRST_PMU_GPU_GRF_P 111
310
311#define SRST_CRYPTO_NIU_A 112
312#define SRST_CRYPTO_NIU_H 113
313#define SRST_CRYPTO_A 114
314#define SRST_CRYPTO_H 115
315#define SRST_CRYPTO 116
316#define SRST_CRYPTO_APK 117
317#define SRST_BUS_NIU_H 120
318#define SRST_USB_NIU_P 121
319#define SRST_BUS_TOP_NIU_P 122
320#define SRST_INTMEM_A 123
321#define SRST_GIC_A 124
322#define SRST_ROM_H 126
323#define SRST_DCF_A 127
324
325#define SRST_DCF_P 128
326#define SRST_PDM_H 129
327#define SRST_PDM 130
328#define SRST_I2S0_H 131
329#define SRST_I2S0_TX 132
330#define SRST_I2S1_H 133
331#define SRST_I2S1 134
332#define SRST_I2S2_H 135
333#define SRST_I2S2 136
334#define SRST_UART1_P 137
335#define SRST_UART1 138
336#define SRST_UART2_P 139
337#define SRST_UART2 140
338#define SRST_UART3_P 141
339#define SRST_UART3 142
340#define SRST_UART4_P 143
341
342#define SRST_UART4 144
343#define SRST_UART5_P 145
344#define SRST_UART5 146
345#define SRST_I2C0_P 147
346#define SRST_I2C0 148
347#define SRST_I2C1_P 149
348#define SRST_I2C1 150
349#define SRST_I2C2_P 151
350#define SRST_I2C2 152
351#define SRST_I2C3_P 153
352#define SRST_I2C3 154
353#define SRST_PWM0_P 157
354#define SRST_PWM0 158
355#define SRST_PWM1_P 159
356
357#define SRST_PWM1 160
358#define SRST_SPI0_P 161
359#define SRST_SPI0 162
360#define SRST_SPI1_P 163
361#define SRST_SPI1 164
362#define SRST_SARADC_P 165
363#define SRST_SARADC 166
364#define SRST_TSADC_P 167
365#define SRST_TSADC 168
366#define SRST_TIMER_P 169
367#define SRST_TIMER0 170
368#define SRST_TIMER1 171
369#define SRST_TIMER2 172
370#define SRST_TIMER3 173
371#define SRST_TIMER4 174
372#define SRST_TIMER5 175
373
374#define SRST_OTP_NS_P 176
375#define SRST_OTP_NS_SBPI 177
376#define SRST_OTP_NS_USR 178
377#define SRST_OTP_PHY_P 179
378#define SRST_OTP_PHY 180
379#define SRST_WDT_NS_P 181
380#define SRST_GPIO1_P 182
381#define SRST_GPIO2_P 183
382#define SRST_GPIO3_P 184
383#define SRST_SGRF_P 185
384#define SRST_GRF_P 186
385#define SRST_I2S0_RX 191
386
387#endif