Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/char/watchdog/sp805-wdt.c
4 *
5 * Watchdog driver for ARM SP805 watchdog module
6 *
7 * Copyright (C) 2010 ST Microelectronics
8 * Viresh Kumar <vireshk@kernel.org>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2 or later. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/device.h>
16#include <linux/resource.h>
17#include <linux/amba/bus.h>
18#include <linux/bitops.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/kernel.h>
23#include <linux/math64.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pm.h>
27#include <linux/property.h>
28#include <linux/reset.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/types.h>
32#include <linux/watchdog.h>
33
34/* default timeout in seconds */
35#define DEFAULT_TIMEOUT 60
36
37#define MODULE_NAME "sp805-wdt"
38
39/* watchdog register offsets and masks */
40#define WDTLOAD 0x000
41 #define LOAD_MIN 0x00000001
42 #define LOAD_MAX 0xFFFFFFFF
43#define WDTVALUE 0x004
44#define WDTCONTROL 0x008
45 /* control register masks */
46 #define INT_ENABLE (1 << 0)
47 #define RESET_ENABLE (1 << 1)
48 #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
49#define WDTINTCLR 0x00C
50#define WDTRIS 0x010
51#define WDTMIS 0x014
52 #define INT_MASK (1 << 0)
53#define WDTLOCK 0xC00
54 #define UNLOCK 0x1ACCE551
55 #define LOCK 0x00000001
56
57/**
58 * struct sp805_wdt: sp805 wdt device structure
59 * @wdd: instance of struct watchdog_device
60 * @lock: spin lock protecting dev structure and io access
61 * @base: base address of wdt
62 * @clk: (optional) clock structure of wdt
63 * @rate: (optional) clock rate when provided via properties
64 * @adev: amba device structure of wdt
65 * @status: current status of wdt
66 * @load_val: load value to be set for current timeout
67 */
68struct sp805_wdt {
69 struct watchdog_device wdd;
70 spinlock_t lock;
71 void __iomem *base;
72 struct clk *clk;
73 u64 rate;
74 struct amba_device *adev;
75 unsigned int load_val;
76};
77
78static bool nowayout = WATCHDOG_NOWAYOUT;
79module_param(nowayout, bool, 0);
80MODULE_PARM_DESC(nowayout,
81 "Set to 1 to keep watchdog running after device release");
82
83/* returns true if wdt is running; otherwise returns false */
84static bool wdt_is_running(struct watchdog_device *wdd)
85{
86 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
87 u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
88
89 return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
90}
91
92/* This routine finds load value that will reset system in required timeout */
93static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
94{
95 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
96 u64 load, rate;
97
98 rate = wdt->rate;
99
100 /*
101 * sp805 runs counter with given value twice, after the end of first
102 * counter it gives an interrupt and then starts counter again. If
103 * interrupt already occurred then it resets the system. This is why
104 * load is half of what should be required.
105 */
106 load = div_u64(rate, 2) * timeout - 1;
107
108 load = (load > LOAD_MAX) ? LOAD_MAX : load;
109 load = (load < LOAD_MIN) ? LOAD_MIN : load;
110
111 spin_lock(&wdt->lock);
112 wdt->load_val = load;
113 /* roundup timeout to closest positive integer value */
114 wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
115 spin_unlock(&wdt->lock);
116
117 return 0;
118}
119
120/* returns number of seconds left for reset to occur */
121static unsigned int wdt_timeleft(struct watchdog_device *wdd)
122{
123 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
124 u64 load;
125
126 spin_lock(&wdt->lock);
127 load = readl_relaxed(wdt->base + WDTVALUE);
128
129 /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
130 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
131 load += wdt->load_val + 1;
132 spin_unlock(&wdt->lock);
133
134 return div_u64(load, wdt->rate);
135}
136
137static int
138wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd)
139{
140 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
141
142 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
143 writel_relaxed(0, wdt->base + WDTCONTROL);
144 writel_relaxed(0, wdt->base + WDTLOAD);
145 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
146
147 /* Flush posted writes. */
148 readl_relaxed(wdt->base + WDTLOCK);
149
150 return 0;
151}
152
153static int wdt_config(struct watchdog_device *wdd, bool ping)
154{
155 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
156 int ret;
157
158 if (!ping) {
159
160 ret = clk_prepare_enable(wdt->clk);
161 if (ret) {
162 dev_err(&wdt->adev->dev, "clock enable fail");
163 return ret;
164 }
165 }
166
167 spin_lock(&wdt->lock);
168
169 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
170 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
171 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
172
173 if (!ping)
174 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
175 WDTCONTROL);
176
177 writel_relaxed(LOCK, wdt->base + WDTLOCK);
178
179 /* Flush posted writes. */
180 readl_relaxed(wdt->base + WDTLOCK);
181 spin_unlock(&wdt->lock);
182
183 return 0;
184}
185
186static int wdt_ping(struct watchdog_device *wdd)
187{
188 return wdt_config(wdd, true);
189}
190
191/* enables watchdog timers reset */
192static int wdt_enable(struct watchdog_device *wdd)
193{
194 return wdt_config(wdd, false);
195}
196
197/* disables watchdog timers reset */
198static int wdt_disable(struct watchdog_device *wdd)
199{
200 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
201
202 spin_lock(&wdt->lock);
203
204 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
205 writel_relaxed(0, wdt->base + WDTCONTROL);
206 writel_relaxed(LOCK, wdt->base + WDTLOCK);
207
208 /* Flush posted writes. */
209 readl_relaxed(wdt->base + WDTLOCK);
210 spin_unlock(&wdt->lock);
211
212 clk_disable_unprepare(wdt->clk);
213
214 return 0;
215}
216
217static const struct watchdog_info wdt_info = {
218 .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
219 .identity = MODULE_NAME,
220};
221
222static const struct watchdog_ops wdt_ops = {
223 .owner = THIS_MODULE,
224 .start = wdt_enable,
225 .stop = wdt_disable,
226 .ping = wdt_ping,
227 .set_timeout = wdt_setload,
228 .get_timeleft = wdt_timeleft,
229 .restart = wdt_restart,
230};
231
232static int
233sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
234{
235 struct sp805_wdt *wdt;
236 struct reset_control *rst;
237 u64 rate = 0;
238 int ret = 0;
239
240 wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
241 if (!wdt) {
242 ret = -ENOMEM;
243 goto err;
244 }
245
246 wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
247 if (IS_ERR(wdt->base))
248 return PTR_ERR(wdt->base);
249
250 /*
251 * When driver probe with ACPI device, clock devices
252 * are not available, so watchdog rate get from
253 * clock-frequency property given in _DSD object.
254 */
255 device_property_read_u64(&adev->dev, "clock-frequency", &rate);
256
257 wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
258 if (IS_ERR(wdt->clk))
259 return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");
260
261 wdt->rate = clk_get_rate(wdt->clk);
262 if (!wdt->rate)
263 wdt->rate = rate;
264 if (!wdt->rate) {
265 dev_err(&adev->dev, "no clock-frequency property\n");
266 return -ENODEV;
267 }
268
269 rst = devm_reset_control_get_optional_exclusive(&adev->dev, NULL);
270 if (IS_ERR(rst))
271 return dev_err_probe(&adev->dev, PTR_ERR(rst), "Can not get reset\n");
272
273 reset_control_deassert(rst);
274
275 wdt->adev = adev;
276 wdt->wdd.info = &wdt_info;
277 wdt->wdd.ops = &wdt_ops;
278 wdt->wdd.parent = &adev->dev;
279
280 spin_lock_init(&wdt->lock);
281 watchdog_set_nowayout(&wdt->wdd, nowayout);
282 watchdog_set_drvdata(&wdt->wdd, wdt);
283 watchdog_set_restart_priority(&wdt->wdd, 128);
284 watchdog_stop_on_unregister(&wdt->wdd);
285
286 /*
287 * If 'timeout-sec' devicetree property is specified, use that.
288 * Otherwise, use DEFAULT_TIMEOUT
289 */
290 wdt->wdd.timeout = DEFAULT_TIMEOUT;
291 watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
292 wdt_setload(&wdt->wdd, wdt->wdd.timeout);
293
294 /*
295 * If HW is already running, enable/reset the wdt and set the running
296 * bit to tell the wdt subsystem
297 */
298 if (wdt_is_running(&wdt->wdd)) {
299 wdt_enable(&wdt->wdd);
300 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
301 }
302
303 watchdog_stop_on_reboot(&wdt->wdd);
304 ret = watchdog_register_device(&wdt->wdd);
305 if (ret)
306 goto err;
307 amba_set_drvdata(adev, wdt);
308
309 dev_info(&adev->dev, "registration successful\n");
310 return 0;
311
312err:
313 dev_err(&adev->dev, "Probe Failed!!!\n");
314 return ret;
315}
316
317static void sp805_wdt_remove(struct amba_device *adev)
318{
319 struct sp805_wdt *wdt = amba_get_drvdata(adev);
320
321 watchdog_unregister_device(&wdt->wdd);
322 watchdog_set_drvdata(&wdt->wdd, NULL);
323}
324
325static int __maybe_unused sp805_wdt_suspend(struct device *dev)
326{
327 struct sp805_wdt *wdt = dev_get_drvdata(dev);
328
329 if (watchdog_active(&wdt->wdd))
330 return wdt_disable(&wdt->wdd);
331
332 return 0;
333}
334
335static int __maybe_unused sp805_wdt_resume(struct device *dev)
336{
337 struct sp805_wdt *wdt = dev_get_drvdata(dev);
338
339 if (watchdog_active(&wdt->wdd))
340 return wdt_enable(&wdt->wdd);
341
342 return 0;
343}
344
345static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
346 sp805_wdt_resume);
347
348static const struct amba_id sp805_wdt_ids[] = {
349 {
350 .id = 0x00141805,
351 .mask = 0x00ffffff,
352 },
353 {
354 .id = 0x001bb824,
355 .mask = 0x00ffffff,
356 },
357 { 0, 0 },
358};
359
360MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
361
362static struct amba_driver sp805_wdt_driver = {
363 .drv = {
364 .name = MODULE_NAME,
365 .pm = &sp805_wdt_dev_pm_ops,
366 },
367 .id_table = sp805_wdt_ids,
368 .probe = sp805_wdt_probe,
369 .remove = sp805_wdt_remove,
370};
371
372module_amba_driver(sp805_wdt_driver);
373
374MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
375MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
376MODULE_LICENSE("GPL");
1/*
2 * drivers/char/watchdog/sp805-wdt.c
3 *
4 * Watchdog driver for ARM SP805 watchdog module
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Viresh Kumar <vireshk@kernel.org>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2 or later. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/device.h>
15#include <linux/resource.h>
16#include <linux/amba/bus.h>
17#include <linux/bitops.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/kernel.h>
22#include <linux/math64.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/pm.h>
26#include <linux/slab.h>
27#include <linux/spinlock.h>
28#include <linux/types.h>
29#include <linux/watchdog.h>
30
31/* default timeout in seconds */
32#define DEFAULT_TIMEOUT 60
33
34#define MODULE_NAME "sp805-wdt"
35
36/* watchdog register offsets and masks */
37#define WDTLOAD 0x000
38 #define LOAD_MIN 0x00000001
39 #define LOAD_MAX 0xFFFFFFFF
40#define WDTVALUE 0x004
41#define WDTCONTROL 0x008
42 /* control register masks */
43 #define INT_ENABLE (1 << 0)
44 #define RESET_ENABLE (1 << 1)
45#define WDTINTCLR 0x00C
46#define WDTRIS 0x010
47#define WDTMIS 0x014
48 #define INT_MASK (1 << 0)
49#define WDTLOCK 0xC00
50 #define UNLOCK 0x1ACCE551
51 #define LOCK 0x00000001
52
53/**
54 * struct sp805_wdt: sp805 wdt device structure
55 * @wdd: instance of struct watchdog_device
56 * @lock: spin lock protecting dev structure and io access
57 * @base: base address of wdt
58 * @clk: clock structure of wdt
59 * @adev: amba device structure of wdt
60 * @status: current status of wdt
61 * @load_val: load value to be set for current timeout
62 */
63struct sp805_wdt {
64 struct watchdog_device wdd;
65 spinlock_t lock;
66 void __iomem *base;
67 struct clk *clk;
68 struct amba_device *adev;
69 unsigned int load_val;
70};
71
72static bool nowayout = WATCHDOG_NOWAYOUT;
73module_param(nowayout, bool, 0);
74MODULE_PARM_DESC(nowayout,
75 "Set to 1 to keep watchdog running after device release");
76
77/* This routine finds load value that will reset system in required timout */
78static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
79{
80 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
81 u64 load, rate;
82
83 rate = clk_get_rate(wdt->clk);
84
85 /*
86 * sp805 runs counter with given value twice, after the end of first
87 * counter it gives an interrupt and then starts counter again. If
88 * interrupt already occurred then it resets the system. This is why
89 * load is half of what should be required.
90 */
91 load = div_u64(rate, 2) * timeout - 1;
92
93 load = (load > LOAD_MAX) ? LOAD_MAX : load;
94 load = (load < LOAD_MIN) ? LOAD_MIN : load;
95
96 spin_lock(&wdt->lock);
97 wdt->load_val = load;
98 /* roundup timeout to closest positive integer value */
99 wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
100 spin_unlock(&wdt->lock);
101
102 return 0;
103}
104
105/* returns number of seconds left for reset to occur */
106static unsigned int wdt_timeleft(struct watchdog_device *wdd)
107{
108 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
109 u64 load, rate;
110
111 rate = clk_get_rate(wdt->clk);
112
113 spin_lock(&wdt->lock);
114 load = readl_relaxed(wdt->base + WDTVALUE);
115
116 /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
117 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
118 load += wdt->load_val + 1;
119 spin_unlock(&wdt->lock);
120
121 return div_u64(load, rate);
122}
123
124static int wdt_config(struct watchdog_device *wdd, bool ping)
125{
126 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
127 int ret;
128
129 if (!ping) {
130
131 ret = clk_prepare_enable(wdt->clk);
132 if (ret) {
133 dev_err(&wdt->adev->dev, "clock enable fail");
134 return ret;
135 }
136 }
137
138 spin_lock(&wdt->lock);
139
140 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
141 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
142 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
143
144 if (!ping)
145 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
146 WDTCONTROL);
147
148 writel_relaxed(LOCK, wdt->base + WDTLOCK);
149
150 /* Flush posted writes. */
151 readl_relaxed(wdt->base + WDTLOCK);
152 spin_unlock(&wdt->lock);
153
154 return 0;
155}
156
157static int wdt_ping(struct watchdog_device *wdd)
158{
159 return wdt_config(wdd, true);
160}
161
162/* enables watchdog timers reset */
163static int wdt_enable(struct watchdog_device *wdd)
164{
165 return wdt_config(wdd, false);
166}
167
168/* disables watchdog timers reset */
169static int wdt_disable(struct watchdog_device *wdd)
170{
171 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
172
173 spin_lock(&wdt->lock);
174
175 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
176 writel_relaxed(0, wdt->base + WDTCONTROL);
177 writel_relaxed(LOCK, wdt->base + WDTLOCK);
178
179 /* Flush posted writes. */
180 readl_relaxed(wdt->base + WDTLOCK);
181 spin_unlock(&wdt->lock);
182
183 clk_disable_unprepare(wdt->clk);
184
185 return 0;
186}
187
188static const struct watchdog_info wdt_info = {
189 .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
190 .identity = MODULE_NAME,
191};
192
193static const struct watchdog_ops wdt_ops = {
194 .owner = THIS_MODULE,
195 .start = wdt_enable,
196 .stop = wdt_disable,
197 .ping = wdt_ping,
198 .set_timeout = wdt_setload,
199 .get_timeleft = wdt_timeleft,
200};
201
202static int
203sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
204{
205 struct sp805_wdt *wdt;
206 int ret = 0;
207
208 wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
209 if (!wdt) {
210 ret = -ENOMEM;
211 goto err;
212 }
213
214 wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
215 if (IS_ERR(wdt->base))
216 return PTR_ERR(wdt->base);
217
218 wdt->clk = devm_clk_get(&adev->dev, NULL);
219 if (IS_ERR(wdt->clk)) {
220 dev_warn(&adev->dev, "Clock not found\n");
221 ret = PTR_ERR(wdt->clk);
222 goto err;
223 }
224
225 wdt->adev = adev;
226 wdt->wdd.info = &wdt_info;
227 wdt->wdd.ops = &wdt_ops;
228 wdt->wdd.parent = &adev->dev;
229
230 spin_lock_init(&wdt->lock);
231 watchdog_set_nowayout(&wdt->wdd, nowayout);
232 watchdog_set_drvdata(&wdt->wdd, wdt);
233 wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
234
235 ret = watchdog_register_device(&wdt->wdd);
236 if (ret) {
237 dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
238 ret);
239 goto err;
240 }
241 amba_set_drvdata(adev, wdt);
242
243 dev_info(&adev->dev, "registration successful\n");
244 return 0;
245
246err:
247 dev_err(&adev->dev, "Probe Failed!!!\n");
248 return ret;
249}
250
251static int sp805_wdt_remove(struct amba_device *adev)
252{
253 struct sp805_wdt *wdt = amba_get_drvdata(adev);
254
255 watchdog_unregister_device(&wdt->wdd);
256 watchdog_set_drvdata(&wdt->wdd, NULL);
257
258 return 0;
259}
260
261static int __maybe_unused sp805_wdt_suspend(struct device *dev)
262{
263 struct sp805_wdt *wdt = dev_get_drvdata(dev);
264
265 if (watchdog_active(&wdt->wdd))
266 return wdt_disable(&wdt->wdd);
267
268 return 0;
269}
270
271static int __maybe_unused sp805_wdt_resume(struct device *dev)
272{
273 struct sp805_wdt *wdt = dev_get_drvdata(dev);
274
275 if (watchdog_active(&wdt->wdd))
276 return wdt_enable(&wdt->wdd);
277
278 return 0;
279}
280
281static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
282 sp805_wdt_resume);
283
284static const struct amba_id sp805_wdt_ids[] = {
285 {
286 .id = 0x00141805,
287 .mask = 0x00ffffff,
288 },
289 { 0, 0 },
290};
291
292MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
293
294static struct amba_driver sp805_wdt_driver = {
295 .drv = {
296 .name = MODULE_NAME,
297 .pm = &sp805_wdt_dev_pm_ops,
298 },
299 .id_table = sp805_wdt_ids,
300 .probe = sp805_wdt_probe,
301 .remove = sp805_wdt_remove,
302};
303
304module_amba_driver(sp805_wdt_driver);
305
306MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
307MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
308MODULE_LICENSE("GPL");