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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * intel TCO Watchdog Driver
4 *
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6 *
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
10 *
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
37 */
38
39/*
40 * Includes, defines, variables, module parameters, ...
41 */
42
43/* Module and version information */
44#define DRV_NAME "iTCO_wdt"
45#define DRV_VERSION "1.11"
46
47/* Includes */
48#include <linux/acpi.h> /* For ACPI support */
49#include <linux/bits.h> /* For BIT() */
50#include <linux/module.h> /* For module specific items */
51#include <linux/moduleparam.h> /* For new moduleparam's */
52#include <linux/types.h> /* For standard types (like size_t) */
53#include <linux/errno.h> /* For the -ENODEV/... values */
54#include <linux/kernel.h> /* For printk/panic/... */
55#include <linux/watchdog.h> /* For the watchdog specific items */
56#include <linux/init.h> /* For __init/__exit/... */
57#include <linux/fs.h> /* For file operations */
58#include <linux/platform_device.h> /* For platform_driver framework */
59#include <linux/pci.h> /* For pci functions */
60#include <linux/ioport.h> /* For io-port access */
61#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
62#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
63#include <linux/io.h> /* For inb/outb/... */
64#include <linux/platform_data/itco_wdt.h>
65#include <linux/mfd/intel_pmc_bxt.h>
66
67#include "iTCO_vendor.h"
68
69/* Address definitions for the TCO */
70/* TCO base address */
71#define TCOBASE(p) ((p)->tco_res->start)
72/* SMI Control and Enable Register */
73#define SMI_EN(p) ((p)->smi_res->start)
74
75#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
76#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
84
85/*
86 * NMI_NOW is bit 8 of TCO1_CNT register
87 * Read/Write
88 * This bit is implemented as RW but has no effect on HW.
89 */
90#define NMI_NOW BIT(8)
91
92/* internal variables */
93struct iTCO_wdt_private {
94 struct watchdog_device wddev;
95
96 /* TCO version/generation */
97 unsigned int iTCO_version;
98 struct resource *tco_res;
99 struct resource *smi_res;
100 /*
101 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
102 * or memory-mapped PMC register bit 4 (TCO version 3).
103 */
104 unsigned long __iomem *gcs_pmc;
105 /* the lock for io operations */
106 spinlock_t io_lock;
107 /* the PCI-device */
108 struct pci_dev *pci_dev;
109 /* whether or not the watchdog has been suspended */
110 bool suspended;
111 /* no reboot API private data */
112 void *no_reboot_priv;
113 /* no reboot update function pointer */
114 int (*update_no_reboot_bit)(void *p, bool set);
115};
116
117/* module parameters */
118#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
119static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
120module_param(heartbeat, int, 0);
121MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
122 "5..76 (TCO v1) or 3..614 (TCO v2), default="
123 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
124
125static bool nowayout = WATCHDOG_NOWAYOUT;
126module_param(nowayout, bool, 0);
127MODULE_PARM_DESC(nowayout,
128 "Watchdog cannot be stopped once started (default="
129 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
130
131static int turn_SMI_watchdog_clear_off = 1;
132module_param(turn_SMI_watchdog_clear_off, int, 0);
133MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
134 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
135
136/*
137 * Some TCO specific functions
138 */
139
140/*
141 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
142 * every 0.6 seconds. v3's internal timer is stored as seconds (some
143 * datasheets incorrectly state 0.6 seconds).
144 */
145static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
146 int secs)
147{
148 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
149}
150
151static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
152 int ticks)
153{
154 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
155}
156
157static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
158{
159 u32 enable_bit;
160
161 switch (p->iTCO_version) {
162 case 5:
163 case 3:
164 enable_bit = 0x00000010;
165 break;
166 case 2:
167 enable_bit = 0x00000020;
168 break;
169 case 4:
170 case 1:
171 default:
172 enable_bit = 0x00000002;
173 break;
174 }
175
176 return enable_bit;
177}
178
179static int update_no_reboot_bit_def(void *priv, bool set)
180{
181 return 0;
182}
183
184static int update_no_reboot_bit_pci(void *priv, bool set)
185{
186 struct iTCO_wdt_private *p = priv;
187 u32 val32 = 0, newval32 = 0;
188
189 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
190 if (set)
191 val32 |= no_reboot_bit(p);
192 else
193 val32 &= ~no_reboot_bit(p);
194 pci_write_config_dword(p->pci_dev, 0xd4, val32);
195 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
196
197 /* make sure the update is successful */
198 if (val32 != newval32)
199 return -EIO;
200
201 return 0;
202}
203
204static int update_no_reboot_bit_mem(void *priv, bool set)
205{
206 struct iTCO_wdt_private *p = priv;
207 u32 val32 = 0, newval32 = 0;
208
209 val32 = readl(p->gcs_pmc);
210 if (set)
211 val32 |= no_reboot_bit(p);
212 else
213 val32 &= ~no_reboot_bit(p);
214 writel(val32, p->gcs_pmc);
215 newval32 = readl(p->gcs_pmc);
216
217 /* make sure the update is successful */
218 if (val32 != newval32)
219 return -EIO;
220
221 return 0;
222}
223
224static int update_no_reboot_bit_cnt(void *priv, bool set)
225{
226 struct iTCO_wdt_private *p = priv;
227 u16 val, newval;
228
229 /*
230 * writing back 1b1 to NMI_NOW of TCO1_CNT register
231 * causes NMI_NOW bit inversion what consequently does
232 * not allow to perform the register's value comparison
233 * properly.
234 *
235 * NMI_NOW bit masking for TCO1_CNT register values
236 * helps to avoid possible NMI_NOW bit inversions on
237 * following write operation.
238 */
239 val = inw(TCO1_CNT(p)) & ~NMI_NOW;
240 if (set)
241 val |= BIT(0);
242 else
243 val &= ~BIT(0);
244 outw(val, TCO1_CNT(p));
245 newval = inw(TCO1_CNT(p)) & ~NMI_NOW;
246
247 /* make sure the update is successful */
248 return val != newval ? -EIO : 0;
249}
250
251static int update_no_reboot_bit_pmc(void *priv, bool set)
252{
253 struct intel_pmc_dev *pmc = priv;
254 u32 bits = PMC_CFG_NO_REBOOT_EN;
255 u32 value = set ? bits : 0;
256
257 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
258}
259
260static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
261 struct platform_device *pdev,
262 struct itco_wdt_platform_data *pdata)
263{
264 if (pdata->no_reboot_use_pmc) {
265 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
266
267 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
268 p->no_reboot_priv = pmc;
269 return;
270 }
271
272 if (p->iTCO_version >= 6)
273 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
274 else if (p->iTCO_version >= 2)
275 p->update_no_reboot_bit = update_no_reboot_bit_mem;
276 else if (p->iTCO_version == 1)
277 p->update_no_reboot_bit = update_no_reboot_bit_pci;
278 else
279 p->update_no_reboot_bit = update_no_reboot_bit_def;
280
281 p->no_reboot_priv = p;
282}
283
284static int iTCO_wdt_start(struct watchdog_device *wd_dev)
285{
286 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
287 unsigned int val;
288
289 spin_lock(&p->io_lock);
290
291 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
292
293 /* disable chipset's NO_REBOOT bit */
294 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
295 spin_unlock(&p->io_lock);
296 dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
297 return -EIO;
298 }
299
300 /* Force the timer to its reload value by writing to the TCO_RLD
301 register */
302 if (p->iTCO_version >= 2)
303 outw(0x01, TCO_RLD(p));
304 else if (p->iTCO_version == 1)
305 outb(0x01, TCO_RLD(p));
306
307 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
308 val = inw(TCO1_CNT(p));
309 val &= 0xf7ff;
310 outw(val, TCO1_CNT(p));
311 val = inw(TCO1_CNT(p));
312 spin_unlock(&p->io_lock);
313
314 if (val & 0x0800)
315 return -1;
316 return 0;
317}
318
319static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
320{
321 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
322 unsigned int val;
323
324 spin_lock(&p->io_lock);
325
326 iTCO_vendor_pre_stop(p->smi_res);
327
328 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
329 val = inw(TCO1_CNT(p));
330 val |= 0x0800;
331 outw(val, TCO1_CNT(p));
332 val = inw(TCO1_CNT(p));
333
334 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
335 p->update_no_reboot_bit(p->no_reboot_priv, true);
336
337 spin_unlock(&p->io_lock);
338
339 if ((val & 0x0800) == 0)
340 return -1;
341 return 0;
342}
343
344static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
345{
346 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
347
348 spin_lock(&p->io_lock);
349
350 /* Reload the timer by writing to the TCO Timer Counter register */
351 if (p->iTCO_version >= 2) {
352 outw(0x01, TCO_RLD(p));
353 } else if (p->iTCO_version == 1) {
354 /* Reset the timeout status bit so that the timer
355 * needs to count down twice again before rebooting */
356 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
357
358 outb(0x01, TCO_RLD(p));
359 }
360
361 spin_unlock(&p->io_lock);
362 return 0;
363}
364
365static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
366{
367 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
368 unsigned int val16;
369 unsigned char val8;
370 unsigned int tmrval;
371
372 tmrval = seconds_to_ticks(p, t);
373
374 /* For TCO v1 the timer counts down twice before rebooting */
375 if (p->iTCO_version == 1)
376 tmrval /= 2;
377
378 /* from the specs: */
379 /* "Values of 0h-3h are ignored and should not be attempted" */
380 if (tmrval < 0x04)
381 return -EINVAL;
382 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
383 (p->iTCO_version == 1 && tmrval > 0x03f))
384 return -EINVAL;
385
386 /* Write new heartbeat to watchdog */
387 if (p->iTCO_version >= 2) {
388 spin_lock(&p->io_lock);
389 val16 = inw(TCOv2_TMR(p));
390 val16 &= 0xfc00;
391 val16 |= tmrval;
392 outw(val16, TCOv2_TMR(p));
393 val16 = inw(TCOv2_TMR(p));
394 spin_unlock(&p->io_lock);
395
396 if ((val16 & 0x3ff) != tmrval)
397 return -EINVAL;
398 } else if (p->iTCO_version == 1) {
399 spin_lock(&p->io_lock);
400 val8 = inb(TCOv1_TMR(p));
401 val8 &= 0xc0;
402 val8 |= (tmrval & 0xff);
403 outb(val8, TCOv1_TMR(p));
404 val8 = inb(TCOv1_TMR(p));
405 spin_unlock(&p->io_lock);
406
407 if ((val8 & 0x3f) != tmrval)
408 return -EINVAL;
409 }
410
411 wd_dev->timeout = t;
412 return 0;
413}
414
415static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
416{
417 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
418 unsigned int val16;
419 unsigned char val8;
420 unsigned int time_left = 0;
421
422 /* read the TCO Timer */
423 if (p->iTCO_version >= 2) {
424 spin_lock(&p->io_lock);
425 val16 = inw(TCO_RLD(p));
426 val16 &= 0x3ff;
427 spin_unlock(&p->io_lock);
428
429 time_left = ticks_to_seconds(p, val16);
430 } else if (p->iTCO_version == 1) {
431 spin_lock(&p->io_lock);
432 val8 = inb(TCO_RLD(p));
433 val8 &= 0x3f;
434 if (!(inw(TCO1_STS(p)) & 0x0008))
435 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
436 spin_unlock(&p->io_lock);
437
438 time_left = ticks_to_seconds(p, val8);
439 }
440 return time_left;
441}
442
443/* Returns true if the watchdog was running */
444static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
445{
446 u16 val;
447
448 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
449 val = inw(TCO1_CNT(p));
450 if (!(val & BIT(11))) {
451 set_bit(WDOG_HW_RUNNING, &p->wddev.status);
452 return true;
453 }
454 return false;
455}
456
457/*
458 * Kernel Interfaces
459 */
460
461static struct watchdog_info ident = {
462 .options = WDIOF_SETTIMEOUT |
463 WDIOF_KEEPALIVEPING |
464 WDIOF_MAGICCLOSE,
465 .identity = DRV_NAME,
466};
467
468static const struct watchdog_ops iTCO_wdt_ops = {
469 .owner = THIS_MODULE,
470 .start = iTCO_wdt_start,
471 .stop = iTCO_wdt_stop,
472 .ping = iTCO_wdt_ping,
473 .set_timeout = iTCO_wdt_set_timeout,
474 .get_timeleft = iTCO_wdt_get_timeleft,
475};
476
477/*
478 * Init & exit routines
479 */
480
481static int iTCO_wdt_probe(struct platform_device *pdev)
482{
483 struct device *dev = &pdev->dev;
484 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
485 struct iTCO_wdt_private *p;
486 unsigned long val32;
487 int ret;
488
489 if (!pdata)
490 return -ENODEV;
491
492 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
493 if (!p)
494 return -ENOMEM;
495
496 spin_lock_init(&p->io_lock);
497
498 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
499 if (!p->tco_res)
500 return -ENODEV;
501
502 p->iTCO_version = pdata->version;
503 p->pci_dev = to_pci_dev(dev->parent);
504
505 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
506 if (p->smi_res) {
507 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
508 if (!devm_request_region(dev, p->smi_res->start,
509 resource_size(p->smi_res),
510 pdev->name)) {
511 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
512 (u64)SMI_EN(p));
513 return -EBUSY;
514 }
515 } else if (iTCO_vendorsupport ||
516 turn_SMI_watchdog_clear_off >= p->iTCO_version) {
517 dev_err(dev, "SMI I/O resource is missing\n");
518 return -ENODEV;
519 }
520
521 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
522
523 /*
524 * Get the Memory-Mapped GCS or PMC register, we need it for the
525 * NO_REBOOT flag (TCO v2 and v3).
526 */
527 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
528 !pdata->no_reboot_use_pmc) {
529 p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
530 if (IS_ERR(p->gcs_pmc))
531 return PTR_ERR(p->gcs_pmc);
532 }
533
534 /* Check chipset's NO_REBOOT bit */
535 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
536 iTCO_vendor_check_noreboot_on()) {
537 dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
538 return -ENODEV; /* Cannot reset NO_REBOOT bit */
539 }
540
541 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
542 /*
543 * Bit 13: TCO_EN -> 0
544 * Disables TCO logic generating an SMI#
545 */
546 val32 = inl(SMI_EN(p));
547 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
548 outl(val32, SMI_EN(p));
549 }
550
551 if (!devm_request_region(dev, p->tco_res->start,
552 resource_size(p->tco_res),
553 pdev->name)) {
554 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
555 (u64)TCOBASE(p));
556 return -EBUSY;
557 }
558
559 dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
560 pdata->name, pdata->version, (u64)TCOBASE(p));
561
562 /* Clear out the (probably old) status */
563 switch (p->iTCO_version) {
564 case 6:
565 case 5:
566 case 4:
567 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
568 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
569 break;
570 case 3:
571 outl(0x20008, TCO1_STS(p));
572 break;
573 case 2:
574 case 1:
575 default:
576 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
577 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
578 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
579 break;
580 }
581
582 ident.firmware_version = p->iTCO_version;
583 p->wddev.info = &ident;
584 p->wddev.ops = &iTCO_wdt_ops;
585 p->wddev.bootstatus = 0;
586 p->wddev.timeout = WATCHDOG_TIMEOUT;
587 watchdog_set_nowayout(&p->wddev, nowayout);
588 p->wddev.parent = dev;
589
590 watchdog_set_drvdata(&p->wddev, p);
591 platform_set_drvdata(pdev, p);
592
593 if (!iTCO_wdt_set_running(p)) {
594 /*
595 * If the watchdog was not running set NO_REBOOT now to
596 * prevent later reboots.
597 */
598 p->update_no_reboot_bit(p->no_reboot_priv, true);
599 }
600
601 /* Check that the heartbeat value is within it's range;
602 if not reset to the default */
603 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
604 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
605 dev_info(dev, "timeout value out of range, using %d\n",
606 WATCHDOG_TIMEOUT);
607 }
608
609 watchdog_stop_on_reboot(&p->wddev);
610 watchdog_stop_on_unregister(&p->wddev);
611 ret = devm_watchdog_register_device(dev, &p->wddev);
612 if (ret != 0)
613 return ret;
614
615 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
616 heartbeat, nowayout);
617
618 return 0;
619}
620
621/*
622 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
623 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
624 * watchdog is stopped by the platform firmware.
625 */
626
627#ifdef CONFIG_ACPI
628static inline bool __maybe_unused need_suspend(void)
629{
630 return acpi_target_system_state() == ACPI_STATE_S0;
631}
632#else
633static inline bool __maybe_unused need_suspend(void) { return true; }
634#endif
635
636static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
637{
638 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
639 int ret = 0;
640
641 p->suspended = false;
642 if (watchdog_active(&p->wddev) && need_suspend()) {
643 ret = iTCO_wdt_stop(&p->wddev);
644 if (!ret)
645 p->suspended = true;
646 }
647 return ret;
648}
649
650static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
651{
652 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
653
654 if (p->suspended)
655 iTCO_wdt_start(&p->wddev);
656
657 return 0;
658}
659
660static const struct dev_pm_ops iTCO_wdt_pm = {
661 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
662 iTCO_wdt_resume_noirq)
663};
664
665static struct platform_driver iTCO_wdt_driver = {
666 .probe = iTCO_wdt_probe,
667 .driver = {
668 .name = DRV_NAME,
669 .pm = &iTCO_wdt_pm,
670 },
671};
672
673module_platform_driver(iTCO_wdt_driver);
674
675MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
676MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
677MODULE_VERSION(DRV_VERSION);
678MODULE_LICENSE("GPL");
679MODULE_ALIAS("platform:" DRV_NAME);
1/*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 * document number TBD : Patsburg (PBG)
37 * document number TBD : DH89xxCC
38 * document number TBD : Panther Point
39 * document number TBD : Lynx Point
40 * document number TBD : Lynx Point-LP
41 */
42
43/*
44 * Includes, defines, variables, module parameters, ...
45 */
46
47#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
49/* Module and version information */
50#define DRV_NAME "iTCO_wdt"
51#define DRV_VERSION "1.11"
52
53/* Includes */
54#include <linux/acpi.h> /* For ACPI support */
55#include <linux/module.h> /* For module specific items */
56#include <linux/moduleparam.h> /* For new moduleparam's */
57#include <linux/types.h> /* For standard types (like size_t) */
58#include <linux/errno.h> /* For the -ENODEV/... values */
59#include <linux/kernel.h> /* For printk/panic/... */
60#include <linux/watchdog.h> /* For the watchdog specific items */
61#include <linux/init.h> /* For __init/__exit/... */
62#include <linux/fs.h> /* For file operations */
63#include <linux/platform_device.h> /* For platform_driver framework */
64#include <linux/pci.h> /* For pci functions */
65#include <linux/ioport.h> /* For io-port access */
66#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
67#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
68#include <linux/io.h> /* For inb/outb/... */
69#include <linux/platform_data/itco_wdt.h>
70
71#include "iTCO_vendor.h"
72
73/* Address definitions for the TCO */
74/* TCO base address */
75#define TCOBASE(p) ((p)->tco_res->start)
76/* SMI Control and Enable Register */
77#define SMI_EN(p) ((p)->smi_res->start)
78
79#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
80#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
81#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
82#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
83#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
84#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
85#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
86#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
87#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
88
89/* internal variables */
90struct iTCO_wdt_private {
91 struct watchdog_device wddev;
92
93 /* TCO version/generation */
94 unsigned int iTCO_version;
95 struct resource *tco_res;
96 struct resource *smi_res;
97 /*
98 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
99 * or memory-mapped PMC register bit 4 (TCO version 3).
100 */
101 struct resource *gcs_pmc_res;
102 unsigned long __iomem *gcs_pmc;
103 /* the lock for io operations */
104 spinlock_t io_lock;
105 /* the PCI-device */
106 struct pci_dev *pci_dev;
107 /* whether or not the watchdog has been suspended */
108 bool suspended;
109 /* no reboot API private data */
110 void *no_reboot_priv;
111 /* no reboot update function pointer */
112 int (*update_no_reboot_bit)(void *p, bool set);
113};
114
115/* module parameters */
116#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
117static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
118module_param(heartbeat, int, 0);
119MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
120 "5..76 (TCO v1) or 3..614 (TCO v2), default="
121 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
122
123static bool nowayout = WATCHDOG_NOWAYOUT;
124module_param(nowayout, bool, 0);
125MODULE_PARM_DESC(nowayout,
126 "Watchdog cannot be stopped once started (default="
127 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
128
129static int turn_SMI_watchdog_clear_off = 1;
130module_param(turn_SMI_watchdog_clear_off, int, 0);
131MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
132 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
133
134/*
135 * Some TCO specific functions
136 */
137
138/*
139 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
140 * every 0.6 seconds. v3's internal timer is stored as seconds (some
141 * datasheets incorrectly state 0.6 seconds).
142 */
143static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
144 int secs)
145{
146 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
147}
148
149static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
150 int ticks)
151{
152 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
153}
154
155static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
156{
157 u32 enable_bit;
158
159 switch (p->iTCO_version) {
160 case 5:
161 case 3:
162 enable_bit = 0x00000010;
163 break;
164 case 2:
165 enable_bit = 0x00000020;
166 break;
167 case 4:
168 case 1:
169 default:
170 enable_bit = 0x00000002;
171 break;
172 }
173
174 return enable_bit;
175}
176
177static int update_no_reboot_bit_def(void *priv, bool set)
178{
179 return 0;
180}
181
182static int update_no_reboot_bit_pci(void *priv, bool set)
183{
184 struct iTCO_wdt_private *p = priv;
185 u32 val32 = 0, newval32 = 0;
186
187 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
188 if (set)
189 val32 |= no_reboot_bit(p);
190 else
191 val32 &= ~no_reboot_bit(p);
192 pci_write_config_dword(p->pci_dev, 0xd4, val32);
193 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
194
195 /* make sure the update is successful */
196 if (val32 != newval32)
197 return -EIO;
198
199 return 0;
200}
201
202static int update_no_reboot_bit_mem(void *priv, bool set)
203{
204 struct iTCO_wdt_private *p = priv;
205 u32 val32 = 0, newval32 = 0;
206
207 val32 = readl(p->gcs_pmc);
208 if (set)
209 val32 |= no_reboot_bit(p);
210 else
211 val32 &= ~no_reboot_bit(p);
212 writel(val32, p->gcs_pmc);
213 newval32 = readl(p->gcs_pmc);
214
215 /* make sure the update is successful */
216 if (val32 != newval32)
217 return -EIO;
218
219 return 0;
220}
221
222static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
223 struct itco_wdt_platform_data *pdata)
224{
225 if (pdata->update_no_reboot_bit) {
226 p->update_no_reboot_bit = pdata->update_no_reboot_bit;
227 p->no_reboot_priv = pdata->no_reboot_priv;
228 return;
229 }
230
231 if (p->iTCO_version >= 2)
232 p->update_no_reboot_bit = update_no_reboot_bit_mem;
233 else if (p->iTCO_version == 1)
234 p->update_no_reboot_bit = update_no_reboot_bit_pci;
235 else
236 p->update_no_reboot_bit = update_no_reboot_bit_def;
237
238 p->no_reboot_priv = p;
239}
240
241static int iTCO_wdt_start(struct watchdog_device *wd_dev)
242{
243 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
244 unsigned int val;
245
246 spin_lock(&p->io_lock);
247
248 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
249
250 /* disable chipset's NO_REBOOT bit */
251 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
252 spin_unlock(&p->io_lock);
253 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
254 return -EIO;
255 }
256
257 /* Force the timer to its reload value by writing to the TCO_RLD
258 register */
259 if (p->iTCO_version >= 2)
260 outw(0x01, TCO_RLD(p));
261 else if (p->iTCO_version == 1)
262 outb(0x01, TCO_RLD(p));
263
264 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
265 val = inw(TCO1_CNT(p));
266 val &= 0xf7ff;
267 outw(val, TCO1_CNT(p));
268 val = inw(TCO1_CNT(p));
269 spin_unlock(&p->io_lock);
270
271 if (val & 0x0800)
272 return -1;
273 return 0;
274}
275
276static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
277{
278 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
279 unsigned int val;
280
281 spin_lock(&p->io_lock);
282
283 iTCO_vendor_pre_stop(p->smi_res);
284
285 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
286 val = inw(TCO1_CNT(p));
287 val |= 0x0800;
288 outw(val, TCO1_CNT(p));
289 val = inw(TCO1_CNT(p));
290
291 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
292 p->update_no_reboot_bit(p->no_reboot_priv, true);
293
294 spin_unlock(&p->io_lock);
295
296 if ((val & 0x0800) == 0)
297 return -1;
298 return 0;
299}
300
301static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
302{
303 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
304
305 spin_lock(&p->io_lock);
306
307 iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout);
308
309 /* Reload the timer by writing to the TCO Timer Counter register */
310 if (p->iTCO_version >= 2) {
311 outw(0x01, TCO_RLD(p));
312 } else if (p->iTCO_version == 1) {
313 /* Reset the timeout status bit so that the timer
314 * needs to count down twice again before rebooting */
315 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
316
317 outb(0x01, TCO_RLD(p));
318 }
319
320 spin_unlock(&p->io_lock);
321 return 0;
322}
323
324static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
325{
326 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
327 unsigned int val16;
328 unsigned char val8;
329 unsigned int tmrval;
330
331 tmrval = seconds_to_ticks(p, t);
332
333 /* For TCO v1 the timer counts down twice before rebooting */
334 if (p->iTCO_version == 1)
335 tmrval /= 2;
336
337 /* from the specs: */
338 /* "Values of 0h-3h are ignored and should not be attempted" */
339 if (tmrval < 0x04)
340 return -EINVAL;
341 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
342 (p->iTCO_version == 1 && tmrval > 0x03f))
343 return -EINVAL;
344
345 iTCO_vendor_pre_set_heartbeat(tmrval);
346
347 /* Write new heartbeat to watchdog */
348 if (p->iTCO_version >= 2) {
349 spin_lock(&p->io_lock);
350 val16 = inw(TCOv2_TMR(p));
351 val16 &= 0xfc00;
352 val16 |= tmrval;
353 outw(val16, TCOv2_TMR(p));
354 val16 = inw(TCOv2_TMR(p));
355 spin_unlock(&p->io_lock);
356
357 if ((val16 & 0x3ff) != tmrval)
358 return -EINVAL;
359 } else if (p->iTCO_version == 1) {
360 spin_lock(&p->io_lock);
361 val8 = inb(TCOv1_TMR(p));
362 val8 &= 0xc0;
363 val8 |= (tmrval & 0xff);
364 outb(val8, TCOv1_TMR(p));
365 val8 = inb(TCOv1_TMR(p));
366 spin_unlock(&p->io_lock);
367
368 if ((val8 & 0x3f) != tmrval)
369 return -EINVAL;
370 }
371
372 wd_dev->timeout = t;
373 return 0;
374}
375
376static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
377{
378 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
379 unsigned int val16;
380 unsigned char val8;
381 unsigned int time_left = 0;
382
383 /* read the TCO Timer */
384 if (p->iTCO_version >= 2) {
385 spin_lock(&p->io_lock);
386 val16 = inw(TCO_RLD(p));
387 val16 &= 0x3ff;
388 spin_unlock(&p->io_lock);
389
390 time_left = ticks_to_seconds(p, val16);
391 } else if (p->iTCO_version == 1) {
392 spin_lock(&p->io_lock);
393 val8 = inb(TCO_RLD(p));
394 val8 &= 0x3f;
395 if (!(inw(TCO1_STS(p)) & 0x0008))
396 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
397 spin_unlock(&p->io_lock);
398
399 time_left = ticks_to_seconds(p, val8);
400 }
401 return time_left;
402}
403
404/*
405 * Kernel Interfaces
406 */
407
408static const struct watchdog_info ident = {
409 .options = WDIOF_SETTIMEOUT |
410 WDIOF_KEEPALIVEPING |
411 WDIOF_MAGICCLOSE,
412 .firmware_version = 0,
413 .identity = DRV_NAME,
414};
415
416static const struct watchdog_ops iTCO_wdt_ops = {
417 .owner = THIS_MODULE,
418 .start = iTCO_wdt_start,
419 .stop = iTCO_wdt_stop,
420 .ping = iTCO_wdt_ping,
421 .set_timeout = iTCO_wdt_set_timeout,
422 .get_timeleft = iTCO_wdt_get_timeleft,
423};
424
425/*
426 * Init & exit routines
427 */
428
429static int iTCO_wdt_probe(struct platform_device *pdev)
430{
431 struct device *dev = &pdev->dev;
432 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
433 struct iTCO_wdt_private *p;
434 unsigned long val32;
435 int ret;
436
437 if (!pdata)
438 return -ENODEV;
439
440 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
441 if (!p)
442 return -ENOMEM;
443
444 spin_lock_init(&p->io_lock);
445
446 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
447 if (!p->tco_res)
448 return -ENODEV;
449
450 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
451 if (!p->smi_res)
452 return -ENODEV;
453
454 p->iTCO_version = pdata->version;
455 p->pci_dev = to_pci_dev(dev->parent);
456
457 iTCO_wdt_no_reboot_bit_setup(p, pdata);
458
459 /*
460 * Get the Memory-Mapped GCS or PMC register, we need it for the
461 * NO_REBOOT flag (TCO v2 and v3).
462 */
463 if (p->iTCO_version >= 2 && !pdata->update_no_reboot_bit) {
464 p->gcs_pmc_res = platform_get_resource(pdev,
465 IORESOURCE_MEM,
466 ICH_RES_MEM_GCS_PMC);
467 p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
468 if (IS_ERR(p->gcs_pmc))
469 return PTR_ERR(p->gcs_pmc);
470 }
471
472 /* Check chipset's NO_REBOOT bit */
473 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
474 iTCO_vendor_check_noreboot_on()) {
475 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
476 return -ENODEV; /* Cannot reset NO_REBOOT bit */
477 }
478
479 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
480 p->update_no_reboot_bit(p->no_reboot_priv, true);
481
482 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
483 if (!devm_request_region(dev, p->smi_res->start,
484 resource_size(p->smi_res),
485 pdev->name)) {
486 pr_err("I/O address 0x%04llx already in use, device disabled\n",
487 (u64)SMI_EN(p));
488 return -EBUSY;
489 }
490 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
491 /*
492 * Bit 13: TCO_EN -> 0
493 * Disables TCO logic generating an SMI#
494 */
495 val32 = inl(SMI_EN(p));
496 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
497 outl(val32, SMI_EN(p));
498 }
499
500 if (!devm_request_region(dev, p->tco_res->start,
501 resource_size(p->tco_res),
502 pdev->name)) {
503 pr_err("I/O address 0x%04llx already in use, device disabled\n",
504 (u64)TCOBASE(p));
505 return -EBUSY;
506 }
507
508 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
509 pdata->name, pdata->version, (u64)TCOBASE(p));
510
511 /* Clear out the (probably old) status */
512 switch (p->iTCO_version) {
513 case 5:
514 case 4:
515 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
516 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
517 break;
518 case 3:
519 outl(0x20008, TCO1_STS(p));
520 break;
521 case 2:
522 case 1:
523 default:
524 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
525 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
526 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
527 break;
528 }
529
530 p->wddev.info = &ident,
531 p->wddev.ops = &iTCO_wdt_ops,
532 p->wddev.bootstatus = 0;
533 p->wddev.timeout = WATCHDOG_TIMEOUT;
534 watchdog_set_nowayout(&p->wddev, nowayout);
535 p->wddev.parent = dev;
536
537 watchdog_set_drvdata(&p->wddev, p);
538 platform_set_drvdata(pdev, p);
539
540 /* Make sure the watchdog is not running */
541 iTCO_wdt_stop(&p->wddev);
542
543 /* Check that the heartbeat value is within it's range;
544 if not reset to the default */
545 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
546 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
547 pr_info("timeout value out of range, using %d\n",
548 WATCHDOG_TIMEOUT);
549 }
550
551 watchdog_stop_on_reboot(&p->wddev);
552 ret = devm_watchdog_register_device(dev, &p->wddev);
553 if (ret != 0) {
554 pr_err("cannot register watchdog device (err=%d)\n", ret);
555 return ret;
556 }
557
558 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
559 heartbeat, nowayout);
560
561 return 0;
562}
563
564static int iTCO_wdt_remove(struct platform_device *pdev)
565{
566 struct iTCO_wdt_private *p = platform_get_drvdata(pdev);
567
568 /* Stop the timer before we leave */
569 if (!nowayout)
570 iTCO_wdt_stop(&p->wddev);
571
572 return 0;
573}
574
575#ifdef CONFIG_PM_SLEEP
576/*
577 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
578 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
579 * watchdog is stopped by the platform firmware.
580 */
581
582#ifdef CONFIG_ACPI
583static inline bool need_suspend(void)
584{
585 return acpi_target_system_state() == ACPI_STATE_S0;
586}
587#else
588static inline bool need_suspend(void) { return true; }
589#endif
590
591static int iTCO_wdt_suspend_noirq(struct device *dev)
592{
593 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
594 int ret = 0;
595
596 p->suspended = false;
597 if (watchdog_active(&p->wddev) && need_suspend()) {
598 ret = iTCO_wdt_stop(&p->wddev);
599 if (!ret)
600 p->suspended = true;
601 }
602 return ret;
603}
604
605static int iTCO_wdt_resume_noirq(struct device *dev)
606{
607 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
608
609 if (p->suspended)
610 iTCO_wdt_start(&p->wddev);
611
612 return 0;
613}
614
615static const struct dev_pm_ops iTCO_wdt_pm = {
616 .suspend_noirq = iTCO_wdt_suspend_noirq,
617 .resume_noirq = iTCO_wdt_resume_noirq,
618};
619
620#define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
621#else
622#define ITCO_WDT_PM_OPS NULL
623#endif /* CONFIG_PM_SLEEP */
624
625static struct platform_driver iTCO_wdt_driver = {
626 .probe = iTCO_wdt_probe,
627 .remove = iTCO_wdt_remove,
628 .driver = {
629 .name = DRV_NAME,
630 .pm = ITCO_WDT_PM_OPS,
631 },
632};
633
634static int __init iTCO_wdt_init_module(void)
635{
636 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
637
638 return platform_driver_register(&iTCO_wdt_driver);
639}
640
641static void __exit iTCO_wdt_cleanup_module(void)
642{
643 platform_driver_unregister(&iTCO_wdt_driver);
644 pr_info("Watchdog Module Unloaded\n");
645}
646
647module_init(iTCO_wdt_init_module);
648module_exit(iTCO_wdt_cleanup_module);
649
650MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
651MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
652MODULE_VERSION(DRV_VERSION);
653MODULE_LICENSE("GPL");
654MODULE_ALIAS("platform:" DRV_NAME);