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1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static const char driver_name[] = "SyncLink GT";
91static const char tty_dev_prefix[] = "ttySLG";
92MODULE_DESCRIPTION("Device driver for Microgate SyncLink GT serial adapters");
93MODULE_LICENSE("GPL");
94#define MAX_DEVICES 32
95
96static const struct pci_device_id pci_table[] = {
97 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT_DEVICE_ID) },
98 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT2_DEVICE_ID) },
99 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT4_DEVICE_ID) },
100 { PCI_VDEVICE(MICROGATE, SYNCLINK_AC_DEVICE_ID) },
101 { 0 }, /* terminate list */
102};
103MODULE_DEVICE_TABLE(pci, pci_table);
104
105static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
106static void remove_one(struct pci_dev *dev);
107static struct pci_driver pci_driver = {
108 .name = "synclink_gt",
109 .id_table = pci_table,
110 .probe = init_one,
111 .remove = remove_one,
112};
113
114static bool pci_registered;
115
116/*
117 * module configuration and status
118 */
119static struct slgt_info *slgt_device_list;
120static int slgt_device_count;
121
122static int ttymajor;
123static int debug_level;
124static int maxframe[MAX_DEVICES];
125
126module_param(ttymajor, int, 0);
127module_param(debug_level, int, 0);
128module_param_array(maxframe, int, NULL, 0);
129
130MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
131MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
132MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
133
134/*
135 * tty support and callbacks
136 */
137static struct tty_driver *serial_driver;
138
139static void wait_until_sent(struct tty_struct *tty, int timeout);
140static void flush_buffer(struct tty_struct *tty);
141static void tx_release(struct tty_struct *tty);
142
143/*
144 * generic HDLC support
145 */
146#define dev_to_port(D) (dev_to_hdlc(D)->priv)
147
148
149/*
150 * device specific structures, macros and functions
151 */
152
153#define SLGT_MAX_PORTS 4
154#define SLGT_REG_SIZE 256
155
156/*
157 * conditional wait facility
158 */
159struct cond_wait {
160 struct cond_wait *next;
161 wait_queue_head_t q;
162 wait_queue_entry_t wait;
163 unsigned int data;
164};
165static void flush_cond_wait(struct cond_wait **head);
166
167/*
168 * DMA buffer descriptor and access macros
169 */
170struct slgt_desc
171{
172 __le16 count;
173 __le16 status;
174 __le32 pbuf; /* physical address of data buffer */
175 __le32 next; /* physical address of next descriptor */
176
177 /* driver book keeping */
178 char *buf; /* virtual address of data buffer */
179 unsigned int pdesc; /* physical address of this descriptor */
180 dma_addr_t buf_dma_addr;
181 unsigned short buf_count;
182};
183
184#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
185#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
186#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
187#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
188#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
189#define desc_count(a) (le16_to_cpu((a).count))
190#define desc_status(a) (le16_to_cpu((a).status))
191#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
192#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
193#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
194#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
195#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
196
197struct _input_signal_events {
198 int ri_up;
199 int ri_down;
200 int dsr_up;
201 int dsr_down;
202 int dcd_up;
203 int dcd_down;
204 int cts_up;
205 int cts_down;
206};
207
208/*
209 * device instance data structure
210 */
211struct slgt_info {
212 void *if_ptr; /* General purpose pointer (used by SPPP) */
213 struct tty_port port;
214
215 struct slgt_info *next_device; /* device list link */
216
217 char device_name[25];
218 struct pci_dev *pdev;
219
220 int port_count; /* count of ports on adapter */
221 int adapter_num; /* adapter instance number */
222 int port_num; /* port instance number */
223
224 /* array of pointers to port contexts on this adapter */
225 struct slgt_info *port_array[SLGT_MAX_PORTS];
226
227 int line; /* tty line instance number */
228
229 struct mgsl_icount icount;
230
231 int timeout;
232 int x_char; /* xon/xoff character */
233 unsigned int read_status_mask;
234 unsigned int ignore_status_mask;
235
236 wait_queue_head_t status_event_wait_q;
237 wait_queue_head_t event_wait_q;
238 struct timer_list tx_timer;
239 struct timer_list rx_timer;
240
241 unsigned int gpio_present;
242 struct cond_wait *gpio_wait_q;
243
244 spinlock_t lock; /* spinlock for synchronizing with ISR */
245
246 struct work_struct task;
247 u32 pending_bh;
248 bool bh_requested;
249 bool bh_running;
250
251 int isr_overflow;
252 bool irq_requested; /* true if IRQ requested */
253 bool irq_occurred; /* for diagnostics use */
254
255 /* device configuration */
256
257 unsigned int bus_type;
258 unsigned int irq_level;
259 unsigned long irq_flags;
260
261 unsigned char __iomem * reg_addr; /* memory mapped registers address */
262 u32 phys_reg_addr;
263 bool reg_addr_requested;
264
265 MGSL_PARAMS params; /* communications parameters */
266 u32 idle_mode;
267 u32 max_frame_size; /* as set by device config */
268
269 unsigned int rbuf_fill_level;
270 unsigned int rx_pio;
271 unsigned int if_mode;
272 unsigned int base_clock;
273 unsigned int xsync;
274 unsigned int xctrl;
275
276 /* device status */
277
278 bool rx_enabled;
279 bool rx_restart;
280
281 bool tx_enabled;
282 bool tx_active;
283
284 unsigned char signals; /* serial signal states */
285 int init_error; /* initialization error */
286
287 unsigned char *tx_buf;
288 int tx_count;
289
290 bool drop_rts_on_tx_done;
291 struct _input_signal_events input_signal_events;
292
293 int dcd_chkcount; /* check counts to prevent */
294 int cts_chkcount; /* too many IRQs if a signal */
295 int dsr_chkcount; /* is floating */
296 int ri_chkcount;
297
298 char *bufs; /* virtual address of DMA buffer lists */
299 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
300
301 unsigned int rbuf_count;
302 struct slgt_desc *rbufs;
303 unsigned int rbuf_current;
304 unsigned int rbuf_index;
305 unsigned int rbuf_fill_index;
306 unsigned short rbuf_fill_count;
307
308 unsigned int tbuf_count;
309 struct slgt_desc *tbufs;
310 unsigned int tbuf_current;
311 unsigned int tbuf_start;
312
313 unsigned char *tmp_rbuf;
314 unsigned int tmp_rbuf_count;
315
316 /* SPPP/Cisco HDLC device parts */
317
318 int netcount;
319 spinlock_t netlock;
320#if SYNCLINK_GENERIC_HDLC
321 struct net_device *netdev;
322#endif
323
324};
325
326static const MGSL_PARAMS default_params = {
327 .mode = MGSL_MODE_HDLC,
328 .loopback = 0,
329 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
330 .encoding = HDLC_ENCODING_NRZI_SPACE,
331 .clock_speed = 0,
332 .addr_filter = 0xff,
333 .crc_type = HDLC_CRC_16_CCITT,
334 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
335 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
336 .data_rate = 9600,
337 .data_bits = 8,
338 .stop_bits = 1,
339 .parity = ASYNC_PARITY_NONE
340};
341
342
343#define BH_RECEIVE 1
344#define BH_TRANSMIT 2
345#define BH_STATUS 4
346#define IO_PIN_SHUTDOWN_LIMIT 100
347
348#define DMABUFSIZE 256
349#define DESC_LIST_SIZE 4096
350
351#define MASK_PARITY BIT1
352#define MASK_FRAMING BIT0
353#define MASK_BREAK BIT14
354#define MASK_OVERRUN BIT4
355
356#define GSR 0x00 /* global status */
357#define JCR 0x04 /* JTAG control */
358#define IODR 0x08 /* GPIO direction */
359#define IOER 0x0c /* GPIO interrupt enable */
360#define IOVR 0x10 /* GPIO value */
361#define IOSR 0x14 /* GPIO interrupt status */
362#define TDR 0x80 /* tx data */
363#define RDR 0x80 /* rx data */
364#define TCR 0x82 /* tx control */
365#define TIR 0x84 /* tx idle */
366#define TPR 0x85 /* tx preamble */
367#define RCR 0x86 /* rx control */
368#define VCR 0x88 /* V.24 control */
369#define CCR 0x89 /* clock control */
370#define BDR 0x8a /* baud divisor */
371#define SCR 0x8c /* serial control */
372#define SSR 0x8e /* serial status */
373#define RDCSR 0x90 /* rx DMA control/status */
374#define TDCSR 0x94 /* tx DMA control/status */
375#define RDDAR 0x98 /* rx DMA descriptor address */
376#define TDDAR 0x9c /* tx DMA descriptor address */
377#define XSR 0x40 /* extended sync pattern */
378#define XCR 0x44 /* extended control */
379
380#define RXIDLE BIT14
381#define RXBREAK BIT14
382#define IRQ_TXDATA BIT13
383#define IRQ_TXIDLE BIT12
384#define IRQ_TXUNDER BIT11 /* HDLC */
385#define IRQ_RXDATA BIT10
386#define IRQ_RXIDLE BIT9 /* HDLC */
387#define IRQ_RXBREAK BIT9 /* async */
388#define IRQ_RXOVER BIT8
389#define IRQ_DSR BIT7
390#define IRQ_CTS BIT6
391#define IRQ_DCD BIT5
392#define IRQ_RI BIT4
393#define IRQ_ALL 0x3ff0
394#define IRQ_MASTER BIT0
395
396#define slgt_irq_on(info, mask) \
397 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
398#define slgt_irq_off(info, mask) \
399 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
400
401static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
402static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
403static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
404static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
405static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
406static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
407
408static void msc_set_vcr(struct slgt_info *info);
409
410static int startup(struct slgt_info *info);
411static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
412static void shutdown(struct slgt_info *info);
413static void program_hw(struct slgt_info *info);
414static void change_params(struct slgt_info *info);
415
416static int adapter_test(struct slgt_info *info);
417
418static void reset_port(struct slgt_info *info);
419static void async_mode(struct slgt_info *info);
420static void sync_mode(struct slgt_info *info);
421
422static void rx_stop(struct slgt_info *info);
423static void rx_start(struct slgt_info *info);
424static void reset_rbufs(struct slgt_info *info);
425static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
426static bool rx_get_frame(struct slgt_info *info);
427static bool rx_get_buf(struct slgt_info *info);
428
429static void tx_start(struct slgt_info *info);
430static void tx_stop(struct slgt_info *info);
431static void tx_set_idle(struct slgt_info *info);
432static unsigned int tbuf_bytes(struct slgt_info *info);
433static void reset_tbufs(struct slgt_info *info);
434static void tdma_reset(struct slgt_info *info);
435static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int count);
436
437static void get_gtsignals(struct slgt_info *info);
438static void set_gtsignals(struct slgt_info *info);
439static void set_rate(struct slgt_info *info, u32 data_rate);
440
441static void bh_transmit(struct slgt_info *info);
442static void isr_txeom(struct slgt_info *info, unsigned short status);
443
444static void tx_timeout(struct timer_list *t);
445static void rx_timeout(struct timer_list *t);
446
447/*
448 * ioctl handlers
449 */
450static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
451static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
452static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
453static int get_txidle(struct slgt_info *info, int __user *idle_mode);
454static int set_txidle(struct slgt_info *info, int idle_mode);
455static int tx_enable(struct slgt_info *info, int enable);
456static int tx_abort(struct slgt_info *info);
457static int rx_enable(struct slgt_info *info, int enable);
458static int modem_input_wait(struct slgt_info *info,int arg);
459static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
460static int get_interface(struct slgt_info *info, int __user *if_mode);
461static int set_interface(struct slgt_info *info, int if_mode);
462static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
463static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
465static int get_xsync(struct slgt_info *info, int __user *if_mode);
466static int set_xsync(struct slgt_info *info, int if_mode);
467static int get_xctrl(struct slgt_info *info, int __user *if_mode);
468static int set_xctrl(struct slgt_info *info, int if_mode);
469
470/*
471 * driver functions
472 */
473static void release_resources(struct slgt_info *info);
474
475/*
476 * DEBUG OUTPUT CODE
477 */
478#ifndef DBGINFO
479#define DBGINFO(fmt)
480#endif
481#ifndef DBGERR
482#define DBGERR(fmt)
483#endif
484#ifndef DBGBH
485#define DBGBH(fmt)
486#endif
487#ifndef DBGISR
488#define DBGISR(fmt)
489#endif
490
491#ifdef DBGDATA
492static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
493{
494 int i;
495 int linecount;
496 printk("%s %s data:\n",info->device_name, label);
497 while(count) {
498 linecount = (count > 16) ? 16 : count;
499 for(i=0; i < linecount; i++)
500 printk("%02X ",(unsigned char)data[i]);
501 for(;i<17;i++)
502 printk(" ");
503 for(i=0;i<linecount;i++) {
504 if (data[i]>=040 && data[i]<=0176)
505 printk("%c",data[i]);
506 else
507 printk(".");
508 }
509 printk("\n");
510 data += linecount;
511 count -= linecount;
512 }
513}
514#else
515#define DBGDATA(info, buf, size, label)
516#endif
517
518#ifdef DBGTBUF
519static void dump_tbufs(struct slgt_info *info)
520{
521 int i;
522 printk("tbuf_current=%d\n", info->tbuf_current);
523 for (i=0 ; i < info->tbuf_count ; i++) {
524 printk("%d: count=%04X status=%04X\n",
525 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
526 }
527}
528#else
529#define DBGTBUF(info)
530#endif
531
532#ifdef DBGRBUF
533static void dump_rbufs(struct slgt_info *info)
534{
535 int i;
536 printk("rbuf_current=%d\n", info->rbuf_current);
537 for (i=0 ; i < info->rbuf_count ; i++) {
538 printk("%d: count=%04X status=%04X\n",
539 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
540 }
541}
542#else
543#define DBGRBUF(info)
544#endif
545
546static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
547{
548#ifdef SANITY_CHECK
549 if (!info) {
550 printk("null struct slgt_info for (%s) in %s\n", devname, name);
551 return 1;
552 }
553#else
554 if (!info)
555 return 1;
556#endif
557 return 0;
558}
559
560/*
561 * line discipline callback wrappers
562 *
563 * The wrappers maintain line discipline references
564 * while calling into the line discipline.
565 *
566 * ldisc_receive_buf - pass receive data to line discipline
567 */
568static void ldisc_receive_buf(struct tty_struct *tty,
569 const __u8 *data, char *flags, int count)
570{
571 struct tty_ldisc *ld;
572 if (!tty)
573 return;
574 ld = tty_ldisc_ref(tty);
575 if (ld) {
576 if (ld->ops->receive_buf)
577 ld->ops->receive_buf(tty, data, flags, count);
578 tty_ldisc_deref(ld);
579 }
580}
581
582/* tty callbacks */
583
584static int open(struct tty_struct *tty, struct file *filp)
585{
586 struct slgt_info *info;
587 int retval, line;
588 unsigned long flags;
589
590 line = tty->index;
591 if (line >= slgt_device_count) {
592 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
593 return -ENODEV;
594 }
595
596 info = slgt_device_list;
597 while(info && info->line != line)
598 info = info->next_device;
599 if (sanity_check(info, tty->name, "open"))
600 return -ENODEV;
601 if (info->init_error) {
602 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
603 return -ENODEV;
604 }
605
606 tty->driver_data = info;
607 info->port.tty = tty;
608
609 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
610
611 mutex_lock(&info->port.mutex);
612
613 spin_lock_irqsave(&info->netlock, flags);
614 if (info->netcount) {
615 retval = -EBUSY;
616 spin_unlock_irqrestore(&info->netlock, flags);
617 mutex_unlock(&info->port.mutex);
618 goto cleanup;
619 }
620 info->port.count++;
621 spin_unlock_irqrestore(&info->netlock, flags);
622
623 if (info->port.count == 1) {
624 /* 1st open on this device, init hardware */
625 retval = startup(info);
626 if (retval < 0) {
627 mutex_unlock(&info->port.mutex);
628 goto cleanup;
629 }
630 }
631 mutex_unlock(&info->port.mutex);
632 retval = block_til_ready(tty, filp, info);
633 if (retval) {
634 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
635 goto cleanup;
636 }
637
638 retval = 0;
639
640cleanup:
641 if (retval) {
642 if (tty->count == 1)
643 info->port.tty = NULL; /* tty layer will release tty struct */
644 if(info->port.count)
645 info->port.count--;
646 }
647
648 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
649 return retval;
650}
651
652static void close(struct tty_struct *tty, struct file *filp)
653{
654 struct slgt_info *info = tty->driver_data;
655
656 if (sanity_check(info, tty->name, "close"))
657 return;
658 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
659
660 if (tty_port_close_start(&info->port, tty, filp) == 0)
661 goto cleanup;
662
663 mutex_lock(&info->port.mutex);
664 if (tty_port_initialized(&info->port))
665 wait_until_sent(tty, info->timeout);
666 flush_buffer(tty);
667 tty_ldisc_flush(tty);
668
669 shutdown(info);
670 mutex_unlock(&info->port.mutex);
671
672 tty_port_close_end(&info->port, tty);
673 info->port.tty = NULL;
674cleanup:
675 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
676}
677
678static void hangup(struct tty_struct *tty)
679{
680 struct slgt_info *info = tty->driver_data;
681 unsigned long flags;
682
683 if (sanity_check(info, tty->name, "hangup"))
684 return;
685 DBGINFO(("%s hangup\n", info->device_name));
686
687 flush_buffer(tty);
688
689 mutex_lock(&info->port.mutex);
690 shutdown(info);
691
692 spin_lock_irqsave(&info->port.lock, flags);
693 info->port.count = 0;
694 info->port.tty = NULL;
695 spin_unlock_irqrestore(&info->port.lock, flags);
696 tty_port_set_active(&info->port, false);
697 mutex_unlock(&info->port.mutex);
698
699 wake_up_interruptible(&info->port.open_wait);
700}
701
702static void set_termios(struct tty_struct *tty,
703 const struct ktermios *old_termios)
704{
705 struct slgt_info *info = tty->driver_data;
706 unsigned long flags;
707
708 DBGINFO(("%s set_termios\n", tty->driver->name));
709
710 change_params(info);
711
712 /* Handle transition to B0 status */
713 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
714 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
715 spin_lock_irqsave(&info->lock,flags);
716 set_gtsignals(info);
717 spin_unlock_irqrestore(&info->lock,flags);
718 }
719
720 /* Handle transition away from B0 status */
721 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
722 info->signals |= SerialSignal_DTR;
723 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
724 info->signals |= SerialSignal_RTS;
725 spin_lock_irqsave(&info->lock,flags);
726 set_gtsignals(info);
727 spin_unlock_irqrestore(&info->lock,flags);
728 }
729
730 /* Handle turning off CRTSCTS */
731 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
732 tty->hw_stopped = false;
733 tx_release(tty);
734 }
735}
736
737static void update_tx_timer(struct slgt_info *info)
738{
739 /*
740 * use worst case speed of 1200bps to calculate transmit timeout
741 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
742 */
743 if (info->params.mode == MGSL_MODE_HDLC) {
744 int timeout = (tbuf_bytes(info) * 7) + 1000;
745 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
746 }
747}
748
749static ssize_t write(struct tty_struct *tty, const u8 *buf, size_t count)
750{
751 int ret = 0;
752 struct slgt_info *info = tty->driver_data;
753 unsigned long flags;
754
755 if (sanity_check(info, tty->name, "write"))
756 return -EIO;
757
758 DBGINFO(("%s write count=%zu\n", info->device_name, count));
759
760 if (!info->tx_buf || (count > info->max_frame_size))
761 return -EIO;
762
763 if (!count || tty->flow.stopped || tty->hw_stopped)
764 return 0;
765
766 spin_lock_irqsave(&info->lock, flags);
767
768 if (info->tx_count) {
769 /* send accumulated data from send_char() */
770 if (!tx_load(info, info->tx_buf, info->tx_count))
771 goto cleanup;
772 info->tx_count = 0;
773 }
774
775 if (tx_load(info, buf, count))
776 ret = count;
777
778cleanup:
779 spin_unlock_irqrestore(&info->lock, flags);
780 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
781 return ret;
782}
783
784static int put_char(struct tty_struct *tty, u8 ch)
785{
786 struct slgt_info *info = tty->driver_data;
787 unsigned long flags;
788 int ret = 0;
789
790 if (sanity_check(info, tty->name, "put_char"))
791 return 0;
792 DBGINFO(("%s put_char(%u)\n", info->device_name, ch));
793 if (!info->tx_buf)
794 return 0;
795 spin_lock_irqsave(&info->lock,flags);
796 if (info->tx_count < info->max_frame_size) {
797 info->tx_buf[info->tx_count++] = ch;
798 ret = 1;
799 }
800 spin_unlock_irqrestore(&info->lock,flags);
801 return ret;
802}
803
804static void send_xchar(struct tty_struct *tty, char ch)
805{
806 struct slgt_info *info = tty->driver_data;
807 unsigned long flags;
808
809 if (sanity_check(info, tty->name, "send_xchar"))
810 return;
811 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
812 info->x_char = ch;
813 if (ch) {
814 spin_lock_irqsave(&info->lock,flags);
815 if (!info->tx_enabled)
816 tx_start(info);
817 spin_unlock_irqrestore(&info->lock,flags);
818 }
819}
820
821static void wait_until_sent(struct tty_struct *tty, int timeout)
822{
823 struct slgt_info *info = tty->driver_data;
824 unsigned long orig_jiffies, char_time;
825
826 if (!info )
827 return;
828 if (sanity_check(info, tty->name, "wait_until_sent"))
829 return;
830 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
831 if (!tty_port_initialized(&info->port))
832 goto exit;
833
834 orig_jiffies = jiffies;
835
836 /* Set check interval to 1/5 of estimated time to
837 * send a character, and make it at least 1. The check
838 * interval should also be less than the timeout.
839 * Note: use tight timings here to satisfy the NIST-PCTS.
840 */
841
842 if (info->params.data_rate) {
843 char_time = info->timeout/(32 * 5);
844 if (!char_time)
845 char_time++;
846 } else
847 char_time = 1;
848
849 if (timeout)
850 char_time = min_t(unsigned long, char_time, timeout);
851
852 while (info->tx_active) {
853 msleep_interruptible(jiffies_to_msecs(char_time));
854 if (signal_pending(current))
855 break;
856 if (timeout && time_after(jiffies, orig_jiffies + timeout))
857 break;
858 }
859exit:
860 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
861}
862
863static unsigned int write_room(struct tty_struct *tty)
864{
865 struct slgt_info *info = tty->driver_data;
866 unsigned int ret;
867
868 if (sanity_check(info, tty->name, "write_room"))
869 return 0;
870 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
871 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
872 return ret;
873}
874
875static void flush_chars(struct tty_struct *tty)
876{
877 struct slgt_info *info = tty->driver_data;
878 unsigned long flags;
879
880 if (sanity_check(info, tty->name, "flush_chars"))
881 return;
882 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
883
884 if (info->tx_count <= 0 || tty->flow.stopped ||
885 tty->hw_stopped || !info->tx_buf)
886 return;
887
888 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
889
890 spin_lock_irqsave(&info->lock,flags);
891 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
892 info->tx_count = 0;
893 spin_unlock_irqrestore(&info->lock,flags);
894}
895
896static void flush_buffer(struct tty_struct *tty)
897{
898 struct slgt_info *info = tty->driver_data;
899 unsigned long flags;
900
901 if (sanity_check(info, tty->name, "flush_buffer"))
902 return;
903 DBGINFO(("%s flush_buffer\n", info->device_name));
904
905 spin_lock_irqsave(&info->lock, flags);
906 info->tx_count = 0;
907 spin_unlock_irqrestore(&info->lock, flags);
908
909 tty_wakeup(tty);
910}
911
912/*
913 * throttle (stop) transmitter
914 */
915static void tx_hold(struct tty_struct *tty)
916{
917 struct slgt_info *info = tty->driver_data;
918 unsigned long flags;
919
920 if (sanity_check(info, tty->name, "tx_hold"))
921 return;
922 DBGINFO(("%s tx_hold\n", info->device_name));
923 spin_lock_irqsave(&info->lock,flags);
924 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
925 tx_stop(info);
926 spin_unlock_irqrestore(&info->lock,flags);
927}
928
929/*
930 * release (start) transmitter
931 */
932static void tx_release(struct tty_struct *tty)
933{
934 struct slgt_info *info = tty->driver_data;
935 unsigned long flags;
936
937 if (sanity_check(info, tty->name, "tx_release"))
938 return;
939 DBGINFO(("%s tx_release\n", info->device_name));
940 spin_lock_irqsave(&info->lock, flags);
941 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
942 info->tx_count = 0;
943 spin_unlock_irqrestore(&info->lock, flags);
944}
945
946/*
947 * Service an IOCTL request
948 *
949 * Arguments
950 *
951 * tty pointer to tty instance data
952 * cmd IOCTL command code
953 * arg command argument/context
954 *
955 * Return 0 if success, otherwise error code
956 */
957static int ioctl(struct tty_struct *tty,
958 unsigned int cmd, unsigned long arg)
959{
960 struct slgt_info *info = tty->driver_data;
961 void __user *argp = (void __user *)arg;
962 int ret;
963
964 if (sanity_check(info, tty->name, "ioctl"))
965 return -ENODEV;
966 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
967
968 if (cmd != TIOCMIWAIT) {
969 if (tty_io_error(tty))
970 return -EIO;
971 }
972
973 switch (cmd) {
974 case MGSL_IOCWAITEVENT:
975 return wait_mgsl_event(info, argp);
976 case TIOCMIWAIT:
977 return modem_input_wait(info,(int)arg);
978 case MGSL_IOCSGPIO:
979 return set_gpio(info, argp);
980 case MGSL_IOCGGPIO:
981 return get_gpio(info, argp);
982 case MGSL_IOCWAITGPIO:
983 return wait_gpio(info, argp);
984 case MGSL_IOCGXSYNC:
985 return get_xsync(info, argp);
986 case MGSL_IOCSXSYNC:
987 return set_xsync(info, (int)arg);
988 case MGSL_IOCGXCTRL:
989 return get_xctrl(info, argp);
990 case MGSL_IOCSXCTRL:
991 return set_xctrl(info, (int)arg);
992 }
993 mutex_lock(&info->port.mutex);
994 switch (cmd) {
995 case MGSL_IOCGPARAMS:
996 ret = get_params(info, argp);
997 break;
998 case MGSL_IOCSPARAMS:
999 ret = set_params(info, argp);
1000 break;
1001 case MGSL_IOCGTXIDLE:
1002 ret = get_txidle(info, argp);
1003 break;
1004 case MGSL_IOCSTXIDLE:
1005 ret = set_txidle(info, (int)arg);
1006 break;
1007 case MGSL_IOCTXENABLE:
1008 ret = tx_enable(info, (int)arg);
1009 break;
1010 case MGSL_IOCRXENABLE:
1011 ret = rx_enable(info, (int)arg);
1012 break;
1013 case MGSL_IOCTXABORT:
1014 ret = tx_abort(info);
1015 break;
1016 case MGSL_IOCGSTATS:
1017 ret = get_stats(info, argp);
1018 break;
1019 case MGSL_IOCGIF:
1020 ret = get_interface(info, argp);
1021 break;
1022 case MGSL_IOCSIF:
1023 ret = set_interface(info,(int)arg);
1024 break;
1025 default:
1026 ret = -ENOIOCTLCMD;
1027 }
1028 mutex_unlock(&info->port.mutex);
1029 return ret;
1030}
1031
1032static int get_icount(struct tty_struct *tty,
1033 struct serial_icounter_struct *icount)
1034
1035{
1036 struct slgt_info *info = tty->driver_data;
1037 struct mgsl_icount cnow; /* kernel counter temps */
1038 unsigned long flags;
1039
1040 spin_lock_irqsave(&info->lock,flags);
1041 cnow = info->icount;
1042 spin_unlock_irqrestore(&info->lock,flags);
1043
1044 icount->cts = cnow.cts;
1045 icount->dsr = cnow.dsr;
1046 icount->rng = cnow.rng;
1047 icount->dcd = cnow.dcd;
1048 icount->rx = cnow.rx;
1049 icount->tx = cnow.tx;
1050 icount->frame = cnow.frame;
1051 icount->overrun = cnow.overrun;
1052 icount->parity = cnow.parity;
1053 icount->brk = cnow.brk;
1054 icount->buf_overrun = cnow.buf_overrun;
1055
1056 return 0;
1057}
1058
1059/*
1060 * support for 32 bit ioctl calls on 64 bit systems
1061 */
1062#ifdef CONFIG_COMPAT
1063static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1064{
1065 struct MGSL_PARAMS32 tmp_params;
1066
1067 DBGINFO(("%s get_params32\n", info->device_name));
1068 memset(&tmp_params, 0, sizeof(tmp_params));
1069 tmp_params.mode = (compat_ulong_t)info->params.mode;
1070 tmp_params.loopback = info->params.loopback;
1071 tmp_params.flags = info->params.flags;
1072 tmp_params.encoding = info->params.encoding;
1073 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1074 tmp_params.addr_filter = info->params.addr_filter;
1075 tmp_params.crc_type = info->params.crc_type;
1076 tmp_params.preamble_length = info->params.preamble_length;
1077 tmp_params.preamble = info->params.preamble;
1078 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1079 tmp_params.data_bits = info->params.data_bits;
1080 tmp_params.stop_bits = info->params.stop_bits;
1081 tmp_params.parity = info->params.parity;
1082 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1083 return -EFAULT;
1084 return 0;
1085}
1086
1087static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1088{
1089 struct MGSL_PARAMS32 tmp_params;
1090 unsigned long flags;
1091
1092 DBGINFO(("%s set_params32\n", info->device_name));
1093 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1094 return -EFAULT;
1095
1096 spin_lock_irqsave(&info->lock, flags);
1097 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1098 info->base_clock = tmp_params.clock_speed;
1099 } else {
1100 info->params.mode = tmp_params.mode;
1101 info->params.loopback = tmp_params.loopback;
1102 info->params.flags = tmp_params.flags;
1103 info->params.encoding = tmp_params.encoding;
1104 info->params.clock_speed = tmp_params.clock_speed;
1105 info->params.addr_filter = tmp_params.addr_filter;
1106 info->params.crc_type = tmp_params.crc_type;
1107 info->params.preamble_length = tmp_params.preamble_length;
1108 info->params.preamble = tmp_params.preamble;
1109 info->params.data_rate = tmp_params.data_rate;
1110 info->params.data_bits = tmp_params.data_bits;
1111 info->params.stop_bits = tmp_params.stop_bits;
1112 info->params.parity = tmp_params.parity;
1113 }
1114 spin_unlock_irqrestore(&info->lock, flags);
1115
1116 program_hw(info);
1117
1118 return 0;
1119}
1120
1121static long slgt_compat_ioctl(struct tty_struct *tty,
1122 unsigned int cmd, unsigned long arg)
1123{
1124 struct slgt_info *info = tty->driver_data;
1125 int rc;
1126
1127 if (sanity_check(info, tty->name, "compat_ioctl"))
1128 return -ENODEV;
1129 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1130
1131 switch (cmd) {
1132 case MGSL_IOCSPARAMS32:
1133 rc = set_params32(info, compat_ptr(arg));
1134 break;
1135
1136 case MGSL_IOCGPARAMS32:
1137 rc = get_params32(info, compat_ptr(arg));
1138 break;
1139
1140 case MGSL_IOCGPARAMS:
1141 case MGSL_IOCSPARAMS:
1142 case MGSL_IOCGTXIDLE:
1143 case MGSL_IOCGSTATS:
1144 case MGSL_IOCWAITEVENT:
1145 case MGSL_IOCGIF:
1146 case MGSL_IOCSGPIO:
1147 case MGSL_IOCGGPIO:
1148 case MGSL_IOCWAITGPIO:
1149 case MGSL_IOCGXSYNC:
1150 case MGSL_IOCGXCTRL:
1151 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1152 break;
1153 default:
1154 rc = ioctl(tty, cmd, arg);
1155 }
1156 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1157 return rc;
1158}
1159#else
1160#define slgt_compat_ioctl NULL
1161#endif /* ifdef CONFIG_COMPAT */
1162
1163/*
1164 * proc fs support
1165 */
1166static inline void line_info(struct seq_file *m, struct slgt_info *info)
1167{
1168 char stat_buf[30];
1169 unsigned long flags;
1170
1171 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1172 info->device_name, info->phys_reg_addr,
1173 info->irq_level, info->max_frame_size);
1174
1175 /* output current serial signal states */
1176 spin_lock_irqsave(&info->lock,flags);
1177 get_gtsignals(info);
1178 spin_unlock_irqrestore(&info->lock,flags);
1179
1180 stat_buf[0] = 0;
1181 stat_buf[1] = 0;
1182 if (info->signals & SerialSignal_RTS)
1183 strcat(stat_buf, "|RTS");
1184 if (info->signals & SerialSignal_CTS)
1185 strcat(stat_buf, "|CTS");
1186 if (info->signals & SerialSignal_DTR)
1187 strcat(stat_buf, "|DTR");
1188 if (info->signals & SerialSignal_DSR)
1189 strcat(stat_buf, "|DSR");
1190 if (info->signals & SerialSignal_DCD)
1191 strcat(stat_buf, "|CD");
1192 if (info->signals & SerialSignal_RI)
1193 strcat(stat_buf, "|RI");
1194
1195 if (info->params.mode != MGSL_MODE_ASYNC) {
1196 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1197 info->icount.txok, info->icount.rxok);
1198 if (info->icount.txunder)
1199 seq_printf(m, " txunder:%d", info->icount.txunder);
1200 if (info->icount.txabort)
1201 seq_printf(m, " txabort:%d", info->icount.txabort);
1202 if (info->icount.rxshort)
1203 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1204 if (info->icount.rxlong)
1205 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1206 if (info->icount.rxover)
1207 seq_printf(m, " rxover:%d", info->icount.rxover);
1208 if (info->icount.rxcrc)
1209 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1210 } else {
1211 seq_printf(m, "\tASYNC tx:%d rx:%d",
1212 info->icount.tx, info->icount.rx);
1213 if (info->icount.frame)
1214 seq_printf(m, " fe:%d", info->icount.frame);
1215 if (info->icount.parity)
1216 seq_printf(m, " pe:%d", info->icount.parity);
1217 if (info->icount.brk)
1218 seq_printf(m, " brk:%d", info->icount.brk);
1219 if (info->icount.overrun)
1220 seq_printf(m, " oe:%d", info->icount.overrun);
1221 }
1222
1223 /* Append serial signal status to end */
1224 seq_printf(m, " %s\n", stat_buf+1);
1225
1226 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1227 info->tx_active,info->bh_requested,info->bh_running,
1228 info->pending_bh);
1229}
1230
1231/* Called to print information about devices
1232 */
1233static int synclink_gt_proc_show(struct seq_file *m, void *v)
1234{
1235 struct slgt_info *info;
1236
1237 seq_puts(m, "synclink_gt driver\n");
1238
1239 info = slgt_device_list;
1240 while( info ) {
1241 line_info(m, info);
1242 info = info->next_device;
1243 }
1244 return 0;
1245}
1246
1247/*
1248 * return count of bytes in transmit buffer
1249 */
1250static unsigned int chars_in_buffer(struct tty_struct *tty)
1251{
1252 struct slgt_info *info = tty->driver_data;
1253 unsigned int count;
1254 if (sanity_check(info, tty->name, "chars_in_buffer"))
1255 return 0;
1256 count = tbuf_bytes(info);
1257 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1258 return count;
1259}
1260
1261/*
1262 * signal remote device to throttle send data (our receive data)
1263 */
1264static void throttle(struct tty_struct * tty)
1265{
1266 struct slgt_info *info = tty->driver_data;
1267 unsigned long flags;
1268
1269 if (sanity_check(info, tty->name, "throttle"))
1270 return;
1271 DBGINFO(("%s throttle\n", info->device_name));
1272 if (I_IXOFF(tty))
1273 send_xchar(tty, STOP_CHAR(tty));
1274 if (C_CRTSCTS(tty)) {
1275 spin_lock_irqsave(&info->lock,flags);
1276 info->signals &= ~SerialSignal_RTS;
1277 set_gtsignals(info);
1278 spin_unlock_irqrestore(&info->lock,flags);
1279 }
1280}
1281
1282/*
1283 * signal remote device to stop throttling send data (our receive data)
1284 */
1285static void unthrottle(struct tty_struct * tty)
1286{
1287 struct slgt_info *info = tty->driver_data;
1288 unsigned long flags;
1289
1290 if (sanity_check(info, tty->name, "unthrottle"))
1291 return;
1292 DBGINFO(("%s unthrottle\n", info->device_name));
1293 if (I_IXOFF(tty)) {
1294 if (info->x_char)
1295 info->x_char = 0;
1296 else
1297 send_xchar(tty, START_CHAR(tty));
1298 }
1299 if (C_CRTSCTS(tty)) {
1300 spin_lock_irqsave(&info->lock,flags);
1301 info->signals |= SerialSignal_RTS;
1302 set_gtsignals(info);
1303 spin_unlock_irqrestore(&info->lock,flags);
1304 }
1305}
1306
1307/*
1308 * set or clear transmit break condition
1309 * break_state -1=set break condition, 0=clear
1310 */
1311static int set_break(struct tty_struct *tty, int break_state)
1312{
1313 struct slgt_info *info = tty->driver_data;
1314 unsigned short value;
1315 unsigned long flags;
1316
1317 if (sanity_check(info, tty->name, "set_break"))
1318 return -EINVAL;
1319 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1320
1321 spin_lock_irqsave(&info->lock,flags);
1322 value = rd_reg16(info, TCR);
1323 if (break_state == -1)
1324 value |= BIT6;
1325 else
1326 value &= ~BIT6;
1327 wr_reg16(info, TCR, value);
1328 spin_unlock_irqrestore(&info->lock,flags);
1329 return 0;
1330}
1331
1332#if SYNCLINK_GENERIC_HDLC
1333
1334/**
1335 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1336 * @dev: pointer to network device structure
1337 * @encoding: serial encoding setting
1338 * @parity: FCS setting
1339 *
1340 * Set encoding and frame check sequence (FCS) options.
1341 *
1342 * Return: 0 if success, otherwise error code
1343 */
1344static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1345 unsigned short parity)
1346{
1347 struct slgt_info *info = dev_to_port(dev);
1348 unsigned char new_encoding;
1349 unsigned short new_crctype;
1350
1351 /* return error if TTY interface open */
1352 if (info->port.count)
1353 return -EBUSY;
1354
1355 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1356
1357 switch (encoding)
1358 {
1359 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1360 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1361 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1362 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1363 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1364 default: return -EINVAL;
1365 }
1366
1367 switch (parity)
1368 {
1369 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1370 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1371 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1372 default: return -EINVAL;
1373 }
1374
1375 info->params.encoding = new_encoding;
1376 info->params.crc_type = new_crctype;
1377
1378 /* if network interface up, reprogram hardware */
1379 if (info->netcount)
1380 program_hw(info);
1381
1382 return 0;
1383}
1384
1385/**
1386 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1387 * @skb: socket buffer containing HDLC frame
1388 * @dev: pointer to network device structure
1389 */
1390static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1391 struct net_device *dev)
1392{
1393 struct slgt_info *info = dev_to_port(dev);
1394 unsigned long flags;
1395
1396 DBGINFO(("%s hdlc_xmit\n", dev->name));
1397
1398 if (!skb->len)
1399 return NETDEV_TX_OK;
1400
1401 /* stop sending until this frame completes */
1402 netif_stop_queue(dev);
1403
1404 /* update network statistics */
1405 dev->stats.tx_packets++;
1406 dev->stats.tx_bytes += skb->len;
1407
1408 /* save start time for transmit timeout detection */
1409 netif_trans_update(dev);
1410
1411 spin_lock_irqsave(&info->lock, flags);
1412 tx_load(info, skb->data, skb->len);
1413 spin_unlock_irqrestore(&info->lock, flags);
1414
1415 /* done with socket buffer, so free it */
1416 dev_kfree_skb(skb);
1417
1418 return NETDEV_TX_OK;
1419}
1420
1421/**
1422 * hdlcdev_open - called by network layer when interface enabled
1423 * @dev: pointer to network device structure
1424 *
1425 * Claim resources and initialize hardware.
1426 *
1427 * Return: 0 if success, otherwise error code
1428 */
1429static int hdlcdev_open(struct net_device *dev)
1430{
1431 struct slgt_info *info = dev_to_port(dev);
1432 int rc;
1433 unsigned long flags;
1434
1435 DBGINFO(("%s hdlcdev_open\n", dev->name));
1436
1437 /* arbitrate between network and tty opens */
1438 spin_lock_irqsave(&info->netlock, flags);
1439 if (info->port.count != 0 || info->netcount != 0) {
1440 DBGINFO(("%s hdlc_open busy\n", dev->name));
1441 spin_unlock_irqrestore(&info->netlock, flags);
1442 return -EBUSY;
1443 }
1444 info->netcount=1;
1445 spin_unlock_irqrestore(&info->netlock, flags);
1446
1447 /* claim resources and init adapter */
1448 if ((rc = startup(info)) != 0) {
1449 spin_lock_irqsave(&info->netlock, flags);
1450 info->netcount=0;
1451 spin_unlock_irqrestore(&info->netlock, flags);
1452 return rc;
1453 }
1454
1455 /* generic HDLC layer open processing */
1456 rc = hdlc_open(dev);
1457 if (rc) {
1458 shutdown(info);
1459 spin_lock_irqsave(&info->netlock, flags);
1460 info->netcount = 0;
1461 spin_unlock_irqrestore(&info->netlock, flags);
1462 return rc;
1463 }
1464
1465 /* assert RTS and DTR, apply hardware settings */
1466 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1467 program_hw(info);
1468
1469 /* enable network layer transmit */
1470 netif_trans_update(dev);
1471 netif_start_queue(dev);
1472
1473 /* inform generic HDLC layer of current DCD status */
1474 spin_lock_irqsave(&info->lock, flags);
1475 get_gtsignals(info);
1476 spin_unlock_irqrestore(&info->lock, flags);
1477 if (info->signals & SerialSignal_DCD)
1478 netif_carrier_on(dev);
1479 else
1480 netif_carrier_off(dev);
1481 return 0;
1482}
1483
1484/**
1485 * hdlcdev_close - called by network layer when interface is disabled
1486 * @dev: pointer to network device structure
1487 *
1488 * Shutdown hardware and release resources.
1489 *
1490 * Return: 0 if success, otherwise error code
1491 */
1492static int hdlcdev_close(struct net_device *dev)
1493{
1494 struct slgt_info *info = dev_to_port(dev);
1495 unsigned long flags;
1496
1497 DBGINFO(("%s hdlcdev_close\n", dev->name));
1498
1499 netif_stop_queue(dev);
1500
1501 /* shutdown adapter and release resources */
1502 shutdown(info);
1503
1504 hdlc_close(dev);
1505
1506 spin_lock_irqsave(&info->netlock, flags);
1507 info->netcount=0;
1508 spin_unlock_irqrestore(&info->netlock, flags);
1509
1510 return 0;
1511}
1512
1513/**
1514 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1515 * @dev: pointer to network device structure
1516 * @ifr: pointer to network interface request structure
1517 * @cmd: IOCTL command code
1518 *
1519 * Return: 0 if success, otherwise error code
1520 */
1521static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1522{
1523 const size_t size = sizeof(sync_serial_settings);
1524 sync_serial_settings new_line;
1525 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1526 struct slgt_info *info = dev_to_port(dev);
1527 unsigned int flags;
1528
1529 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1530
1531 /* return error if TTY interface open */
1532 if (info->port.count)
1533 return -EBUSY;
1534
1535 memset(&new_line, 0, sizeof(new_line));
1536
1537 switch (ifs->type) {
1538 case IF_GET_IFACE: /* return current sync_serial_settings */
1539
1540 ifs->type = IF_IFACE_SYNC_SERIAL;
1541 if (ifs->size < size) {
1542 ifs->size = size; /* data size wanted */
1543 return -ENOBUFS;
1544 }
1545
1546 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1547 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1548 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1549 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1550
1551 switch (flags){
1552 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1553 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1554 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1555 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1556 default: new_line.clock_type = CLOCK_DEFAULT;
1557 }
1558
1559 new_line.clock_rate = info->params.clock_speed;
1560 new_line.loopback = info->params.loopback ? 1:0;
1561
1562 if (copy_to_user(line, &new_line, size))
1563 return -EFAULT;
1564 return 0;
1565
1566 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1567
1568 if(!capable(CAP_NET_ADMIN))
1569 return -EPERM;
1570 if (copy_from_user(&new_line, line, size))
1571 return -EFAULT;
1572
1573 switch (new_line.clock_type)
1574 {
1575 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1576 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1577 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1578 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1579 case CLOCK_DEFAULT: flags = info->params.flags &
1580 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1581 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1582 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1583 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1584 default: return -EINVAL;
1585 }
1586
1587 if (new_line.loopback != 0 && new_line.loopback != 1)
1588 return -EINVAL;
1589
1590 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1591 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1592 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1593 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1594 info->params.flags |= flags;
1595
1596 info->params.loopback = new_line.loopback;
1597
1598 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1599 info->params.clock_speed = new_line.clock_rate;
1600 else
1601 info->params.clock_speed = 0;
1602
1603 /* if network interface up, reprogram hardware */
1604 if (info->netcount)
1605 program_hw(info);
1606 return 0;
1607
1608 default:
1609 return hdlc_ioctl(dev, ifs);
1610 }
1611}
1612
1613/**
1614 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1615 * @dev: pointer to network device structure
1616 * @txqueue: unused
1617 */
1618static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1619{
1620 struct slgt_info *info = dev_to_port(dev);
1621 unsigned long flags;
1622
1623 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1624
1625 dev->stats.tx_errors++;
1626 dev->stats.tx_aborted_errors++;
1627
1628 spin_lock_irqsave(&info->lock,flags);
1629 tx_stop(info);
1630 spin_unlock_irqrestore(&info->lock,flags);
1631
1632 netif_wake_queue(dev);
1633}
1634
1635/**
1636 * hdlcdev_tx_done - called by device driver when transmit completes
1637 * @info: pointer to device instance information
1638 *
1639 * Reenable network layer transmit if stopped.
1640 */
1641static void hdlcdev_tx_done(struct slgt_info *info)
1642{
1643 if (netif_queue_stopped(info->netdev))
1644 netif_wake_queue(info->netdev);
1645}
1646
1647/**
1648 * hdlcdev_rx - called by device driver when frame received
1649 * @info: pointer to device instance information
1650 * @buf: pointer to buffer contianing frame data
1651 * @size: count of data bytes in buf
1652 *
1653 * Pass frame to network layer.
1654 */
1655static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1656{
1657 struct sk_buff *skb = dev_alloc_skb(size);
1658 struct net_device *dev = info->netdev;
1659
1660 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1661
1662 if (skb == NULL) {
1663 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1664 dev->stats.rx_dropped++;
1665 return;
1666 }
1667
1668 skb_put_data(skb, buf, size);
1669
1670 skb->protocol = hdlc_type_trans(skb, dev);
1671
1672 dev->stats.rx_packets++;
1673 dev->stats.rx_bytes += size;
1674
1675 netif_rx(skb);
1676}
1677
1678static const struct net_device_ops hdlcdev_ops = {
1679 .ndo_open = hdlcdev_open,
1680 .ndo_stop = hdlcdev_close,
1681 .ndo_start_xmit = hdlc_start_xmit,
1682 .ndo_siocwandev = hdlcdev_ioctl,
1683 .ndo_tx_timeout = hdlcdev_tx_timeout,
1684};
1685
1686/**
1687 * hdlcdev_init - called by device driver when adding device instance
1688 * @info: pointer to device instance information
1689 *
1690 * Do generic HDLC initialization.
1691 *
1692 * Return: 0 if success, otherwise error code
1693 */
1694static int hdlcdev_init(struct slgt_info *info)
1695{
1696 int rc;
1697 struct net_device *dev;
1698 hdlc_device *hdlc;
1699
1700 /* allocate and initialize network and HDLC layer objects */
1701
1702 dev = alloc_hdlcdev(info);
1703 if (!dev) {
1704 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1705 return -ENOMEM;
1706 }
1707
1708 /* for network layer reporting purposes only */
1709 dev->mem_start = info->phys_reg_addr;
1710 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1711 dev->irq = info->irq_level;
1712
1713 /* network layer callbacks and settings */
1714 dev->netdev_ops = &hdlcdev_ops;
1715 dev->watchdog_timeo = 10 * HZ;
1716 dev->tx_queue_len = 50;
1717
1718 /* generic HDLC layer callbacks and settings */
1719 hdlc = dev_to_hdlc(dev);
1720 hdlc->attach = hdlcdev_attach;
1721 hdlc->xmit = hdlcdev_xmit;
1722
1723 /* register objects with HDLC layer */
1724 rc = register_hdlc_device(dev);
1725 if (rc) {
1726 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1727 free_netdev(dev);
1728 return rc;
1729 }
1730
1731 info->netdev = dev;
1732 return 0;
1733}
1734
1735/**
1736 * hdlcdev_exit - called by device driver when removing device instance
1737 * @info: pointer to device instance information
1738 *
1739 * Do generic HDLC cleanup.
1740 */
1741static void hdlcdev_exit(struct slgt_info *info)
1742{
1743 if (!info->netdev)
1744 return;
1745 unregister_hdlc_device(info->netdev);
1746 free_netdev(info->netdev);
1747 info->netdev = NULL;
1748}
1749
1750#endif /* ifdef CONFIG_HDLC */
1751
1752/*
1753 * get async data from rx DMA buffers
1754 */
1755static void rx_async(struct slgt_info *info)
1756{
1757 struct mgsl_icount *icount = &info->icount;
1758 unsigned int start, end;
1759 unsigned char *p;
1760 unsigned char status;
1761 struct slgt_desc *bufs = info->rbufs;
1762 int i, count;
1763 int chars = 0;
1764 int stat;
1765 unsigned char ch;
1766
1767 start = end = info->rbuf_current;
1768
1769 while(desc_complete(bufs[end])) {
1770 count = desc_count(bufs[end]) - info->rbuf_index;
1771 p = bufs[end].buf + info->rbuf_index;
1772
1773 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1774 DBGDATA(info, p, count, "rx");
1775
1776 for(i=0 ; i < count; i+=2, p+=2) {
1777 ch = *p;
1778 icount->rx++;
1779
1780 stat = 0;
1781
1782 status = *(p + 1) & (BIT1 + BIT0);
1783 if (status) {
1784 if (status & BIT1)
1785 icount->parity++;
1786 else if (status & BIT0)
1787 icount->frame++;
1788 /* discard char if tty control flags say so */
1789 if (status & info->ignore_status_mask)
1790 continue;
1791 if (status & BIT1)
1792 stat = TTY_PARITY;
1793 else if (status & BIT0)
1794 stat = TTY_FRAME;
1795 }
1796 tty_insert_flip_char(&info->port, ch, stat);
1797 chars++;
1798 }
1799
1800 if (i < count) {
1801 /* receive buffer not completed */
1802 info->rbuf_index += i;
1803 mod_timer(&info->rx_timer, jiffies + 1);
1804 break;
1805 }
1806
1807 info->rbuf_index = 0;
1808 free_rbufs(info, end, end);
1809
1810 if (++end == info->rbuf_count)
1811 end = 0;
1812
1813 /* if entire list searched then no frame available */
1814 if (end == start)
1815 break;
1816 }
1817
1818 if (chars)
1819 tty_flip_buffer_push(&info->port);
1820}
1821
1822/*
1823 * return next bottom half action to perform
1824 */
1825static int bh_action(struct slgt_info *info)
1826{
1827 unsigned long flags;
1828 int rc;
1829
1830 spin_lock_irqsave(&info->lock,flags);
1831
1832 if (info->pending_bh & BH_RECEIVE) {
1833 info->pending_bh &= ~BH_RECEIVE;
1834 rc = BH_RECEIVE;
1835 } else if (info->pending_bh & BH_TRANSMIT) {
1836 info->pending_bh &= ~BH_TRANSMIT;
1837 rc = BH_TRANSMIT;
1838 } else if (info->pending_bh & BH_STATUS) {
1839 info->pending_bh &= ~BH_STATUS;
1840 rc = BH_STATUS;
1841 } else {
1842 /* Mark BH routine as complete */
1843 info->bh_running = false;
1844 info->bh_requested = false;
1845 rc = 0;
1846 }
1847
1848 spin_unlock_irqrestore(&info->lock,flags);
1849
1850 return rc;
1851}
1852
1853/*
1854 * perform bottom half processing
1855 */
1856static void bh_handler(struct work_struct *work)
1857{
1858 struct slgt_info *info = container_of(work, struct slgt_info, task);
1859 int action;
1860
1861 info->bh_running = true;
1862
1863 while((action = bh_action(info))) {
1864 switch (action) {
1865 case BH_RECEIVE:
1866 DBGBH(("%s bh receive\n", info->device_name));
1867 switch(info->params.mode) {
1868 case MGSL_MODE_ASYNC:
1869 rx_async(info);
1870 break;
1871 case MGSL_MODE_HDLC:
1872 while(rx_get_frame(info));
1873 break;
1874 case MGSL_MODE_RAW:
1875 case MGSL_MODE_MONOSYNC:
1876 case MGSL_MODE_BISYNC:
1877 case MGSL_MODE_XSYNC:
1878 while(rx_get_buf(info));
1879 break;
1880 }
1881 /* restart receiver if rx DMA buffers exhausted */
1882 if (info->rx_restart)
1883 rx_start(info);
1884 break;
1885 case BH_TRANSMIT:
1886 bh_transmit(info);
1887 break;
1888 case BH_STATUS:
1889 DBGBH(("%s bh status\n", info->device_name));
1890 info->ri_chkcount = 0;
1891 info->dsr_chkcount = 0;
1892 info->dcd_chkcount = 0;
1893 info->cts_chkcount = 0;
1894 break;
1895 default:
1896 DBGBH(("%s unknown action\n", info->device_name));
1897 break;
1898 }
1899 }
1900 DBGBH(("%s bh_handler exit\n", info->device_name));
1901}
1902
1903static void bh_transmit(struct slgt_info *info)
1904{
1905 struct tty_struct *tty = info->port.tty;
1906
1907 DBGBH(("%s bh_transmit\n", info->device_name));
1908 if (tty)
1909 tty_wakeup(tty);
1910}
1911
1912static void dsr_change(struct slgt_info *info, unsigned short status)
1913{
1914 if (status & BIT3) {
1915 info->signals |= SerialSignal_DSR;
1916 info->input_signal_events.dsr_up++;
1917 } else {
1918 info->signals &= ~SerialSignal_DSR;
1919 info->input_signal_events.dsr_down++;
1920 }
1921 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1922 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1923 slgt_irq_off(info, IRQ_DSR);
1924 return;
1925 }
1926 info->icount.dsr++;
1927 wake_up_interruptible(&info->status_event_wait_q);
1928 wake_up_interruptible(&info->event_wait_q);
1929 info->pending_bh |= BH_STATUS;
1930}
1931
1932static void cts_change(struct slgt_info *info, unsigned short status)
1933{
1934 if (status & BIT2) {
1935 info->signals |= SerialSignal_CTS;
1936 info->input_signal_events.cts_up++;
1937 } else {
1938 info->signals &= ~SerialSignal_CTS;
1939 info->input_signal_events.cts_down++;
1940 }
1941 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1942 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1943 slgt_irq_off(info, IRQ_CTS);
1944 return;
1945 }
1946 info->icount.cts++;
1947 wake_up_interruptible(&info->status_event_wait_q);
1948 wake_up_interruptible(&info->event_wait_q);
1949 info->pending_bh |= BH_STATUS;
1950
1951 if (tty_port_cts_enabled(&info->port)) {
1952 if (info->port.tty) {
1953 if (info->port.tty->hw_stopped) {
1954 if (info->signals & SerialSignal_CTS) {
1955 info->port.tty->hw_stopped = false;
1956 info->pending_bh |= BH_TRANSMIT;
1957 return;
1958 }
1959 } else {
1960 if (!(info->signals & SerialSignal_CTS))
1961 info->port.tty->hw_stopped = true;
1962 }
1963 }
1964 }
1965}
1966
1967static void dcd_change(struct slgt_info *info, unsigned short status)
1968{
1969 if (status & BIT1) {
1970 info->signals |= SerialSignal_DCD;
1971 info->input_signal_events.dcd_up++;
1972 } else {
1973 info->signals &= ~SerialSignal_DCD;
1974 info->input_signal_events.dcd_down++;
1975 }
1976 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1977 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1978 slgt_irq_off(info, IRQ_DCD);
1979 return;
1980 }
1981 info->icount.dcd++;
1982#if SYNCLINK_GENERIC_HDLC
1983 if (info->netcount) {
1984 if (info->signals & SerialSignal_DCD)
1985 netif_carrier_on(info->netdev);
1986 else
1987 netif_carrier_off(info->netdev);
1988 }
1989#endif
1990 wake_up_interruptible(&info->status_event_wait_q);
1991 wake_up_interruptible(&info->event_wait_q);
1992 info->pending_bh |= BH_STATUS;
1993
1994 if (tty_port_check_carrier(&info->port)) {
1995 if (info->signals & SerialSignal_DCD)
1996 wake_up_interruptible(&info->port.open_wait);
1997 else {
1998 if (info->port.tty)
1999 tty_hangup(info->port.tty);
2000 }
2001 }
2002}
2003
2004static void ri_change(struct slgt_info *info, unsigned short status)
2005{
2006 if (status & BIT0) {
2007 info->signals |= SerialSignal_RI;
2008 info->input_signal_events.ri_up++;
2009 } else {
2010 info->signals &= ~SerialSignal_RI;
2011 info->input_signal_events.ri_down++;
2012 }
2013 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2014 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2015 slgt_irq_off(info, IRQ_RI);
2016 return;
2017 }
2018 info->icount.rng++;
2019 wake_up_interruptible(&info->status_event_wait_q);
2020 wake_up_interruptible(&info->event_wait_q);
2021 info->pending_bh |= BH_STATUS;
2022}
2023
2024static void isr_rxdata(struct slgt_info *info)
2025{
2026 unsigned int count = info->rbuf_fill_count;
2027 unsigned int i = info->rbuf_fill_index;
2028 unsigned short reg;
2029
2030 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2031 reg = rd_reg16(info, RDR);
2032 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2033 if (desc_complete(info->rbufs[i])) {
2034 /* all buffers full */
2035 rx_stop(info);
2036 info->rx_restart = true;
2037 continue;
2038 }
2039 info->rbufs[i].buf[count++] = (unsigned char)reg;
2040 /* async mode saves status byte to buffer for each data byte */
2041 if (info->params.mode == MGSL_MODE_ASYNC)
2042 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2043 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2044 /* buffer full or end of frame */
2045 set_desc_count(info->rbufs[i], count);
2046 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2047 info->rbuf_fill_count = count = 0;
2048 if (++i == info->rbuf_count)
2049 i = 0;
2050 info->pending_bh |= BH_RECEIVE;
2051 }
2052 }
2053
2054 info->rbuf_fill_index = i;
2055 info->rbuf_fill_count = count;
2056}
2057
2058static void isr_serial(struct slgt_info *info)
2059{
2060 unsigned short status = rd_reg16(info, SSR);
2061
2062 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2063
2064 wr_reg16(info, SSR, status); /* clear pending */
2065
2066 info->irq_occurred = true;
2067
2068 if (info->params.mode == MGSL_MODE_ASYNC) {
2069 if (status & IRQ_TXIDLE) {
2070 if (info->tx_active)
2071 isr_txeom(info, status);
2072 }
2073 if (info->rx_pio && (status & IRQ_RXDATA))
2074 isr_rxdata(info);
2075 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2076 info->icount.brk++;
2077 /* process break detection if tty control allows */
2078 if (info->port.tty) {
2079 if (!(status & info->ignore_status_mask)) {
2080 if (info->read_status_mask & MASK_BREAK) {
2081 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2082 if (info->port.flags & ASYNC_SAK)
2083 do_SAK(info->port.tty);
2084 }
2085 }
2086 }
2087 }
2088 } else {
2089 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2090 isr_txeom(info, status);
2091 if (info->rx_pio && (status & IRQ_RXDATA))
2092 isr_rxdata(info);
2093 if (status & IRQ_RXIDLE) {
2094 if (status & RXIDLE)
2095 info->icount.rxidle++;
2096 else
2097 info->icount.exithunt++;
2098 wake_up_interruptible(&info->event_wait_q);
2099 }
2100
2101 if (status & IRQ_RXOVER)
2102 rx_start(info);
2103 }
2104
2105 if (status & IRQ_DSR)
2106 dsr_change(info, status);
2107 if (status & IRQ_CTS)
2108 cts_change(info, status);
2109 if (status & IRQ_DCD)
2110 dcd_change(info, status);
2111 if (status & IRQ_RI)
2112 ri_change(info, status);
2113}
2114
2115static void isr_rdma(struct slgt_info *info)
2116{
2117 unsigned int status = rd_reg32(info, RDCSR);
2118
2119 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2120
2121 /* RDCSR (rx DMA control/status)
2122 *
2123 * 31..07 reserved
2124 * 06 save status byte to DMA buffer
2125 * 05 error
2126 * 04 eol (end of list)
2127 * 03 eob (end of buffer)
2128 * 02 IRQ enable
2129 * 01 reset
2130 * 00 enable
2131 */
2132 wr_reg32(info, RDCSR, status); /* clear pending */
2133
2134 if (status & (BIT5 + BIT4)) {
2135 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2136 info->rx_restart = true;
2137 }
2138 info->pending_bh |= BH_RECEIVE;
2139}
2140
2141static void isr_tdma(struct slgt_info *info)
2142{
2143 unsigned int status = rd_reg32(info, TDCSR);
2144
2145 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2146
2147 /* TDCSR (tx DMA control/status)
2148 *
2149 * 31..06 reserved
2150 * 05 error
2151 * 04 eol (end of list)
2152 * 03 eob (end of buffer)
2153 * 02 IRQ enable
2154 * 01 reset
2155 * 00 enable
2156 */
2157 wr_reg32(info, TDCSR, status); /* clear pending */
2158
2159 if (status & (BIT5 + BIT4 + BIT3)) {
2160 // another transmit buffer has completed
2161 // run bottom half to get more send data from user
2162 info->pending_bh |= BH_TRANSMIT;
2163 }
2164}
2165
2166/*
2167 * return true if there are unsent tx DMA buffers, otherwise false
2168 *
2169 * if there are unsent buffers then info->tbuf_start
2170 * is set to index of first unsent buffer
2171 */
2172static bool unsent_tbufs(struct slgt_info *info)
2173{
2174 unsigned int i = info->tbuf_current;
2175 bool rc = false;
2176
2177 /*
2178 * search backwards from last loaded buffer (precedes tbuf_current)
2179 * for first unsent buffer (desc_count > 0)
2180 */
2181
2182 do {
2183 if (i)
2184 i--;
2185 else
2186 i = info->tbuf_count - 1;
2187 if (!desc_count(info->tbufs[i]))
2188 break;
2189 info->tbuf_start = i;
2190 rc = true;
2191 } while (i != info->tbuf_current);
2192
2193 return rc;
2194}
2195
2196static void isr_txeom(struct slgt_info *info, unsigned short status)
2197{
2198 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2199
2200 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2201 tdma_reset(info);
2202 if (status & IRQ_TXUNDER) {
2203 unsigned short val = rd_reg16(info, TCR);
2204 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2205 wr_reg16(info, TCR, val); /* clear reset bit */
2206 }
2207
2208 if (info->tx_active) {
2209 if (info->params.mode != MGSL_MODE_ASYNC) {
2210 if (status & IRQ_TXUNDER)
2211 info->icount.txunder++;
2212 else if (status & IRQ_TXIDLE)
2213 info->icount.txok++;
2214 }
2215
2216 if (unsent_tbufs(info)) {
2217 tx_start(info);
2218 update_tx_timer(info);
2219 return;
2220 }
2221 info->tx_active = false;
2222
2223 del_timer(&info->tx_timer);
2224
2225 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2226 info->signals &= ~SerialSignal_RTS;
2227 info->drop_rts_on_tx_done = false;
2228 set_gtsignals(info);
2229 }
2230
2231#if SYNCLINK_GENERIC_HDLC
2232 if (info->netcount)
2233 hdlcdev_tx_done(info);
2234 else
2235#endif
2236 {
2237 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2238 tx_stop(info);
2239 return;
2240 }
2241 info->pending_bh |= BH_TRANSMIT;
2242 }
2243 }
2244}
2245
2246static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2247{
2248 struct cond_wait *w, *prev;
2249
2250 /* wake processes waiting for specific transitions */
2251 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2252 if (w->data & changed) {
2253 w->data = state;
2254 wake_up_interruptible(&w->q);
2255 if (prev != NULL)
2256 prev->next = w->next;
2257 else
2258 info->gpio_wait_q = w->next;
2259 } else
2260 prev = w;
2261 }
2262}
2263
2264/* interrupt service routine
2265 *
2266 * irq interrupt number
2267 * dev_id device ID supplied during interrupt registration
2268 */
2269static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2270{
2271 struct slgt_info *info = dev_id;
2272 unsigned int gsr;
2273 unsigned int i;
2274
2275 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2276
2277 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2278 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2279 info->irq_occurred = true;
2280 for(i=0; i < info->port_count ; i++) {
2281 if (info->port_array[i] == NULL)
2282 continue;
2283 spin_lock(&info->port_array[i]->lock);
2284 if (gsr & (BIT8 << i))
2285 isr_serial(info->port_array[i]);
2286 if (gsr & (BIT16 << (i*2)))
2287 isr_rdma(info->port_array[i]);
2288 if (gsr & (BIT17 << (i*2)))
2289 isr_tdma(info->port_array[i]);
2290 spin_unlock(&info->port_array[i]->lock);
2291 }
2292 }
2293
2294 if (info->gpio_present) {
2295 unsigned int state;
2296 unsigned int changed;
2297 spin_lock(&info->lock);
2298 while ((changed = rd_reg32(info, IOSR)) != 0) {
2299 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2300 /* read latched state of GPIO signals */
2301 state = rd_reg32(info, IOVR);
2302 /* clear pending GPIO interrupt bits */
2303 wr_reg32(info, IOSR, changed);
2304 for (i=0 ; i < info->port_count ; i++) {
2305 if (info->port_array[i] != NULL)
2306 isr_gpio(info->port_array[i], changed, state);
2307 }
2308 }
2309 spin_unlock(&info->lock);
2310 }
2311
2312 for(i=0; i < info->port_count ; i++) {
2313 struct slgt_info *port = info->port_array[i];
2314 if (port == NULL)
2315 continue;
2316 spin_lock(&port->lock);
2317 if ((port->port.count || port->netcount) &&
2318 port->pending_bh && !port->bh_running &&
2319 !port->bh_requested) {
2320 DBGISR(("%s bh queued\n", port->device_name));
2321 schedule_work(&port->task);
2322 port->bh_requested = true;
2323 }
2324 spin_unlock(&port->lock);
2325 }
2326
2327 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2328 return IRQ_HANDLED;
2329}
2330
2331static int startup(struct slgt_info *info)
2332{
2333 DBGINFO(("%s startup\n", info->device_name));
2334
2335 if (tty_port_initialized(&info->port))
2336 return 0;
2337
2338 if (!info->tx_buf) {
2339 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2340 if (!info->tx_buf) {
2341 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2342 return -ENOMEM;
2343 }
2344 }
2345
2346 info->pending_bh = 0;
2347
2348 memset(&info->icount, 0, sizeof(info->icount));
2349
2350 /* program hardware for current parameters */
2351 change_params(info);
2352
2353 if (info->port.tty)
2354 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2355
2356 tty_port_set_initialized(&info->port, true);
2357
2358 return 0;
2359}
2360
2361/*
2362 * called by close() and hangup() to shutdown hardware
2363 */
2364static void shutdown(struct slgt_info *info)
2365{
2366 unsigned long flags;
2367
2368 if (!tty_port_initialized(&info->port))
2369 return;
2370
2371 DBGINFO(("%s shutdown\n", info->device_name));
2372
2373 /* clear status wait queue because status changes */
2374 /* can't happen after shutting down the hardware */
2375 wake_up_interruptible(&info->status_event_wait_q);
2376 wake_up_interruptible(&info->event_wait_q);
2377
2378 del_timer_sync(&info->tx_timer);
2379 del_timer_sync(&info->rx_timer);
2380
2381 kfree(info->tx_buf);
2382 info->tx_buf = NULL;
2383
2384 spin_lock_irqsave(&info->lock,flags);
2385
2386 tx_stop(info);
2387 rx_stop(info);
2388
2389 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2390
2391 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2392 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2393 set_gtsignals(info);
2394 }
2395
2396 flush_cond_wait(&info->gpio_wait_q);
2397
2398 spin_unlock_irqrestore(&info->lock,flags);
2399
2400 if (info->port.tty)
2401 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2402
2403 tty_port_set_initialized(&info->port, false);
2404}
2405
2406static void program_hw(struct slgt_info *info)
2407{
2408 unsigned long flags;
2409
2410 spin_lock_irqsave(&info->lock,flags);
2411
2412 rx_stop(info);
2413 tx_stop(info);
2414
2415 if (info->params.mode != MGSL_MODE_ASYNC ||
2416 info->netcount)
2417 sync_mode(info);
2418 else
2419 async_mode(info);
2420
2421 set_gtsignals(info);
2422
2423 info->dcd_chkcount = 0;
2424 info->cts_chkcount = 0;
2425 info->ri_chkcount = 0;
2426 info->dsr_chkcount = 0;
2427
2428 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2429 get_gtsignals(info);
2430
2431 if (info->netcount ||
2432 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2433 rx_start(info);
2434
2435 spin_unlock_irqrestore(&info->lock,flags);
2436}
2437
2438/*
2439 * reconfigure adapter based on new parameters
2440 */
2441static void change_params(struct slgt_info *info)
2442{
2443 unsigned cflag;
2444 int bits_per_char;
2445
2446 if (!info->port.tty)
2447 return;
2448 DBGINFO(("%s change_params\n", info->device_name));
2449
2450 cflag = info->port.tty->termios.c_cflag;
2451
2452 /* if B0 rate (hangup) specified then negate RTS and DTR */
2453 /* otherwise assert RTS and DTR */
2454 if (cflag & CBAUD)
2455 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2456 else
2457 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2458
2459 /* byte size and parity */
2460
2461 info->params.data_bits = tty_get_char_size(cflag);
2462 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2463
2464 if (cflag & PARENB)
2465 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2466 else
2467 info->params.parity = ASYNC_PARITY_NONE;
2468
2469 /* calculate number of jiffies to transmit a full
2470 * FIFO (32 bytes) at specified data rate
2471 */
2472 bits_per_char = info->params.data_bits +
2473 info->params.stop_bits + 1;
2474
2475 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2476
2477 if (info->params.data_rate) {
2478 info->timeout = (32*HZ*bits_per_char) /
2479 info->params.data_rate;
2480 }
2481 info->timeout += HZ/50; /* Add .02 seconds of slop */
2482
2483 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2484 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2485
2486 /* process tty input control flags */
2487
2488 info->read_status_mask = IRQ_RXOVER;
2489 if (I_INPCK(info->port.tty))
2490 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2491 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2492 info->read_status_mask |= MASK_BREAK;
2493 if (I_IGNPAR(info->port.tty))
2494 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2495 if (I_IGNBRK(info->port.tty)) {
2496 info->ignore_status_mask |= MASK_BREAK;
2497 /* If ignoring parity and break indicators, ignore
2498 * overruns too. (For real raw support).
2499 */
2500 if (I_IGNPAR(info->port.tty))
2501 info->ignore_status_mask |= MASK_OVERRUN;
2502 }
2503
2504 program_hw(info);
2505}
2506
2507static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2508{
2509 DBGINFO(("%s get_stats\n", info->device_name));
2510 if (!user_icount) {
2511 memset(&info->icount, 0, sizeof(info->icount));
2512 } else {
2513 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2514 return -EFAULT;
2515 }
2516 return 0;
2517}
2518
2519static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2520{
2521 DBGINFO(("%s get_params\n", info->device_name));
2522 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2523 return -EFAULT;
2524 return 0;
2525}
2526
2527static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2528{
2529 unsigned long flags;
2530 MGSL_PARAMS tmp_params;
2531
2532 DBGINFO(("%s set_params\n", info->device_name));
2533 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2534 return -EFAULT;
2535
2536 spin_lock_irqsave(&info->lock, flags);
2537 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2538 info->base_clock = tmp_params.clock_speed;
2539 else
2540 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2541 spin_unlock_irqrestore(&info->lock, flags);
2542
2543 program_hw(info);
2544
2545 return 0;
2546}
2547
2548static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2549{
2550 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2551 if (put_user(info->idle_mode, idle_mode))
2552 return -EFAULT;
2553 return 0;
2554}
2555
2556static int set_txidle(struct slgt_info *info, int idle_mode)
2557{
2558 unsigned long flags;
2559 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2560 spin_lock_irqsave(&info->lock,flags);
2561 info->idle_mode = idle_mode;
2562 if (info->params.mode != MGSL_MODE_ASYNC)
2563 tx_set_idle(info);
2564 spin_unlock_irqrestore(&info->lock,flags);
2565 return 0;
2566}
2567
2568static int tx_enable(struct slgt_info *info, int enable)
2569{
2570 unsigned long flags;
2571 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2572 spin_lock_irqsave(&info->lock,flags);
2573 if (enable) {
2574 if (!info->tx_enabled)
2575 tx_start(info);
2576 } else {
2577 if (info->tx_enabled)
2578 tx_stop(info);
2579 }
2580 spin_unlock_irqrestore(&info->lock,flags);
2581 return 0;
2582}
2583
2584/*
2585 * abort transmit HDLC frame
2586 */
2587static int tx_abort(struct slgt_info *info)
2588{
2589 unsigned long flags;
2590 DBGINFO(("%s tx_abort\n", info->device_name));
2591 spin_lock_irqsave(&info->lock,flags);
2592 tdma_reset(info);
2593 spin_unlock_irqrestore(&info->lock,flags);
2594 return 0;
2595}
2596
2597static int rx_enable(struct slgt_info *info, int enable)
2598{
2599 unsigned long flags;
2600 unsigned int rbuf_fill_level;
2601 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2602 spin_lock_irqsave(&info->lock,flags);
2603 /*
2604 * enable[31..16] = receive DMA buffer fill level
2605 * 0 = noop (leave fill level unchanged)
2606 * fill level must be multiple of 4 and <= buffer size
2607 */
2608 rbuf_fill_level = ((unsigned int)enable) >> 16;
2609 if (rbuf_fill_level) {
2610 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2611 spin_unlock_irqrestore(&info->lock, flags);
2612 return -EINVAL;
2613 }
2614 info->rbuf_fill_level = rbuf_fill_level;
2615 if (rbuf_fill_level < 128)
2616 info->rx_pio = 1; /* PIO mode */
2617 else
2618 info->rx_pio = 0; /* DMA mode */
2619 rx_stop(info); /* restart receiver to use new fill level */
2620 }
2621
2622 /*
2623 * enable[1..0] = receiver enable command
2624 * 0 = disable
2625 * 1 = enable
2626 * 2 = enable or force hunt mode if already enabled
2627 */
2628 enable &= 3;
2629 if (enable) {
2630 if (!info->rx_enabled)
2631 rx_start(info);
2632 else if (enable == 2) {
2633 /* force hunt mode (write 1 to RCR[3]) */
2634 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2635 }
2636 } else {
2637 if (info->rx_enabled)
2638 rx_stop(info);
2639 }
2640 spin_unlock_irqrestore(&info->lock,flags);
2641 return 0;
2642}
2643
2644/*
2645 * wait for specified event to occur
2646 */
2647static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2648{
2649 unsigned long flags;
2650 int s;
2651 int rc=0;
2652 struct mgsl_icount cprev, cnow;
2653 int events;
2654 int mask;
2655 struct _input_signal_events oldsigs, newsigs;
2656 DECLARE_WAITQUEUE(wait, current);
2657
2658 if (get_user(mask, mask_ptr))
2659 return -EFAULT;
2660
2661 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2662
2663 spin_lock_irqsave(&info->lock,flags);
2664
2665 /* return immediately if state matches requested events */
2666 get_gtsignals(info);
2667 s = info->signals;
2668
2669 events = mask &
2670 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2671 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2672 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2673 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2674 if (events) {
2675 spin_unlock_irqrestore(&info->lock,flags);
2676 goto exit;
2677 }
2678
2679 /* save current irq counts */
2680 cprev = info->icount;
2681 oldsigs = info->input_signal_events;
2682
2683 /* enable hunt and idle irqs if needed */
2684 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2685 unsigned short val = rd_reg16(info, SCR);
2686 if (!(val & IRQ_RXIDLE))
2687 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2688 }
2689
2690 set_current_state(TASK_INTERRUPTIBLE);
2691 add_wait_queue(&info->event_wait_q, &wait);
2692
2693 spin_unlock_irqrestore(&info->lock,flags);
2694
2695 for(;;) {
2696 schedule();
2697 if (signal_pending(current)) {
2698 rc = -ERESTARTSYS;
2699 break;
2700 }
2701
2702 /* get current irq counts */
2703 spin_lock_irqsave(&info->lock,flags);
2704 cnow = info->icount;
2705 newsigs = info->input_signal_events;
2706 set_current_state(TASK_INTERRUPTIBLE);
2707 spin_unlock_irqrestore(&info->lock,flags);
2708
2709 /* if no change, wait aborted for some reason */
2710 if (newsigs.dsr_up == oldsigs.dsr_up &&
2711 newsigs.dsr_down == oldsigs.dsr_down &&
2712 newsigs.dcd_up == oldsigs.dcd_up &&
2713 newsigs.dcd_down == oldsigs.dcd_down &&
2714 newsigs.cts_up == oldsigs.cts_up &&
2715 newsigs.cts_down == oldsigs.cts_down &&
2716 newsigs.ri_up == oldsigs.ri_up &&
2717 newsigs.ri_down == oldsigs.ri_down &&
2718 cnow.exithunt == cprev.exithunt &&
2719 cnow.rxidle == cprev.rxidle) {
2720 rc = -EIO;
2721 break;
2722 }
2723
2724 events = mask &
2725 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2726 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2727 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2728 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2729 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2730 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2731 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2732 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2733 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2734 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2735 if (events)
2736 break;
2737
2738 cprev = cnow;
2739 oldsigs = newsigs;
2740 }
2741
2742 remove_wait_queue(&info->event_wait_q, &wait);
2743 set_current_state(TASK_RUNNING);
2744
2745
2746 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2747 spin_lock_irqsave(&info->lock,flags);
2748 if (!waitqueue_active(&info->event_wait_q)) {
2749 /* disable enable exit hunt mode/idle rcvd IRQs */
2750 wr_reg16(info, SCR,
2751 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2752 }
2753 spin_unlock_irqrestore(&info->lock,flags);
2754 }
2755exit:
2756 if (rc == 0)
2757 rc = put_user(events, mask_ptr);
2758 return rc;
2759}
2760
2761static int get_interface(struct slgt_info *info, int __user *if_mode)
2762{
2763 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2764 if (put_user(info->if_mode, if_mode))
2765 return -EFAULT;
2766 return 0;
2767}
2768
2769static int set_interface(struct slgt_info *info, int if_mode)
2770{
2771 unsigned long flags;
2772 unsigned short val;
2773
2774 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2775 spin_lock_irqsave(&info->lock,flags);
2776 info->if_mode = if_mode;
2777
2778 msc_set_vcr(info);
2779
2780 /* TCR (tx control) 07 1=RTS driver control */
2781 val = rd_reg16(info, TCR);
2782 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2783 val |= BIT7;
2784 else
2785 val &= ~BIT7;
2786 wr_reg16(info, TCR, val);
2787
2788 spin_unlock_irqrestore(&info->lock,flags);
2789 return 0;
2790}
2791
2792static int get_xsync(struct slgt_info *info, int __user *xsync)
2793{
2794 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2795 if (put_user(info->xsync, xsync))
2796 return -EFAULT;
2797 return 0;
2798}
2799
2800/*
2801 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2802 *
2803 * sync pattern is contained in least significant bytes of value
2804 * most significant byte of sync pattern is oldest (1st sent/detected)
2805 */
2806static int set_xsync(struct slgt_info *info, int xsync)
2807{
2808 unsigned long flags;
2809
2810 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2811 spin_lock_irqsave(&info->lock, flags);
2812 info->xsync = xsync;
2813 wr_reg32(info, XSR, xsync);
2814 spin_unlock_irqrestore(&info->lock, flags);
2815 return 0;
2816}
2817
2818static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2819{
2820 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2821 if (put_user(info->xctrl, xctrl))
2822 return -EFAULT;
2823 return 0;
2824}
2825
2826/*
2827 * set extended control options
2828 *
2829 * xctrl[31:19] reserved, must be zero
2830 * xctrl[18:17] extended sync pattern length in bytes
2831 * 00 = 1 byte in xsr[7:0]
2832 * 01 = 2 bytes in xsr[15:0]
2833 * 10 = 3 bytes in xsr[23:0]
2834 * 11 = 4 bytes in xsr[31:0]
2835 * xctrl[16] 1 = enable terminal count, 0=disabled
2836 * xctrl[15:0] receive terminal count for fixed length packets
2837 * value is count minus one (0 = 1 byte packet)
2838 * when terminal count is reached, receiver
2839 * automatically returns to hunt mode and receive
2840 * FIFO contents are flushed to DMA buffers with
2841 * end of frame (EOF) status
2842 */
2843static int set_xctrl(struct slgt_info *info, int xctrl)
2844{
2845 unsigned long flags;
2846
2847 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2848 spin_lock_irqsave(&info->lock, flags);
2849 info->xctrl = xctrl;
2850 wr_reg32(info, XCR, xctrl);
2851 spin_unlock_irqrestore(&info->lock, flags);
2852 return 0;
2853}
2854
2855/*
2856 * set general purpose IO pin state and direction
2857 *
2858 * user_gpio fields:
2859 * state each bit indicates a pin state
2860 * smask set bit indicates pin state to set
2861 * dir each bit indicates a pin direction (0=input, 1=output)
2862 * dmask set bit indicates pin direction to set
2863 */
2864static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2865{
2866 unsigned long flags;
2867 struct gpio_desc gpio;
2868 __u32 data;
2869
2870 if (!info->gpio_present)
2871 return -EINVAL;
2872 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2873 return -EFAULT;
2874 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2875 info->device_name, gpio.state, gpio.smask,
2876 gpio.dir, gpio.dmask));
2877
2878 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2879 if (gpio.dmask) {
2880 data = rd_reg32(info, IODR);
2881 data |= gpio.dmask & gpio.dir;
2882 data &= ~(gpio.dmask & ~gpio.dir);
2883 wr_reg32(info, IODR, data);
2884 }
2885 if (gpio.smask) {
2886 data = rd_reg32(info, IOVR);
2887 data |= gpio.smask & gpio.state;
2888 data &= ~(gpio.smask & ~gpio.state);
2889 wr_reg32(info, IOVR, data);
2890 }
2891 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2892
2893 return 0;
2894}
2895
2896/*
2897 * get general purpose IO pin state and direction
2898 */
2899static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2900{
2901 struct gpio_desc gpio;
2902 if (!info->gpio_present)
2903 return -EINVAL;
2904 gpio.state = rd_reg32(info, IOVR);
2905 gpio.smask = 0xffffffff;
2906 gpio.dir = rd_reg32(info, IODR);
2907 gpio.dmask = 0xffffffff;
2908 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2909 return -EFAULT;
2910 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2911 info->device_name, gpio.state, gpio.dir));
2912 return 0;
2913}
2914
2915/*
2916 * conditional wait facility
2917 */
2918static void init_cond_wait(struct cond_wait *w, unsigned int data)
2919{
2920 init_waitqueue_head(&w->q);
2921 init_waitqueue_entry(&w->wait, current);
2922 w->data = data;
2923}
2924
2925static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2926{
2927 set_current_state(TASK_INTERRUPTIBLE);
2928 add_wait_queue(&w->q, &w->wait);
2929 w->next = *head;
2930 *head = w;
2931}
2932
2933static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2934{
2935 struct cond_wait *w, *prev;
2936 remove_wait_queue(&cw->q, &cw->wait);
2937 set_current_state(TASK_RUNNING);
2938 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2939 if (w == cw) {
2940 if (prev != NULL)
2941 prev->next = w->next;
2942 else
2943 *head = w->next;
2944 break;
2945 }
2946 }
2947}
2948
2949static void flush_cond_wait(struct cond_wait **head)
2950{
2951 while (*head != NULL) {
2952 wake_up_interruptible(&(*head)->q);
2953 *head = (*head)->next;
2954 }
2955}
2956
2957/*
2958 * wait for general purpose I/O pin(s) to enter specified state
2959 *
2960 * user_gpio fields:
2961 * state - bit indicates target pin state
2962 * smask - set bit indicates watched pin
2963 *
2964 * The wait ends when at least one watched pin enters the specified
2965 * state. When 0 (no error) is returned, user_gpio->state is set to the
2966 * state of all GPIO pins when the wait ends.
2967 *
2968 * Note: Each pin may be a dedicated input, dedicated output, or
2969 * configurable input/output. The number and configuration of pins
2970 * varies with the specific adapter model. Only input pins (dedicated
2971 * or configured) can be monitored with this function.
2972 */
2973static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2974{
2975 unsigned long flags;
2976 int rc = 0;
2977 struct gpio_desc gpio;
2978 struct cond_wait wait;
2979 u32 state;
2980
2981 if (!info->gpio_present)
2982 return -EINVAL;
2983 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2984 return -EFAULT;
2985 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2986 info->device_name, gpio.state, gpio.smask));
2987 /* ignore output pins identified by set IODR bit */
2988 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2989 return -EINVAL;
2990 init_cond_wait(&wait, gpio.smask);
2991
2992 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2993 /* enable interrupts for watched pins */
2994 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2995 /* get current pin states */
2996 state = rd_reg32(info, IOVR);
2997
2998 if (gpio.smask & ~(state ^ gpio.state)) {
2999 /* already in target state */
3000 gpio.state = state;
3001 } else {
3002 /* wait for target state */
3003 add_cond_wait(&info->gpio_wait_q, &wait);
3004 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3005 schedule();
3006 if (signal_pending(current))
3007 rc = -ERESTARTSYS;
3008 else
3009 gpio.state = wait.data;
3010 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3011 remove_cond_wait(&info->gpio_wait_q, &wait);
3012 }
3013
3014 /* disable all GPIO interrupts if no waiting processes */
3015 if (info->gpio_wait_q == NULL)
3016 wr_reg32(info, IOER, 0);
3017 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3018
3019 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3020 rc = -EFAULT;
3021 return rc;
3022}
3023
3024static int modem_input_wait(struct slgt_info *info,int arg)
3025{
3026 unsigned long flags;
3027 int rc;
3028 struct mgsl_icount cprev, cnow;
3029 DECLARE_WAITQUEUE(wait, current);
3030
3031 /* save current irq counts */
3032 spin_lock_irqsave(&info->lock,flags);
3033 cprev = info->icount;
3034 add_wait_queue(&info->status_event_wait_q, &wait);
3035 set_current_state(TASK_INTERRUPTIBLE);
3036 spin_unlock_irqrestore(&info->lock,flags);
3037
3038 for(;;) {
3039 schedule();
3040 if (signal_pending(current)) {
3041 rc = -ERESTARTSYS;
3042 break;
3043 }
3044
3045 /* get new irq counts */
3046 spin_lock_irqsave(&info->lock,flags);
3047 cnow = info->icount;
3048 set_current_state(TASK_INTERRUPTIBLE);
3049 spin_unlock_irqrestore(&info->lock,flags);
3050
3051 /* if no change, wait aborted for some reason */
3052 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3053 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3054 rc = -EIO;
3055 break;
3056 }
3057
3058 /* check for change in caller specified modem input */
3059 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3060 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3061 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3062 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3063 rc = 0;
3064 break;
3065 }
3066
3067 cprev = cnow;
3068 }
3069 remove_wait_queue(&info->status_event_wait_q, &wait);
3070 set_current_state(TASK_RUNNING);
3071 return rc;
3072}
3073
3074/*
3075 * return state of serial control and status signals
3076 */
3077static int tiocmget(struct tty_struct *tty)
3078{
3079 struct slgt_info *info = tty->driver_data;
3080 unsigned int result;
3081 unsigned long flags;
3082
3083 spin_lock_irqsave(&info->lock,flags);
3084 get_gtsignals(info);
3085 spin_unlock_irqrestore(&info->lock,flags);
3086
3087 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3088 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3089 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3090 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3091 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3092 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3093
3094 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3095 return result;
3096}
3097
3098/*
3099 * set modem control signals (DTR/RTS)
3100 *
3101 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3102 * TIOCMSET = set/clear signal values
3103 * value bit mask for command
3104 */
3105static int tiocmset(struct tty_struct *tty,
3106 unsigned int set, unsigned int clear)
3107{
3108 struct slgt_info *info = tty->driver_data;
3109 unsigned long flags;
3110
3111 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3112
3113 if (set & TIOCM_RTS)
3114 info->signals |= SerialSignal_RTS;
3115 if (set & TIOCM_DTR)
3116 info->signals |= SerialSignal_DTR;
3117 if (clear & TIOCM_RTS)
3118 info->signals &= ~SerialSignal_RTS;
3119 if (clear & TIOCM_DTR)
3120 info->signals &= ~SerialSignal_DTR;
3121
3122 spin_lock_irqsave(&info->lock,flags);
3123 set_gtsignals(info);
3124 spin_unlock_irqrestore(&info->lock,flags);
3125 return 0;
3126}
3127
3128static bool carrier_raised(struct tty_port *port)
3129{
3130 unsigned long flags;
3131 struct slgt_info *info = container_of(port, struct slgt_info, port);
3132
3133 spin_lock_irqsave(&info->lock,flags);
3134 get_gtsignals(info);
3135 spin_unlock_irqrestore(&info->lock,flags);
3136
3137 return info->signals & SerialSignal_DCD;
3138}
3139
3140static void dtr_rts(struct tty_port *port, bool active)
3141{
3142 unsigned long flags;
3143 struct slgt_info *info = container_of(port, struct slgt_info, port);
3144
3145 spin_lock_irqsave(&info->lock,flags);
3146 if (active)
3147 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3148 else
3149 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3150 set_gtsignals(info);
3151 spin_unlock_irqrestore(&info->lock,flags);
3152}
3153
3154
3155/*
3156 * block current process until the device is ready to open
3157 */
3158static int block_til_ready(struct tty_struct *tty, struct file *filp,
3159 struct slgt_info *info)
3160{
3161 DECLARE_WAITQUEUE(wait, current);
3162 int retval;
3163 bool do_clocal = false;
3164 unsigned long flags;
3165 bool cd;
3166 struct tty_port *port = &info->port;
3167
3168 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3169
3170 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3171 /* nonblock mode is set or port is not enabled */
3172 tty_port_set_active(port, true);
3173 return 0;
3174 }
3175
3176 if (C_CLOCAL(tty))
3177 do_clocal = true;
3178
3179 /* Wait for carrier detect and the line to become
3180 * free (i.e., not in use by the callout). While we are in
3181 * this loop, port->count is dropped by one, so that
3182 * close() knows when to free things. We restore it upon
3183 * exit, either normal or abnormal.
3184 */
3185
3186 retval = 0;
3187 add_wait_queue(&port->open_wait, &wait);
3188
3189 spin_lock_irqsave(&info->lock, flags);
3190 port->count--;
3191 spin_unlock_irqrestore(&info->lock, flags);
3192 port->blocked_open++;
3193
3194 while (1) {
3195 if (C_BAUD(tty) && tty_port_initialized(port))
3196 tty_port_raise_dtr_rts(port);
3197
3198 set_current_state(TASK_INTERRUPTIBLE);
3199
3200 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3201 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3202 -EAGAIN : -ERESTARTSYS;
3203 break;
3204 }
3205
3206 cd = tty_port_carrier_raised(port);
3207 if (do_clocal || cd)
3208 break;
3209
3210 if (signal_pending(current)) {
3211 retval = -ERESTARTSYS;
3212 break;
3213 }
3214
3215 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3216 tty_unlock(tty);
3217 schedule();
3218 tty_lock(tty);
3219 }
3220
3221 set_current_state(TASK_RUNNING);
3222 remove_wait_queue(&port->open_wait, &wait);
3223
3224 if (!tty_hung_up_p(filp))
3225 port->count++;
3226 port->blocked_open--;
3227
3228 if (!retval)
3229 tty_port_set_active(port, true);
3230
3231 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3232 return retval;
3233}
3234
3235/*
3236 * allocate buffers used for calling line discipline receive_buf
3237 * directly in synchronous mode
3238 * note: add 5 bytes to max frame size to allow appending
3239 * 32-bit CRC and status byte when configured to do so
3240 */
3241static int alloc_tmp_rbuf(struct slgt_info *info)
3242{
3243 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3244 if (info->tmp_rbuf == NULL)
3245 return -ENOMEM;
3246
3247 return 0;
3248}
3249
3250static void free_tmp_rbuf(struct slgt_info *info)
3251{
3252 kfree(info->tmp_rbuf);
3253 info->tmp_rbuf = NULL;
3254}
3255
3256/*
3257 * allocate DMA descriptor lists.
3258 */
3259static int alloc_desc(struct slgt_info *info)
3260{
3261 unsigned int i;
3262 unsigned int pbufs;
3263
3264 /* allocate memory to hold descriptor lists */
3265 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3266 &info->bufs_dma_addr, GFP_KERNEL);
3267 if (info->bufs == NULL)
3268 return -ENOMEM;
3269
3270 info->rbufs = (struct slgt_desc*)info->bufs;
3271 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3272
3273 pbufs = (unsigned int)info->bufs_dma_addr;
3274
3275 /*
3276 * Build circular lists of descriptors
3277 */
3278
3279 for (i=0; i < info->rbuf_count; i++) {
3280 /* physical address of this descriptor */
3281 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3282
3283 /* physical address of next descriptor */
3284 if (i == info->rbuf_count - 1)
3285 info->rbufs[i].next = cpu_to_le32(pbufs);
3286 else
3287 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3288 set_desc_count(info->rbufs[i], DMABUFSIZE);
3289 }
3290
3291 for (i=0; i < info->tbuf_count; i++) {
3292 /* physical address of this descriptor */
3293 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3294
3295 /* physical address of next descriptor */
3296 if (i == info->tbuf_count - 1)
3297 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3298 else
3299 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3300 }
3301
3302 return 0;
3303}
3304
3305static void free_desc(struct slgt_info *info)
3306{
3307 if (info->bufs != NULL) {
3308 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3309 info->bufs, info->bufs_dma_addr);
3310 info->bufs = NULL;
3311 info->rbufs = NULL;
3312 info->tbufs = NULL;
3313 }
3314}
3315
3316static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3317{
3318 int i;
3319 for (i=0; i < count; i++) {
3320 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3321 &bufs[i].buf_dma_addr, GFP_KERNEL);
3322 if (!bufs[i].buf)
3323 return -ENOMEM;
3324 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3325 }
3326 return 0;
3327}
3328
3329static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3330{
3331 int i;
3332 for (i=0; i < count; i++) {
3333 if (bufs[i].buf == NULL)
3334 continue;
3335 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3336 bufs[i].buf_dma_addr);
3337 bufs[i].buf = NULL;
3338 }
3339}
3340
3341static int alloc_dma_bufs(struct slgt_info *info)
3342{
3343 info->rbuf_count = 32;
3344 info->tbuf_count = 32;
3345
3346 if (alloc_desc(info) < 0 ||
3347 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3348 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3349 alloc_tmp_rbuf(info) < 0) {
3350 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3351 return -ENOMEM;
3352 }
3353 reset_rbufs(info);
3354 return 0;
3355}
3356
3357static void free_dma_bufs(struct slgt_info *info)
3358{
3359 if (info->bufs) {
3360 free_bufs(info, info->rbufs, info->rbuf_count);
3361 free_bufs(info, info->tbufs, info->tbuf_count);
3362 free_desc(info);
3363 }
3364 free_tmp_rbuf(info);
3365}
3366
3367static int claim_resources(struct slgt_info *info)
3368{
3369 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3370 DBGERR(("%s reg addr conflict, addr=%08X\n",
3371 info->device_name, info->phys_reg_addr));
3372 info->init_error = DiagStatus_AddressConflict;
3373 goto errout;
3374 }
3375 else
3376 info->reg_addr_requested = true;
3377
3378 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3379 if (!info->reg_addr) {
3380 DBGERR(("%s can't map device registers, addr=%08X\n",
3381 info->device_name, info->phys_reg_addr));
3382 info->init_error = DiagStatus_CantAssignPciResources;
3383 goto errout;
3384 }
3385 return 0;
3386
3387errout:
3388 release_resources(info);
3389 return -ENODEV;
3390}
3391
3392static void release_resources(struct slgt_info *info)
3393{
3394 if (info->irq_requested) {
3395 free_irq(info->irq_level, info);
3396 info->irq_requested = false;
3397 }
3398
3399 if (info->reg_addr_requested) {
3400 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3401 info->reg_addr_requested = false;
3402 }
3403
3404 if (info->reg_addr) {
3405 iounmap(info->reg_addr);
3406 info->reg_addr = NULL;
3407 }
3408}
3409
3410/* Add the specified device instance data structure to the
3411 * global linked list of devices and increment the device count.
3412 */
3413static void add_device(struct slgt_info *info)
3414{
3415 char *devstr;
3416
3417 info->next_device = NULL;
3418 info->line = slgt_device_count;
3419 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3420
3421 if (info->line < MAX_DEVICES) {
3422 if (maxframe[info->line])
3423 info->max_frame_size = maxframe[info->line];
3424 }
3425
3426 slgt_device_count++;
3427
3428 if (!slgt_device_list)
3429 slgt_device_list = info;
3430 else {
3431 struct slgt_info *current_dev = slgt_device_list;
3432 while(current_dev->next_device)
3433 current_dev = current_dev->next_device;
3434 current_dev->next_device = info;
3435 }
3436
3437 if (info->max_frame_size < 4096)
3438 info->max_frame_size = 4096;
3439 else if (info->max_frame_size > 65535)
3440 info->max_frame_size = 65535;
3441
3442 switch(info->pdev->device) {
3443 case SYNCLINK_GT_DEVICE_ID:
3444 devstr = "GT";
3445 break;
3446 case SYNCLINK_GT2_DEVICE_ID:
3447 devstr = "GT2";
3448 break;
3449 case SYNCLINK_GT4_DEVICE_ID:
3450 devstr = "GT4";
3451 break;
3452 case SYNCLINK_AC_DEVICE_ID:
3453 devstr = "AC";
3454 info->params.mode = MGSL_MODE_ASYNC;
3455 break;
3456 default:
3457 devstr = "(unknown model)";
3458 }
3459 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3460 devstr, info->device_name, info->phys_reg_addr,
3461 info->irq_level, info->max_frame_size);
3462
3463#if SYNCLINK_GENERIC_HDLC
3464 hdlcdev_init(info);
3465#endif
3466}
3467
3468static const struct tty_port_operations slgt_port_ops = {
3469 .carrier_raised = carrier_raised,
3470 .dtr_rts = dtr_rts,
3471};
3472
3473/*
3474 * allocate device instance structure, return NULL on failure
3475 */
3476static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3477{
3478 struct slgt_info *info;
3479
3480 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3481
3482 if (!info) {
3483 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3484 driver_name, adapter_num, port_num));
3485 } else {
3486 tty_port_init(&info->port);
3487 info->port.ops = &slgt_port_ops;
3488 INIT_WORK(&info->task, bh_handler);
3489 info->max_frame_size = 4096;
3490 info->base_clock = 14745600;
3491 info->rbuf_fill_level = DMABUFSIZE;
3492 init_waitqueue_head(&info->status_event_wait_q);
3493 init_waitqueue_head(&info->event_wait_q);
3494 spin_lock_init(&info->netlock);
3495 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3496 info->idle_mode = HDLC_TXIDLE_FLAGS;
3497 info->adapter_num = adapter_num;
3498 info->port_num = port_num;
3499
3500 timer_setup(&info->tx_timer, tx_timeout, 0);
3501 timer_setup(&info->rx_timer, rx_timeout, 0);
3502
3503 /* Copy configuration info to device instance data */
3504 info->pdev = pdev;
3505 info->irq_level = pdev->irq;
3506 info->phys_reg_addr = pci_resource_start(pdev,0);
3507
3508 info->bus_type = MGSL_BUS_TYPE_PCI;
3509 info->irq_flags = IRQF_SHARED;
3510
3511 info->init_error = -1; /* assume error, set to 0 on successful init */
3512 }
3513
3514 return info;
3515}
3516
3517static void device_init(int adapter_num, struct pci_dev *pdev)
3518{
3519 struct slgt_info *port_array[SLGT_MAX_PORTS];
3520 int i;
3521 int port_count = 1;
3522
3523 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3524 port_count = 2;
3525 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3526 port_count = 4;
3527
3528 /* allocate device instances for all ports */
3529 for (i=0; i < port_count; ++i) {
3530 port_array[i] = alloc_dev(adapter_num, i, pdev);
3531 if (port_array[i] == NULL) {
3532 for (--i; i >= 0; --i) {
3533 tty_port_destroy(&port_array[i]->port);
3534 kfree(port_array[i]);
3535 }
3536 return;
3537 }
3538 }
3539
3540 /* give copy of port_array to all ports and add to device list */
3541 for (i=0; i < port_count; ++i) {
3542 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3543 add_device(port_array[i]);
3544 port_array[i]->port_count = port_count;
3545 spin_lock_init(&port_array[i]->lock);
3546 }
3547
3548 /* Allocate and claim adapter resources */
3549 if (!claim_resources(port_array[0])) {
3550
3551 alloc_dma_bufs(port_array[0]);
3552
3553 /* copy resource information from first port to others */
3554 for (i = 1; i < port_count; ++i) {
3555 port_array[i]->irq_level = port_array[0]->irq_level;
3556 port_array[i]->reg_addr = port_array[0]->reg_addr;
3557 alloc_dma_bufs(port_array[i]);
3558 }
3559
3560 if (request_irq(port_array[0]->irq_level,
3561 slgt_interrupt,
3562 port_array[0]->irq_flags,
3563 port_array[0]->device_name,
3564 port_array[0]) < 0) {
3565 DBGERR(("%s request_irq failed IRQ=%d\n",
3566 port_array[0]->device_name,
3567 port_array[0]->irq_level));
3568 } else {
3569 port_array[0]->irq_requested = true;
3570 adapter_test(port_array[0]);
3571 for (i=1 ; i < port_count ; i++) {
3572 port_array[i]->init_error = port_array[0]->init_error;
3573 port_array[i]->gpio_present = port_array[0]->gpio_present;
3574 }
3575 }
3576 }
3577
3578 for (i = 0; i < port_count; ++i) {
3579 struct slgt_info *info = port_array[i];
3580 tty_port_register_device(&info->port, serial_driver, info->line,
3581 &info->pdev->dev);
3582 }
3583}
3584
3585static int init_one(struct pci_dev *dev,
3586 const struct pci_device_id *ent)
3587{
3588 if (pci_enable_device(dev)) {
3589 printk("error enabling pci device %p\n", dev);
3590 return -EIO;
3591 }
3592 pci_set_master(dev);
3593 device_init(slgt_device_count, dev);
3594 return 0;
3595}
3596
3597static void remove_one(struct pci_dev *dev)
3598{
3599}
3600
3601static const struct tty_operations ops = {
3602 .open = open,
3603 .close = close,
3604 .write = write,
3605 .put_char = put_char,
3606 .flush_chars = flush_chars,
3607 .write_room = write_room,
3608 .chars_in_buffer = chars_in_buffer,
3609 .flush_buffer = flush_buffer,
3610 .ioctl = ioctl,
3611 .compat_ioctl = slgt_compat_ioctl,
3612 .throttle = throttle,
3613 .unthrottle = unthrottle,
3614 .send_xchar = send_xchar,
3615 .break_ctl = set_break,
3616 .wait_until_sent = wait_until_sent,
3617 .set_termios = set_termios,
3618 .stop = tx_hold,
3619 .start = tx_release,
3620 .hangup = hangup,
3621 .tiocmget = tiocmget,
3622 .tiocmset = tiocmset,
3623 .get_icount = get_icount,
3624 .proc_show = synclink_gt_proc_show,
3625};
3626
3627static void slgt_cleanup(void)
3628{
3629 struct slgt_info *info;
3630 struct slgt_info *tmp;
3631
3632 if (serial_driver) {
3633 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3634 tty_unregister_device(serial_driver, info->line);
3635 tty_unregister_driver(serial_driver);
3636 tty_driver_kref_put(serial_driver);
3637 }
3638
3639 /* reset devices */
3640 info = slgt_device_list;
3641 while(info) {
3642 reset_port(info);
3643 info = info->next_device;
3644 }
3645
3646 /* release devices */
3647 info = slgt_device_list;
3648 while(info) {
3649#if SYNCLINK_GENERIC_HDLC
3650 hdlcdev_exit(info);
3651#endif
3652 free_dma_bufs(info);
3653 free_tmp_rbuf(info);
3654 if (info->port_num == 0)
3655 release_resources(info);
3656 tmp = info;
3657 info = info->next_device;
3658 tty_port_destroy(&tmp->port);
3659 kfree(tmp);
3660 }
3661
3662 if (pci_registered)
3663 pci_unregister_driver(&pci_driver);
3664}
3665
3666/*
3667 * Driver initialization entry point.
3668 */
3669static int __init slgt_init(void)
3670{
3671 int rc;
3672
3673 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3674 TTY_DRIVER_DYNAMIC_DEV);
3675 if (IS_ERR(serial_driver)) {
3676 printk("%s can't allocate tty driver\n", driver_name);
3677 return PTR_ERR(serial_driver);
3678 }
3679
3680 /* Initialize the tty_driver structure */
3681
3682 serial_driver->driver_name = "synclink_gt";
3683 serial_driver->name = tty_dev_prefix;
3684 serial_driver->major = ttymajor;
3685 serial_driver->minor_start = 64;
3686 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3687 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3688 serial_driver->init_termios = tty_std_termios;
3689 serial_driver->init_termios.c_cflag =
3690 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3691 serial_driver->init_termios.c_ispeed = 9600;
3692 serial_driver->init_termios.c_ospeed = 9600;
3693 tty_set_operations(serial_driver, &ops);
3694 if ((rc = tty_register_driver(serial_driver)) < 0) {
3695 DBGERR(("%s can't register serial driver\n", driver_name));
3696 tty_driver_kref_put(serial_driver);
3697 serial_driver = NULL;
3698 goto error;
3699 }
3700
3701 slgt_device_count = 0;
3702 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3703 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3704 goto error;
3705 }
3706 pci_registered = true;
3707
3708 return 0;
3709
3710error:
3711 slgt_cleanup();
3712 return rc;
3713}
3714
3715static void __exit slgt_exit(void)
3716{
3717 slgt_cleanup();
3718}
3719
3720module_init(slgt_init);
3721module_exit(slgt_exit);
3722
3723/*
3724 * register access routines
3725 */
3726
3727static inline void __iomem *calc_regaddr(struct slgt_info *info,
3728 unsigned int addr)
3729{
3730 void __iomem *reg_addr = info->reg_addr + addr;
3731
3732 if (addr >= 0x80)
3733 reg_addr += info->port_num * 32;
3734 else if (addr >= 0x40)
3735 reg_addr += info->port_num * 16;
3736
3737 return reg_addr;
3738}
3739
3740static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3741{
3742 return readb(calc_regaddr(info, addr));
3743}
3744
3745static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3746{
3747 writeb(value, calc_regaddr(info, addr));
3748}
3749
3750static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3751{
3752 return readw(calc_regaddr(info, addr));
3753}
3754
3755static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3756{
3757 writew(value, calc_regaddr(info, addr));
3758}
3759
3760static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3761{
3762 return readl(calc_regaddr(info, addr));
3763}
3764
3765static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3766{
3767 writel(value, calc_regaddr(info, addr));
3768}
3769
3770static void rdma_reset(struct slgt_info *info)
3771{
3772 unsigned int i;
3773
3774 /* set reset bit */
3775 wr_reg32(info, RDCSR, BIT1);
3776
3777 /* wait for enable bit cleared */
3778 for(i=0 ; i < 1000 ; i++)
3779 if (!(rd_reg32(info, RDCSR) & BIT0))
3780 break;
3781}
3782
3783static void tdma_reset(struct slgt_info *info)
3784{
3785 unsigned int i;
3786
3787 /* set reset bit */
3788 wr_reg32(info, TDCSR, BIT1);
3789
3790 /* wait for enable bit cleared */
3791 for(i=0 ; i < 1000 ; i++)
3792 if (!(rd_reg32(info, TDCSR) & BIT0))
3793 break;
3794}
3795
3796/*
3797 * enable internal loopback
3798 * TxCLK and RxCLK are generated from BRG
3799 * and TxD is looped back to RxD internally.
3800 */
3801static void enable_loopback(struct slgt_info *info)
3802{
3803 /* SCR (serial control) BIT2=loopback enable */
3804 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3805
3806 if (info->params.mode != MGSL_MODE_ASYNC) {
3807 /* CCR (clock control)
3808 * 07..05 tx clock source (010 = BRG)
3809 * 04..02 rx clock source (010 = BRG)
3810 * 01 auxclk enable (0 = disable)
3811 * 00 BRG enable (1 = enable)
3812 *
3813 * 0100 1001
3814 */
3815 wr_reg8(info, CCR, 0x49);
3816
3817 /* set speed if available, otherwise use default */
3818 if (info->params.clock_speed)
3819 set_rate(info, info->params.clock_speed);
3820 else
3821 set_rate(info, 3686400);
3822 }
3823}
3824
3825/*
3826 * set baud rate generator to specified rate
3827 */
3828static void set_rate(struct slgt_info *info, u32 rate)
3829{
3830 unsigned int div;
3831 unsigned int osc = info->base_clock;
3832
3833 /* div = osc/rate - 1
3834 *
3835 * Round div up if osc/rate is not integer to
3836 * force to next slowest rate.
3837 */
3838
3839 if (rate) {
3840 div = osc/rate;
3841 if (!(osc % rate) && div)
3842 div--;
3843 wr_reg16(info, BDR, (unsigned short)div);
3844 }
3845}
3846
3847static void rx_stop(struct slgt_info *info)
3848{
3849 unsigned short val;
3850
3851 /* disable and reset receiver */
3852 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3853 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3854 wr_reg16(info, RCR, val); /* clear reset bit */
3855
3856 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3857
3858 /* clear pending rx interrupts */
3859 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3860
3861 rdma_reset(info);
3862
3863 info->rx_enabled = false;
3864 info->rx_restart = false;
3865}
3866
3867static void rx_start(struct slgt_info *info)
3868{
3869 unsigned short val;
3870
3871 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3872
3873 /* clear pending rx overrun IRQ */
3874 wr_reg16(info, SSR, IRQ_RXOVER);
3875
3876 /* reset and disable receiver */
3877 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3878 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3879 wr_reg16(info, RCR, val); /* clear reset bit */
3880
3881 rdma_reset(info);
3882 reset_rbufs(info);
3883
3884 if (info->rx_pio) {
3885 /* rx request when rx FIFO not empty */
3886 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3887 slgt_irq_on(info, IRQ_RXDATA);
3888 if (info->params.mode == MGSL_MODE_ASYNC) {
3889 /* enable saving of rx status */
3890 wr_reg32(info, RDCSR, BIT6);
3891 }
3892 } else {
3893 /* rx request when rx FIFO half full */
3894 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3895 /* set 1st descriptor address */
3896 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3897
3898 if (info->params.mode != MGSL_MODE_ASYNC) {
3899 /* enable rx DMA and DMA interrupt */
3900 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3901 } else {
3902 /* enable saving of rx status, rx DMA and DMA interrupt */
3903 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3904 }
3905 }
3906
3907 slgt_irq_on(info, IRQ_RXOVER);
3908
3909 /* enable receiver */
3910 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3911
3912 info->rx_restart = false;
3913 info->rx_enabled = true;
3914}
3915
3916static void tx_start(struct slgt_info *info)
3917{
3918 if (!info->tx_enabled) {
3919 wr_reg16(info, TCR,
3920 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3921 info->tx_enabled = true;
3922 }
3923
3924 if (desc_count(info->tbufs[info->tbuf_start])) {
3925 info->drop_rts_on_tx_done = false;
3926
3927 if (info->params.mode != MGSL_MODE_ASYNC) {
3928 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3929 get_gtsignals(info);
3930 if (!(info->signals & SerialSignal_RTS)) {
3931 info->signals |= SerialSignal_RTS;
3932 set_gtsignals(info);
3933 info->drop_rts_on_tx_done = true;
3934 }
3935 }
3936
3937 slgt_irq_off(info, IRQ_TXDATA);
3938 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3939 /* clear tx idle and underrun status bits */
3940 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3941 } else {
3942 slgt_irq_off(info, IRQ_TXDATA);
3943 slgt_irq_on(info, IRQ_TXIDLE);
3944 /* clear tx idle status bit */
3945 wr_reg16(info, SSR, IRQ_TXIDLE);
3946 }
3947 /* set 1st descriptor address and start DMA */
3948 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3949 wr_reg32(info, TDCSR, BIT2 + BIT0);
3950 info->tx_active = true;
3951 }
3952}
3953
3954static void tx_stop(struct slgt_info *info)
3955{
3956 unsigned short val;
3957
3958 del_timer(&info->tx_timer);
3959
3960 tdma_reset(info);
3961
3962 /* reset and disable transmitter */
3963 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3964 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3965
3966 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3967
3968 /* clear tx idle and underrun status bit */
3969 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3970
3971 reset_tbufs(info);
3972
3973 info->tx_enabled = false;
3974 info->tx_active = false;
3975}
3976
3977static void reset_port(struct slgt_info *info)
3978{
3979 if (!info->reg_addr)
3980 return;
3981
3982 tx_stop(info);
3983 rx_stop(info);
3984
3985 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3986 set_gtsignals(info);
3987
3988 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3989}
3990
3991static void reset_adapter(struct slgt_info *info)
3992{
3993 int i;
3994 for (i=0; i < info->port_count; ++i) {
3995 if (info->port_array[i])
3996 reset_port(info->port_array[i]);
3997 }
3998}
3999
4000static void async_mode(struct slgt_info *info)
4001{
4002 unsigned short val;
4003
4004 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4005 tx_stop(info);
4006 rx_stop(info);
4007
4008 /* TCR (tx control)
4009 *
4010 * 15..13 mode, 010=async
4011 * 12..10 encoding, 000=NRZ
4012 * 09 parity enable
4013 * 08 1=odd parity, 0=even parity
4014 * 07 1=RTS driver control
4015 * 06 1=break enable
4016 * 05..04 character length
4017 * 00=5 bits
4018 * 01=6 bits
4019 * 10=7 bits
4020 * 11=8 bits
4021 * 03 0=1 stop bit, 1=2 stop bits
4022 * 02 reset
4023 * 01 enable
4024 * 00 auto-CTS enable
4025 */
4026 val = 0x4000;
4027
4028 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4029 val |= BIT7;
4030
4031 if (info->params.parity != ASYNC_PARITY_NONE) {
4032 val |= BIT9;
4033 if (info->params.parity == ASYNC_PARITY_ODD)
4034 val |= BIT8;
4035 }
4036
4037 switch (info->params.data_bits)
4038 {
4039 case 6: val |= BIT4; break;
4040 case 7: val |= BIT5; break;
4041 case 8: val |= BIT5 + BIT4; break;
4042 }
4043
4044 if (info->params.stop_bits != 1)
4045 val |= BIT3;
4046
4047 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4048 val |= BIT0;
4049
4050 wr_reg16(info, TCR, val);
4051
4052 /* RCR (rx control)
4053 *
4054 * 15..13 mode, 010=async
4055 * 12..10 encoding, 000=NRZ
4056 * 09 parity enable
4057 * 08 1=odd parity, 0=even parity
4058 * 07..06 reserved, must be 0
4059 * 05..04 character length
4060 * 00=5 bits
4061 * 01=6 bits
4062 * 10=7 bits
4063 * 11=8 bits
4064 * 03 reserved, must be zero
4065 * 02 reset
4066 * 01 enable
4067 * 00 auto-DCD enable
4068 */
4069 val = 0x4000;
4070
4071 if (info->params.parity != ASYNC_PARITY_NONE) {
4072 val |= BIT9;
4073 if (info->params.parity == ASYNC_PARITY_ODD)
4074 val |= BIT8;
4075 }
4076
4077 switch (info->params.data_bits)
4078 {
4079 case 6: val |= BIT4; break;
4080 case 7: val |= BIT5; break;
4081 case 8: val |= BIT5 + BIT4; break;
4082 }
4083
4084 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4085 val |= BIT0;
4086
4087 wr_reg16(info, RCR, val);
4088
4089 /* CCR (clock control)
4090 *
4091 * 07..05 011 = tx clock source is BRG/16
4092 * 04..02 010 = rx clock source is BRG
4093 * 01 0 = auxclk disabled
4094 * 00 1 = BRG enabled
4095 *
4096 * 0110 1001
4097 */
4098 wr_reg8(info, CCR, 0x69);
4099
4100 msc_set_vcr(info);
4101
4102 /* SCR (serial control)
4103 *
4104 * 15 1=tx req on FIFO half empty
4105 * 14 1=rx req on FIFO half full
4106 * 13 tx data IRQ enable
4107 * 12 tx idle IRQ enable
4108 * 11 rx break on IRQ enable
4109 * 10 rx data IRQ enable
4110 * 09 rx break off IRQ enable
4111 * 08 overrun IRQ enable
4112 * 07 DSR IRQ enable
4113 * 06 CTS IRQ enable
4114 * 05 DCD IRQ enable
4115 * 04 RI IRQ enable
4116 * 03 0=16x sampling, 1=8x sampling
4117 * 02 1=txd->rxd internal loopback enable
4118 * 01 reserved, must be zero
4119 * 00 1=master IRQ enable
4120 */
4121 val = BIT15 + BIT14 + BIT0;
4122 /* JCR[8] : 1 = x8 async mode feature available */
4123 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4124 ((info->base_clock < (info->params.data_rate * 16)) ||
4125 (info->base_clock % (info->params.data_rate * 16)))) {
4126 /* use 8x sampling */
4127 val |= BIT3;
4128 set_rate(info, info->params.data_rate * 8);
4129 } else {
4130 /* use 16x sampling */
4131 set_rate(info, info->params.data_rate * 16);
4132 }
4133 wr_reg16(info, SCR, val);
4134
4135 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4136
4137 if (info->params.loopback)
4138 enable_loopback(info);
4139}
4140
4141static void sync_mode(struct slgt_info *info)
4142{
4143 unsigned short val;
4144
4145 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4146 tx_stop(info);
4147 rx_stop(info);
4148
4149 /* TCR (tx control)
4150 *
4151 * 15..13 mode
4152 * 000=HDLC/SDLC
4153 * 001=raw bit synchronous
4154 * 010=asynchronous/isochronous
4155 * 011=monosync byte synchronous
4156 * 100=bisync byte synchronous
4157 * 101=xsync byte synchronous
4158 * 12..10 encoding
4159 * 09 CRC enable
4160 * 08 CRC32
4161 * 07 1=RTS driver control
4162 * 06 preamble enable
4163 * 05..04 preamble length
4164 * 03 share open/close flag
4165 * 02 reset
4166 * 01 enable
4167 * 00 auto-CTS enable
4168 */
4169 val = BIT2;
4170
4171 switch(info->params.mode) {
4172 case MGSL_MODE_XSYNC:
4173 val |= BIT15 + BIT13;
4174 break;
4175 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4176 case MGSL_MODE_BISYNC: val |= BIT15; break;
4177 case MGSL_MODE_RAW: val |= BIT13; break;
4178 }
4179 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4180 val |= BIT7;
4181
4182 switch(info->params.encoding)
4183 {
4184 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4185 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4186 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4187 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4188 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4189 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4190 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4191 }
4192
4193 switch (info->params.crc_type & HDLC_CRC_MASK)
4194 {
4195 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4196 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4197 }
4198
4199 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4200 val |= BIT6;
4201
4202 switch (info->params.preamble_length)
4203 {
4204 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4205 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4206 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4207 }
4208
4209 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4210 val |= BIT0;
4211
4212 wr_reg16(info, TCR, val);
4213
4214 /* TPR (transmit preamble) */
4215
4216 switch (info->params.preamble)
4217 {
4218 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4219 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4220 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4221 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4222 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4223 default: val = 0x7e; break;
4224 }
4225 wr_reg8(info, TPR, (unsigned char)val);
4226
4227 /* RCR (rx control)
4228 *
4229 * 15..13 mode
4230 * 000=HDLC/SDLC
4231 * 001=raw bit synchronous
4232 * 010=asynchronous/isochronous
4233 * 011=monosync byte synchronous
4234 * 100=bisync byte synchronous
4235 * 101=xsync byte synchronous
4236 * 12..10 encoding
4237 * 09 CRC enable
4238 * 08 CRC32
4239 * 07..03 reserved, must be 0
4240 * 02 reset
4241 * 01 enable
4242 * 00 auto-DCD enable
4243 */
4244 val = 0;
4245
4246 switch(info->params.mode) {
4247 case MGSL_MODE_XSYNC:
4248 val |= BIT15 + BIT13;
4249 break;
4250 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4251 case MGSL_MODE_BISYNC: val |= BIT15; break;
4252 case MGSL_MODE_RAW: val |= BIT13; break;
4253 }
4254
4255 switch(info->params.encoding)
4256 {
4257 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4258 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4259 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4260 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4261 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4262 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4263 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4264 }
4265
4266 switch (info->params.crc_type & HDLC_CRC_MASK)
4267 {
4268 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4269 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4270 }
4271
4272 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4273 val |= BIT0;
4274
4275 wr_reg16(info, RCR, val);
4276
4277 /* CCR (clock control)
4278 *
4279 * 07..05 tx clock source
4280 * 04..02 rx clock source
4281 * 01 auxclk enable
4282 * 00 BRG enable
4283 */
4284 val = 0;
4285
4286 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4287 {
4288 // when RxC source is DPLL, BRG generates 16X DPLL
4289 // reference clock, so take TxC from BRG/16 to get
4290 // transmit clock at actual data rate
4291 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4292 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4293 else
4294 val |= BIT6; /* 010, txclk = BRG */
4295 }
4296 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4297 val |= BIT7; /* 100, txclk = DPLL Input */
4298 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4299 val |= BIT5; /* 001, txclk = RXC Input */
4300
4301 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4302 val |= BIT3; /* 010, rxclk = BRG */
4303 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4304 val |= BIT4; /* 100, rxclk = DPLL */
4305 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4306 val |= BIT2; /* 001, rxclk = TXC Input */
4307
4308 if (info->params.clock_speed)
4309 val |= BIT1 + BIT0;
4310
4311 wr_reg8(info, CCR, (unsigned char)val);
4312
4313 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4314 {
4315 // program DPLL mode
4316 switch(info->params.encoding)
4317 {
4318 case HDLC_ENCODING_BIPHASE_MARK:
4319 case HDLC_ENCODING_BIPHASE_SPACE:
4320 val = BIT7; break;
4321 case HDLC_ENCODING_BIPHASE_LEVEL:
4322 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4323 val = BIT7 + BIT6; break;
4324 default: val = BIT6; // NRZ encodings
4325 }
4326 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4327
4328 // DPLL requires a 16X reference clock from BRG
4329 set_rate(info, info->params.clock_speed * 16);
4330 }
4331 else
4332 set_rate(info, info->params.clock_speed);
4333
4334 tx_set_idle(info);
4335
4336 msc_set_vcr(info);
4337
4338 /* SCR (serial control)
4339 *
4340 * 15 1=tx req on FIFO half empty
4341 * 14 1=rx req on FIFO half full
4342 * 13 tx data IRQ enable
4343 * 12 tx idle IRQ enable
4344 * 11 underrun IRQ enable
4345 * 10 rx data IRQ enable
4346 * 09 rx idle IRQ enable
4347 * 08 overrun IRQ enable
4348 * 07 DSR IRQ enable
4349 * 06 CTS IRQ enable
4350 * 05 DCD IRQ enable
4351 * 04 RI IRQ enable
4352 * 03 reserved, must be zero
4353 * 02 1=txd->rxd internal loopback enable
4354 * 01 reserved, must be zero
4355 * 00 1=master IRQ enable
4356 */
4357 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4358
4359 if (info->params.loopback)
4360 enable_loopback(info);
4361}
4362
4363/*
4364 * set transmit idle mode
4365 */
4366static void tx_set_idle(struct slgt_info *info)
4367{
4368 unsigned char val;
4369 unsigned short tcr;
4370
4371 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4372 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4373 */
4374 tcr = rd_reg16(info, TCR);
4375 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4376 /* disable preamble, set idle size to 16 bits */
4377 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4378 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4379 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4380 } else if (!(tcr & BIT6)) {
4381 /* preamble is disabled, set idle size to 8 bits */
4382 tcr &= ~(BIT5 + BIT4);
4383 }
4384 wr_reg16(info, TCR, tcr);
4385
4386 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4387 /* LSB of custom tx idle specified in tx idle register */
4388 val = (unsigned char)(info->idle_mode & 0xff);
4389 } else {
4390 /* standard 8 bit idle patterns */
4391 switch(info->idle_mode)
4392 {
4393 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4394 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4395 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4396 case HDLC_TXIDLE_ZEROS:
4397 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4398 default: val = 0xff;
4399 }
4400 }
4401
4402 wr_reg8(info, TIR, val);
4403}
4404
4405/*
4406 * get state of V24 status (input) signals
4407 */
4408static void get_gtsignals(struct slgt_info *info)
4409{
4410 unsigned short status = rd_reg16(info, SSR);
4411
4412 /* clear all serial signals except RTS and DTR */
4413 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4414
4415 if (status & BIT3)
4416 info->signals |= SerialSignal_DSR;
4417 if (status & BIT2)
4418 info->signals |= SerialSignal_CTS;
4419 if (status & BIT1)
4420 info->signals |= SerialSignal_DCD;
4421 if (status & BIT0)
4422 info->signals |= SerialSignal_RI;
4423}
4424
4425/*
4426 * set V.24 Control Register based on current configuration
4427 */
4428static void msc_set_vcr(struct slgt_info *info)
4429{
4430 unsigned char val = 0;
4431
4432 /* VCR (V.24 control)
4433 *
4434 * 07..04 serial IF select
4435 * 03 DTR
4436 * 02 RTS
4437 * 01 LL
4438 * 00 RL
4439 */
4440
4441 switch(info->if_mode & MGSL_INTERFACE_MASK)
4442 {
4443 case MGSL_INTERFACE_RS232:
4444 val |= BIT5; /* 0010 */
4445 break;
4446 case MGSL_INTERFACE_V35:
4447 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4448 break;
4449 case MGSL_INTERFACE_RS422:
4450 val |= BIT6; /* 0100 */
4451 break;
4452 }
4453
4454 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4455 val |= BIT4;
4456 if (info->signals & SerialSignal_DTR)
4457 val |= BIT3;
4458 if (info->signals & SerialSignal_RTS)
4459 val |= BIT2;
4460 if (info->if_mode & MGSL_INTERFACE_LL)
4461 val |= BIT1;
4462 if (info->if_mode & MGSL_INTERFACE_RL)
4463 val |= BIT0;
4464 wr_reg8(info, VCR, val);
4465}
4466
4467/*
4468 * set state of V24 control (output) signals
4469 */
4470static void set_gtsignals(struct slgt_info *info)
4471{
4472 unsigned char val = rd_reg8(info, VCR);
4473 if (info->signals & SerialSignal_DTR)
4474 val |= BIT3;
4475 else
4476 val &= ~BIT3;
4477 if (info->signals & SerialSignal_RTS)
4478 val |= BIT2;
4479 else
4480 val &= ~BIT2;
4481 wr_reg8(info, VCR, val);
4482}
4483
4484/*
4485 * free range of receive DMA buffers (i to last)
4486 */
4487static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4488{
4489 int done = 0;
4490
4491 while(!done) {
4492 /* reset current buffer for reuse */
4493 info->rbufs[i].status = 0;
4494 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4495 if (i == last)
4496 done = 1;
4497 if (++i == info->rbuf_count)
4498 i = 0;
4499 }
4500 info->rbuf_current = i;
4501}
4502
4503/*
4504 * mark all receive DMA buffers as free
4505 */
4506static void reset_rbufs(struct slgt_info *info)
4507{
4508 free_rbufs(info, 0, info->rbuf_count - 1);
4509 info->rbuf_fill_index = 0;
4510 info->rbuf_fill_count = 0;
4511}
4512
4513/*
4514 * pass receive HDLC frame to upper layer
4515 *
4516 * return true if frame available, otherwise false
4517 */
4518static bool rx_get_frame(struct slgt_info *info)
4519{
4520 unsigned int start, end;
4521 unsigned short status;
4522 unsigned int framesize = 0;
4523 unsigned long flags;
4524 struct tty_struct *tty = info->port.tty;
4525 unsigned char addr_field = 0xff;
4526 unsigned int crc_size = 0;
4527
4528 switch (info->params.crc_type & HDLC_CRC_MASK) {
4529 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4530 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4531 }
4532
4533check_again:
4534
4535 framesize = 0;
4536 addr_field = 0xff;
4537 start = end = info->rbuf_current;
4538
4539 for (;;) {
4540 if (!desc_complete(info->rbufs[end]))
4541 goto cleanup;
4542
4543 if (framesize == 0 && info->params.addr_filter != 0xff)
4544 addr_field = info->rbufs[end].buf[0];
4545
4546 framesize += desc_count(info->rbufs[end]);
4547
4548 if (desc_eof(info->rbufs[end]))
4549 break;
4550
4551 if (++end == info->rbuf_count)
4552 end = 0;
4553
4554 if (end == info->rbuf_current) {
4555 if (info->rx_enabled){
4556 spin_lock_irqsave(&info->lock,flags);
4557 rx_start(info);
4558 spin_unlock_irqrestore(&info->lock,flags);
4559 }
4560 goto cleanup;
4561 }
4562 }
4563
4564 /* status
4565 *
4566 * 15 buffer complete
4567 * 14..06 reserved
4568 * 05..04 residue
4569 * 02 eof (end of frame)
4570 * 01 CRC error
4571 * 00 abort
4572 */
4573 status = desc_status(info->rbufs[end]);
4574
4575 /* ignore CRC bit if not using CRC (bit is undefined) */
4576 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4577 status &= ~BIT1;
4578
4579 if (framesize == 0 ||
4580 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4581 free_rbufs(info, start, end);
4582 goto check_again;
4583 }
4584
4585 if (framesize < (2 + crc_size) || status & BIT0) {
4586 info->icount.rxshort++;
4587 framesize = 0;
4588 } else if (status & BIT1) {
4589 info->icount.rxcrc++;
4590 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4591 framesize = 0;
4592 }
4593
4594#if SYNCLINK_GENERIC_HDLC
4595 if (framesize == 0) {
4596 info->netdev->stats.rx_errors++;
4597 info->netdev->stats.rx_frame_errors++;
4598 }
4599#endif
4600
4601 DBGBH(("%s rx frame status=%04X size=%d\n",
4602 info->device_name, status, framesize));
4603 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4604
4605 if (framesize) {
4606 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4607 framesize -= crc_size;
4608 crc_size = 0;
4609 }
4610
4611 if (framesize > info->max_frame_size + crc_size)
4612 info->icount.rxlong++;
4613 else {
4614 /* copy dma buffer(s) to contiguous temp buffer */
4615 int copy_count = framesize;
4616 int i = start;
4617 unsigned char *p = info->tmp_rbuf;
4618 info->tmp_rbuf_count = framesize;
4619
4620 info->icount.rxok++;
4621
4622 while(copy_count) {
4623 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4624 memcpy(p, info->rbufs[i].buf, partial_count);
4625 p += partial_count;
4626 copy_count -= partial_count;
4627 if (++i == info->rbuf_count)
4628 i = 0;
4629 }
4630
4631 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4632 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4633 framesize++;
4634 }
4635
4636#if SYNCLINK_GENERIC_HDLC
4637 if (info->netcount)
4638 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4639 else
4640#endif
4641 ldisc_receive_buf(tty, info->tmp_rbuf, NULL,
4642 framesize);
4643 }
4644 }
4645 free_rbufs(info, start, end);
4646 return true;
4647
4648cleanup:
4649 return false;
4650}
4651
4652/*
4653 * pass receive buffer (RAW synchronous mode) to tty layer
4654 * return true if buffer available, otherwise false
4655 */
4656static bool rx_get_buf(struct slgt_info *info)
4657{
4658 unsigned int i = info->rbuf_current;
4659 unsigned int count;
4660
4661 if (!desc_complete(info->rbufs[i]))
4662 return false;
4663 count = desc_count(info->rbufs[i]);
4664 switch(info->params.mode) {
4665 case MGSL_MODE_MONOSYNC:
4666 case MGSL_MODE_BISYNC:
4667 case MGSL_MODE_XSYNC:
4668 /* ignore residue in byte synchronous modes */
4669 if (desc_residue(info->rbufs[i]))
4670 count--;
4671 break;
4672 }
4673 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4674 DBGINFO(("rx_get_buf size=%d\n", count));
4675 if (count)
4676 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, NULL,
4677 count);
4678 free_rbufs(info, i, i);
4679 return true;
4680}
4681
4682static void reset_tbufs(struct slgt_info *info)
4683{
4684 unsigned int i;
4685 info->tbuf_current = 0;
4686 for (i=0 ; i < info->tbuf_count ; i++) {
4687 info->tbufs[i].status = 0;
4688 info->tbufs[i].count = 0;
4689 }
4690}
4691
4692/*
4693 * return number of free transmit DMA buffers
4694 */
4695static unsigned int free_tbuf_count(struct slgt_info *info)
4696{
4697 unsigned int count = 0;
4698 unsigned int i = info->tbuf_current;
4699
4700 do
4701 {
4702 if (desc_count(info->tbufs[i]))
4703 break; /* buffer in use */
4704 ++count;
4705 if (++i == info->tbuf_count)
4706 i=0;
4707 } while (i != info->tbuf_current);
4708
4709 /* if tx DMA active, last zero count buffer is in use */
4710 if (count && (rd_reg32(info, TDCSR) & BIT0))
4711 --count;
4712
4713 return count;
4714}
4715
4716/*
4717 * return number of bytes in unsent transmit DMA buffers
4718 * and the serial controller tx FIFO
4719 */
4720static unsigned int tbuf_bytes(struct slgt_info *info)
4721{
4722 unsigned int total_count = 0;
4723 unsigned int i = info->tbuf_current;
4724 unsigned int reg_value;
4725 unsigned int count;
4726 unsigned int active_buf_count = 0;
4727
4728 /*
4729 * Add descriptor counts for all tx DMA buffers.
4730 * If count is zero (cleared by DMA controller after read),
4731 * the buffer is complete or is actively being read from.
4732 *
4733 * Record buf_count of last buffer with zero count starting
4734 * from current ring position. buf_count is mirror
4735 * copy of count and is not cleared by serial controller.
4736 * If DMA controller is active, that buffer is actively
4737 * being read so add to total.
4738 */
4739 do {
4740 count = desc_count(info->tbufs[i]);
4741 if (count)
4742 total_count += count;
4743 else if (!total_count)
4744 active_buf_count = info->tbufs[i].buf_count;
4745 if (++i == info->tbuf_count)
4746 i = 0;
4747 } while (i != info->tbuf_current);
4748
4749 /* read tx DMA status register */
4750 reg_value = rd_reg32(info, TDCSR);
4751
4752 /* if tx DMA active, last zero count buffer is in use */
4753 if (reg_value & BIT0)
4754 total_count += active_buf_count;
4755
4756 /* add tx FIFO count = reg_value[15..8] */
4757 total_count += (reg_value >> 8) & 0xff;
4758
4759 /* if transmitter active add one byte for shift register */
4760 if (info->tx_active)
4761 total_count++;
4762
4763 return total_count;
4764}
4765
4766/*
4767 * load data into transmit DMA buffer ring and start transmitter if needed
4768 * return true if data accepted, otherwise false (buffers full)
4769 */
4770static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int size)
4771{
4772 unsigned short count;
4773 unsigned int i;
4774 struct slgt_desc *d;
4775
4776 /* check required buffer space */
4777 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4778 return false;
4779
4780 DBGDATA(info, buf, size, "tx");
4781
4782 /*
4783 * copy data to one or more DMA buffers in circular ring
4784 * tbuf_start = first buffer for this data
4785 * tbuf_current = next free buffer
4786 *
4787 * Copy all data before making data visible to DMA controller by
4788 * setting descriptor count of the first buffer.
4789 * This prevents an active DMA controller from reading the first DMA
4790 * buffers of a frame and stopping before the final buffers are filled.
4791 */
4792
4793 info->tbuf_start = i = info->tbuf_current;
4794
4795 while (size) {
4796 d = &info->tbufs[i];
4797
4798 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4799 memcpy(d->buf, buf, count);
4800
4801 size -= count;
4802 buf += count;
4803
4804 /*
4805 * set EOF bit for last buffer of HDLC frame or
4806 * for every buffer in raw mode
4807 */
4808 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4809 info->params.mode == MGSL_MODE_RAW)
4810 set_desc_eof(*d, 1);
4811 else
4812 set_desc_eof(*d, 0);
4813
4814 /* set descriptor count for all but first buffer */
4815 if (i != info->tbuf_start)
4816 set_desc_count(*d, count);
4817 d->buf_count = count;
4818
4819 if (++i == info->tbuf_count)
4820 i = 0;
4821 }
4822
4823 info->tbuf_current = i;
4824
4825 /* set first buffer count to make new data visible to DMA controller */
4826 d = &info->tbufs[info->tbuf_start];
4827 set_desc_count(*d, d->buf_count);
4828
4829 /* start transmitter if needed and update transmit timeout */
4830 if (!info->tx_active)
4831 tx_start(info);
4832 update_tx_timer(info);
4833
4834 return true;
4835}
4836
4837static int register_test(struct slgt_info *info)
4838{
4839 static unsigned short patterns[] =
4840 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4841 static unsigned int count = ARRAY_SIZE(patterns);
4842 unsigned int i;
4843 int rc = 0;
4844
4845 for (i=0 ; i < count ; i++) {
4846 wr_reg16(info, TIR, patterns[i]);
4847 wr_reg16(info, BDR, patterns[(i+1)%count]);
4848 if ((rd_reg16(info, TIR) != patterns[i]) ||
4849 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4850 rc = -ENODEV;
4851 break;
4852 }
4853 }
4854 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4855 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4856 return rc;
4857}
4858
4859static int irq_test(struct slgt_info *info)
4860{
4861 unsigned long timeout;
4862 unsigned long flags;
4863 struct tty_struct *oldtty = info->port.tty;
4864 u32 speed = info->params.data_rate;
4865
4866 info->params.data_rate = 921600;
4867 info->port.tty = NULL;
4868
4869 spin_lock_irqsave(&info->lock, flags);
4870 async_mode(info);
4871 slgt_irq_on(info, IRQ_TXIDLE);
4872
4873 /* enable transmitter */
4874 wr_reg16(info, TCR,
4875 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4876
4877 /* write one byte and wait for tx idle */
4878 wr_reg16(info, TDR, 0);
4879
4880 /* assume failure */
4881 info->init_error = DiagStatus_IrqFailure;
4882 info->irq_occurred = false;
4883
4884 spin_unlock_irqrestore(&info->lock, flags);
4885
4886 timeout=100;
4887 while(timeout-- && !info->irq_occurred)
4888 msleep_interruptible(10);
4889
4890 spin_lock_irqsave(&info->lock,flags);
4891 reset_port(info);
4892 spin_unlock_irqrestore(&info->lock,flags);
4893
4894 info->params.data_rate = speed;
4895 info->port.tty = oldtty;
4896
4897 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4898 return info->irq_occurred ? 0 : -ENODEV;
4899}
4900
4901static int loopback_test_rx(struct slgt_info *info)
4902{
4903 unsigned char *src, *dest;
4904 int count;
4905
4906 if (desc_complete(info->rbufs[0])) {
4907 count = desc_count(info->rbufs[0]);
4908 src = info->rbufs[0].buf;
4909 dest = info->tmp_rbuf;
4910
4911 for( ; count ; count-=2, src+=2) {
4912 /* src=data byte (src+1)=status byte */
4913 if (!(*(src+1) & (BIT9 + BIT8))) {
4914 *dest = *src;
4915 dest++;
4916 info->tmp_rbuf_count++;
4917 }
4918 }
4919 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4920 return 1;
4921 }
4922 return 0;
4923}
4924
4925static int loopback_test(struct slgt_info *info)
4926{
4927#define TESTFRAMESIZE 20
4928
4929 unsigned long timeout;
4930 u16 count;
4931 unsigned char buf[TESTFRAMESIZE];
4932 int rc = -ENODEV;
4933 unsigned long flags;
4934
4935 struct tty_struct *oldtty = info->port.tty;
4936 MGSL_PARAMS params;
4937
4938 memcpy(¶ms, &info->params, sizeof(params));
4939
4940 info->params.mode = MGSL_MODE_ASYNC;
4941 info->params.data_rate = 921600;
4942 info->params.loopback = 1;
4943 info->port.tty = NULL;
4944
4945 /* build and send transmit frame */
4946 for (count = 0; count < TESTFRAMESIZE; ++count)
4947 buf[count] = (unsigned char)count;
4948
4949 info->tmp_rbuf_count = 0;
4950 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4951
4952 /* program hardware for HDLC and enabled receiver */
4953 spin_lock_irqsave(&info->lock,flags);
4954 async_mode(info);
4955 rx_start(info);
4956 tx_load(info, buf, count);
4957 spin_unlock_irqrestore(&info->lock, flags);
4958
4959 /* wait for receive complete */
4960 for (timeout = 100; timeout; --timeout) {
4961 msleep_interruptible(10);
4962 if (loopback_test_rx(info)) {
4963 rc = 0;
4964 break;
4965 }
4966 }
4967
4968 /* verify received frame length and contents */
4969 if (!rc && (info->tmp_rbuf_count != count ||
4970 memcmp(buf, info->tmp_rbuf, count))) {
4971 rc = -ENODEV;
4972 }
4973
4974 spin_lock_irqsave(&info->lock,flags);
4975 reset_adapter(info);
4976 spin_unlock_irqrestore(&info->lock,flags);
4977
4978 memcpy(&info->params, ¶ms, sizeof(info->params));
4979 info->port.tty = oldtty;
4980
4981 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4982 return rc;
4983}
4984
4985static int adapter_test(struct slgt_info *info)
4986{
4987 DBGINFO(("testing %s\n", info->device_name));
4988 if (register_test(info) < 0) {
4989 printk("register test failure %s addr=%08X\n",
4990 info->device_name, info->phys_reg_addr);
4991 } else if (irq_test(info) < 0) {
4992 printk("IRQ test failure %s IRQ=%d\n",
4993 info->device_name, info->irq_level);
4994 } else if (loopback_test(info) < 0) {
4995 printk("loopback test failure %s\n", info->device_name);
4996 }
4997 return info->init_error;
4998}
4999
5000/*
5001 * transmit timeout handler
5002 */
5003static void tx_timeout(struct timer_list *t)
5004{
5005 struct slgt_info *info = from_timer(info, t, tx_timer);
5006 unsigned long flags;
5007
5008 DBGINFO(("%s tx_timeout\n", info->device_name));
5009 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5010 info->icount.txtimeout++;
5011 }
5012 spin_lock_irqsave(&info->lock,flags);
5013 tx_stop(info);
5014 spin_unlock_irqrestore(&info->lock,flags);
5015
5016#if SYNCLINK_GENERIC_HDLC
5017 if (info->netcount)
5018 hdlcdev_tx_done(info);
5019 else
5020#endif
5021 bh_transmit(info);
5022}
5023
5024/*
5025 * receive buffer polling timer
5026 */
5027static void rx_timeout(struct timer_list *t)
5028{
5029 struct slgt_info *info = from_timer(info, t, rx_timer);
5030 unsigned long flags;
5031
5032 DBGINFO(("%s rx_timeout\n", info->device_name));
5033 spin_lock_irqsave(&info->lock, flags);
5034 info->pending_bh |= BH_RECEIVE;
5035 spin_unlock_irqrestore(&info->lock, flags);
5036 bh_handler(&info->task);
5037}
5038
1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
91static char *slgt_driver_name = "synclink_gt";
92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MGSL_MAGIC 0x5401
95#define MAX_DEVICES 32
96
97static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
103};
104MODULE_DEVICE_TABLE(pci, pci_table);
105
106static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107static void remove_one(struct pci_dev *dev);
108static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
111 .probe = init_one,
112 .remove = remove_one,
113};
114
115static bool pci_registered;
116
117/*
118 * module configuration and status
119 */
120static struct slgt_info *slgt_device_list;
121static int slgt_device_count;
122
123static int ttymajor;
124static int debug_level;
125static int maxframe[MAX_DEVICES];
126
127module_param(ttymajor, int, 0);
128module_param(debug_level, int, 0);
129module_param_array(maxframe, int, NULL, 0);
130
131MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
134
135/*
136 * tty support and callbacks
137 */
138static struct tty_driver *serial_driver;
139
140static int open(struct tty_struct *tty, struct file * filp);
141static void close(struct tty_struct *tty, struct file * filp);
142static void hangup(struct tty_struct *tty);
143static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
144
145static int write(struct tty_struct *tty, const unsigned char *buf, int count);
146static int put_char(struct tty_struct *tty, unsigned char ch);
147static void send_xchar(struct tty_struct *tty, char ch);
148static void wait_until_sent(struct tty_struct *tty, int timeout);
149static int write_room(struct tty_struct *tty);
150static void flush_chars(struct tty_struct *tty);
151static void flush_buffer(struct tty_struct *tty);
152static void tx_hold(struct tty_struct *tty);
153static void tx_release(struct tty_struct *tty);
154
155static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
156static int chars_in_buffer(struct tty_struct *tty);
157static void throttle(struct tty_struct * tty);
158static void unthrottle(struct tty_struct * tty);
159static int set_break(struct tty_struct *tty, int break_state);
160
161/*
162 * generic HDLC support and callbacks
163 */
164#if SYNCLINK_GENERIC_HDLC
165#define dev_to_port(D) (dev_to_hdlc(D)->priv)
166static void hdlcdev_tx_done(struct slgt_info *info);
167static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
168static int hdlcdev_init(struct slgt_info *info);
169static void hdlcdev_exit(struct slgt_info *info);
170#endif
171
172
173/*
174 * device specific structures, macros and functions
175 */
176
177#define SLGT_MAX_PORTS 4
178#define SLGT_REG_SIZE 256
179
180/*
181 * conditional wait facility
182 */
183struct cond_wait {
184 struct cond_wait *next;
185 wait_queue_head_t q;
186 wait_queue_entry_t wait;
187 unsigned int data;
188};
189static void init_cond_wait(struct cond_wait *w, unsigned int data);
190static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
191static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void flush_cond_wait(struct cond_wait **head);
193
194/*
195 * DMA buffer descriptor and access macros
196 */
197struct slgt_desc
198{
199 __le16 count;
200 __le16 status;
201 __le32 pbuf; /* physical address of data buffer */
202 __le32 next; /* physical address of next descriptor */
203
204 /* driver book keeping */
205 char *buf; /* virtual address of data buffer */
206 unsigned int pdesc; /* physical address of this descriptor */
207 dma_addr_t buf_dma_addr;
208 unsigned short buf_count;
209};
210
211#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
212#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
213#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
214#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
215#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
216#define desc_count(a) (le16_to_cpu((a).count))
217#define desc_status(a) (le16_to_cpu((a).status))
218#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
219#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
220#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
221#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
222#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
223
224struct _input_signal_events {
225 int ri_up;
226 int ri_down;
227 int dsr_up;
228 int dsr_down;
229 int dcd_up;
230 int dcd_down;
231 int cts_up;
232 int cts_down;
233};
234
235/*
236 * device instance data structure
237 */
238struct slgt_info {
239 void *if_ptr; /* General purpose pointer (used by SPPP) */
240 struct tty_port port;
241
242 struct slgt_info *next_device; /* device list link */
243
244 int magic;
245
246 char device_name[25];
247 struct pci_dev *pdev;
248
249 int port_count; /* count of ports on adapter */
250 int adapter_num; /* adapter instance number */
251 int port_num; /* port instance number */
252
253 /* array of pointers to port contexts on this adapter */
254 struct slgt_info *port_array[SLGT_MAX_PORTS];
255
256 int line; /* tty line instance number */
257
258 struct mgsl_icount icount;
259
260 int timeout;
261 int x_char; /* xon/xoff character */
262 unsigned int read_status_mask;
263 unsigned int ignore_status_mask;
264
265 wait_queue_head_t status_event_wait_q;
266 wait_queue_head_t event_wait_q;
267 struct timer_list tx_timer;
268 struct timer_list rx_timer;
269
270 unsigned int gpio_present;
271 struct cond_wait *gpio_wait_q;
272
273 spinlock_t lock; /* spinlock for synchronizing with ISR */
274
275 struct work_struct task;
276 u32 pending_bh;
277 bool bh_requested;
278 bool bh_running;
279
280 int isr_overflow;
281 bool irq_requested; /* true if IRQ requested */
282 bool irq_occurred; /* for diagnostics use */
283
284 /* device configuration */
285
286 unsigned int bus_type;
287 unsigned int irq_level;
288 unsigned long irq_flags;
289
290 unsigned char __iomem * reg_addr; /* memory mapped registers address */
291 u32 phys_reg_addr;
292 bool reg_addr_requested;
293
294 MGSL_PARAMS params; /* communications parameters */
295 u32 idle_mode;
296 u32 max_frame_size; /* as set by device config */
297
298 unsigned int rbuf_fill_level;
299 unsigned int rx_pio;
300 unsigned int if_mode;
301 unsigned int base_clock;
302 unsigned int xsync;
303 unsigned int xctrl;
304
305 /* device status */
306
307 bool rx_enabled;
308 bool rx_restart;
309
310 bool tx_enabled;
311 bool tx_active;
312
313 unsigned char signals; /* serial signal states */
314 int init_error; /* initialization error */
315
316 unsigned char *tx_buf;
317 int tx_count;
318
319 char *flag_buf;
320 bool drop_rts_on_tx_done;
321 struct _input_signal_events input_signal_events;
322
323 int dcd_chkcount; /* check counts to prevent */
324 int cts_chkcount; /* too many IRQs if a signal */
325 int dsr_chkcount; /* is floating */
326 int ri_chkcount;
327
328 char *bufs; /* virtual address of DMA buffer lists */
329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
330
331 unsigned int rbuf_count;
332 struct slgt_desc *rbufs;
333 unsigned int rbuf_current;
334 unsigned int rbuf_index;
335 unsigned int rbuf_fill_index;
336 unsigned short rbuf_fill_count;
337
338 unsigned int tbuf_count;
339 struct slgt_desc *tbufs;
340 unsigned int tbuf_current;
341 unsigned int tbuf_start;
342
343 unsigned char *tmp_rbuf;
344 unsigned int tmp_rbuf_count;
345
346 /* SPPP/Cisco HDLC device parts */
347
348 int netcount;
349 spinlock_t netlock;
350#if SYNCLINK_GENERIC_HDLC
351 struct net_device *netdev;
352#endif
353
354};
355
356static MGSL_PARAMS default_params = {
357 .mode = MGSL_MODE_HDLC,
358 .loopback = 0,
359 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
360 .encoding = HDLC_ENCODING_NRZI_SPACE,
361 .clock_speed = 0,
362 .addr_filter = 0xff,
363 .crc_type = HDLC_CRC_16_CCITT,
364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
365 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
366 .data_rate = 9600,
367 .data_bits = 8,
368 .stop_bits = 1,
369 .parity = ASYNC_PARITY_NONE
370};
371
372
373#define BH_RECEIVE 1
374#define BH_TRANSMIT 2
375#define BH_STATUS 4
376#define IO_PIN_SHUTDOWN_LIMIT 100
377
378#define DMABUFSIZE 256
379#define DESC_LIST_SIZE 4096
380
381#define MASK_PARITY BIT1
382#define MASK_FRAMING BIT0
383#define MASK_BREAK BIT14
384#define MASK_OVERRUN BIT4
385
386#define GSR 0x00 /* global status */
387#define JCR 0x04 /* JTAG control */
388#define IODR 0x08 /* GPIO direction */
389#define IOER 0x0c /* GPIO interrupt enable */
390#define IOVR 0x10 /* GPIO value */
391#define IOSR 0x14 /* GPIO interrupt status */
392#define TDR 0x80 /* tx data */
393#define RDR 0x80 /* rx data */
394#define TCR 0x82 /* tx control */
395#define TIR 0x84 /* tx idle */
396#define TPR 0x85 /* tx preamble */
397#define RCR 0x86 /* rx control */
398#define VCR 0x88 /* V.24 control */
399#define CCR 0x89 /* clock control */
400#define BDR 0x8a /* baud divisor */
401#define SCR 0x8c /* serial control */
402#define SSR 0x8e /* serial status */
403#define RDCSR 0x90 /* rx DMA control/status */
404#define TDCSR 0x94 /* tx DMA control/status */
405#define RDDAR 0x98 /* rx DMA descriptor address */
406#define TDDAR 0x9c /* tx DMA descriptor address */
407#define XSR 0x40 /* extended sync pattern */
408#define XCR 0x44 /* extended control */
409
410#define RXIDLE BIT14
411#define RXBREAK BIT14
412#define IRQ_TXDATA BIT13
413#define IRQ_TXIDLE BIT12
414#define IRQ_TXUNDER BIT11 /* HDLC */
415#define IRQ_RXDATA BIT10
416#define IRQ_RXIDLE BIT9 /* HDLC */
417#define IRQ_RXBREAK BIT9 /* async */
418#define IRQ_RXOVER BIT8
419#define IRQ_DSR BIT7
420#define IRQ_CTS BIT6
421#define IRQ_DCD BIT5
422#define IRQ_RI BIT4
423#define IRQ_ALL 0x3ff0
424#define IRQ_MASTER BIT0
425
426#define slgt_irq_on(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
428#define slgt_irq_off(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430
431static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
432static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
433static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
434static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
435static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
436static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437
438static void msc_set_vcr(struct slgt_info *info);
439
440static int startup(struct slgt_info *info);
441static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
442static void shutdown(struct slgt_info *info);
443static void program_hw(struct slgt_info *info);
444static void change_params(struct slgt_info *info);
445
446static int register_test(struct slgt_info *info);
447static int irq_test(struct slgt_info *info);
448static int loopback_test(struct slgt_info *info);
449static int adapter_test(struct slgt_info *info);
450
451static void reset_adapter(struct slgt_info *info);
452static void reset_port(struct slgt_info *info);
453static void async_mode(struct slgt_info *info);
454static void sync_mode(struct slgt_info *info);
455
456static void rx_stop(struct slgt_info *info);
457static void rx_start(struct slgt_info *info);
458static void reset_rbufs(struct slgt_info *info);
459static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
460static void rdma_reset(struct slgt_info *info);
461static bool rx_get_frame(struct slgt_info *info);
462static bool rx_get_buf(struct slgt_info *info);
463
464static void tx_start(struct slgt_info *info);
465static void tx_stop(struct slgt_info *info);
466static void tx_set_idle(struct slgt_info *info);
467static unsigned int free_tbuf_count(struct slgt_info *info);
468static unsigned int tbuf_bytes(struct slgt_info *info);
469static void reset_tbufs(struct slgt_info *info);
470static void tdma_reset(struct slgt_info *info);
471static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
472
473static void get_signals(struct slgt_info *info);
474static void set_signals(struct slgt_info *info);
475static void enable_loopback(struct slgt_info *info);
476static void set_rate(struct slgt_info *info, u32 data_rate);
477
478static int bh_action(struct slgt_info *info);
479static void bh_handler(struct work_struct *work);
480static void bh_transmit(struct slgt_info *info);
481static void isr_serial(struct slgt_info *info);
482static void isr_rdma(struct slgt_info *info);
483static void isr_txeom(struct slgt_info *info, unsigned short status);
484static void isr_tdma(struct slgt_info *info);
485
486static int alloc_dma_bufs(struct slgt_info *info);
487static void free_dma_bufs(struct slgt_info *info);
488static int alloc_desc(struct slgt_info *info);
489static void free_desc(struct slgt_info *info);
490static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492
493static int alloc_tmp_rbuf(struct slgt_info *info);
494static void free_tmp_rbuf(struct slgt_info *info);
495
496static void tx_timeout(struct timer_list *t);
497static void rx_timeout(struct timer_list *t);
498
499/*
500 * ioctl handlers
501 */
502static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
503static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int get_txidle(struct slgt_info *info, int __user *idle_mode);
506static int set_txidle(struct slgt_info *info, int idle_mode);
507static int tx_enable(struct slgt_info *info, int enable);
508static int tx_abort(struct slgt_info *info);
509static int rx_enable(struct slgt_info *info, int enable);
510static int modem_input_wait(struct slgt_info *info,int arg);
511static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
512static int tiocmget(struct tty_struct *tty);
513static int tiocmset(struct tty_struct *tty,
514 unsigned int set, unsigned int clear);
515static int set_break(struct tty_struct *tty, int break_state);
516static int get_interface(struct slgt_info *info, int __user *if_mode);
517static int set_interface(struct slgt_info *info, int if_mode);
518static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521static int get_xsync(struct slgt_info *info, int __user *if_mode);
522static int set_xsync(struct slgt_info *info, int if_mode);
523static int get_xctrl(struct slgt_info *info, int __user *if_mode);
524static int set_xctrl(struct slgt_info *info, int if_mode);
525
526/*
527 * driver functions
528 */
529static void add_device(struct slgt_info *info);
530static void device_init(int adapter_num, struct pci_dev *pdev);
531static int claim_resources(struct slgt_info *info);
532static void release_resources(struct slgt_info *info);
533
534/*
535 * DEBUG OUTPUT CODE
536 */
537#ifndef DBGINFO
538#define DBGINFO(fmt)
539#endif
540#ifndef DBGERR
541#define DBGERR(fmt)
542#endif
543#ifndef DBGBH
544#define DBGBH(fmt)
545#endif
546#ifndef DBGISR
547#define DBGISR(fmt)
548#endif
549
550#ifdef DBGDATA
551static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
552{
553 int i;
554 int linecount;
555 printk("%s %s data:\n",info->device_name, label);
556 while(count) {
557 linecount = (count > 16) ? 16 : count;
558 for(i=0; i < linecount; i++)
559 printk("%02X ",(unsigned char)data[i]);
560 for(;i<17;i++)
561 printk(" ");
562 for(i=0;i<linecount;i++) {
563 if (data[i]>=040 && data[i]<=0176)
564 printk("%c",data[i]);
565 else
566 printk(".");
567 }
568 printk("\n");
569 data += linecount;
570 count -= linecount;
571 }
572}
573#else
574#define DBGDATA(info, buf, size, label)
575#endif
576
577#ifdef DBGTBUF
578static void dump_tbufs(struct slgt_info *info)
579{
580 int i;
581 printk("tbuf_current=%d\n", info->tbuf_current);
582 for (i=0 ; i < info->tbuf_count ; i++) {
583 printk("%d: count=%04X status=%04X\n",
584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
585 }
586}
587#else
588#define DBGTBUF(info)
589#endif
590
591#ifdef DBGRBUF
592static void dump_rbufs(struct slgt_info *info)
593{
594 int i;
595 printk("rbuf_current=%d\n", info->rbuf_current);
596 for (i=0 ; i < info->rbuf_count ; i++) {
597 printk("%d: count=%04X status=%04X\n",
598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
599 }
600}
601#else
602#define DBGRBUF(info)
603#endif
604
605static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
606{
607#ifdef SANITY_CHECK
608 if (!info) {
609 printk("null struct slgt_info for (%s) in %s\n", devname, name);
610 return 1;
611 }
612 if (info->magic != MGSL_MAGIC) {
613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
614 return 1;
615 }
616#else
617 if (!info)
618 return 1;
619#endif
620 return 0;
621}
622
623/**
624 * line discipline callback wrappers
625 *
626 * The wrappers maintain line discipline references
627 * while calling into the line discipline.
628 *
629 * ldisc_receive_buf - pass receive data to line discipline
630 */
631static void ldisc_receive_buf(struct tty_struct *tty,
632 const __u8 *data, char *flags, int count)
633{
634 struct tty_ldisc *ld;
635 if (!tty)
636 return;
637 ld = tty_ldisc_ref(tty);
638 if (ld) {
639 if (ld->ops->receive_buf)
640 ld->ops->receive_buf(tty, data, flags, count);
641 tty_ldisc_deref(ld);
642 }
643}
644
645/* tty callbacks */
646
647static int open(struct tty_struct *tty, struct file *filp)
648{
649 struct slgt_info *info;
650 int retval, line;
651 unsigned long flags;
652
653 line = tty->index;
654 if (line >= slgt_device_count) {
655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
656 return -ENODEV;
657 }
658
659 info = slgt_device_list;
660 while(info && info->line != line)
661 info = info->next_device;
662 if (sanity_check(info, tty->name, "open"))
663 return -ENODEV;
664 if (info->init_error) {
665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
666 return -ENODEV;
667 }
668
669 tty->driver_data = info;
670 info->port.tty = tty;
671
672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
673
674 mutex_lock(&info->port.mutex);
675 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
676
677 spin_lock_irqsave(&info->netlock, flags);
678 if (info->netcount) {
679 retval = -EBUSY;
680 spin_unlock_irqrestore(&info->netlock, flags);
681 mutex_unlock(&info->port.mutex);
682 goto cleanup;
683 }
684 info->port.count++;
685 spin_unlock_irqrestore(&info->netlock, flags);
686
687 if (info->port.count == 1) {
688 /* 1st open on this device, init hardware */
689 retval = startup(info);
690 if (retval < 0) {
691 mutex_unlock(&info->port.mutex);
692 goto cleanup;
693 }
694 }
695 mutex_unlock(&info->port.mutex);
696 retval = block_til_ready(tty, filp, info);
697 if (retval) {
698 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
699 goto cleanup;
700 }
701
702 retval = 0;
703
704cleanup:
705 if (retval) {
706 if (tty->count == 1)
707 info->port.tty = NULL; /* tty layer will release tty struct */
708 if(info->port.count)
709 info->port.count--;
710 }
711
712 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
713 return retval;
714}
715
716static void close(struct tty_struct *tty, struct file *filp)
717{
718 struct slgt_info *info = tty->driver_data;
719
720 if (sanity_check(info, tty->name, "close"))
721 return;
722 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
723
724 if (tty_port_close_start(&info->port, tty, filp) == 0)
725 goto cleanup;
726
727 mutex_lock(&info->port.mutex);
728 if (tty_port_initialized(&info->port))
729 wait_until_sent(tty, info->timeout);
730 flush_buffer(tty);
731 tty_ldisc_flush(tty);
732
733 shutdown(info);
734 mutex_unlock(&info->port.mutex);
735
736 tty_port_close_end(&info->port, tty);
737 info->port.tty = NULL;
738cleanup:
739 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
740}
741
742static void hangup(struct tty_struct *tty)
743{
744 struct slgt_info *info = tty->driver_data;
745 unsigned long flags;
746
747 if (sanity_check(info, tty->name, "hangup"))
748 return;
749 DBGINFO(("%s hangup\n", info->device_name));
750
751 flush_buffer(tty);
752
753 mutex_lock(&info->port.mutex);
754 shutdown(info);
755
756 spin_lock_irqsave(&info->port.lock, flags);
757 info->port.count = 0;
758 info->port.tty = NULL;
759 spin_unlock_irqrestore(&info->port.lock, flags);
760 tty_port_set_active(&info->port, 0);
761 mutex_unlock(&info->port.mutex);
762
763 wake_up_interruptible(&info->port.open_wait);
764}
765
766static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
767{
768 struct slgt_info *info = tty->driver_data;
769 unsigned long flags;
770
771 DBGINFO(("%s set_termios\n", tty->driver->name));
772
773 change_params(info);
774
775 /* Handle transition to B0 status */
776 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
777 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
778 spin_lock_irqsave(&info->lock,flags);
779 set_signals(info);
780 spin_unlock_irqrestore(&info->lock,flags);
781 }
782
783 /* Handle transition away from B0 status */
784 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
785 info->signals |= SerialSignal_DTR;
786 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
787 info->signals |= SerialSignal_RTS;
788 spin_lock_irqsave(&info->lock,flags);
789 set_signals(info);
790 spin_unlock_irqrestore(&info->lock,flags);
791 }
792
793 /* Handle turning off CRTSCTS */
794 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
795 tty->hw_stopped = 0;
796 tx_release(tty);
797 }
798}
799
800static void update_tx_timer(struct slgt_info *info)
801{
802 /*
803 * use worst case speed of 1200bps to calculate transmit timeout
804 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
805 */
806 if (info->params.mode == MGSL_MODE_HDLC) {
807 int timeout = (tbuf_bytes(info) * 7) + 1000;
808 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
809 }
810}
811
812static int write(struct tty_struct *tty,
813 const unsigned char *buf, int count)
814{
815 int ret = 0;
816 struct slgt_info *info = tty->driver_data;
817 unsigned long flags;
818
819 if (sanity_check(info, tty->name, "write"))
820 return -EIO;
821
822 DBGINFO(("%s write count=%d\n", info->device_name, count));
823
824 if (!info->tx_buf || (count > info->max_frame_size))
825 return -EIO;
826
827 if (!count || tty->stopped || tty->hw_stopped)
828 return 0;
829
830 spin_lock_irqsave(&info->lock, flags);
831
832 if (info->tx_count) {
833 /* send accumulated data from send_char() */
834 if (!tx_load(info, info->tx_buf, info->tx_count))
835 goto cleanup;
836 info->tx_count = 0;
837 }
838
839 if (tx_load(info, buf, count))
840 ret = count;
841
842cleanup:
843 spin_unlock_irqrestore(&info->lock, flags);
844 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
845 return ret;
846}
847
848static int put_char(struct tty_struct *tty, unsigned char ch)
849{
850 struct slgt_info *info = tty->driver_data;
851 unsigned long flags;
852 int ret = 0;
853
854 if (sanity_check(info, tty->name, "put_char"))
855 return 0;
856 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
857 if (!info->tx_buf)
858 return 0;
859 spin_lock_irqsave(&info->lock,flags);
860 if (info->tx_count < info->max_frame_size) {
861 info->tx_buf[info->tx_count++] = ch;
862 ret = 1;
863 }
864 spin_unlock_irqrestore(&info->lock,flags);
865 return ret;
866}
867
868static void send_xchar(struct tty_struct *tty, char ch)
869{
870 struct slgt_info *info = tty->driver_data;
871 unsigned long flags;
872
873 if (sanity_check(info, tty->name, "send_xchar"))
874 return;
875 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
876 info->x_char = ch;
877 if (ch) {
878 spin_lock_irqsave(&info->lock,flags);
879 if (!info->tx_enabled)
880 tx_start(info);
881 spin_unlock_irqrestore(&info->lock,flags);
882 }
883}
884
885static void wait_until_sent(struct tty_struct *tty, int timeout)
886{
887 struct slgt_info *info = tty->driver_data;
888 unsigned long orig_jiffies, char_time;
889
890 if (!info )
891 return;
892 if (sanity_check(info, tty->name, "wait_until_sent"))
893 return;
894 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
895 if (!tty_port_initialized(&info->port))
896 goto exit;
897
898 orig_jiffies = jiffies;
899
900 /* Set check interval to 1/5 of estimated time to
901 * send a character, and make it at least 1. The check
902 * interval should also be less than the timeout.
903 * Note: use tight timings here to satisfy the NIST-PCTS.
904 */
905
906 if (info->params.data_rate) {
907 char_time = info->timeout/(32 * 5);
908 if (!char_time)
909 char_time++;
910 } else
911 char_time = 1;
912
913 if (timeout)
914 char_time = min_t(unsigned long, char_time, timeout);
915
916 while (info->tx_active) {
917 msleep_interruptible(jiffies_to_msecs(char_time));
918 if (signal_pending(current))
919 break;
920 if (timeout && time_after(jiffies, orig_jiffies + timeout))
921 break;
922 }
923exit:
924 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
925}
926
927static int write_room(struct tty_struct *tty)
928{
929 struct slgt_info *info = tty->driver_data;
930 int ret;
931
932 if (sanity_check(info, tty->name, "write_room"))
933 return 0;
934 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
935 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
936 return ret;
937}
938
939static void flush_chars(struct tty_struct *tty)
940{
941 struct slgt_info *info = tty->driver_data;
942 unsigned long flags;
943
944 if (sanity_check(info, tty->name, "flush_chars"))
945 return;
946 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
947
948 if (info->tx_count <= 0 || tty->stopped ||
949 tty->hw_stopped || !info->tx_buf)
950 return;
951
952 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
953
954 spin_lock_irqsave(&info->lock,flags);
955 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
956 info->tx_count = 0;
957 spin_unlock_irqrestore(&info->lock,flags);
958}
959
960static void flush_buffer(struct tty_struct *tty)
961{
962 struct slgt_info *info = tty->driver_data;
963 unsigned long flags;
964
965 if (sanity_check(info, tty->name, "flush_buffer"))
966 return;
967 DBGINFO(("%s flush_buffer\n", info->device_name));
968
969 spin_lock_irqsave(&info->lock, flags);
970 info->tx_count = 0;
971 spin_unlock_irqrestore(&info->lock, flags);
972
973 tty_wakeup(tty);
974}
975
976/*
977 * throttle (stop) transmitter
978 */
979static void tx_hold(struct tty_struct *tty)
980{
981 struct slgt_info *info = tty->driver_data;
982 unsigned long flags;
983
984 if (sanity_check(info, tty->name, "tx_hold"))
985 return;
986 DBGINFO(("%s tx_hold\n", info->device_name));
987 spin_lock_irqsave(&info->lock,flags);
988 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
989 tx_stop(info);
990 spin_unlock_irqrestore(&info->lock,flags);
991}
992
993/*
994 * release (start) transmitter
995 */
996static void tx_release(struct tty_struct *tty)
997{
998 struct slgt_info *info = tty->driver_data;
999 unsigned long flags;
1000
1001 if (sanity_check(info, tty->name, "tx_release"))
1002 return;
1003 DBGINFO(("%s tx_release\n", info->device_name));
1004 spin_lock_irqsave(&info->lock, flags);
1005 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1006 info->tx_count = 0;
1007 spin_unlock_irqrestore(&info->lock, flags);
1008}
1009
1010/*
1011 * Service an IOCTL request
1012 *
1013 * Arguments
1014 *
1015 * tty pointer to tty instance data
1016 * cmd IOCTL command code
1017 * arg command argument/context
1018 *
1019 * Return 0 if success, otherwise error code
1020 */
1021static int ioctl(struct tty_struct *tty,
1022 unsigned int cmd, unsigned long arg)
1023{
1024 struct slgt_info *info = tty->driver_data;
1025 void __user *argp = (void __user *)arg;
1026 int ret;
1027
1028 if (sanity_check(info, tty->name, "ioctl"))
1029 return -ENODEV;
1030 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1031
1032 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1033 (cmd != TIOCMIWAIT)) {
1034 if (tty_io_error(tty))
1035 return -EIO;
1036 }
1037
1038 switch (cmd) {
1039 case MGSL_IOCWAITEVENT:
1040 return wait_mgsl_event(info, argp);
1041 case TIOCMIWAIT:
1042 return modem_input_wait(info,(int)arg);
1043 case MGSL_IOCSGPIO:
1044 return set_gpio(info, argp);
1045 case MGSL_IOCGGPIO:
1046 return get_gpio(info, argp);
1047 case MGSL_IOCWAITGPIO:
1048 return wait_gpio(info, argp);
1049 case MGSL_IOCGXSYNC:
1050 return get_xsync(info, argp);
1051 case MGSL_IOCSXSYNC:
1052 return set_xsync(info, (int)arg);
1053 case MGSL_IOCGXCTRL:
1054 return get_xctrl(info, argp);
1055 case MGSL_IOCSXCTRL:
1056 return set_xctrl(info, (int)arg);
1057 }
1058 mutex_lock(&info->port.mutex);
1059 switch (cmd) {
1060 case MGSL_IOCGPARAMS:
1061 ret = get_params(info, argp);
1062 break;
1063 case MGSL_IOCSPARAMS:
1064 ret = set_params(info, argp);
1065 break;
1066 case MGSL_IOCGTXIDLE:
1067 ret = get_txidle(info, argp);
1068 break;
1069 case MGSL_IOCSTXIDLE:
1070 ret = set_txidle(info, (int)arg);
1071 break;
1072 case MGSL_IOCTXENABLE:
1073 ret = tx_enable(info, (int)arg);
1074 break;
1075 case MGSL_IOCRXENABLE:
1076 ret = rx_enable(info, (int)arg);
1077 break;
1078 case MGSL_IOCTXABORT:
1079 ret = tx_abort(info);
1080 break;
1081 case MGSL_IOCGSTATS:
1082 ret = get_stats(info, argp);
1083 break;
1084 case MGSL_IOCGIF:
1085 ret = get_interface(info, argp);
1086 break;
1087 case MGSL_IOCSIF:
1088 ret = set_interface(info,(int)arg);
1089 break;
1090 default:
1091 ret = -ENOIOCTLCMD;
1092 }
1093 mutex_unlock(&info->port.mutex);
1094 return ret;
1095}
1096
1097static int get_icount(struct tty_struct *tty,
1098 struct serial_icounter_struct *icount)
1099
1100{
1101 struct slgt_info *info = tty->driver_data;
1102 struct mgsl_icount cnow; /* kernel counter temps */
1103 unsigned long flags;
1104
1105 spin_lock_irqsave(&info->lock,flags);
1106 cnow = info->icount;
1107 spin_unlock_irqrestore(&info->lock,flags);
1108
1109 icount->cts = cnow.cts;
1110 icount->dsr = cnow.dsr;
1111 icount->rng = cnow.rng;
1112 icount->dcd = cnow.dcd;
1113 icount->rx = cnow.rx;
1114 icount->tx = cnow.tx;
1115 icount->frame = cnow.frame;
1116 icount->overrun = cnow.overrun;
1117 icount->parity = cnow.parity;
1118 icount->brk = cnow.brk;
1119 icount->buf_overrun = cnow.buf_overrun;
1120
1121 return 0;
1122}
1123
1124/*
1125 * support for 32 bit ioctl calls on 64 bit systems
1126 */
1127#ifdef CONFIG_COMPAT
1128static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1129{
1130 struct MGSL_PARAMS32 tmp_params;
1131
1132 DBGINFO(("%s get_params32\n", info->device_name));
1133 memset(&tmp_params, 0, sizeof(tmp_params));
1134 tmp_params.mode = (compat_ulong_t)info->params.mode;
1135 tmp_params.loopback = info->params.loopback;
1136 tmp_params.flags = info->params.flags;
1137 tmp_params.encoding = info->params.encoding;
1138 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1139 tmp_params.addr_filter = info->params.addr_filter;
1140 tmp_params.crc_type = info->params.crc_type;
1141 tmp_params.preamble_length = info->params.preamble_length;
1142 tmp_params.preamble = info->params.preamble;
1143 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1144 tmp_params.data_bits = info->params.data_bits;
1145 tmp_params.stop_bits = info->params.stop_bits;
1146 tmp_params.parity = info->params.parity;
1147 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1148 return -EFAULT;
1149 return 0;
1150}
1151
1152static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1153{
1154 struct MGSL_PARAMS32 tmp_params;
1155
1156 DBGINFO(("%s set_params32\n", info->device_name));
1157 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1158 return -EFAULT;
1159
1160 spin_lock(&info->lock);
1161 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1162 info->base_clock = tmp_params.clock_speed;
1163 } else {
1164 info->params.mode = tmp_params.mode;
1165 info->params.loopback = tmp_params.loopback;
1166 info->params.flags = tmp_params.flags;
1167 info->params.encoding = tmp_params.encoding;
1168 info->params.clock_speed = tmp_params.clock_speed;
1169 info->params.addr_filter = tmp_params.addr_filter;
1170 info->params.crc_type = tmp_params.crc_type;
1171 info->params.preamble_length = tmp_params.preamble_length;
1172 info->params.preamble = tmp_params.preamble;
1173 info->params.data_rate = tmp_params.data_rate;
1174 info->params.data_bits = tmp_params.data_bits;
1175 info->params.stop_bits = tmp_params.stop_bits;
1176 info->params.parity = tmp_params.parity;
1177 }
1178 spin_unlock(&info->lock);
1179
1180 program_hw(info);
1181
1182 return 0;
1183}
1184
1185static long slgt_compat_ioctl(struct tty_struct *tty,
1186 unsigned int cmd, unsigned long arg)
1187{
1188 struct slgt_info *info = tty->driver_data;
1189 int rc = -ENOIOCTLCMD;
1190
1191 if (sanity_check(info, tty->name, "compat_ioctl"))
1192 return -ENODEV;
1193 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1194
1195 switch (cmd) {
1196
1197 case MGSL_IOCSPARAMS32:
1198 rc = set_params32(info, compat_ptr(arg));
1199 break;
1200
1201 case MGSL_IOCGPARAMS32:
1202 rc = get_params32(info, compat_ptr(arg));
1203 break;
1204
1205 case MGSL_IOCGPARAMS:
1206 case MGSL_IOCSPARAMS:
1207 case MGSL_IOCGTXIDLE:
1208 case MGSL_IOCGSTATS:
1209 case MGSL_IOCWAITEVENT:
1210 case MGSL_IOCGIF:
1211 case MGSL_IOCSGPIO:
1212 case MGSL_IOCGGPIO:
1213 case MGSL_IOCWAITGPIO:
1214 case MGSL_IOCGXSYNC:
1215 case MGSL_IOCGXCTRL:
1216 case MGSL_IOCSTXIDLE:
1217 case MGSL_IOCTXENABLE:
1218 case MGSL_IOCRXENABLE:
1219 case MGSL_IOCTXABORT:
1220 case TIOCMIWAIT:
1221 case MGSL_IOCSIF:
1222 case MGSL_IOCSXSYNC:
1223 case MGSL_IOCSXCTRL:
1224 rc = ioctl(tty, cmd, arg);
1225 break;
1226 }
1227
1228 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1229 return rc;
1230}
1231#else
1232#define slgt_compat_ioctl NULL
1233#endif /* ifdef CONFIG_COMPAT */
1234
1235/*
1236 * proc fs support
1237 */
1238static inline void line_info(struct seq_file *m, struct slgt_info *info)
1239{
1240 char stat_buf[30];
1241 unsigned long flags;
1242
1243 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1244 info->device_name, info->phys_reg_addr,
1245 info->irq_level, info->max_frame_size);
1246
1247 /* output current serial signal states */
1248 spin_lock_irqsave(&info->lock,flags);
1249 get_signals(info);
1250 spin_unlock_irqrestore(&info->lock,flags);
1251
1252 stat_buf[0] = 0;
1253 stat_buf[1] = 0;
1254 if (info->signals & SerialSignal_RTS)
1255 strcat(stat_buf, "|RTS");
1256 if (info->signals & SerialSignal_CTS)
1257 strcat(stat_buf, "|CTS");
1258 if (info->signals & SerialSignal_DTR)
1259 strcat(stat_buf, "|DTR");
1260 if (info->signals & SerialSignal_DSR)
1261 strcat(stat_buf, "|DSR");
1262 if (info->signals & SerialSignal_DCD)
1263 strcat(stat_buf, "|CD");
1264 if (info->signals & SerialSignal_RI)
1265 strcat(stat_buf, "|RI");
1266
1267 if (info->params.mode != MGSL_MODE_ASYNC) {
1268 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1269 info->icount.txok, info->icount.rxok);
1270 if (info->icount.txunder)
1271 seq_printf(m, " txunder:%d", info->icount.txunder);
1272 if (info->icount.txabort)
1273 seq_printf(m, " txabort:%d", info->icount.txabort);
1274 if (info->icount.rxshort)
1275 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1276 if (info->icount.rxlong)
1277 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1278 if (info->icount.rxover)
1279 seq_printf(m, " rxover:%d", info->icount.rxover);
1280 if (info->icount.rxcrc)
1281 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1282 } else {
1283 seq_printf(m, "\tASYNC tx:%d rx:%d",
1284 info->icount.tx, info->icount.rx);
1285 if (info->icount.frame)
1286 seq_printf(m, " fe:%d", info->icount.frame);
1287 if (info->icount.parity)
1288 seq_printf(m, " pe:%d", info->icount.parity);
1289 if (info->icount.brk)
1290 seq_printf(m, " brk:%d", info->icount.brk);
1291 if (info->icount.overrun)
1292 seq_printf(m, " oe:%d", info->icount.overrun);
1293 }
1294
1295 /* Append serial signal status to end */
1296 seq_printf(m, " %s\n", stat_buf+1);
1297
1298 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1299 info->tx_active,info->bh_requested,info->bh_running,
1300 info->pending_bh);
1301}
1302
1303/* Called to print information about devices
1304 */
1305static int synclink_gt_proc_show(struct seq_file *m, void *v)
1306{
1307 struct slgt_info *info;
1308
1309 seq_puts(m, "synclink_gt driver\n");
1310
1311 info = slgt_device_list;
1312 while( info ) {
1313 line_info(m, info);
1314 info = info->next_device;
1315 }
1316 return 0;
1317}
1318
1319static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1320{
1321 return single_open(file, synclink_gt_proc_show, NULL);
1322}
1323
1324static const struct file_operations synclink_gt_proc_fops = {
1325 .owner = THIS_MODULE,
1326 .open = synclink_gt_proc_open,
1327 .read = seq_read,
1328 .llseek = seq_lseek,
1329 .release = single_release,
1330};
1331
1332/*
1333 * return count of bytes in transmit buffer
1334 */
1335static int chars_in_buffer(struct tty_struct *tty)
1336{
1337 struct slgt_info *info = tty->driver_data;
1338 int count;
1339 if (sanity_check(info, tty->name, "chars_in_buffer"))
1340 return 0;
1341 count = tbuf_bytes(info);
1342 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1343 return count;
1344}
1345
1346/*
1347 * signal remote device to throttle send data (our receive data)
1348 */
1349static void throttle(struct tty_struct * tty)
1350{
1351 struct slgt_info *info = tty->driver_data;
1352 unsigned long flags;
1353
1354 if (sanity_check(info, tty->name, "throttle"))
1355 return;
1356 DBGINFO(("%s throttle\n", info->device_name));
1357 if (I_IXOFF(tty))
1358 send_xchar(tty, STOP_CHAR(tty));
1359 if (C_CRTSCTS(tty)) {
1360 spin_lock_irqsave(&info->lock,flags);
1361 info->signals &= ~SerialSignal_RTS;
1362 set_signals(info);
1363 spin_unlock_irqrestore(&info->lock,flags);
1364 }
1365}
1366
1367/*
1368 * signal remote device to stop throttling send data (our receive data)
1369 */
1370static void unthrottle(struct tty_struct * tty)
1371{
1372 struct slgt_info *info = tty->driver_data;
1373 unsigned long flags;
1374
1375 if (sanity_check(info, tty->name, "unthrottle"))
1376 return;
1377 DBGINFO(("%s unthrottle\n", info->device_name));
1378 if (I_IXOFF(tty)) {
1379 if (info->x_char)
1380 info->x_char = 0;
1381 else
1382 send_xchar(tty, START_CHAR(tty));
1383 }
1384 if (C_CRTSCTS(tty)) {
1385 spin_lock_irqsave(&info->lock,flags);
1386 info->signals |= SerialSignal_RTS;
1387 set_signals(info);
1388 spin_unlock_irqrestore(&info->lock,flags);
1389 }
1390}
1391
1392/*
1393 * set or clear transmit break condition
1394 * break_state -1=set break condition, 0=clear
1395 */
1396static int set_break(struct tty_struct *tty, int break_state)
1397{
1398 struct slgt_info *info = tty->driver_data;
1399 unsigned short value;
1400 unsigned long flags;
1401
1402 if (sanity_check(info, tty->name, "set_break"))
1403 return -EINVAL;
1404 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1405
1406 spin_lock_irqsave(&info->lock,flags);
1407 value = rd_reg16(info, TCR);
1408 if (break_state == -1)
1409 value |= BIT6;
1410 else
1411 value &= ~BIT6;
1412 wr_reg16(info, TCR, value);
1413 spin_unlock_irqrestore(&info->lock,flags);
1414 return 0;
1415}
1416
1417#if SYNCLINK_GENERIC_HDLC
1418
1419/**
1420 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1421 * set encoding and frame check sequence (FCS) options
1422 *
1423 * dev pointer to network device structure
1424 * encoding serial encoding setting
1425 * parity FCS setting
1426 *
1427 * returns 0 if success, otherwise error code
1428 */
1429static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1430 unsigned short parity)
1431{
1432 struct slgt_info *info = dev_to_port(dev);
1433 unsigned char new_encoding;
1434 unsigned short new_crctype;
1435
1436 /* return error if TTY interface open */
1437 if (info->port.count)
1438 return -EBUSY;
1439
1440 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1441
1442 switch (encoding)
1443 {
1444 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1445 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1446 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1447 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1448 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1449 default: return -EINVAL;
1450 }
1451
1452 switch (parity)
1453 {
1454 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1455 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1456 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1457 default: return -EINVAL;
1458 }
1459
1460 info->params.encoding = new_encoding;
1461 info->params.crc_type = new_crctype;
1462
1463 /* if network interface up, reprogram hardware */
1464 if (info->netcount)
1465 program_hw(info);
1466
1467 return 0;
1468}
1469
1470/**
1471 * called by generic HDLC layer to send frame
1472 *
1473 * skb socket buffer containing HDLC frame
1474 * dev pointer to network device structure
1475 */
1476static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1477 struct net_device *dev)
1478{
1479 struct slgt_info *info = dev_to_port(dev);
1480 unsigned long flags;
1481
1482 DBGINFO(("%s hdlc_xmit\n", dev->name));
1483
1484 if (!skb->len)
1485 return NETDEV_TX_OK;
1486
1487 /* stop sending until this frame completes */
1488 netif_stop_queue(dev);
1489
1490 /* update network statistics */
1491 dev->stats.tx_packets++;
1492 dev->stats.tx_bytes += skb->len;
1493
1494 /* save start time for transmit timeout detection */
1495 netif_trans_update(dev);
1496
1497 spin_lock_irqsave(&info->lock, flags);
1498 tx_load(info, skb->data, skb->len);
1499 spin_unlock_irqrestore(&info->lock, flags);
1500
1501 /* done with socket buffer, so free it */
1502 dev_kfree_skb(skb);
1503
1504 return NETDEV_TX_OK;
1505}
1506
1507/**
1508 * called by network layer when interface enabled
1509 * claim resources and initialize hardware
1510 *
1511 * dev pointer to network device structure
1512 *
1513 * returns 0 if success, otherwise error code
1514 */
1515static int hdlcdev_open(struct net_device *dev)
1516{
1517 struct slgt_info *info = dev_to_port(dev);
1518 int rc;
1519 unsigned long flags;
1520
1521 if (!try_module_get(THIS_MODULE))
1522 return -EBUSY;
1523
1524 DBGINFO(("%s hdlcdev_open\n", dev->name));
1525
1526 /* generic HDLC layer open processing */
1527 rc = hdlc_open(dev);
1528 if (rc)
1529 return rc;
1530
1531 /* arbitrate between network and tty opens */
1532 spin_lock_irqsave(&info->netlock, flags);
1533 if (info->port.count != 0 || info->netcount != 0) {
1534 DBGINFO(("%s hdlc_open busy\n", dev->name));
1535 spin_unlock_irqrestore(&info->netlock, flags);
1536 return -EBUSY;
1537 }
1538 info->netcount=1;
1539 spin_unlock_irqrestore(&info->netlock, flags);
1540
1541 /* claim resources and init adapter */
1542 if ((rc = startup(info)) != 0) {
1543 spin_lock_irqsave(&info->netlock, flags);
1544 info->netcount=0;
1545 spin_unlock_irqrestore(&info->netlock, flags);
1546 return rc;
1547 }
1548
1549 /* assert RTS and DTR, apply hardware settings */
1550 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1551 program_hw(info);
1552
1553 /* enable network layer transmit */
1554 netif_trans_update(dev);
1555 netif_start_queue(dev);
1556
1557 /* inform generic HDLC layer of current DCD status */
1558 spin_lock_irqsave(&info->lock, flags);
1559 get_signals(info);
1560 spin_unlock_irqrestore(&info->lock, flags);
1561 if (info->signals & SerialSignal_DCD)
1562 netif_carrier_on(dev);
1563 else
1564 netif_carrier_off(dev);
1565 return 0;
1566}
1567
1568/**
1569 * called by network layer when interface is disabled
1570 * shutdown hardware and release resources
1571 *
1572 * dev pointer to network device structure
1573 *
1574 * returns 0 if success, otherwise error code
1575 */
1576static int hdlcdev_close(struct net_device *dev)
1577{
1578 struct slgt_info *info = dev_to_port(dev);
1579 unsigned long flags;
1580
1581 DBGINFO(("%s hdlcdev_close\n", dev->name));
1582
1583 netif_stop_queue(dev);
1584
1585 /* shutdown adapter and release resources */
1586 shutdown(info);
1587
1588 hdlc_close(dev);
1589
1590 spin_lock_irqsave(&info->netlock, flags);
1591 info->netcount=0;
1592 spin_unlock_irqrestore(&info->netlock, flags);
1593
1594 module_put(THIS_MODULE);
1595 return 0;
1596}
1597
1598/**
1599 * called by network layer to process IOCTL call to network device
1600 *
1601 * dev pointer to network device structure
1602 * ifr pointer to network interface request structure
1603 * cmd IOCTL command code
1604 *
1605 * returns 0 if success, otherwise error code
1606 */
1607static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1608{
1609 const size_t size = sizeof(sync_serial_settings);
1610 sync_serial_settings new_line;
1611 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1612 struct slgt_info *info = dev_to_port(dev);
1613 unsigned int flags;
1614
1615 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1616
1617 /* return error if TTY interface open */
1618 if (info->port.count)
1619 return -EBUSY;
1620
1621 if (cmd != SIOCWANDEV)
1622 return hdlc_ioctl(dev, ifr, cmd);
1623
1624 memset(&new_line, 0, sizeof(new_line));
1625
1626 switch(ifr->ifr_settings.type) {
1627 case IF_GET_IFACE: /* return current sync_serial_settings */
1628
1629 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1630 if (ifr->ifr_settings.size < size) {
1631 ifr->ifr_settings.size = size; /* data size wanted */
1632 return -ENOBUFS;
1633 }
1634
1635 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1636 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1637 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1638 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1639
1640 switch (flags){
1641 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1642 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1643 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1644 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1645 default: new_line.clock_type = CLOCK_DEFAULT;
1646 }
1647
1648 new_line.clock_rate = info->params.clock_speed;
1649 new_line.loopback = info->params.loopback ? 1:0;
1650
1651 if (copy_to_user(line, &new_line, size))
1652 return -EFAULT;
1653 return 0;
1654
1655 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1656
1657 if(!capable(CAP_NET_ADMIN))
1658 return -EPERM;
1659 if (copy_from_user(&new_line, line, size))
1660 return -EFAULT;
1661
1662 switch (new_line.clock_type)
1663 {
1664 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1665 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1666 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1667 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1668 case CLOCK_DEFAULT: flags = info->params.flags &
1669 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1670 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1671 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1672 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1673 default: return -EINVAL;
1674 }
1675
1676 if (new_line.loopback != 0 && new_line.loopback != 1)
1677 return -EINVAL;
1678
1679 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1680 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1681 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1682 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1683 info->params.flags |= flags;
1684
1685 info->params.loopback = new_line.loopback;
1686
1687 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1688 info->params.clock_speed = new_line.clock_rate;
1689 else
1690 info->params.clock_speed = 0;
1691
1692 /* if network interface up, reprogram hardware */
1693 if (info->netcount)
1694 program_hw(info);
1695 return 0;
1696
1697 default:
1698 return hdlc_ioctl(dev, ifr, cmd);
1699 }
1700}
1701
1702/**
1703 * called by network layer when transmit timeout is detected
1704 *
1705 * dev pointer to network device structure
1706 */
1707static void hdlcdev_tx_timeout(struct net_device *dev)
1708{
1709 struct slgt_info *info = dev_to_port(dev);
1710 unsigned long flags;
1711
1712 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1713
1714 dev->stats.tx_errors++;
1715 dev->stats.tx_aborted_errors++;
1716
1717 spin_lock_irqsave(&info->lock,flags);
1718 tx_stop(info);
1719 spin_unlock_irqrestore(&info->lock,flags);
1720
1721 netif_wake_queue(dev);
1722}
1723
1724/**
1725 * called by device driver when transmit completes
1726 * reenable network layer transmit if stopped
1727 *
1728 * info pointer to device instance information
1729 */
1730static void hdlcdev_tx_done(struct slgt_info *info)
1731{
1732 if (netif_queue_stopped(info->netdev))
1733 netif_wake_queue(info->netdev);
1734}
1735
1736/**
1737 * called by device driver when frame received
1738 * pass frame to network layer
1739 *
1740 * info pointer to device instance information
1741 * buf pointer to buffer contianing frame data
1742 * size count of data bytes in buf
1743 */
1744static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1745{
1746 struct sk_buff *skb = dev_alloc_skb(size);
1747 struct net_device *dev = info->netdev;
1748
1749 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1750
1751 if (skb == NULL) {
1752 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1753 dev->stats.rx_dropped++;
1754 return;
1755 }
1756
1757 skb_put_data(skb, buf, size);
1758
1759 skb->protocol = hdlc_type_trans(skb, dev);
1760
1761 dev->stats.rx_packets++;
1762 dev->stats.rx_bytes += size;
1763
1764 netif_rx(skb);
1765}
1766
1767static const struct net_device_ops hdlcdev_ops = {
1768 .ndo_open = hdlcdev_open,
1769 .ndo_stop = hdlcdev_close,
1770 .ndo_start_xmit = hdlc_start_xmit,
1771 .ndo_do_ioctl = hdlcdev_ioctl,
1772 .ndo_tx_timeout = hdlcdev_tx_timeout,
1773};
1774
1775/**
1776 * called by device driver when adding device instance
1777 * do generic HDLC initialization
1778 *
1779 * info pointer to device instance information
1780 *
1781 * returns 0 if success, otherwise error code
1782 */
1783static int hdlcdev_init(struct slgt_info *info)
1784{
1785 int rc;
1786 struct net_device *dev;
1787 hdlc_device *hdlc;
1788
1789 /* allocate and initialize network and HDLC layer objects */
1790
1791 dev = alloc_hdlcdev(info);
1792 if (!dev) {
1793 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1794 return -ENOMEM;
1795 }
1796
1797 /* for network layer reporting purposes only */
1798 dev->mem_start = info->phys_reg_addr;
1799 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1800 dev->irq = info->irq_level;
1801
1802 /* network layer callbacks and settings */
1803 dev->netdev_ops = &hdlcdev_ops;
1804 dev->watchdog_timeo = 10 * HZ;
1805 dev->tx_queue_len = 50;
1806
1807 /* generic HDLC layer callbacks and settings */
1808 hdlc = dev_to_hdlc(dev);
1809 hdlc->attach = hdlcdev_attach;
1810 hdlc->xmit = hdlcdev_xmit;
1811
1812 /* register objects with HDLC layer */
1813 rc = register_hdlc_device(dev);
1814 if (rc) {
1815 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1816 free_netdev(dev);
1817 return rc;
1818 }
1819
1820 info->netdev = dev;
1821 return 0;
1822}
1823
1824/**
1825 * called by device driver when removing device instance
1826 * do generic HDLC cleanup
1827 *
1828 * info pointer to device instance information
1829 */
1830static void hdlcdev_exit(struct slgt_info *info)
1831{
1832 unregister_hdlc_device(info->netdev);
1833 free_netdev(info->netdev);
1834 info->netdev = NULL;
1835}
1836
1837#endif /* ifdef CONFIG_HDLC */
1838
1839/*
1840 * get async data from rx DMA buffers
1841 */
1842static void rx_async(struct slgt_info *info)
1843{
1844 struct mgsl_icount *icount = &info->icount;
1845 unsigned int start, end;
1846 unsigned char *p;
1847 unsigned char status;
1848 struct slgt_desc *bufs = info->rbufs;
1849 int i, count;
1850 int chars = 0;
1851 int stat;
1852 unsigned char ch;
1853
1854 start = end = info->rbuf_current;
1855
1856 while(desc_complete(bufs[end])) {
1857 count = desc_count(bufs[end]) - info->rbuf_index;
1858 p = bufs[end].buf + info->rbuf_index;
1859
1860 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1861 DBGDATA(info, p, count, "rx");
1862
1863 for(i=0 ; i < count; i+=2, p+=2) {
1864 ch = *p;
1865 icount->rx++;
1866
1867 stat = 0;
1868
1869 status = *(p + 1) & (BIT1 + BIT0);
1870 if (status) {
1871 if (status & BIT1)
1872 icount->parity++;
1873 else if (status & BIT0)
1874 icount->frame++;
1875 /* discard char if tty control flags say so */
1876 if (status & info->ignore_status_mask)
1877 continue;
1878 if (status & BIT1)
1879 stat = TTY_PARITY;
1880 else if (status & BIT0)
1881 stat = TTY_FRAME;
1882 }
1883 tty_insert_flip_char(&info->port, ch, stat);
1884 chars++;
1885 }
1886
1887 if (i < count) {
1888 /* receive buffer not completed */
1889 info->rbuf_index += i;
1890 mod_timer(&info->rx_timer, jiffies + 1);
1891 break;
1892 }
1893
1894 info->rbuf_index = 0;
1895 free_rbufs(info, end, end);
1896
1897 if (++end == info->rbuf_count)
1898 end = 0;
1899
1900 /* if entire list searched then no frame available */
1901 if (end == start)
1902 break;
1903 }
1904
1905 if (chars)
1906 tty_flip_buffer_push(&info->port);
1907}
1908
1909/*
1910 * return next bottom half action to perform
1911 */
1912static int bh_action(struct slgt_info *info)
1913{
1914 unsigned long flags;
1915 int rc;
1916
1917 spin_lock_irqsave(&info->lock,flags);
1918
1919 if (info->pending_bh & BH_RECEIVE) {
1920 info->pending_bh &= ~BH_RECEIVE;
1921 rc = BH_RECEIVE;
1922 } else if (info->pending_bh & BH_TRANSMIT) {
1923 info->pending_bh &= ~BH_TRANSMIT;
1924 rc = BH_TRANSMIT;
1925 } else if (info->pending_bh & BH_STATUS) {
1926 info->pending_bh &= ~BH_STATUS;
1927 rc = BH_STATUS;
1928 } else {
1929 /* Mark BH routine as complete */
1930 info->bh_running = false;
1931 info->bh_requested = false;
1932 rc = 0;
1933 }
1934
1935 spin_unlock_irqrestore(&info->lock,flags);
1936
1937 return rc;
1938}
1939
1940/*
1941 * perform bottom half processing
1942 */
1943static void bh_handler(struct work_struct *work)
1944{
1945 struct slgt_info *info = container_of(work, struct slgt_info, task);
1946 int action;
1947
1948 info->bh_running = true;
1949
1950 while((action = bh_action(info))) {
1951 switch (action) {
1952 case BH_RECEIVE:
1953 DBGBH(("%s bh receive\n", info->device_name));
1954 switch(info->params.mode) {
1955 case MGSL_MODE_ASYNC:
1956 rx_async(info);
1957 break;
1958 case MGSL_MODE_HDLC:
1959 while(rx_get_frame(info));
1960 break;
1961 case MGSL_MODE_RAW:
1962 case MGSL_MODE_MONOSYNC:
1963 case MGSL_MODE_BISYNC:
1964 case MGSL_MODE_XSYNC:
1965 while(rx_get_buf(info));
1966 break;
1967 }
1968 /* restart receiver if rx DMA buffers exhausted */
1969 if (info->rx_restart)
1970 rx_start(info);
1971 break;
1972 case BH_TRANSMIT:
1973 bh_transmit(info);
1974 break;
1975 case BH_STATUS:
1976 DBGBH(("%s bh status\n", info->device_name));
1977 info->ri_chkcount = 0;
1978 info->dsr_chkcount = 0;
1979 info->dcd_chkcount = 0;
1980 info->cts_chkcount = 0;
1981 break;
1982 default:
1983 DBGBH(("%s unknown action\n", info->device_name));
1984 break;
1985 }
1986 }
1987 DBGBH(("%s bh_handler exit\n", info->device_name));
1988}
1989
1990static void bh_transmit(struct slgt_info *info)
1991{
1992 struct tty_struct *tty = info->port.tty;
1993
1994 DBGBH(("%s bh_transmit\n", info->device_name));
1995 if (tty)
1996 tty_wakeup(tty);
1997}
1998
1999static void dsr_change(struct slgt_info *info, unsigned short status)
2000{
2001 if (status & BIT3) {
2002 info->signals |= SerialSignal_DSR;
2003 info->input_signal_events.dsr_up++;
2004 } else {
2005 info->signals &= ~SerialSignal_DSR;
2006 info->input_signal_events.dsr_down++;
2007 }
2008 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2009 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2010 slgt_irq_off(info, IRQ_DSR);
2011 return;
2012 }
2013 info->icount.dsr++;
2014 wake_up_interruptible(&info->status_event_wait_q);
2015 wake_up_interruptible(&info->event_wait_q);
2016 info->pending_bh |= BH_STATUS;
2017}
2018
2019static void cts_change(struct slgt_info *info, unsigned short status)
2020{
2021 if (status & BIT2) {
2022 info->signals |= SerialSignal_CTS;
2023 info->input_signal_events.cts_up++;
2024 } else {
2025 info->signals &= ~SerialSignal_CTS;
2026 info->input_signal_events.cts_down++;
2027 }
2028 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2029 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2030 slgt_irq_off(info, IRQ_CTS);
2031 return;
2032 }
2033 info->icount.cts++;
2034 wake_up_interruptible(&info->status_event_wait_q);
2035 wake_up_interruptible(&info->event_wait_q);
2036 info->pending_bh |= BH_STATUS;
2037
2038 if (tty_port_cts_enabled(&info->port)) {
2039 if (info->port.tty) {
2040 if (info->port.tty->hw_stopped) {
2041 if (info->signals & SerialSignal_CTS) {
2042 info->port.tty->hw_stopped = 0;
2043 info->pending_bh |= BH_TRANSMIT;
2044 return;
2045 }
2046 } else {
2047 if (!(info->signals & SerialSignal_CTS))
2048 info->port.tty->hw_stopped = 1;
2049 }
2050 }
2051 }
2052}
2053
2054static void dcd_change(struct slgt_info *info, unsigned short status)
2055{
2056 if (status & BIT1) {
2057 info->signals |= SerialSignal_DCD;
2058 info->input_signal_events.dcd_up++;
2059 } else {
2060 info->signals &= ~SerialSignal_DCD;
2061 info->input_signal_events.dcd_down++;
2062 }
2063 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2064 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2065 slgt_irq_off(info, IRQ_DCD);
2066 return;
2067 }
2068 info->icount.dcd++;
2069#if SYNCLINK_GENERIC_HDLC
2070 if (info->netcount) {
2071 if (info->signals & SerialSignal_DCD)
2072 netif_carrier_on(info->netdev);
2073 else
2074 netif_carrier_off(info->netdev);
2075 }
2076#endif
2077 wake_up_interruptible(&info->status_event_wait_q);
2078 wake_up_interruptible(&info->event_wait_q);
2079 info->pending_bh |= BH_STATUS;
2080
2081 if (tty_port_check_carrier(&info->port)) {
2082 if (info->signals & SerialSignal_DCD)
2083 wake_up_interruptible(&info->port.open_wait);
2084 else {
2085 if (info->port.tty)
2086 tty_hangup(info->port.tty);
2087 }
2088 }
2089}
2090
2091static void ri_change(struct slgt_info *info, unsigned short status)
2092{
2093 if (status & BIT0) {
2094 info->signals |= SerialSignal_RI;
2095 info->input_signal_events.ri_up++;
2096 } else {
2097 info->signals &= ~SerialSignal_RI;
2098 info->input_signal_events.ri_down++;
2099 }
2100 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2101 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2102 slgt_irq_off(info, IRQ_RI);
2103 return;
2104 }
2105 info->icount.rng++;
2106 wake_up_interruptible(&info->status_event_wait_q);
2107 wake_up_interruptible(&info->event_wait_q);
2108 info->pending_bh |= BH_STATUS;
2109}
2110
2111static void isr_rxdata(struct slgt_info *info)
2112{
2113 unsigned int count = info->rbuf_fill_count;
2114 unsigned int i = info->rbuf_fill_index;
2115 unsigned short reg;
2116
2117 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2118 reg = rd_reg16(info, RDR);
2119 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2120 if (desc_complete(info->rbufs[i])) {
2121 /* all buffers full */
2122 rx_stop(info);
2123 info->rx_restart = 1;
2124 continue;
2125 }
2126 info->rbufs[i].buf[count++] = (unsigned char)reg;
2127 /* async mode saves status byte to buffer for each data byte */
2128 if (info->params.mode == MGSL_MODE_ASYNC)
2129 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2130 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2131 /* buffer full or end of frame */
2132 set_desc_count(info->rbufs[i], count);
2133 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2134 info->rbuf_fill_count = count = 0;
2135 if (++i == info->rbuf_count)
2136 i = 0;
2137 info->pending_bh |= BH_RECEIVE;
2138 }
2139 }
2140
2141 info->rbuf_fill_index = i;
2142 info->rbuf_fill_count = count;
2143}
2144
2145static void isr_serial(struct slgt_info *info)
2146{
2147 unsigned short status = rd_reg16(info, SSR);
2148
2149 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2150
2151 wr_reg16(info, SSR, status); /* clear pending */
2152
2153 info->irq_occurred = true;
2154
2155 if (info->params.mode == MGSL_MODE_ASYNC) {
2156 if (status & IRQ_TXIDLE) {
2157 if (info->tx_active)
2158 isr_txeom(info, status);
2159 }
2160 if (info->rx_pio && (status & IRQ_RXDATA))
2161 isr_rxdata(info);
2162 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2163 info->icount.brk++;
2164 /* process break detection if tty control allows */
2165 if (info->port.tty) {
2166 if (!(status & info->ignore_status_mask)) {
2167 if (info->read_status_mask & MASK_BREAK) {
2168 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2169 if (info->port.flags & ASYNC_SAK)
2170 do_SAK(info->port.tty);
2171 }
2172 }
2173 }
2174 }
2175 } else {
2176 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2177 isr_txeom(info, status);
2178 if (info->rx_pio && (status & IRQ_RXDATA))
2179 isr_rxdata(info);
2180 if (status & IRQ_RXIDLE) {
2181 if (status & RXIDLE)
2182 info->icount.rxidle++;
2183 else
2184 info->icount.exithunt++;
2185 wake_up_interruptible(&info->event_wait_q);
2186 }
2187
2188 if (status & IRQ_RXOVER)
2189 rx_start(info);
2190 }
2191
2192 if (status & IRQ_DSR)
2193 dsr_change(info, status);
2194 if (status & IRQ_CTS)
2195 cts_change(info, status);
2196 if (status & IRQ_DCD)
2197 dcd_change(info, status);
2198 if (status & IRQ_RI)
2199 ri_change(info, status);
2200}
2201
2202static void isr_rdma(struct slgt_info *info)
2203{
2204 unsigned int status = rd_reg32(info, RDCSR);
2205
2206 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2207
2208 /* RDCSR (rx DMA control/status)
2209 *
2210 * 31..07 reserved
2211 * 06 save status byte to DMA buffer
2212 * 05 error
2213 * 04 eol (end of list)
2214 * 03 eob (end of buffer)
2215 * 02 IRQ enable
2216 * 01 reset
2217 * 00 enable
2218 */
2219 wr_reg32(info, RDCSR, status); /* clear pending */
2220
2221 if (status & (BIT5 + BIT4)) {
2222 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2223 info->rx_restart = true;
2224 }
2225 info->pending_bh |= BH_RECEIVE;
2226}
2227
2228static void isr_tdma(struct slgt_info *info)
2229{
2230 unsigned int status = rd_reg32(info, TDCSR);
2231
2232 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2233
2234 /* TDCSR (tx DMA control/status)
2235 *
2236 * 31..06 reserved
2237 * 05 error
2238 * 04 eol (end of list)
2239 * 03 eob (end of buffer)
2240 * 02 IRQ enable
2241 * 01 reset
2242 * 00 enable
2243 */
2244 wr_reg32(info, TDCSR, status); /* clear pending */
2245
2246 if (status & (BIT5 + BIT4 + BIT3)) {
2247 // another transmit buffer has completed
2248 // run bottom half to get more send data from user
2249 info->pending_bh |= BH_TRANSMIT;
2250 }
2251}
2252
2253/*
2254 * return true if there are unsent tx DMA buffers, otherwise false
2255 *
2256 * if there are unsent buffers then info->tbuf_start
2257 * is set to index of first unsent buffer
2258 */
2259static bool unsent_tbufs(struct slgt_info *info)
2260{
2261 unsigned int i = info->tbuf_current;
2262 bool rc = false;
2263
2264 /*
2265 * search backwards from last loaded buffer (precedes tbuf_current)
2266 * for first unsent buffer (desc_count > 0)
2267 */
2268
2269 do {
2270 if (i)
2271 i--;
2272 else
2273 i = info->tbuf_count - 1;
2274 if (!desc_count(info->tbufs[i]))
2275 break;
2276 info->tbuf_start = i;
2277 rc = true;
2278 } while (i != info->tbuf_current);
2279
2280 return rc;
2281}
2282
2283static void isr_txeom(struct slgt_info *info, unsigned short status)
2284{
2285 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2286
2287 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2288 tdma_reset(info);
2289 if (status & IRQ_TXUNDER) {
2290 unsigned short val = rd_reg16(info, TCR);
2291 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2292 wr_reg16(info, TCR, val); /* clear reset bit */
2293 }
2294
2295 if (info->tx_active) {
2296 if (info->params.mode != MGSL_MODE_ASYNC) {
2297 if (status & IRQ_TXUNDER)
2298 info->icount.txunder++;
2299 else if (status & IRQ_TXIDLE)
2300 info->icount.txok++;
2301 }
2302
2303 if (unsent_tbufs(info)) {
2304 tx_start(info);
2305 update_tx_timer(info);
2306 return;
2307 }
2308 info->tx_active = false;
2309
2310 del_timer(&info->tx_timer);
2311
2312 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2313 info->signals &= ~SerialSignal_RTS;
2314 info->drop_rts_on_tx_done = false;
2315 set_signals(info);
2316 }
2317
2318#if SYNCLINK_GENERIC_HDLC
2319 if (info->netcount)
2320 hdlcdev_tx_done(info);
2321 else
2322#endif
2323 {
2324 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2325 tx_stop(info);
2326 return;
2327 }
2328 info->pending_bh |= BH_TRANSMIT;
2329 }
2330 }
2331}
2332
2333static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2334{
2335 struct cond_wait *w, *prev;
2336
2337 /* wake processes waiting for specific transitions */
2338 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2339 if (w->data & changed) {
2340 w->data = state;
2341 wake_up_interruptible(&w->q);
2342 if (prev != NULL)
2343 prev->next = w->next;
2344 else
2345 info->gpio_wait_q = w->next;
2346 } else
2347 prev = w;
2348 }
2349}
2350
2351/* interrupt service routine
2352 *
2353 * irq interrupt number
2354 * dev_id device ID supplied during interrupt registration
2355 */
2356static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2357{
2358 struct slgt_info *info = dev_id;
2359 unsigned int gsr;
2360 unsigned int i;
2361
2362 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2363
2364 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2365 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2366 info->irq_occurred = true;
2367 for(i=0; i < info->port_count ; i++) {
2368 if (info->port_array[i] == NULL)
2369 continue;
2370 spin_lock(&info->port_array[i]->lock);
2371 if (gsr & (BIT8 << i))
2372 isr_serial(info->port_array[i]);
2373 if (gsr & (BIT16 << (i*2)))
2374 isr_rdma(info->port_array[i]);
2375 if (gsr & (BIT17 << (i*2)))
2376 isr_tdma(info->port_array[i]);
2377 spin_unlock(&info->port_array[i]->lock);
2378 }
2379 }
2380
2381 if (info->gpio_present) {
2382 unsigned int state;
2383 unsigned int changed;
2384 spin_lock(&info->lock);
2385 while ((changed = rd_reg32(info, IOSR)) != 0) {
2386 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2387 /* read latched state of GPIO signals */
2388 state = rd_reg32(info, IOVR);
2389 /* clear pending GPIO interrupt bits */
2390 wr_reg32(info, IOSR, changed);
2391 for (i=0 ; i < info->port_count ; i++) {
2392 if (info->port_array[i] != NULL)
2393 isr_gpio(info->port_array[i], changed, state);
2394 }
2395 }
2396 spin_unlock(&info->lock);
2397 }
2398
2399 for(i=0; i < info->port_count ; i++) {
2400 struct slgt_info *port = info->port_array[i];
2401 if (port == NULL)
2402 continue;
2403 spin_lock(&port->lock);
2404 if ((port->port.count || port->netcount) &&
2405 port->pending_bh && !port->bh_running &&
2406 !port->bh_requested) {
2407 DBGISR(("%s bh queued\n", port->device_name));
2408 schedule_work(&port->task);
2409 port->bh_requested = true;
2410 }
2411 spin_unlock(&port->lock);
2412 }
2413
2414 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2415 return IRQ_HANDLED;
2416}
2417
2418static int startup(struct slgt_info *info)
2419{
2420 DBGINFO(("%s startup\n", info->device_name));
2421
2422 if (tty_port_initialized(&info->port))
2423 return 0;
2424
2425 if (!info->tx_buf) {
2426 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2427 if (!info->tx_buf) {
2428 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2429 return -ENOMEM;
2430 }
2431 }
2432
2433 info->pending_bh = 0;
2434
2435 memset(&info->icount, 0, sizeof(info->icount));
2436
2437 /* program hardware for current parameters */
2438 change_params(info);
2439
2440 if (info->port.tty)
2441 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2442
2443 tty_port_set_initialized(&info->port, 1);
2444
2445 return 0;
2446}
2447
2448/*
2449 * called by close() and hangup() to shutdown hardware
2450 */
2451static void shutdown(struct slgt_info *info)
2452{
2453 unsigned long flags;
2454
2455 if (!tty_port_initialized(&info->port))
2456 return;
2457
2458 DBGINFO(("%s shutdown\n", info->device_name));
2459
2460 /* clear status wait queue because status changes */
2461 /* can't happen after shutting down the hardware */
2462 wake_up_interruptible(&info->status_event_wait_q);
2463 wake_up_interruptible(&info->event_wait_q);
2464
2465 del_timer_sync(&info->tx_timer);
2466 del_timer_sync(&info->rx_timer);
2467
2468 kfree(info->tx_buf);
2469 info->tx_buf = NULL;
2470
2471 spin_lock_irqsave(&info->lock,flags);
2472
2473 tx_stop(info);
2474 rx_stop(info);
2475
2476 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2477
2478 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2479 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2480 set_signals(info);
2481 }
2482
2483 flush_cond_wait(&info->gpio_wait_q);
2484
2485 spin_unlock_irqrestore(&info->lock,flags);
2486
2487 if (info->port.tty)
2488 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2489
2490 tty_port_set_initialized(&info->port, 0);
2491}
2492
2493static void program_hw(struct slgt_info *info)
2494{
2495 unsigned long flags;
2496
2497 spin_lock_irqsave(&info->lock,flags);
2498
2499 rx_stop(info);
2500 tx_stop(info);
2501
2502 if (info->params.mode != MGSL_MODE_ASYNC ||
2503 info->netcount)
2504 sync_mode(info);
2505 else
2506 async_mode(info);
2507
2508 set_signals(info);
2509
2510 info->dcd_chkcount = 0;
2511 info->cts_chkcount = 0;
2512 info->ri_chkcount = 0;
2513 info->dsr_chkcount = 0;
2514
2515 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2516 get_signals(info);
2517
2518 if (info->netcount ||
2519 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2520 rx_start(info);
2521
2522 spin_unlock_irqrestore(&info->lock,flags);
2523}
2524
2525/*
2526 * reconfigure adapter based on new parameters
2527 */
2528static void change_params(struct slgt_info *info)
2529{
2530 unsigned cflag;
2531 int bits_per_char;
2532
2533 if (!info->port.tty)
2534 return;
2535 DBGINFO(("%s change_params\n", info->device_name));
2536
2537 cflag = info->port.tty->termios.c_cflag;
2538
2539 /* if B0 rate (hangup) specified then negate RTS and DTR */
2540 /* otherwise assert RTS and DTR */
2541 if (cflag & CBAUD)
2542 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2543 else
2544 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2545
2546 /* byte size and parity */
2547
2548 switch (cflag & CSIZE) {
2549 case CS5: info->params.data_bits = 5; break;
2550 case CS6: info->params.data_bits = 6; break;
2551 case CS7: info->params.data_bits = 7; break;
2552 case CS8: info->params.data_bits = 8; break;
2553 default: info->params.data_bits = 7; break;
2554 }
2555
2556 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2557
2558 if (cflag & PARENB)
2559 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2560 else
2561 info->params.parity = ASYNC_PARITY_NONE;
2562
2563 /* calculate number of jiffies to transmit a full
2564 * FIFO (32 bytes) at specified data rate
2565 */
2566 bits_per_char = info->params.data_bits +
2567 info->params.stop_bits + 1;
2568
2569 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2570
2571 if (info->params.data_rate) {
2572 info->timeout = (32*HZ*bits_per_char) /
2573 info->params.data_rate;
2574 }
2575 info->timeout += HZ/50; /* Add .02 seconds of slop */
2576
2577 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2578 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2579
2580 /* process tty input control flags */
2581
2582 info->read_status_mask = IRQ_RXOVER;
2583 if (I_INPCK(info->port.tty))
2584 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2585 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2586 info->read_status_mask |= MASK_BREAK;
2587 if (I_IGNPAR(info->port.tty))
2588 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2589 if (I_IGNBRK(info->port.tty)) {
2590 info->ignore_status_mask |= MASK_BREAK;
2591 /* If ignoring parity and break indicators, ignore
2592 * overruns too. (For real raw support).
2593 */
2594 if (I_IGNPAR(info->port.tty))
2595 info->ignore_status_mask |= MASK_OVERRUN;
2596 }
2597
2598 program_hw(info);
2599}
2600
2601static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2602{
2603 DBGINFO(("%s get_stats\n", info->device_name));
2604 if (!user_icount) {
2605 memset(&info->icount, 0, sizeof(info->icount));
2606 } else {
2607 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2608 return -EFAULT;
2609 }
2610 return 0;
2611}
2612
2613static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2614{
2615 DBGINFO(("%s get_params\n", info->device_name));
2616 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2617 return -EFAULT;
2618 return 0;
2619}
2620
2621static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2622{
2623 unsigned long flags;
2624 MGSL_PARAMS tmp_params;
2625
2626 DBGINFO(("%s set_params\n", info->device_name));
2627 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2628 return -EFAULT;
2629
2630 spin_lock_irqsave(&info->lock, flags);
2631 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2632 info->base_clock = tmp_params.clock_speed;
2633 else
2634 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2635 spin_unlock_irqrestore(&info->lock, flags);
2636
2637 program_hw(info);
2638
2639 return 0;
2640}
2641
2642static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2643{
2644 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2645 if (put_user(info->idle_mode, idle_mode))
2646 return -EFAULT;
2647 return 0;
2648}
2649
2650static int set_txidle(struct slgt_info *info, int idle_mode)
2651{
2652 unsigned long flags;
2653 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2654 spin_lock_irqsave(&info->lock,flags);
2655 info->idle_mode = idle_mode;
2656 if (info->params.mode != MGSL_MODE_ASYNC)
2657 tx_set_idle(info);
2658 spin_unlock_irqrestore(&info->lock,flags);
2659 return 0;
2660}
2661
2662static int tx_enable(struct slgt_info *info, int enable)
2663{
2664 unsigned long flags;
2665 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2666 spin_lock_irqsave(&info->lock,flags);
2667 if (enable) {
2668 if (!info->tx_enabled)
2669 tx_start(info);
2670 } else {
2671 if (info->tx_enabled)
2672 tx_stop(info);
2673 }
2674 spin_unlock_irqrestore(&info->lock,flags);
2675 return 0;
2676}
2677
2678/*
2679 * abort transmit HDLC frame
2680 */
2681static int tx_abort(struct slgt_info *info)
2682{
2683 unsigned long flags;
2684 DBGINFO(("%s tx_abort\n", info->device_name));
2685 spin_lock_irqsave(&info->lock,flags);
2686 tdma_reset(info);
2687 spin_unlock_irqrestore(&info->lock,flags);
2688 return 0;
2689}
2690
2691static int rx_enable(struct slgt_info *info, int enable)
2692{
2693 unsigned long flags;
2694 unsigned int rbuf_fill_level;
2695 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2696 spin_lock_irqsave(&info->lock,flags);
2697 /*
2698 * enable[31..16] = receive DMA buffer fill level
2699 * 0 = noop (leave fill level unchanged)
2700 * fill level must be multiple of 4 and <= buffer size
2701 */
2702 rbuf_fill_level = ((unsigned int)enable) >> 16;
2703 if (rbuf_fill_level) {
2704 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2705 spin_unlock_irqrestore(&info->lock, flags);
2706 return -EINVAL;
2707 }
2708 info->rbuf_fill_level = rbuf_fill_level;
2709 if (rbuf_fill_level < 128)
2710 info->rx_pio = 1; /* PIO mode */
2711 else
2712 info->rx_pio = 0; /* DMA mode */
2713 rx_stop(info); /* restart receiver to use new fill level */
2714 }
2715
2716 /*
2717 * enable[1..0] = receiver enable command
2718 * 0 = disable
2719 * 1 = enable
2720 * 2 = enable or force hunt mode if already enabled
2721 */
2722 enable &= 3;
2723 if (enable) {
2724 if (!info->rx_enabled)
2725 rx_start(info);
2726 else if (enable == 2) {
2727 /* force hunt mode (write 1 to RCR[3]) */
2728 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2729 }
2730 } else {
2731 if (info->rx_enabled)
2732 rx_stop(info);
2733 }
2734 spin_unlock_irqrestore(&info->lock,flags);
2735 return 0;
2736}
2737
2738/*
2739 * wait for specified event to occur
2740 */
2741static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2742{
2743 unsigned long flags;
2744 int s;
2745 int rc=0;
2746 struct mgsl_icount cprev, cnow;
2747 int events;
2748 int mask;
2749 struct _input_signal_events oldsigs, newsigs;
2750 DECLARE_WAITQUEUE(wait, current);
2751
2752 if (get_user(mask, mask_ptr))
2753 return -EFAULT;
2754
2755 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2756
2757 spin_lock_irqsave(&info->lock,flags);
2758
2759 /* return immediately if state matches requested events */
2760 get_signals(info);
2761 s = info->signals;
2762
2763 events = mask &
2764 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2765 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2766 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2767 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2768 if (events) {
2769 spin_unlock_irqrestore(&info->lock,flags);
2770 goto exit;
2771 }
2772
2773 /* save current irq counts */
2774 cprev = info->icount;
2775 oldsigs = info->input_signal_events;
2776
2777 /* enable hunt and idle irqs if needed */
2778 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2779 unsigned short val = rd_reg16(info, SCR);
2780 if (!(val & IRQ_RXIDLE))
2781 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2782 }
2783
2784 set_current_state(TASK_INTERRUPTIBLE);
2785 add_wait_queue(&info->event_wait_q, &wait);
2786
2787 spin_unlock_irqrestore(&info->lock,flags);
2788
2789 for(;;) {
2790 schedule();
2791 if (signal_pending(current)) {
2792 rc = -ERESTARTSYS;
2793 break;
2794 }
2795
2796 /* get current irq counts */
2797 spin_lock_irqsave(&info->lock,flags);
2798 cnow = info->icount;
2799 newsigs = info->input_signal_events;
2800 set_current_state(TASK_INTERRUPTIBLE);
2801 spin_unlock_irqrestore(&info->lock,flags);
2802
2803 /* if no change, wait aborted for some reason */
2804 if (newsigs.dsr_up == oldsigs.dsr_up &&
2805 newsigs.dsr_down == oldsigs.dsr_down &&
2806 newsigs.dcd_up == oldsigs.dcd_up &&
2807 newsigs.dcd_down == oldsigs.dcd_down &&
2808 newsigs.cts_up == oldsigs.cts_up &&
2809 newsigs.cts_down == oldsigs.cts_down &&
2810 newsigs.ri_up == oldsigs.ri_up &&
2811 newsigs.ri_down == oldsigs.ri_down &&
2812 cnow.exithunt == cprev.exithunt &&
2813 cnow.rxidle == cprev.rxidle) {
2814 rc = -EIO;
2815 break;
2816 }
2817
2818 events = mask &
2819 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2820 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2821 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2822 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2823 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2824 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2825 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2826 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2827 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2828 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2829 if (events)
2830 break;
2831
2832 cprev = cnow;
2833 oldsigs = newsigs;
2834 }
2835
2836 remove_wait_queue(&info->event_wait_q, &wait);
2837 set_current_state(TASK_RUNNING);
2838
2839
2840 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2841 spin_lock_irqsave(&info->lock,flags);
2842 if (!waitqueue_active(&info->event_wait_q)) {
2843 /* disable enable exit hunt mode/idle rcvd IRQs */
2844 wr_reg16(info, SCR,
2845 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2846 }
2847 spin_unlock_irqrestore(&info->lock,flags);
2848 }
2849exit:
2850 if (rc == 0)
2851 rc = put_user(events, mask_ptr);
2852 return rc;
2853}
2854
2855static int get_interface(struct slgt_info *info, int __user *if_mode)
2856{
2857 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2858 if (put_user(info->if_mode, if_mode))
2859 return -EFAULT;
2860 return 0;
2861}
2862
2863static int set_interface(struct slgt_info *info, int if_mode)
2864{
2865 unsigned long flags;
2866 unsigned short val;
2867
2868 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2869 spin_lock_irqsave(&info->lock,flags);
2870 info->if_mode = if_mode;
2871
2872 msc_set_vcr(info);
2873
2874 /* TCR (tx control) 07 1=RTS driver control */
2875 val = rd_reg16(info, TCR);
2876 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2877 val |= BIT7;
2878 else
2879 val &= ~BIT7;
2880 wr_reg16(info, TCR, val);
2881
2882 spin_unlock_irqrestore(&info->lock,flags);
2883 return 0;
2884}
2885
2886static int get_xsync(struct slgt_info *info, int __user *xsync)
2887{
2888 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2889 if (put_user(info->xsync, xsync))
2890 return -EFAULT;
2891 return 0;
2892}
2893
2894/*
2895 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2896 *
2897 * sync pattern is contained in least significant bytes of value
2898 * most significant byte of sync pattern is oldest (1st sent/detected)
2899 */
2900static int set_xsync(struct slgt_info *info, int xsync)
2901{
2902 unsigned long flags;
2903
2904 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2905 spin_lock_irqsave(&info->lock, flags);
2906 info->xsync = xsync;
2907 wr_reg32(info, XSR, xsync);
2908 spin_unlock_irqrestore(&info->lock, flags);
2909 return 0;
2910}
2911
2912static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2913{
2914 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2915 if (put_user(info->xctrl, xctrl))
2916 return -EFAULT;
2917 return 0;
2918}
2919
2920/*
2921 * set extended control options
2922 *
2923 * xctrl[31:19] reserved, must be zero
2924 * xctrl[18:17] extended sync pattern length in bytes
2925 * 00 = 1 byte in xsr[7:0]
2926 * 01 = 2 bytes in xsr[15:0]
2927 * 10 = 3 bytes in xsr[23:0]
2928 * 11 = 4 bytes in xsr[31:0]
2929 * xctrl[16] 1 = enable terminal count, 0=disabled
2930 * xctrl[15:0] receive terminal count for fixed length packets
2931 * value is count minus one (0 = 1 byte packet)
2932 * when terminal count is reached, receiver
2933 * automatically returns to hunt mode and receive
2934 * FIFO contents are flushed to DMA buffers with
2935 * end of frame (EOF) status
2936 */
2937static int set_xctrl(struct slgt_info *info, int xctrl)
2938{
2939 unsigned long flags;
2940
2941 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2942 spin_lock_irqsave(&info->lock, flags);
2943 info->xctrl = xctrl;
2944 wr_reg32(info, XCR, xctrl);
2945 spin_unlock_irqrestore(&info->lock, flags);
2946 return 0;
2947}
2948
2949/*
2950 * set general purpose IO pin state and direction
2951 *
2952 * user_gpio fields:
2953 * state each bit indicates a pin state
2954 * smask set bit indicates pin state to set
2955 * dir each bit indicates a pin direction (0=input, 1=output)
2956 * dmask set bit indicates pin direction to set
2957 */
2958static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2959{
2960 unsigned long flags;
2961 struct gpio_desc gpio;
2962 __u32 data;
2963
2964 if (!info->gpio_present)
2965 return -EINVAL;
2966 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2967 return -EFAULT;
2968 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2969 info->device_name, gpio.state, gpio.smask,
2970 gpio.dir, gpio.dmask));
2971
2972 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2973 if (gpio.dmask) {
2974 data = rd_reg32(info, IODR);
2975 data |= gpio.dmask & gpio.dir;
2976 data &= ~(gpio.dmask & ~gpio.dir);
2977 wr_reg32(info, IODR, data);
2978 }
2979 if (gpio.smask) {
2980 data = rd_reg32(info, IOVR);
2981 data |= gpio.smask & gpio.state;
2982 data &= ~(gpio.smask & ~gpio.state);
2983 wr_reg32(info, IOVR, data);
2984 }
2985 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2986
2987 return 0;
2988}
2989
2990/*
2991 * get general purpose IO pin state and direction
2992 */
2993static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2994{
2995 struct gpio_desc gpio;
2996 if (!info->gpio_present)
2997 return -EINVAL;
2998 gpio.state = rd_reg32(info, IOVR);
2999 gpio.smask = 0xffffffff;
3000 gpio.dir = rd_reg32(info, IODR);
3001 gpio.dmask = 0xffffffff;
3002 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3003 return -EFAULT;
3004 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3005 info->device_name, gpio.state, gpio.dir));
3006 return 0;
3007}
3008
3009/*
3010 * conditional wait facility
3011 */
3012static void init_cond_wait(struct cond_wait *w, unsigned int data)
3013{
3014 init_waitqueue_head(&w->q);
3015 init_waitqueue_entry(&w->wait, current);
3016 w->data = data;
3017}
3018
3019static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3020{
3021 set_current_state(TASK_INTERRUPTIBLE);
3022 add_wait_queue(&w->q, &w->wait);
3023 w->next = *head;
3024 *head = w;
3025}
3026
3027static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3028{
3029 struct cond_wait *w, *prev;
3030 remove_wait_queue(&cw->q, &cw->wait);
3031 set_current_state(TASK_RUNNING);
3032 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3033 if (w == cw) {
3034 if (prev != NULL)
3035 prev->next = w->next;
3036 else
3037 *head = w->next;
3038 break;
3039 }
3040 }
3041}
3042
3043static void flush_cond_wait(struct cond_wait **head)
3044{
3045 while (*head != NULL) {
3046 wake_up_interruptible(&(*head)->q);
3047 *head = (*head)->next;
3048 }
3049}
3050
3051/*
3052 * wait for general purpose I/O pin(s) to enter specified state
3053 *
3054 * user_gpio fields:
3055 * state - bit indicates target pin state
3056 * smask - set bit indicates watched pin
3057 *
3058 * The wait ends when at least one watched pin enters the specified
3059 * state. When 0 (no error) is returned, user_gpio->state is set to the
3060 * state of all GPIO pins when the wait ends.
3061 *
3062 * Note: Each pin may be a dedicated input, dedicated output, or
3063 * configurable input/output. The number and configuration of pins
3064 * varies with the specific adapter model. Only input pins (dedicated
3065 * or configured) can be monitored with this function.
3066 */
3067static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3068{
3069 unsigned long flags;
3070 int rc = 0;
3071 struct gpio_desc gpio;
3072 struct cond_wait wait;
3073 u32 state;
3074
3075 if (!info->gpio_present)
3076 return -EINVAL;
3077 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3078 return -EFAULT;
3079 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3080 info->device_name, gpio.state, gpio.smask));
3081 /* ignore output pins identified by set IODR bit */
3082 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3083 return -EINVAL;
3084 init_cond_wait(&wait, gpio.smask);
3085
3086 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3087 /* enable interrupts for watched pins */
3088 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3089 /* get current pin states */
3090 state = rd_reg32(info, IOVR);
3091
3092 if (gpio.smask & ~(state ^ gpio.state)) {
3093 /* already in target state */
3094 gpio.state = state;
3095 } else {
3096 /* wait for target state */
3097 add_cond_wait(&info->gpio_wait_q, &wait);
3098 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3099 schedule();
3100 if (signal_pending(current))
3101 rc = -ERESTARTSYS;
3102 else
3103 gpio.state = wait.data;
3104 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3105 remove_cond_wait(&info->gpio_wait_q, &wait);
3106 }
3107
3108 /* disable all GPIO interrupts if no waiting processes */
3109 if (info->gpio_wait_q == NULL)
3110 wr_reg32(info, IOER, 0);
3111 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3112
3113 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3114 rc = -EFAULT;
3115 return rc;
3116}
3117
3118static int modem_input_wait(struct slgt_info *info,int arg)
3119{
3120 unsigned long flags;
3121 int rc;
3122 struct mgsl_icount cprev, cnow;
3123 DECLARE_WAITQUEUE(wait, current);
3124
3125 /* save current irq counts */
3126 spin_lock_irqsave(&info->lock,flags);
3127 cprev = info->icount;
3128 add_wait_queue(&info->status_event_wait_q, &wait);
3129 set_current_state(TASK_INTERRUPTIBLE);
3130 spin_unlock_irqrestore(&info->lock,flags);
3131
3132 for(;;) {
3133 schedule();
3134 if (signal_pending(current)) {
3135 rc = -ERESTARTSYS;
3136 break;
3137 }
3138
3139 /* get new irq counts */
3140 spin_lock_irqsave(&info->lock,flags);
3141 cnow = info->icount;
3142 set_current_state(TASK_INTERRUPTIBLE);
3143 spin_unlock_irqrestore(&info->lock,flags);
3144
3145 /* if no change, wait aborted for some reason */
3146 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3147 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3148 rc = -EIO;
3149 break;
3150 }
3151
3152 /* check for change in caller specified modem input */
3153 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3154 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3155 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3156 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3157 rc = 0;
3158 break;
3159 }
3160
3161 cprev = cnow;
3162 }
3163 remove_wait_queue(&info->status_event_wait_q, &wait);
3164 set_current_state(TASK_RUNNING);
3165 return rc;
3166}
3167
3168/*
3169 * return state of serial control and status signals
3170 */
3171static int tiocmget(struct tty_struct *tty)
3172{
3173 struct slgt_info *info = tty->driver_data;
3174 unsigned int result;
3175 unsigned long flags;
3176
3177 spin_lock_irqsave(&info->lock,flags);
3178 get_signals(info);
3179 spin_unlock_irqrestore(&info->lock,flags);
3180
3181 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3182 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3183 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3184 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3185 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3186 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3187
3188 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3189 return result;
3190}
3191
3192/*
3193 * set modem control signals (DTR/RTS)
3194 *
3195 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3196 * TIOCMSET = set/clear signal values
3197 * value bit mask for command
3198 */
3199static int tiocmset(struct tty_struct *tty,
3200 unsigned int set, unsigned int clear)
3201{
3202 struct slgt_info *info = tty->driver_data;
3203 unsigned long flags;
3204
3205 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3206
3207 if (set & TIOCM_RTS)
3208 info->signals |= SerialSignal_RTS;
3209 if (set & TIOCM_DTR)
3210 info->signals |= SerialSignal_DTR;
3211 if (clear & TIOCM_RTS)
3212 info->signals &= ~SerialSignal_RTS;
3213 if (clear & TIOCM_DTR)
3214 info->signals &= ~SerialSignal_DTR;
3215
3216 spin_lock_irqsave(&info->lock,flags);
3217 set_signals(info);
3218 spin_unlock_irqrestore(&info->lock,flags);
3219 return 0;
3220}
3221
3222static int carrier_raised(struct tty_port *port)
3223{
3224 unsigned long flags;
3225 struct slgt_info *info = container_of(port, struct slgt_info, port);
3226
3227 spin_lock_irqsave(&info->lock,flags);
3228 get_signals(info);
3229 spin_unlock_irqrestore(&info->lock,flags);
3230 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3231}
3232
3233static void dtr_rts(struct tty_port *port, int on)
3234{
3235 unsigned long flags;
3236 struct slgt_info *info = container_of(port, struct slgt_info, port);
3237
3238 spin_lock_irqsave(&info->lock,flags);
3239 if (on)
3240 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3241 else
3242 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3243 set_signals(info);
3244 spin_unlock_irqrestore(&info->lock,flags);
3245}
3246
3247
3248/*
3249 * block current process until the device is ready to open
3250 */
3251static int block_til_ready(struct tty_struct *tty, struct file *filp,
3252 struct slgt_info *info)
3253{
3254 DECLARE_WAITQUEUE(wait, current);
3255 int retval;
3256 bool do_clocal = false;
3257 unsigned long flags;
3258 int cd;
3259 struct tty_port *port = &info->port;
3260
3261 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3262
3263 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3264 /* nonblock mode is set or port is not enabled */
3265 tty_port_set_active(port, 1);
3266 return 0;
3267 }
3268
3269 if (C_CLOCAL(tty))
3270 do_clocal = true;
3271
3272 /* Wait for carrier detect and the line to become
3273 * free (i.e., not in use by the callout). While we are in
3274 * this loop, port->count is dropped by one, so that
3275 * close() knows when to free things. We restore it upon
3276 * exit, either normal or abnormal.
3277 */
3278
3279 retval = 0;
3280 add_wait_queue(&port->open_wait, &wait);
3281
3282 spin_lock_irqsave(&info->lock, flags);
3283 port->count--;
3284 spin_unlock_irqrestore(&info->lock, flags);
3285 port->blocked_open++;
3286
3287 while (1) {
3288 if (C_BAUD(tty) && tty_port_initialized(port))
3289 tty_port_raise_dtr_rts(port);
3290
3291 set_current_state(TASK_INTERRUPTIBLE);
3292
3293 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3294 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3295 -EAGAIN : -ERESTARTSYS;
3296 break;
3297 }
3298
3299 cd = tty_port_carrier_raised(port);
3300 if (do_clocal || cd)
3301 break;
3302
3303 if (signal_pending(current)) {
3304 retval = -ERESTARTSYS;
3305 break;
3306 }
3307
3308 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3309 tty_unlock(tty);
3310 schedule();
3311 tty_lock(tty);
3312 }
3313
3314 set_current_state(TASK_RUNNING);
3315 remove_wait_queue(&port->open_wait, &wait);
3316
3317 if (!tty_hung_up_p(filp))
3318 port->count++;
3319 port->blocked_open--;
3320
3321 if (!retval)
3322 tty_port_set_active(port, 1);
3323
3324 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3325 return retval;
3326}
3327
3328/*
3329 * allocate buffers used for calling line discipline receive_buf
3330 * directly in synchronous mode
3331 * note: add 5 bytes to max frame size to allow appending
3332 * 32-bit CRC and status byte when configured to do so
3333 */
3334static int alloc_tmp_rbuf(struct slgt_info *info)
3335{
3336 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3337 if (info->tmp_rbuf == NULL)
3338 return -ENOMEM;
3339 /* unused flag buffer to satisfy receive_buf calling interface */
3340 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3341 if (!info->flag_buf) {
3342 kfree(info->tmp_rbuf);
3343 info->tmp_rbuf = NULL;
3344 return -ENOMEM;
3345 }
3346 return 0;
3347}
3348
3349static void free_tmp_rbuf(struct slgt_info *info)
3350{
3351 kfree(info->tmp_rbuf);
3352 info->tmp_rbuf = NULL;
3353 kfree(info->flag_buf);
3354 info->flag_buf = NULL;
3355}
3356
3357/*
3358 * allocate DMA descriptor lists.
3359 */
3360static int alloc_desc(struct slgt_info *info)
3361{
3362 unsigned int i;
3363 unsigned int pbufs;
3364
3365 /* allocate memory to hold descriptor lists */
3366 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3367 &info->bufs_dma_addr);
3368 if (info->bufs == NULL)
3369 return -ENOMEM;
3370
3371 info->rbufs = (struct slgt_desc*)info->bufs;
3372 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3373
3374 pbufs = (unsigned int)info->bufs_dma_addr;
3375
3376 /*
3377 * Build circular lists of descriptors
3378 */
3379
3380 for (i=0; i < info->rbuf_count; i++) {
3381 /* physical address of this descriptor */
3382 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3383
3384 /* physical address of next descriptor */
3385 if (i == info->rbuf_count - 1)
3386 info->rbufs[i].next = cpu_to_le32(pbufs);
3387 else
3388 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3389 set_desc_count(info->rbufs[i], DMABUFSIZE);
3390 }
3391
3392 for (i=0; i < info->tbuf_count; i++) {
3393 /* physical address of this descriptor */
3394 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3395
3396 /* physical address of next descriptor */
3397 if (i == info->tbuf_count - 1)
3398 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3399 else
3400 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3401 }
3402
3403 return 0;
3404}
3405
3406static void free_desc(struct slgt_info *info)
3407{
3408 if (info->bufs != NULL) {
3409 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3410 info->bufs = NULL;
3411 info->rbufs = NULL;
3412 info->tbufs = NULL;
3413 }
3414}
3415
3416static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3417{
3418 int i;
3419 for (i=0; i < count; i++) {
3420 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3421 return -ENOMEM;
3422 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3423 }
3424 return 0;
3425}
3426
3427static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3428{
3429 int i;
3430 for (i=0; i < count; i++) {
3431 if (bufs[i].buf == NULL)
3432 continue;
3433 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3434 bufs[i].buf = NULL;
3435 }
3436}
3437
3438static int alloc_dma_bufs(struct slgt_info *info)
3439{
3440 info->rbuf_count = 32;
3441 info->tbuf_count = 32;
3442
3443 if (alloc_desc(info) < 0 ||
3444 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3445 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3446 alloc_tmp_rbuf(info) < 0) {
3447 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3448 return -ENOMEM;
3449 }
3450 reset_rbufs(info);
3451 return 0;
3452}
3453
3454static void free_dma_bufs(struct slgt_info *info)
3455{
3456 if (info->bufs) {
3457 free_bufs(info, info->rbufs, info->rbuf_count);
3458 free_bufs(info, info->tbufs, info->tbuf_count);
3459 free_desc(info);
3460 }
3461 free_tmp_rbuf(info);
3462}
3463
3464static int claim_resources(struct slgt_info *info)
3465{
3466 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3467 DBGERR(("%s reg addr conflict, addr=%08X\n",
3468 info->device_name, info->phys_reg_addr));
3469 info->init_error = DiagStatus_AddressConflict;
3470 goto errout;
3471 }
3472 else
3473 info->reg_addr_requested = true;
3474
3475 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3476 if (!info->reg_addr) {
3477 DBGERR(("%s can't map device registers, addr=%08X\n",
3478 info->device_name, info->phys_reg_addr));
3479 info->init_error = DiagStatus_CantAssignPciResources;
3480 goto errout;
3481 }
3482 return 0;
3483
3484errout:
3485 release_resources(info);
3486 return -ENODEV;
3487}
3488
3489static void release_resources(struct slgt_info *info)
3490{
3491 if (info->irq_requested) {
3492 free_irq(info->irq_level, info);
3493 info->irq_requested = false;
3494 }
3495
3496 if (info->reg_addr_requested) {
3497 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3498 info->reg_addr_requested = false;
3499 }
3500
3501 if (info->reg_addr) {
3502 iounmap(info->reg_addr);
3503 info->reg_addr = NULL;
3504 }
3505}
3506
3507/* Add the specified device instance data structure to the
3508 * global linked list of devices and increment the device count.
3509 */
3510static void add_device(struct slgt_info *info)
3511{
3512 char *devstr;
3513
3514 info->next_device = NULL;
3515 info->line = slgt_device_count;
3516 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3517
3518 if (info->line < MAX_DEVICES) {
3519 if (maxframe[info->line])
3520 info->max_frame_size = maxframe[info->line];
3521 }
3522
3523 slgt_device_count++;
3524
3525 if (!slgt_device_list)
3526 slgt_device_list = info;
3527 else {
3528 struct slgt_info *current_dev = slgt_device_list;
3529 while(current_dev->next_device)
3530 current_dev = current_dev->next_device;
3531 current_dev->next_device = info;
3532 }
3533
3534 if (info->max_frame_size < 4096)
3535 info->max_frame_size = 4096;
3536 else if (info->max_frame_size > 65535)
3537 info->max_frame_size = 65535;
3538
3539 switch(info->pdev->device) {
3540 case SYNCLINK_GT_DEVICE_ID:
3541 devstr = "GT";
3542 break;
3543 case SYNCLINK_GT2_DEVICE_ID:
3544 devstr = "GT2";
3545 break;
3546 case SYNCLINK_GT4_DEVICE_ID:
3547 devstr = "GT4";
3548 break;
3549 case SYNCLINK_AC_DEVICE_ID:
3550 devstr = "AC";
3551 info->params.mode = MGSL_MODE_ASYNC;
3552 break;
3553 default:
3554 devstr = "(unknown model)";
3555 }
3556 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3557 devstr, info->device_name, info->phys_reg_addr,
3558 info->irq_level, info->max_frame_size);
3559
3560#if SYNCLINK_GENERIC_HDLC
3561 hdlcdev_init(info);
3562#endif
3563}
3564
3565static const struct tty_port_operations slgt_port_ops = {
3566 .carrier_raised = carrier_raised,
3567 .dtr_rts = dtr_rts,
3568};
3569
3570/*
3571 * allocate device instance structure, return NULL on failure
3572 */
3573static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3574{
3575 struct slgt_info *info;
3576
3577 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3578
3579 if (!info) {
3580 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3581 driver_name, adapter_num, port_num));
3582 } else {
3583 tty_port_init(&info->port);
3584 info->port.ops = &slgt_port_ops;
3585 info->magic = MGSL_MAGIC;
3586 INIT_WORK(&info->task, bh_handler);
3587 info->max_frame_size = 4096;
3588 info->base_clock = 14745600;
3589 info->rbuf_fill_level = DMABUFSIZE;
3590 info->port.close_delay = 5*HZ/10;
3591 info->port.closing_wait = 30*HZ;
3592 init_waitqueue_head(&info->status_event_wait_q);
3593 init_waitqueue_head(&info->event_wait_q);
3594 spin_lock_init(&info->netlock);
3595 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3596 info->idle_mode = HDLC_TXIDLE_FLAGS;
3597 info->adapter_num = adapter_num;
3598 info->port_num = port_num;
3599
3600 timer_setup(&info->tx_timer, tx_timeout, 0);
3601 timer_setup(&info->rx_timer, rx_timeout, 0);
3602
3603 /* Copy configuration info to device instance data */
3604 info->pdev = pdev;
3605 info->irq_level = pdev->irq;
3606 info->phys_reg_addr = pci_resource_start(pdev,0);
3607
3608 info->bus_type = MGSL_BUS_TYPE_PCI;
3609 info->irq_flags = IRQF_SHARED;
3610
3611 info->init_error = -1; /* assume error, set to 0 on successful init */
3612 }
3613
3614 return info;
3615}
3616
3617static void device_init(int adapter_num, struct pci_dev *pdev)
3618{
3619 struct slgt_info *port_array[SLGT_MAX_PORTS];
3620 int i;
3621 int port_count = 1;
3622
3623 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3624 port_count = 2;
3625 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3626 port_count = 4;
3627
3628 /* allocate device instances for all ports */
3629 for (i=0; i < port_count; ++i) {
3630 port_array[i] = alloc_dev(adapter_num, i, pdev);
3631 if (port_array[i] == NULL) {
3632 for (--i; i >= 0; --i) {
3633 tty_port_destroy(&port_array[i]->port);
3634 kfree(port_array[i]);
3635 }
3636 return;
3637 }
3638 }
3639
3640 /* give copy of port_array to all ports and add to device list */
3641 for (i=0; i < port_count; ++i) {
3642 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3643 add_device(port_array[i]);
3644 port_array[i]->port_count = port_count;
3645 spin_lock_init(&port_array[i]->lock);
3646 }
3647
3648 /* Allocate and claim adapter resources */
3649 if (!claim_resources(port_array[0])) {
3650
3651 alloc_dma_bufs(port_array[0]);
3652
3653 /* copy resource information from first port to others */
3654 for (i = 1; i < port_count; ++i) {
3655 port_array[i]->irq_level = port_array[0]->irq_level;
3656 port_array[i]->reg_addr = port_array[0]->reg_addr;
3657 alloc_dma_bufs(port_array[i]);
3658 }
3659
3660 if (request_irq(port_array[0]->irq_level,
3661 slgt_interrupt,
3662 port_array[0]->irq_flags,
3663 port_array[0]->device_name,
3664 port_array[0]) < 0) {
3665 DBGERR(("%s request_irq failed IRQ=%d\n",
3666 port_array[0]->device_name,
3667 port_array[0]->irq_level));
3668 } else {
3669 port_array[0]->irq_requested = true;
3670 adapter_test(port_array[0]);
3671 for (i=1 ; i < port_count ; i++) {
3672 port_array[i]->init_error = port_array[0]->init_error;
3673 port_array[i]->gpio_present = port_array[0]->gpio_present;
3674 }
3675 }
3676 }
3677
3678 for (i = 0; i < port_count; ++i) {
3679 struct slgt_info *info = port_array[i];
3680 tty_port_register_device(&info->port, serial_driver, info->line,
3681 &info->pdev->dev);
3682 }
3683}
3684
3685static int init_one(struct pci_dev *dev,
3686 const struct pci_device_id *ent)
3687{
3688 if (pci_enable_device(dev)) {
3689 printk("error enabling pci device %p\n", dev);
3690 return -EIO;
3691 }
3692 pci_set_master(dev);
3693 device_init(slgt_device_count, dev);
3694 return 0;
3695}
3696
3697static void remove_one(struct pci_dev *dev)
3698{
3699}
3700
3701static const struct tty_operations ops = {
3702 .open = open,
3703 .close = close,
3704 .write = write,
3705 .put_char = put_char,
3706 .flush_chars = flush_chars,
3707 .write_room = write_room,
3708 .chars_in_buffer = chars_in_buffer,
3709 .flush_buffer = flush_buffer,
3710 .ioctl = ioctl,
3711 .compat_ioctl = slgt_compat_ioctl,
3712 .throttle = throttle,
3713 .unthrottle = unthrottle,
3714 .send_xchar = send_xchar,
3715 .break_ctl = set_break,
3716 .wait_until_sent = wait_until_sent,
3717 .set_termios = set_termios,
3718 .stop = tx_hold,
3719 .start = tx_release,
3720 .hangup = hangup,
3721 .tiocmget = tiocmget,
3722 .tiocmset = tiocmset,
3723 .get_icount = get_icount,
3724 .proc_fops = &synclink_gt_proc_fops,
3725};
3726
3727static void slgt_cleanup(void)
3728{
3729 int rc;
3730 struct slgt_info *info;
3731 struct slgt_info *tmp;
3732
3733 printk(KERN_INFO "unload %s\n", driver_name);
3734
3735 if (serial_driver) {
3736 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3737 tty_unregister_device(serial_driver, info->line);
3738 rc = tty_unregister_driver(serial_driver);
3739 if (rc)
3740 DBGERR(("tty_unregister_driver error=%d\n", rc));
3741 put_tty_driver(serial_driver);
3742 }
3743
3744 /* reset devices */
3745 info = slgt_device_list;
3746 while(info) {
3747 reset_port(info);
3748 info = info->next_device;
3749 }
3750
3751 /* release devices */
3752 info = slgt_device_list;
3753 while(info) {
3754#if SYNCLINK_GENERIC_HDLC
3755 hdlcdev_exit(info);
3756#endif
3757 free_dma_bufs(info);
3758 free_tmp_rbuf(info);
3759 if (info->port_num == 0)
3760 release_resources(info);
3761 tmp = info;
3762 info = info->next_device;
3763 tty_port_destroy(&tmp->port);
3764 kfree(tmp);
3765 }
3766
3767 if (pci_registered)
3768 pci_unregister_driver(&pci_driver);
3769}
3770
3771/*
3772 * Driver initialization entry point.
3773 */
3774static int __init slgt_init(void)
3775{
3776 int rc;
3777
3778 printk(KERN_INFO "%s\n", driver_name);
3779
3780 serial_driver = alloc_tty_driver(MAX_DEVICES);
3781 if (!serial_driver) {
3782 printk("%s can't allocate tty driver\n", driver_name);
3783 return -ENOMEM;
3784 }
3785
3786 /* Initialize the tty_driver structure */
3787
3788 serial_driver->driver_name = slgt_driver_name;
3789 serial_driver->name = tty_dev_prefix;
3790 serial_driver->major = ttymajor;
3791 serial_driver->minor_start = 64;
3792 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3793 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3794 serial_driver->init_termios = tty_std_termios;
3795 serial_driver->init_termios.c_cflag =
3796 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3797 serial_driver->init_termios.c_ispeed = 9600;
3798 serial_driver->init_termios.c_ospeed = 9600;
3799 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3800 tty_set_operations(serial_driver, &ops);
3801 if ((rc = tty_register_driver(serial_driver)) < 0) {
3802 DBGERR(("%s can't register serial driver\n", driver_name));
3803 put_tty_driver(serial_driver);
3804 serial_driver = NULL;
3805 goto error;
3806 }
3807
3808 printk(KERN_INFO "%s, tty major#%d\n",
3809 driver_name, serial_driver->major);
3810
3811 slgt_device_count = 0;
3812 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3813 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3814 goto error;
3815 }
3816 pci_registered = true;
3817
3818 if (!slgt_device_list)
3819 printk("%s no devices found\n",driver_name);
3820
3821 return 0;
3822
3823error:
3824 slgt_cleanup();
3825 return rc;
3826}
3827
3828static void __exit slgt_exit(void)
3829{
3830 slgt_cleanup();
3831}
3832
3833module_init(slgt_init);
3834module_exit(slgt_exit);
3835
3836/*
3837 * register access routines
3838 */
3839
3840#define CALC_REGADDR() \
3841 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3842 if (addr >= 0x80) \
3843 reg_addr += (info->port_num) * 32; \
3844 else if (addr >= 0x40) \
3845 reg_addr += (info->port_num) * 16;
3846
3847static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3848{
3849 CALC_REGADDR();
3850 return readb((void __iomem *)reg_addr);
3851}
3852
3853static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3854{
3855 CALC_REGADDR();
3856 writeb(value, (void __iomem *)reg_addr);
3857}
3858
3859static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3860{
3861 CALC_REGADDR();
3862 return readw((void __iomem *)reg_addr);
3863}
3864
3865static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3866{
3867 CALC_REGADDR();
3868 writew(value, (void __iomem *)reg_addr);
3869}
3870
3871static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3872{
3873 CALC_REGADDR();
3874 return readl((void __iomem *)reg_addr);
3875}
3876
3877static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3878{
3879 CALC_REGADDR();
3880 writel(value, (void __iomem *)reg_addr);
3881}
3882
3883static void rdma_reset(struct slgt_info *info)
3884{
3885 unsigned int i;
3886
3887 /* set reset bit */
3888 wr_reg32(info, RDCSR, BIT1);
3889
3890 /* wait for enable bit cleared */
3891 for(i=0 ; i < 1000 ; i++)
3892 if (!(rd_reg32(info, RDCSR) & BIT0))
3893 break;
3894}
3895
3896static void tdma_reset(struct slgt_info *info)
3897{
3898 unsigned int i;
3899
3900 /* set reset bit */
3901 wr_reg32(info, TDCSR, BIT1);
3902
3903 /* wait for enable bit cleared */
3904 for(i=0 ; i < 1000 ; i++)
3905 if (!(rd_reg32(info, TDCSR) & BIT0))
3906 break;
3907}
3908
3909/*
3910 * enable internal loopback
3911 * TxCLK and RxCLK are generated from BRG
3912 * and TxD is looped back to RxD internally.
3913 */
3914static void enable_loopback(struct slgt_info *info)
3915{
3916 /* SCR (serial control) BIT2=loopback enable */
3917 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3918
3919 if (info->params.mode != MGSL_MODE_ASYNC) {
3920 /* CCR (clock control)
3921 * 07..05 tx clock source (010 = BRG)
3922 * 04..02 rx clock source (010 = BRG)
3923 * 01 auxclk enable (0 = disable)
3924 * 00 BRG enable (1 = enable)
3925 *
3926 * 0100 1001
3927 */
3928 wr_reg8(info, CCR, 0x49);
3929
3930 /* set speed if available, otherwise use default */
3931 if (info->params.clock_speed)
3932 set_rate(info, info->params.clock_speed);
3933 else
3934 set_rate(info, 3686400);
3935 }
3936}
3937
3938/*
3939 * set baud rate generator to specified rate
3940 */
3941static void set_rate(struct slgt_info *info, u32 rate)
3942{
3943 unsigned int div;
3944 unsigned int osc = info->base_clock;
3945
3946 /* div = osc/rate - 1
3947 *
3948 * Round div up if osc/rate is not integer to
3949 * force to next slowest rate.
3950 */
3951
3952 if (rate) {
3953 div = osc/rate;
3954 if (!(osc % rate) && div)
3955 div--;
3956 wr_reg16(info, BDR, (unsigned short)div);
3957 }
3958}
3959
3960static void rx_stop(struct slgt_info *info)
3961{
3962 unsigned short val;
3963
3964 /* disable and reset receiver */
3965 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3966 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3967 wr_reg16(info, RCR, val); /* clear reset bit */
3968
3969 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3970
3971 /* clear pending rx interrupts */
3972 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3973
3974 rdma_reset(info);
3975
3976 info->rx_enabled = false;
3977 info->rx_restart = false;
3978}
3979
3980static void rx_start(struct slgt_info *info)
3981{
3982 unsigned short val;
3983
3984 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3985
3986 /* clear pending rx overrun IRQ */
3987 wr_reg16(info, SSR, IRQ_RXOVER);
3988
3989 /* reset and disable receiver */
3990 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3991 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3992 wr_reg16(info, RCR, val); /* clear reset bit */
3993
3994 rdma_reset(info);
3995 reset_rbufs(info);
3996
3997 if (info->rx_pio) {
3998 /* rx request when rx FIFO not empty */
3999 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4000 slgt_irq_on(info, IRQ_RXDATA);
4001 if (info->params.mode == MGSL_MODE_ASYNC) {
4002 /* enable saving of rx status */
4003 wr_reg32(info, RDCSR, BIT6);
4004 }
4005 } else {
4006 /* rx request when rx FIFO half full */
4007 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4008 /* set 1st descriptor address */
4009 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4010
4011 if (info->params.mode != MGSL_MODE_ASYNC) {
4012 /* enable rx DMA and DMA interrupt */
4013 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4014 } else {
4015 /* enable saving of rx status, rx DMA and DMA interrupt */
4016 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4017 }
4018 }
4019
4020 slgt_irq_on(info, IRQ_RXOVER);
4021
4022 /* enable receiver */
4023 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4024
4025 info->rx_restart = false;
4026 info->rx_enabled = true;
4027}
4028
4029static void tx_start(struct slgt_info *info)
4030{
4031 if (!info->tx_enabled) {
4032 wr_reg16(info, TCR,
4033 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4034 info->tx_enabled = true;
4035 }
4036
4037 if (desc_count(info->tbufs[info->tbuf_start])) {
4038 info->drop_rts_on_tx_done = false;
4039
4040 if (info->params.mode != MGSL_MODE_ASYNC) {
4041 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4042 get_signals(info);
4043 if (!(info->signals & SerialSignal_RTS)) {
4044 info->signals |= SerialSignal_RTS;
4045 set_signals(info);
4046 info->drop_rts_on_tx_done = true;
4047 }
4048 }
4049
4050 slgt_irq_off(info, IRQ_TXDATA);
4051 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4052 /* clear tx idle and underrun status bits */
4053 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4054 } else {
4055 slgt_irq_off(info, IRQ_TXDATA);
4056 slgt_irq_on(info, IRQ_TXIDLE);
4057 /* clear tx idle status bit */
4058 wr_reg16(info, SSR, IRQ_TXIDLE);
4059 }
4060 /* set 1st descriptor address and start DMA */
4061 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4062 wr_reg32(info, TDCSR, BIT2 + BIT0);
4063 info->tx_active = true;
4064 }
4065}
4066
4067static void tx_stop(struct slgt_info *info)
4068{
4069 unsigned short val;
4070
4071 del_timer(&info->tx_timer);
4072
4073 tdma_reset(info);
4074
4075 /* reset and disable transmitter */
4076 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4077 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4078
4079 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4080
4081 /* clear tx idle and underrun status bit */
4082 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4083
4084 reset_tbufs(info);
4085
4086 info->tx_enabled = false;
4087 info->tx_active = false;
4088}
4089
4090static void reset_port(struct slgt_info *info)
4091{
4092 if (!info->reg_addr)
4093 return;
4094
4095 tx_stop(info);
4096 rx_stop(info);
4097
4098 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4099 set_signals(info);
4100
4101 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4102}
4103
4104static void reset_adapter(struct slgt_info *info)
4105{
4106 int i;
4107 for (i=0; i < info->port_count; ++i) {
4108 if (info->port_array[i])
4109 reset_port(info->port_array[i]);
4110 }
4111}
4112
4113static void async_mode(struct slgt_info *info)
4114{
4115 unsigned short val;
4116
4117 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4118 tx_stop(info);
4119 rx_stop(info);
4120
4121 /* TCR (tx control)
4122 *
4123 * 15..13 mode, 010=async
4124 * 12..10 encoding, 000=NRZ
4125 * 09 parity enable
4126 * 08 1=odd parity, 0=even parity
4127 * 07 1=RTS driver control
4128 * 06 1=break enable
4129 * 05..04 character length
4130 * 00=5 bits
4131 * 01=6 bits
4132 * 10=7 bits
4133 * 11=8 bits
4134 * 03 0=1 stop bit, 1=2 stop bits
4135 * 02 reset
4136 * 01 enable
4137 * 00 auto-CTS enable
4138 */
4139 val = 0x4000;
4140
4141 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4142 val |= BIT7;
4143
4144 if (info->params.parity != ASYNC_PARITY_NONE) {
4145 val |= BIT9;
4146 if (info->params.parity == ASYNC_PARITY_ODD)
4147 val |= BIT8;
4148 }
4149
4150 switch (info->params.data_bits)
4151 {
4152 case 6: val |= BIT4; break;
4153 case 7: val |= BIT5; break;
4154 case 8: val |= BIT5 + BIT4; break;
4155 }
4156
4157 if (info->params.stop_bits != 1)
4158 val |= BIT3;
4159
4160 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4161 val |= BIT0;
4162
4163 wr_reg16(info, TCR, val);
4164
4165 /* RCR (rx control)
4166 *
4167 * 15..13 mode, 010=async
4168 * 12..10 encoding, 000=NRZ
4169 * 09 parity enable
4170 * 08 1=odd parity, 0=even parity
4171 * 07..06 reserved, must be 0
4172 * 05..04 character length
4173 * 00=5 bits
4174 * 01=6 bits
4175 * 10=7 bits
4176 * 11=8 bits
4177 * 03 reserved, must be zero
4178 * 02 reset
4179 * 01 enable
4180 * 00 auto-DCD enable
4181 */
4182 val = 0x4000;
4183
4184 if (info->params.parity != ASYNC_PARITY_NONE) {
4185 val |= BIT9;
4186 if (info->params.parity == ASYNC_PARITY_ODD)
4187 val |= BIT8;
4188 }
4189
4190 switch (info->params.data_bits)
4191 {
4192 case 6: val |= BIT4; break;
4193 case 7: val |= BIT5; break;
4194 case 8: val |= BIT5 + BIT4; break;
4195 }
4196
4197 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4198 val |= BIT0;
4199
4200 wr_reg16(info, RCR, val);
4201
4202 /* CCR (clock control)
4203 *
4204 * 07..05 011 = tx clock source is BRG/16
4205 * 04..02 010 = rx clock source is BRG
4206 * 01 0 = auxclk disabled
4207 * 00 1 = BRG enabled
4208 *
4209 * 0110 1001
4210 */
4211 wr_reg8(info, CCR, 0x69);
4212
4213 msc_set_vcr(info);
4214
4215 /* SCR (serial control)
4216 *
4217 * 15 1=tx req on FIFO half empty
4218 * 14 1=rx req on FIFO half full
4219 * 13 tx data IRQ enable
4220 * 12 tx idle IRQ enable
4221 * 11 rx break on IRQ enable
4222 * 10 rx data IRQ enable
4223 * 09 rx break off IRQ enable
4224 * 08 overrun IRQ enable
4225 * 07 DSR IRQ enable
4226 * 06 CTS IRQ enable
4227 * 05 DCD IRQ enable
4228 * 04 RI IRQ enable
4229 * 03 0=16x sampling, 1=8x sampling
4230 * 02 1=txd->rxd internal loopback enable
4231 * 01 reserved, must be zero
4232 * 00 1=master IRQ enable
4233 */
4234 val = BIT15 + BIT14 + BIT0;
4235 /* JCR[8] : 1 = x8 async mode feature available */
4236 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4237 ((info->base_clock < (info->params.data_rate * 16)) ||
4238 (info->base_clock % (info->params.data_rate * 16)))) {
4239 /* use 8x sampling */
4240 val |= BIT3;
4241 set_rate(info, info->params.data_rate * 8);
4242 } else {
4243 /* use 16x sampling */
4244 set_rate(info, info->params.data_rate * 16);
4245 }
4246 wr_reg16(info, SCR, val);
4247
4248 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4249
4250 if (info->params.loopback)
4251 enable_loopback(info);
4252}
4253
4254static void sync_mode(struct slgt_info *info)
4255{
4256 unsigned short val;
4257
4258 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4259 tx_stop(info);
4260 rx_stop(info);
4261
4262 /* TCR (tx control)
4263 *
4264 * 15..13 mode
4265 * 000=HDLC/SDLC
4266 * 001=raw bit synchronous
4267 * 010=asynchronous/isochronous
4268 * 011=monosync byte synchronous
4269 * 100=bisync byte synchronous
4270 * 101=xsync byte synchronous
4271 * 12..10 encoding
4272 * 09 CRC enable
4273 * 08 CRC32
4274 * 07 1=RTS driver control
4275 * 06 preamble enable
4276 * 05..04 preamble length
4277 * 03 share open/close flag
4278 * 02 reset
4279 * 01 enable
4280 * 00 auto-CTS enable
4281 */
4282 val = BIT2;
4283
4284 switch(info->params.mode) {
4285 case MGSL_MODE_XSYNC:
4286 val |= BIT15 + BIT13;
4287 break;
4288 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4289 case MGSL_MODE_BISYNC: val |= BIT15; break;
4290 case MGSL_MODE_RAW: val |= BIT13; break;
4291 }
4292 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4293 val |= BIT7;
4294
4295 switch(info->params.encoding)
4296 {
4297 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4298 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4299 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4300 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4301 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4302 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4303 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4304 }
4305
4306 switch (info->params.crc_type & HDLC_CRC_MASK)
4307 {
4308 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4309 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4310 }
4311
4312 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4313 val |= BIT6;
4314
4315 switch (info->params.preamble_length)
4316 {
4317 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4318 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4319 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4320 }
4321
4322 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4323 val |= BIT0;
4324
4325 wr_reg16(info, TCR, val);
4326
4327 /* TPR (transmit preamble) */
4328
4329 switch (info->params.preamble)
4330 {
4331 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4332 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4333 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4334 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4335 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4336 default: val = 0x7e; break;
4337 }
4338 wr_reg8(info, TPR, (unsigned char)val);
4339
4340 /* RCR (rx control)
4341 *
4342 * 15..13 mode
4343 * 000=HDLC/SDLC
4344 * 001=raw bit synchronous
4345 * 010=asynchronous/isochronous
4346 * 011=monosync byte synchronous
4347 * 100=bisync byte synchronous
4348 * 101=xsync byte synchronous
4349 * 12..10 encoding
4350 * 09 CRC enable
4351 * 08 CRC32
4352 * 07..03 reserved, must be 0
4353 * 02 reset
4354 * 01 enable
4355 * 00 auto-DCD enable
4356 */
4357 val = 0;
4358
4359 switch(info->params.mode) {
4360 case MGSL_MODE_XSYNC:
4361 val |= BIT15 + BIT13;
4362 break;
4363 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4364 case MGSL_MODE_BISYNC: val |= BIT15; break;
4365 case MGSL_MODE_RAW: val |= BIT13; break;
4366 }
4367
4368 switch(info->params.encoding)
4369 {
4370 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4371 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4372 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4373 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4374 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4375 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4376 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4377 }
4378
4379 switch (info->params.crc_type & HDLC_CRC_MASK)
4380 {
4381 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4382 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4383 }
4384
4385 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4386 val |= BIT0;
4387
4388 wr_reg16(info, RCR, val);
4389
4390 /* CCR (clock control)
4391 *
4392 * 07..05 tx clock source
4393 * 04..02 rx clock source
4394 * 01 auxclk enable
4395 * 00 BRG enable
4396 */
4397 val = 0;
4398
4399 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4400 {
4401 // when RxC source is DPLL, BRG generates 16X DPLL
4402 // reference clock, so take TxC from BRG/16 to get
4403 // transmit clock at actual data rate
4404 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4405 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4406 else
4407 val |= BIT6; /* 010, txclk = BRG */
4408 }
4409 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4410 val |= BIT7; /* 100, txclk = DPLL Input */
4411 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4412 val |= BIT5; /* 001, txclk = RXC Input */
4413
4414 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4415 val |= BIT3; /* 010, rxclk = BRG */
4416 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4417 val |= BIT4; /* 100, rxclk = DPLL */
4418 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4419 val |= BIT2; /* 001, rxclk = TXC Input */
4420
4421 if (info->params.clock_speed)
4422 val |= BIT1 + BIT0;
4423
4424 wr_reg8(info, CCR, (unsigned char)val);
4425
4426 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4427 {
4428 // program DPLL mode
4429 switch(info->params.encoding)
4430 {
4431 case HDLC_ENCODING_BIPHASE_MARK:
4432 case HDLC_ENCODING_BIPHASE_SPACE:
4433 val = BIT7; break;
4434 case HDLC_ENCODING_BIPHASE_LEVEL:
4435 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4436 val = BIT7 + BIT6; break;
4437 default: val = BIT6; // NRZ encodings
4438 }
4439 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4440
4441 // DPLL requires a 16X reference clock from BRG
4442 set_rate(info, info->params.clock_speed * 16);
4443 }
4444 else
4445 set_rate(info, info->params.clock_speed);
4446
4447 tx_set_idle(info);
4448
4449 msc_set_vcr(info);
4450
4451 /* SCR (serial control)
4452 *
4453 * 15 1=tx req on FIFO half empty
4454 * 14 1=rx req on FIFO half full
4455 * 13 tx data IRQ enable
4456 * 12 tx idle IRQ enable
4457 * 11 underrun IRQ enable
4458 * 10 rx data IRQ enable
4459 * 09 rx idle IRQ enable
4460 * 08 overrun IRQ enable
4461 * 07 DSR IRQ enable
4462 * 06 CTS IRQ enable
4463 * 05 DCD IRQ enable
4464 * 04 RI IRQ enable
4465 * 03 reserved, must be zero
4466 * 02 1=txd->rxd internal loopback enable
4467 * 01 reserved, must be zero
4468 * 00 1=master IRQ enable
4469 */
4470 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4471
4472 if (info->params.loopback)
4473 enable_loopback(info);
4474}
4475
4476/*
4477 * set transmit idle mode
4478 */
4479static void tx_set_idle(struct slgt_info *info)
4480{
4481 unsigned char val;
4482 unsigned short tcr;
4483
4484 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4485 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4486 */
4487 tcr = rd_reg16(info, TCR);
4488 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4489 /* disable preamble, set idle size to 16 bits */
4490 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4491 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4492 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4493 } else if (!(tcr & BIT6)) {
4494 /* preamble is disabled, set idle size to 8 bits */
4495 tcr &= ~(BIT5 + BIT4);
4496 }
4497 wr_reg16(info, TCR, tcr);
4498
4499 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4500 /* LSB of custom tx idle specified in tx idle register */
4501 val = (unsigned char)(info->idle_mode & 0xff);
4502 } else {
4503 /* standard 8 bit idle patterns */
4504 switch(info->idle_mode)
4505 {
4506 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4507 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4508 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4509 case HDLC_TXIDLE_ZEROS:
4510 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4511 default: val = 0xff;
4512 }
4513 }
4514
4515 wr_reg8(info, TIR, val);
4516}
4517
4518/*
4519 * get state of V24 status (input) signals
4520 */
4521static void get_signals(struct slgt_info *info)
4522{
4523 unsigned short status = rd_reg16(info, SSR);
4524
4525 /* clear all serial signals except RTS and DTR */
4526 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4527
4528 if (status & BIT3)
4529 info->signals |= SerialSignal_DSR;
4530 if (status & BIT2)
4531 info->signals |= SerialSignal_CTS;
4532 if (status & BIT1)
4533 info->signals |= SerialSignal_DCD;
4534 if (status & BIT0)
4535 info->signals |= SerialSignal_RI;
4536}
4537
4538/*
4539 * set V.24 Control Register based on current configuration
4540 */
4541static void msc_set_vcr(struct slgt_info *info)
4542{
4543 unsigned char val = 0;
4544
4545 /* VCR (V.24 control)
4546 *
4547 * 07..04 serial IF select
4548 * 03 DTR
4549 * 02 RTS
4550 * 01 LL
4551 * 00 RL
4552 */
4553
4554 switch(info->if_mode & MGSL_INTERFACE_MASK)
4555 {
4556 case MGSL_INTERFACE_RS232:
4557 val |= BIT5; /* 0010 */
4558 break;
4559 case MGSL_INTERFACE_V35:
4560 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4561 break;
4562 case MGSL_INTERFACE_RS422:
4563 val |= BIT6; /* 0100 */
4564 break;
4565 }
4566
4567 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4568 val |= BIT4;
4569 if (info->signals & SerialSignal_DTR)
4570 val |= BIT3;
4571 if (info->signals & SerialSignal_RTS)
4572 val |= BIT2;
4573 if (info->if_mode & MGSL_INTERFACE_LL)
4574 val |= BIT1;
4575 if (info->if_mode & MGSL_INTERFACE_RL)
4576 val |= BIT0;
4577 wr_reg8(info, VCR, val);
4578}
4579
4580/*
4581 * set state of V24 control (output) signals
4582 */
4583static void set_signals(struct slgt_info *info)
4584{
4585 unsigned char val = rd_reg8(info, VCR);
4586 if (info->signals & SerialSignal_DTR)
4587 val |= BIT3;
4588 else
4589 val &= ~BIT3;
4590 if (info->signals & SerialSignal_RTS)
4591 val |= BIT2;
4592 else
4593 val &= ~BIT2;
4594 wr_reg8(info, VCR, val);
4595}
4596
4597/*
4598 * free range of receive DMA buffers (i to last)
4599 */
4600static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4601{
4602 int done = 0;
4603
4604 while(!done) {
4605 /* reset current buffer for reuse */
4606 info->rbufs[i].status = 0;
4607 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4608 if (i == last)
4609 done = 1;
4610 if (++i == info->rbuf_count)
4611 i = 0;
4612 }
4613 info->rbuf_current = i;
4614}
4615
4616/*
4617 * mark all receive DMA buffers as free
4618 */
4619static void reset_rbufs(struct slgt_info *info)
4620{
4621 free_rbufs(info, 0, info->rbuf_count - 1);
4622 info->rbuf_fill_index = 0;
4623 info->rbuf_fill_count = 0;
4624}
4625
4626/*
4627 * pass receive HDLC frame to upper layer
4628 *
4629 * return true if frame available, otherwise false
4630 */
4631static bool rx_get_frame(struct slgt_info *info)
4632{
4633 unsigned int start, end;
4634 unsigned short status;
4635 unsigned int framesize = 0;
4636 unsigned long flags;
4637 struct tty_struct *tty = info->port.tty;
4638 unsigned char addr_field = 0xff;
4639 unsigned int crc_size = 0;
4640
4641 switch (info->params.crc_type & HDLC_CRC_MASK) {
4642 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4643 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4644 }
4645
4646check_again:
4647
4648 framesize = 0;
4649 addr_field = 0xff;
4650 start = end = info->rbuf_current;
4651
4652 for (;;) {
4653 if (!desc_complete(info->rbufs[end]))
4654 goto cleanup;
4655
4656 if (framesize == 0 && info->params.addr_filter != 0xff)
4657 addr_field = info->rbufs[end].buf[0];
4658
4659 framesize += desc_count(info->rbufs[end]);
4660
4661 if (desc_eof(info->rbufs[end]))
4662 break;
4663
4664 if (++end == info->rbuf_count)
4665 end = 0;
4666
4667 if (end == info->rbuf_current) {
4668 if (info->rx_enabled){
4669 spin_lock_irqsave(&info->lock,flags);
4670 rx_start(info);
4671 spin_unlock_irqrestore(&info->lock,flags);
4672 }
4673 goto cleanup;
4674 }
4675 }
4676
4677 /* status
4678 *
4679 * 15 buffer complete
4680 * 14..06 reserved
4681 * 05..04 residue
4682 * 02 eof (end of frame)
4683 * 01 CRC error
4684 * 00 abort
4685 */
4686 status = desc_status(info->rbufs[end]);
4687
4688 /* ignore CRC bit if not using CRC (bit is undefined) */
4689 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4690 status &= ~BIT1;
4691
4692 if (framesize == 0 ||
4693 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4694 free_rbufs(info, start, end);
4695 goto check_again;
4696 }
4697
4698 if (framesize < (2 + crc_size) || status & BIT0) {
4699 info->icount.rxshort++;
4700 framesize = 0;
4701 } else if (status & BIT1) {
4702 info->icount.rxcrc++;
4703 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4704 framesize = 0;
4705 }
4706
4707#if SYNCLINK_GENERIC_HDLC
4708 if (framesize == 0) {
4709 info->netdev->stats.rx_errors++;
4710 info->netdev->stats.rx_frame_errors++;
4711 }
4712#endif
4713
4714 DBGBH(("%s rx frame status=%04X size=%d\n",
4715 info->device_name, status, framesize));
4716 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4717
4718 if (framesize) {
4719 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4720 framesize -= crc_size;
4721 crc_size = 0;
4722 }
4723
4724 if (framesize > info->max_frame_size + crc_size)
4725 info->icount.rxlong++;
4726 else {
4727 /* copy dma buffer(s) to contiguous temp buffer */
4728 int copy_count = framesize;
4729 int i = start;
4730 unsigned char *p = info->tmp_rbuf;
4731 info->tmp_rbuf_count = framesize;
4732
4733 info->icount.rxok++;
4734
4735 while(copy_count) {
4736 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4737 memcpy(p, info->rbufs[i].buf, partial_count);
4738 p += partial_count;
4739 copy_count -= partial_count;
4740 if (++i == info->rbuf_count)
4741 i = 0;
4742 }
4743
4744 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4745 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4746 framesize++;
4747 }
4748
4749#if SYNCLINK_GENERIC_HDLC
4750 if (info->netcount)
4751 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4752 else
4753#endif
4754 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4755 }
4756 }
4757 free_rbufs(info, start, end);
4758 return true;
4759
4760cleanup:
4761 return false;
4762}
4763
4764/*
4765 * pass receive buffer (RAW synchronous mode) to tty layer
4766 * return true if buffer available, otherwise false
4767 */
4768static bool rx_get_buf(struct slgt_info *info)
4769{
4770 unsigned int i = info->rbuf_current;
4771 unsigned int count;
4772
4773 if (!desc_complete(info->rbufs[i]))
4774 return false;
4775 count = desc_count(info->rbufs[i]);
4776 switch(info->params.mode) {
4777 case MGSL_MODE_MONOSYNC:
4778 case MGSL_MODE_BISYNC:
4779 case MGSL_MODE_XSYNC:
4780 /* ignore residue in byte synchronous modes */
4781 if (desc_residue(info->rbufs[i]))
4782 count--;
4783 break;
4784 }
4785 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4786 DBGINFO(("rx_get_buf size=%d\n", count));
4787 if (count)
4788 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4789 info->flag_buf, count);
4790 free_rbufs(info, i, i);
4791 return true;
4792}
4793
4794static void reset_tbufs(struct slgt_info *info)
4795{
4796 unsigned int i;
4797 info->tbuf_current = 0;
4798 for (i=0 ; i < info->tbuf_count ; i++) {
4799 info->tbufs[i].status = 0;
4800 info->tbufs[i].count = 0;
4801 }
4802}
4803
4804/*
4805 * return number of free transmit DMA buffers
4806 */
4807static unsigned int free_tbuf_count(struct slgt_info *info)
4808{
4809 unsigned int count = 0;
4810 unsigned int i = info->tbuf_current;
4811
4812 do
4813 {
4814 if (desc_count(info->tbufs[i]))
4815 break; /* buffer in use */
4816 ++count;
4817 if (++i == info->tbuf_count)
4818 i=0;
4819 } while (i != info->tbuf_current);
4820
4821 /* if tx DMA active, last zero count buffer is in use */
4822 if (count && (rd_reg32(info, TDCSR) & BIT0))
4823 --count;
4824
4825 return count;
4826}
4827
4828/*
4829 * return number of bytes in unsent transmit DMA buffers
4830 * and the serial controller tx FIFO
4831 */
4832static unsigned int tbuf_bytes(struct slgt_info *info)
4833{
4834 unsigned int total_count = 0;
4835 unsigned int i = info->tbuf_current;
4836 unsigned int reg_value;
4837 unsigned int count;
4838 unsigned int active_buf_count = 0;
4839
4840 /*
4841 * Add descriptor counts for all tx DMA buffers.
4842 * If count is zero (cleared by DMA controller after read),
4843 * the buffer is complete or is actively being read from.
4844 *
4845 * Record buf_count of last buffer with zero count starting
4846 * from current ring position. buf_count is mirror
4847 * copy of count and is not cleared by serial controller.
4848 * If DMA controller is active, that buffer is actively
4849 * being read so add to total.
4850 */
4851 do {
4852 count = desc_count(info->tbufs[i]);
4853 if (count)
4854 total_count += count;
4855 else if (!total_count)
4856 active_buf_count = info->tbufs[i].buf_count;
4857 if (++i == info->tbuf_count)
4858 i = 0;
4859 } while (i != info->tbuf_current);
4860
4861 /* read tx DMA status register */
4862 reg_value = rd_reg32(info, TDCSR);
4863
4864 /* if tx DMA active, last zero count buffer is in use */
4865 if (reg_value & BIT0)
4866 total_count += active_buf_count;
4867
4868 /* add tx FIFO count = reg_value[15..8] */
4869 total_count += (reg_value >> 8) & 0xff;
4870
4871 /* if transmitter active add one byte for shift register */
4872 if (info->tx_active)
4873 total_count++;
4874
4875 return total_count;
4876}
4877
4878/*
4879 * load data into transmit DMA buffer ring and start transmitter if needed
4880 * return true if data accepted, otherwise false (buffers full)
4881 */
4882static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4883{
4884 unsigned short count;
4885 unsigned int i;
4886 struct slgt_desc *d;
4887
4888 /* check required buffer space */
4889 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4890 return false;
4891
4892 DBGDATA(info, buf, size, "tx");
4893
4894 /*
4895 * copy data to one or more DMA buffers in circular ring
4896 * tbuf_start = first buffer for this data
4897 * tbuf_current = next free buffer
4898 *
4899 * Copy all data before making data visible to DMA controller by
4900 * setting descriptor count of the first buffer.
4901 * This prevents an active DMA controller from reading the first DMA
4902 * buffers of a frame and stopping before the final buffers are filled.
4903 */
4904
4905 info->tbuf_start = i = info->tbuf_current;
4906
4907 while (size) {
4908 d = &info->tbufs[i];
4909
4910 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4911 memcpy(d->buf, buf, count);
4912
4913 size -= count;
4914 buf += count;
4915
4916 /*
4917 * set EOF bit for last buffer of HDLC frame or
4918 * for every buffer in raw mode
4919 */
4920 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4921 info->params.mode == MGSL_MODE_RAW)
4922 set_desc_eof(*d, 1);
4923 else
4924 set_desc_eof(*d, 0);
4925
4926 /* set descriptor count for all but first buffer */
4927 if (i != info->tbuf_start)
4928 set_desc_count(*d, count);
4929 d->buf_count = count;
4930
4931 if (++i == info->tbuf_count)
4932 i = 0;
4933 }
4934
4935 info->tbuf_current = i;
4936
4937 /* set first buffer count to make new data visible to DMA controller */
4938 d = &info->tbufs[info->tbuf_start];
4939 set_desc_count(*d, d->buf_count);
4940
4941 /* start transmitter if needed and update transmit timeout */
4942 if (!info->tx_active)
4943 tx_start(info);
4944 update_tx_timer(info);
4945
4946 return true;
4947}
4948
4949static int register_test(struct slgt_info *info)
4950{
4951 static unsigned short patterns[] =
4952 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4953 static unsigned int count = ARRAY_SIZE(patterns);
4954 unsigned int i;
4955 int rc = 0;
4956
4957 for (i=0 ; i < count ; i++) {
4958 wr_reg16(info, TIR, patterns[i]);
4959 wr_reg16(info, BDR, patterns[(i+1)%count]);
4960 if ((rd_reg16(info, TIR) != patterns[i]) ||
4961 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4962 rc = -ENODEV;
4963 break;
4964 }
4965 }
4966 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4967 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4968 return rc;
4969}
4970
4971static int irq_test(struct slgt_info *info)
4972{
4973 unsigned long timeout;
4974 unsigned long flags;
4975 struct tty_struct *oldtty = info->port.tty;
4976 u32 speed = info->params.data_rate;
4977
4978 info->params.data_rate = 921600;
4979 info->port.tty = NULL;
4980
4981 spin_lock_irqsave(&info->lock, flags);
4982 async_mode(info);
4983 slgt_irq_on(info, IRQ_TXIDLE);
4984
4985 /* enable transmitter */
4986 wr_reg16(info, TCR,
4987 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4988
4989 /* write one byte and wait for tx idle */
4990 wr_reg16(info, TDR, 0);
4991
4992 /* assume failure */
4993 info->init_error = DiagStatus_IrqFailure;
4994 info->irq_occurred = false;
4995
4996 spin_unlock_irqrestore(&info->lock, flags);
4997
4998 timeout=100;
4999 while(timeout-- && !info->irq_occurred)
5000 msleep_interruptible(10);
5001
5002 spin_lock_irqsave(&info->lock,flags);
5003 reset_port(info);
5004 spin_unlock_irqrestore(&info->lock,flags);
5005
5006 info->params.data_rate = speed;
5007 info->port.tty = oldtty;
5008
5009 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5010 return info->irq_occurred ? 0 : -ENODEV;
5011}
5012
5013static int loopback_test_rx(struct slgt_info *info)
5014{
5015 unsigned char *src, *dest;
5016 int count;
5017
5018 if (desc_complete(info->rbufs[0])) {
5019 count = desc_count(info->rbufs[0]);
5020 src = info->rbufs[0].buf;
5021 dest = info->tmp_rbuf;
5022
5023 for( ; count ; count-=2, src+=2) {
5024 /* src=data byte (src+1)=status byte */
5025 if (!(*(src+1) & (BIT9 + BIT8))) {
5026 *dest = *src;
5027 dest++;
5028 info->tmp_rbuf_count++;
5029 }
5030 }
5031 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5032 return 1;
5033 }
5034 return 0;
5035}
5036
5037static int loopback_test(struct slgt_info *info)
5038{
5039#define TESTFRAMESIZE 20
5040
5041 unsigned long timeout;
5042 u16 count = TESTFRAMESIZE;
5043 unsigned char buf[TESTFRAMESIZE];
5044 int rc = -ENODEV;
5045 unsigned long flags;
5046
5047 struct tty_struct *oldtty = info->port.tty;
5048 MGSL_PARAMS params;
5049
5050 memcpy(¶ms, &info->params, sizeof(params));
5051
5052 info->params.mode = MGSL_MODE_ASYNC;
5053 info->params.data_rate = 921600;
5054 info->params.loopback = 1;
5055 info->port.tty = NULL;
5056
5057 /* build and send transmit frame */
5058 for (count = 0; count < TESTFRAMESIZE; ++count)
5059 buf[count] = (unsigned char)count;
5060
5061 info->tmp_rbuf_count = 0;
5062 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5063
5064 /* program hardware for HDLC and enabled receiver */
5065 spin_lock_irqsave(&info->lock,flags);
5066 async_mode(info);
5067 rx_start(info);
5068 tx_load(info, buf, count);
5069 spin_unlock_irqrestore(&info->lock, flags);
5070
5071 /* wait for receive complete */
5072 for (timeout = 100; timeout; --timeout) {
5073 msleep_interruptible(10);
5074 if (loopback_test_rx(info)) {
5075 rc = 0;
5076 break;
5077 }
5078 }
5079
5080 /* verify received frame length and contents */
5081 if (!rc && (info->tmp_rbuf_count != count ||
5082 memcmp(buf, info->tmp_rbuf, count))) {
5083 rc = -ENODEV;
5084 }
5085
5086 spin_lock_irqsave(&info->lock,flags);
5087 reset_adapter(info);
5088 spin_unlock_irqrestore(&info->lock,flags);
5089
5090 memcpy(&info->params, ¶ms, sizeof(info->params));
5091 info->port.tty = oldtty;
5092
5093 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5094 return rc;
5095}
5096
5097static int adapter_test(struct slgt_info *info)
5098{
5099 DBGINFO(("testing %s\n", info->device_name));
5100 if (register_test(info) < 0) {
5101 printk("register test failure %s addr=%08X\n",
5102 info->device_name, info->phys_reg_addr);
5103 } else if (irq_test(info) < 0) {
5104 printk("IRQ test failure %s IRQ=%d\n",
5105 info->device_name, info->irq_level);
5106 } else if (loopback_test(info) < 0) {
5107 printk("loopback test failure %s\n", info->device_name);
5108 }
5109 return info->init_error;
5110}
5111
5112/*
5113 * transmit timeout handler
5114 */
5115static void tx_timeout(struct timer_list *t)
5116{
5117 struct slgt_info *info = from_timer(info, t, tx_timer);
5118 unsigned long flags;
5119
5120 DBGINFO(("%s tx_timeout\n", info->device_name));
5121 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5122 info->icount.txtimeout++;
5123 }
5124 spin_lock_irqsave(&info->lock,flags);
5125 tx_stop(info);
5126 spin_unlock_irqrestore(&info->lock,flags);
5127
5128#if SYNCLINK_GENERIC_HDLC
5129 if (info->netcount)
5130 hdlcdev_tx_done(info);
5131 else
5132#endif
5133 bh_transmit(info);
5134}
5135
5136/*
5137 * receive buffer polling timer
5138 */
5139static void rx_timeout(struct timer_list *t)
5140{
5141 struct slgt_info *info = from_timer(info, t, rx_timer);
5142 unsigned long flags;
5143
5144 DBGINFO(("%s rx_timeout\n", info->device_name));
5145 spin_lock_irqsave(&info->lock, flags);
5146 info->pending_bh |= BH_RECEIVE;
5147 spin_unlock_irqrestore(&info->lock, flags);
5148 bh_handler(&info->task);
5149}
5150