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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#include <linux/atomic.h>
8#include <linux/bitops.h>
9#include <linux/bug.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/dmaengine.h>
14#include <linux/err.h>
15#include <linux/gpio/consumer.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/math64.h>
20#include <linux/minmax.h>
21#include <linux/module.h>
22#include <linux/pm_runtime.h>
23#include <linux/property.h>
24#include <linux/slab.h>
25#include <linux/types.h>
26
27#include <linux/spi/spi.h>
28
29#include "internals.h"
30#include "spi-pxa2xx.h"
31
32#define TIMOUT_DFLT 1000
33
34/*
35 * For testing SSCR1 changes that require SSP restart, basically
36 * everything except the service and interrupt enables, the PXA270 developer
37 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
38 * list, but the PXA255 developer manual says all bits without really meaning
39 * the service and interrupt enables.
40 */
41#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
42 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
43 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
44 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
45 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
46 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
47
48#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
49 | QUARK_X1000_SSCR1_EFWR \
50 | QUARK_X1000_SSCR1_RFT \
51 | QUARK_X1000_SSCR1_TFT \
52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
53
54#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
56 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
57 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
58 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
60
61struct chip_data {
62 u32 cr1;
63 u32 dds_rate;
64 u32 threshold;
65 u16 lpss_rx_threshold;
66 u16 lpss_tx_threshold;
67};
68
69#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
70#define LPSS_CS_CONTROL_SW_MODE BIT(0)
71#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
72#define LPSS_CAPS_CS_EN_SHIFT 9
73#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
74
75#define LPSS_PRIV_CLOCK_GATE 0x38
76#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
77#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
78
79struct lpss_config {
80 /* LPSS offset from drv_data->ioaddr */
81 unsigned offset;
82 /* Register offsets from drv_data->lpss_base or -1 */
83 int reg_general;
84 int reg_ssp;
85 int reg_cs_ctrl;
86 int reg_capabilities;
87 /* FIFO thresholds */
88 u32 rx_threshold;
89 u32 tx_threshold_lo;
90 u32 tx_threshold_hi;
91 /* Chip select control */
92 unsigned cs_sel_shift;
93 unsigned cs_sel_mask;
94 /* Quirks */
95 unsigned cs_clk_stays_gated : 1;
96};
97
98/* Keep these sorted with enum pxa_ssp_type */
99static const struct lpss_config lpss_platforms[] = {
100 { /* LPSS_LPT_SSP */
101 .offset = 0x800,
102 .reg_general = 0x08,
103 .reg_ssp = 0x0c,
104 .reg_cs_ctrl = 0x18,
105 .reg_capabilities = -1,
106 .rx_threshold = 64,
107 .tx_threshold_lo = 160,
108 .tx_threshold_hi = 224,
109 },
110 { /* LPSS_BYT_SSP */
111 .offset = 0x400,
112 .reg_general = 0x08,
113 .reg_ssp = 0x0c,
114 .reg_cs_ctrl = 0x18,
115 .reg_capabilities = -1,
116 .rx_threshold = 64,
117 .tx_threshold_lo = 160,
118 .tx_threshold_hi = 224,
119 },
120 { /* LPSS_BSW_SSP */
121 .offset = 0x400,
122 .reg_general = 0x08,
123 .reg_ssp = 0x0c,
124 .reg_cs_ctrl = 0x18,
125 .reg_capabilities = -1,
126 .rx_threshold = 64,
127 .tx_threshold_lo = 160,
128 .tx_threshold_hi = 224,
129 .cs_sel_shift = 2,
130 .cs_sel_mask = 1 << 2,
131 },
132 { /* LPSS_SPT_SSP */
133 .offset = 0x200,
134 .reg_general = -1,
135 .reg_ssp = 0x20,
136 .reg_cs_ctrl = 0x24,
137 .reg_capabilities = -1,
138 .rx_threshold = 1,
139 .tx_threshold_lo = 32,
140 .tx_threshold_hi = 56,
141 },
142 { /* LPSS_BXT_SSP */
143 .offset = 0x200,
144 .reg_general = -1,
145 .reg_ssp = 0x20,
146 .reg_cs_ctrl = 0x24,
147 .reg_capabilities = 0xfc,
148 .rx_threshold = 1,
149 .tx_threshold_lo = 16,
150 .tx_threshold_hi = 48,
151 .cs_sel_shift = 8,
152 .cs_sel_mask = 3 << 8,
153 .cs_clk_stays_gated = true,
154 },
155 { /* LPSS_CNL_SSP */
156 .offset = 0x200,
157 .reg_general = -1,
158 .reg_ssp = 0x20,
159 .reg_cs_ctrl = 0x24,
160 .reg_capabilities = 0xfc,
161 .rx_threshold = 1,
162 .tx_threshold_lo = 32,
163 .tx_threshold_hi = 56,
164 .cs_sel_shift = 8,
165 .cs_sel_mask = 3 << 8,
166 .cs_clk_stays_gated = true,
167 },
168};
169
170static inline const struct lpss_config
171*lpss_get_config(const struct driver_data *drv_data)
172{
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
174}
175
176static bool is_lpss_ssp(const struct driver_data *drv_data)
177{
178 switch (drv_data->ssp_type) {
179 case LPSS_LPT_SSP:
180 case LPSS_BYT_SSP:
181 case LPSS_BSW_SSP:
182 case LPSS_SPT_SSP:
183 case LPSS_BXT_SSP:
184 case LPSS_CNL_SSP:
185 return true;
186 default:
187 return false;
188 }
189}
190
191static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
192{
193 return drv_data->ssp_type == QUARK_X1000_SSP;
194}
195
196static bool is_mmp2_ssp(const struct driver_data *drv_data)
197{
198 return drv_data->ssp_type == MMP2_SSP;
199}
200
201static bool is_mrfld_ssp(const struct driver_data *drv_data)
202{
203 return drv_data->ssp_type == MRFLD_SSP;
204}
205
206static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
207{
208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
209 pxa2xx_spi_write(drv_data, reg, value & mask);
210}
211
212static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
213{
214 switch (drv_data->ssp_type) {
215 case QUARK_X1000_SSP:
216 return QUARK_X1000_SSCR1_CHANGE_MASK;
217 case CE4100_SSP:
218 return CE4100_SSCR1_CHANGE_MASK;
219 default:
220 return SSCR1_CHANGE_MASK;
221 }
222}
223
224static u32
225pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
226{
227 switch (drv_data->ssp_type) {
228 case QUARK_X1000_SSP:
229 return RX_THRESH_QUARK_X1000_DFLT;
230 case CE4100_SSP:
231 return RX_THRESH_CE4100_DFLT;
232 default:
233 return RX_THRESH_DFLT;
234 }
235}
236
237static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
238{
239 u32 mask;
240
241 switch (drv_data->ssp_type) {
242 case QUARK_X1000_SSP:
243 mask = QUARK_X1000_SSSR_TFL_MASK;
244 break;
245 case CE4100_SSP:
246 mask = CE4100_SSSR_TFL_MASK;
247 break;
248 default:
249 mask = SSSR_TFL_MASK;
250 break;
251 }
252
253 return read_SSSR_bits(drv_data, mask) == mask;
254}
255
256static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
257 u32 *sccr1_reg)
258{
259 u32 mask;
260
261 switch (drv_data->ssp_type) {
262 case QUARK_X1000_SSP:
263 mask = QUARK_X1000_SSCR1_RFT;
264 break;
265 case CE4100_SSP:
266 mask = CE4100_SSCR1_RFT;
267 break;
268 default:
269 mask = SSCR1_RFT;
270 break;
271 }
272 *sccr1_reg &= ~mask;
273}
274
275static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
276 u32 *sccr1_reg, u32 threshold)
277{
278 switch (drv_data->ssp_type) {
279 case QUARK_X1000_SSP:
280 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
281 break;
282 case CE4100_SSP:
283 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
284 break;
285 default:
286 *sccr1_reg |= SSCR1_RxTresh(threshold);
287 break;
288 }
289}
290
291static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
292 u32 clk_div, u8 bits)
293{
294 switch (drv_data->ssp_type) {
295 case QUARK_X1000_SSP:
296 return clk_div
297 | QUARK_X1000_SSCR0_Motorola
298 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
299 default:
300 return clk_div
301 | SSCR0_Motorola
302 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
303 | (bits > 16 ? SSCR0_EDSS : 0);
304 }
305}
306
307/*
308 * Read and write LPSS SSP private registers. Caller must first check that
309 * is_lpss_ssp() returns true before these can be called.
310 */
311static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
312{
313 WARN_ON(!drv_data->lpss_base);
314 return readl(drv_data->lpss_base + offset);
315}
316
317static void __lpss_ssp_write_priv(struct driver_data *drv_data,
318 unsigned offset, u32 value)
319{
320 WARN_ON(!drv_data->lpss_base);
321 writel(value, drv_data->lpss_base + offset);
322}
323
324/*
325 * lpss_ssp_setup - perform LPSS SSP specific setup
326 * @drv_data: pointer to the driver private data
327 *
328 * Perform LPSS SSP specific setup. This function must be called first if
329 * one is going to use LPSS SSP private registers.
330 */
331static void lpss_ssp_setup(struct driver_data *drv_data)
332{
333 const struct lpss_config *config;
334 u32 value;
335
336 config = lpss_get_config(drv_data);
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
338
339 /* Enable software chip select control */
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
341 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
342 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
344
345 /* Enable multiblock DMA transfers */
346 if (drv_data->controller_info->enable_dma) {
347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
348
349 if (config->reg_general >= 0) {
350 value = __lpss_ssp_read_priv(drv_data,
351 config->reg_general);
352 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
353 __lpss_ssp_write_priv(drv_data,
354 config->reg_general, value);
355 }
356 }
357}
358
359static void lpss_ssp_select_cs(struct spi_device *spi,
360 const struct lpss_config *config)
361{
362 struct driver_data *drv_data =
363 spi_controller_get_devdata(spi->controller);
364 u32 value, cs;
365
366 if (!config->cs_sel_mask)
367 return;
368
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
370
371 cs = spi_get_chipselect(spi, 0);
372 cs <<= config->cs_sel_shift;
373 if (cs != (value & config->cs_sel_mask)) {
374 /*
375 * When switching another chip select output active the
376 * output must be selected first and wait 2 ssp_clk cycles
377 * before changing state to active. Otherwise a short
378 * glitch will occur on the previous chip select since
379 * output select is latched but state control is not.
380 */
381 value &= ~config->cs_sel_mask;
382 value |= cs;
383 __lpss_ssp_write_priv(drv_data,
384 config->reg_cs_ctrl, value);
385 ndelay(1000000000 /
386 (drv_data->controller->max_speed_hz / 2));
387 }
388}
389
390static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
391{
392 struct driver_data *drv_data =
393 spi_controller_get_devdata(spi->controller);
394 const struct lpss_config *config;
395 u32 value;
396
397 config = lpss_get_config(drv_data);
398
399 if (enable)
400 lpss_ssp_select_cs(spi, config);
401
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
403 if (enable)
404 value &= ~LPSS_CS_CONTROL_CS_HIGH;
405 else
406 value |= LPSS_CS_CONTROL_CS_HIGH;
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
408 if (config->cs_clk_stays_gated) {
409 u32 clkgate;
410
411 /*
412 * Changing CS alone when dynamic clock gating is on won't
413 * actually flip CS at that time. This ruins SPI transfers
414 * that specify delays, or have no data. Toggle the clock mode
415 * to force on briefly to poke the CS pin to move.
416 */
417 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
418 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
419 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
420
421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
423 }
424}
425
426static void cs_assert(struct spi_device *spi)
427{
428 struct driver_data *drv_data =
429 spi_controller_get_devdata(spi->controller);
430
431 if (drv_data->ssp_type == CE4100_SSP) {
432 pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0));
433 return;
434 }
435
436 if (is_lpss_ssp(drv_data))
437 lpss_ssp_cs_control(spi, true);
438}
439
440static void cs_deassert(struct spi_device *spi)
441{
442 struct driver_data *drv_data =
443 spi_controller_get_devdata(spi->controller);
444 unsigned long timeout;
445
446 if (drv_data->ssp_type == CE4100_SSP)
447 return;
448
449 /* Wait until SSP becomes idle before deasserting the CS */
450 timeout = jiffies + msecs_to_jiffies(10);
451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
452 !time_after(jiffies, timeout))
453 cpu_relax();
454
455 if (is_lpss_ssp(drv_data))
456 lpss_ssp_cs_control(spi, false);
457}
458
459static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
460{
461 if (level)
462 cs_deassert(spi);
463 else
464 cs_assert(spi);
465}
466
467int pxa2xx_spi_flush(struct driver_data *drv_data)
468{
469 unsigned long limit = loops_per_jiffy << 1;
470
471 do {
472 while (read_SSSR_bits(drv_data, SSSR_RNE))
473 pxa2xx_spi_read(drv_data, SSDR);
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
475 write_SSSR_CS(drv_data, SSSR_ROR);
476
477 return limit;
478}
479
480static void pxa2xx_spi_off(struct driver_data *drv_data)
481{
482 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
483 if (is_mmp2_ssp(drv_data))
484 return;
485
486 pxa_ssp_disable(drv_data->ssp);
487}
488
489static int null_writer(struct driver_data *drv_data)
490{
491 u8 n_bytes = drv_data->n_bytes;
492
493 if (pxa2xx_spi_txfifo_full(drv_data)
494 || (drv_data->tx == drv_data->tx_end))
495 return 0;
496
497 pxa2xx_spi_write(drv_data, SSDR, 0);
498 drv_data->tx += n_bytes;
499
500 return 1;
501}
502
503static int null_reader(struct driver_data *drv_data)
504{
505 u8 n_bytes = drv_data->n_bytes;
506
507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
508 pxa2xx_spi_read(drv_data, SSDR);
509 drv_data->rx += n_bytes;
510 }
511
512 return drv_data->rx == drv_data->rx_end;
513}
514
515static int u8_writer(struct driver_data *drv_data)
516{
517 if (pxa2xx_spi_txfifo_full(drv_data)
518 || (drv_data->tx == drv_data->tx_end))
519 return 0;
520
521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
522 ++drv_data->tx;
523
524 return 1;
525}
526
527static int u8_reader(struct driver_data *drv_data)
528{
529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
531 ++drv_data->rx;
532 }
533
534 return drv_data->rx == drv_data->rx_end;
535}
536
537static int u16_writer(struct driver_data *drv_data)
538{
539 if (pxa2xx_spi_txfifo_full(drv_data)
540 || (drv_data->tx == drv_data->tx_end))
541 return 0;
542
543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
544 drv_data->tx += 2;
545
546 return 1;
547}
548
549static int u16_reader(struct driver_data *drv_data)
550{
551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
553 drv_data->rx += 2;
554 }
555
556 return drv_data->rx == drv_data->rx_end;
557}
558
559static int u32_writer(struct driver_data *drv_data)
560{
561 if (pxa2xx_spi_txfifo_full(drv_data)
562 || (drv_data->tx == drv_data->tx_end))
563 return 0;
564
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
566 drv_data->tx += 4;
567
568 return 1;
569}
570
571static int u32_reader(struct driver_data *drv_data)
572{
573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
575 drv_data->rx += 4;
576 }
577
578 return drv_data->rx == drv_data->rx_end;
579}
580
581static void reset_sccr1(struct driver_data *drv_data)
582{
583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
584 struct chip_data *chip;
585
586 if (drv_data->controller->cur_msg) {
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
588 threshold = chip->threshold;
589 } else {
590 threshold = 0;
591 }
592
593 switch (drv_data->ssp_type) {
594 case QUARK_X1000_SSP:
595 mask |= QUARK_X1000_SSCR1_RFT;
596 break;
597 case CE4100_SSP:
598 mask |= CE4100_SSCR1_RFT;
599 break;
600 default:
601 mask |= SSCR1_RFT;
602 break;
603 }
604
605 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
606}
607
608static void int_stop_and_reset(struct driver_data *drv_data)
609{
610 /* Clear and disable interrupts */
611 write_SSSR_CS(drv_data, drv_data->clear_sr);
612 reset_sccr1(drv_data);
613 if (pxa25x_ssp_comp(drv_data))
614 return;
615
616 pxa2xx_spi_write(drv_data, SSTO, 0);
617}
618
619static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
620{
621 int_stop_and_reset(drv_data);
622 pxa2xx_spi_flush(drv_data);
623 pxa2xx_spi_off(drv_data);
624
625 dev_err(drv_data->ssp->dev, "%s\n", msg);
626
627 drv_data->controller->cur_msg->status = err;
628 spi_finalize_current_transfer(drv_data->controller);
629}
630
631static void int_transfer_complete(struct driver_data *drv_data)
632{
633 int_stop_and_reset(drv_data);
634
635 spi_finalize_current_transfer(drv_data->controller);
636}
637
638static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
639{
640 u32 irq_status;
641
642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
643 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
644 irq_status &= ~SSSR_TFS;
645
646 if (irq_status & SSSR_ROR) {
647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
648 return IRQ_HANDLED;
649 }
650
651 if (irq_status & SSSR_TUR) {
652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
653 return IRQ_HANDLED;
654 }
655
656 if (irq_status & SSSR_TINT) {
657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
658 if (drv_data->read(drv_data)) {
659 int_transfer_complete(drv_data);
660 return IRQ_HANDLED;
661 }
662 }
663
664 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
665 do {
666 if (drv_data->read(drv_data)) {
667 int_transfer_complete(drv_data);
668 return IRQ_HANDLED;
669 }
670 } while (drv_data->write(drv_data));
671
672 if (drv_data->read(drv_data)) {
673 int_transfer_complete(drv_data);
674 return IRQ_HANDLED;
675 }
676
677 if (drv_data->tx == drv_data->tx_end) {
678 u32 bytes_left;
679 u32 sccr1_reg;
680
681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
682 sccr1_reg &= ~SSCR1_TIE;
683
684 /*
685 * PXA25x_SSP has no timeout, set up Rx threshold for
686 * the remaining Rx bytes.
687 */
688 if (pxa25x_ssp_comp(drv_data)) {
689 u32 rx_thre;
690
691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
692
693 bytes_left = drv_data->rx_end - drv_data->rx;
694 switch (drv_data->n_bytes) {
695 case 4:
696 bytes_left >>= 2;
697 break;
698 case 2:
699 bytes_left >>= 1;
700 break;
701 }
702
703 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
704 if (rx_thre > bytes_left)
705 rx_thre = bytes_left;
706
707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
708 }
709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
710 }
711
712 /* We did something */
713 return IRQ_HANDLED;
714}
715
716static void handle_bad_msg(struct driver_data *drv_data)
717{
718 int_stop_and_reset(drv_data);
719 pxa2xx_spi_off(drv_data);
720
721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
722}
723
724static irqreturn_t ssp_int(int irq, void *dev_id)
725{
726 struct driver_data *drv_data = dev_id;
727 u32 sccr1_reg;
728 u32 mask = drv_data->mask_sr;
729 u32 status;
730
731 /*
732 * The IRQ might be shared with other peripherals so we must first
733 * check that are we RPM suspended or not. If we are we assume that
734 * the IRQ was not for us (we shouldn't be RPM suspended when the
735 * interrupt is enabled).
736 */
737 if (pm_runtime_suspended(drv_data->ssp->dev))
738 return IRQ_NONE;
739
740 /*
741 * If the device is not yet in RPM suspended state and we get an
742 * interrupt that is meant for another device, check if status bits
743 * are all set to one. That means that the device is already
744 * powered off.
745 */
746 status = pxa2xx_spi_read(drv_data, SSSR);
747 if (status == ~0)
748 return IRQ_NONE;
749
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
751
752 /* Ignore possible writes if we don't need to write */
753 if (!(sccr1_reg & SSCR1_TIE))
754 mask &= ~SSSR_TFS;
755
756 /* Ignore RX timeout interrupt if it is disabled */
757 if (!(sccr1_reg & SSCR1_TINTE))
758 mask &= ~SSSR_TINT;
759
760 if (!(status & mask))
761 return IRQ_NONE;
762
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
765
766 if (!drv_data->controller->cur_msg) {
767 handle_bad_msg(drv_data);
768 /* Never fail */
769 return IRQ_HANDLED;
770 }
771
772 return drv_data->transfer_handler(drv_data);
773}
774
775/*
776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
777 * input frequency by fractions of 2^24. It also has a divider by 5.
778 *
779 * There are formulas to get baud rate value for given input frequency and
780 * divider parameters, such as DDS_CLK_RATE and SCR:
781 *
782 * Fsys = 200MHz
783 *
784 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
786 *
787 * DDS_CLK_RATE either 2^n or 2^n / 5.
788 * SCR is in range 0 .. 255
789 *
790 * Divisor = 5^i * 2^j * 2 * k
791 * i = [0, 1] i = 1 iff j = 0 or j > 3
792 * j = [0, 23] j = 0 iff i = 1
793 * k = [1, 256]
794 * Special case: j = 0, i = 1: Divisor = 2 / 5
795 *
796 * Accordingly to the specification the recommended values for DDS_CLK_RATE
797 * are:
798 * Case 1: 2^n, n = [0, 23]
799 * Case 2: 2^24 * 2 / 5 (0x666666)
800 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
801 *
802 * In all cases the lowest possible value is better.
803 *
804 * The function calculates parameters for all cases and chooses the one closest
805 * to the asked baud rate.
806 */
807static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
808{
809 unsigned long xtal = 200000000;
810 unsigned long fref = xtal / 2; /* mandatory division by 2,
811 see (2) */
812 /* case 3 */
813 unsigned long fref1 = fref / 2; /* case 1 */
814 unsigned long fref2 = fref * 2 / 5; /* case 2 */
815 unsigned long scale;
816 unsigned long q, q1, q2;
817 long r, r1, r2;
818 u32 mul;
819
820 /* Case 1 */
821
822 /* Set initial value for DDS_CLK_RATE */
823 mul = (1 << 24) >> 1;
824
825 /* Calculate initial quot */
826 q1 = DIV_ROUND_UP(fref1, rate);
827
828 /* Scale q1 if it's too big */
829 if (q1 > 256) {
830 /* Scale q1 to range [1, 512] */
831 scale = fls_long(q1 - 1);
832 if (scale > 9) {
833 q1 >>= scale - 9;
834 mul >>= scale - 9;
835 }
836
837 /* Round the result if we have a remainder */
838 q1 += q1 & 1;
839 }
840
841 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
842 scale = __ffs(q1);
843 q1 >>= scale;
844 mul >>= scale;
845
846 /* Get the remainder */
847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
848
849 /* Case 2 */
850
851 q2 = DIV_ROUND_UP(fref2, rate);
852 r2 = abs(fref2 / q2 - rate);
853
854 /*
855 * Choose the best between two: less remainder we have the better. We
856 * can't go case 2 if q2 is greater than 256 since SCR register can
857 * hold only values 0 .. 255.
858 */
859 if (r2 >= r1 || q2 > 256) {
860 /* case 1 is better */
861 r = r1;
862 q = q1;
863 } else {
864 /* case 2 is better */
865 r = r2;
866 q = q2;
867 mul = (1 << 24) * 2 / 5;
868 }
869
870 /* Check case 3 only if the divisor is big enough */
871 if (fref / rate >= 80) {
872 u64 fssp;
873 u32 m;
874
875 /* Calculate initial quot */
876 q1 = DIV_ROUND_UP(fref, rate);
877 m = (1 << 24) / q1;
878
879 /* Get the remainder */
880 fssp = (u64)fref * m;
881 do_div(fssp, 1 << 24);
882 r1 = abs(fssp - rate);
883
884 /* Choose this one if it suits better */
885 if (r1 < r) {
886 /* case 3 is better */
887 q = 1;
888 mul = m;
889 }
890 }
891
892 *dds = mul;
893 return q - 1;
894}
895
896static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
897{
898 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
899 const struct ssp_device *ssp = drv_data->ssp;
900
901 rate = min_t(int, ssp_clk, rate);
902
903 /*
904 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
905 * that the SSP transmission rate can be greater than the device rate.
906 */
907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
909 else
910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
911}
912
913static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
914 int rate)
915{
916 struct chip_data *chip =
917 spi_get_ctldata(drv_data->controller->cur_msg->spi);
918 unsigned int clk_div;
919
920 switch (drv_data->ssp_type) {
921 case QUARK_X1000_SSP:
922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
923 break;
924 default:
925 clk_div = ssp_get_clk_div(drv_data, rate);
926 break;
927 }
928 return clk_div << 8;
929}
930
931static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
932 struct spi_device *spi,
933 struct spi_transfer *xfer)
934{
935 struct driver_data *drv_data = spi_controller_get_devdata(controller);
936
937 return drv_data->controller_info->enable_dma &&
938 xfer->len <= MAX_DMA_LEN &&
939 xfer->len >= drv_data->controller_info->dma_burst_size;
940}
941
942static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
943 struct spi_device *spi,
944 struct spi_transfer *transfer)
945{
946 struct driver_data *drv_data = spi_controller_get_devdata(controller);
947 struct chip_data *chip = spi_get_ctldata(spi);
948 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
949 u32 dma_thresh;
950 u32 clk_div;
951 u8 bits;
952 u32 speed;
953 u32 cr0;
954 u32 cr1;
955 int err;
956 int dma_mapped;
957
958 /* Check if we can DMA this transfer */
959 if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) {
960 /* Warn ... we force this to PIO mode */
961 dev_warn_ratelimited(&spi->dev,
962 "DMA disabled for transfer length %u greater than %d\n",
963 transfer->len, MAX_DMA_LEN);
964 }
965
966 /* Setup the transfer state based on the type of transfer */
967 if (pxa2xx_spi_flush(drv_data) == 0) {
968 dev_err(&spi->dev, "Flush failed\n");
969 return -EIO;
970 }
971 drv_data->tx = (void *)transfer->tx_buf;
972 drv_data->tx_end = drv_data->tx + transfer->len;
973 drv_data->rx = transfer->rx_buf;
974 drv_data->rx_end = drv_data->rx + transfer->len;
975
976 /* Change speed and bit per word on a per transfer */
977 bits = transfer->bits_per_word;
978 speed = transfer->speed_hz;
979
980 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
981
982 if (bits <= 8) {
983 drv_data->n_bytes = 1;
984 drv_data->read = drv_data->rx ? u8_reader : null_reader;
985 drv_data->write = drv_data->tx ? u8_writer : null_writer;
986 } else if (bits <= 16) {
987 drv_data->n_bytes = 2;
988 drv_data->read = drv_data->rx ? u16_reader : null_reader;
989 drv_data->write = drv_data->tx ? u16_writer : null_writer;
990 } else if (bits <= 32) {
991 drv_data->n_bytes = 4;
992 drv_data->read = drv_data->rx ? u32_reader : null_reader;
993 drv_data->write = drv_data->tx ? u32_writer : null_writer;
994 }
995
996 dma_thresh = SSCR1_RxTresh(RX_THRESH_DFLT) | SSCR1_TxTresh(TX_THRESH_DFLT);
997 dma_mapped = spi_xfer_is_dma_mapped(controller, spi, transfer);
998 if (dma_mapped) {
999 /* Ensure we have the correct interrupt handler */
1000 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1001
1002 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1003 if (err)
1004 return err;
1005
1006 /* Clear status and start DMA engine */
1007 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1008 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1009
1010 pxa2xx_spi_dma_start(drv_data);
1011 } else {
1012 /* Ensure we have the correct interrupt handler */
1013 drv_data->transfer_handler = interrupt_transfer;
1014
1015 /* Clear status */
1016 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1017 write_SSSR_CS(drv_data, drv_data->clear_sr);
1018 }
1019
1020 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1021 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1022 if (!pxa25x_ssp_comp(drv_data))
1023 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1024 controller->max_speed_hz
1025 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1026 dma_mapped ? "DMA" : "PIO");
1027 else
1028 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1029 controller->max_speed_hz / 2
1030 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1031 dma_mapped ? "DMA" : "PIO");
1032
1033 if (is_lpss_ssp(drv_data)) {
1034 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1035 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1036 }
1037
1038 if (is_mrfld_ssp(drv_data)) {
1039 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1040 u32 thresh = 0;
1041
1042 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1043 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1044
1045 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1046 }
1047
1048 if (is_quark_x1000_ssp(drv_data))
1049 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1050
1051 /* Stop the SSP */
1052 if (!is_mmp2_ssp(drv_data))
1053 pxa_ssp_disable(drv_data->ssp);
1054
1055 if (!pxa25x_ssp_comp(drv_data))
1056 pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT);
1057
1058 /* First set CR1 without interrupt and service enables */
1059 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1060
1061 /* See if we need to reload the configuration registers */
1062 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1063
1064 /* Restart the SSP */
1065 pxa_ssp_enable(drv_data->ssp);
1066
1067 if (is_mmp2_ssp(drv_data)) {
1068 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1069
1070 if (tx_level) {
1071 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1072 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1073 if (tx_level > transfer->len)
1074 tx_level = transfer->len;
1075 drv_data->tx += tx_level;
1076 }
1077 }
1078
1079 if (spi_controller_is_target(controller)) {
1080 while (drv_data->write(drv_data))
1081 ;
1082 if (drv_data->gpiod_ready) {
1083 gpiod_set_value(drv_data->gpiod_ready, 1);
1084 udelay(1);
1085 gpiod_set_value(drv_data->gpiod_ready, 0);
1086 }
1087 }
1088
1089 /*
1090 * Release the data by enabling service requests and interrupts,
1091 * without changing any mode bits.
1092 */
1093 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1094
1095 return 1;
1096}
1097
1098static int pxa2xx_spi_target_abort(struct spi_controller *controller)
1099{
1100 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1101
1102 int_error_stop(drv_data, "transfer aborted", -EINTR);
1103
1104 return 0;
1105}
1106
1107static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1108 struct spi_message *msg)
1109{
1110 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1111
1112 int_stop_and_reset(drv_data);
1113
1114 /* Disable the SSP */
1115 pxa2xx_spi_off(drv_data);
1116
1117 /*
1118 * Stop the DMA if running. Note DMA callback handler may have unset
1119 * the dma_running already, which is fine as stopping is not needed
1120 * then but we shouldn't rely this flag for anything else than
1121 * stopping. For instance to differentiate between PIO and DMA
1122 * transfers.
1123 */
1124 if (atomic_read(&drv_data->dma_running))
1125 pxa2xx_spi_dma_stop(drv_data);
1126}
1127
1128static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1129{
1130 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1131
1132 /* Disable the SSP now */
1133 pxa2xx_spi_off(drv_data);
1134
1135 return 0;
1136}
1137
1138static int setup(struct spi_device *spi)
1139{
1140 struct chip_data *chip;
1141 const struct lpss_config *config;
1142 struct driver_data *drv_data =
1143 spi_controller_get_devdata(spi->controller);
1144 uint tx_thres, tx_hi_thres, rx_thres;
1145
1146 switch (drv_data->ssp_type) {
1147 case QUARK_X1000_SSP:
1148 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1149 tx_hi_thres = 0;
1150 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1151 break;
1152 case MRFLD_SSP:
1153 tx_thres = TX_THRESH_MRFLD_DFLT;
1154 tx_hi_thres = 0;
1155 rx_thres = RX_THRESH_MRFLD_DFLT;
1156 break;
1157 case CE4100_SSP:
1158 tx_thres = TX_THRESH_CE4100_DFLT;
1159 tx_hi_thres = 0;
1160 rx_thres = RX_THRESH_CE4100_DFLT;
1161 break;
1162 case LPSS_LPT_SSP:
1163 case LPSS_BYT_SSP:
1164 case LPSS_BSW_SSP:
1165 case LPSS_SPT_SSP:
1166 case LPSS_BXT_SSP:
1167 case LPSS_CNL_SSP:
1168 config = lpss_get_config(drv_data);
1169 tx_thres = config->tx_threshold_lo;
1170 tx_hi_thres = config->tx_threshold_hi;
1171 rx_thres = config->rx_threshold;
1172 break;
1173 default:
1174 tx_hi_thres = 0;
1175 if (spi_controller_is_target(drv_data->controller)) {
1176 tx_thres = 1;
1177 rx_thres = 2;
1178 } else {
1179 tx_thres = TX_THRESH_DFLT;
1180 rx_thres = RX_THRESH_DFLT;
1181 }
1182 break;
1183 }
1184
1185 if (drv_data->ssp_type == CE4100_SSP) {
1186 if (spi_get_chipselect(spi, 0) > 4) {
1187 dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n");
1188 return -EINVAL;
1189 }
1190 }
1191
1192 /* Only allocate on the first setup */
1193 chip = spi_get_ctldata(spi);
1194 if (!chip) {
1195 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1196 if (!chip)
1197 return -ENOMEM;
1198 }
1199
1200 chip->cr1 = 0;
1201 if (spi_controller_is_target(drv_data->controller)) {
1202 chip->cr1 |= SSCR1_SCFR;
1203 chip->cr1 |= SSCR1_SCLKDIR;
1204 chip->cr1 |= SSCR1_SFRMDIR;
1205 chip->cr1 |= SSCR1_SPH;
1206 }
1207
1208 if (is_lpss_ssp(drv_data)) {
1209 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1210 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1211 SSITF_TxHiThresh(tx_hi_thres);
1212 }
1213
1214 if (is_mrfld_ssp(drv_data)) {
1215 chip->lpss_rx_threshold = rx_thres;
1216 chip->lpss_tx_threshold = tx_thres;
1217 }
1218
1219 switch (drv_data->ssp_type) {
1220 case QUARK_X1000_SSP:
1221 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1222 & QUARK_X1000_SSCR1_RFT)
1223 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1224 & QUARK_X1000_SSCR1_TFT);
1225 break;
1226 case CE4100_SSP:
1227 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1228 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1229 break;
1230 default:
1231 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1232 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1233 break;
1234 }
1235
1236 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1237 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1238 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1239
1240 if (spi->mode & SPI_LOOP)
1241 chip->cr1 |= SSCR1_LBM;
1242
1243 spi_set_ctldata(spi, chip);
1244
1245 return 0;
1246}
1247
1248static void cleanup(struct spi_device *spi)
1249{
1250 struct chip_data *chip = spi_get_ctldata(spi);
1251
1252 kfree(chip);
1253}
1254
1255static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1256 unsigned int cs)
1257{
1258 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1259
1260 switch (drv_data->ssp_type) {
1261 /*
1262 * For some of Intel Atoms the ACPI DeviceSelection used by the Windows
1263 * driver starts from 1 instead of 0 so translate it here to match what
1264 * Linux expects.
1265 */
1266 case LPSS_BYT_SSP:
1267 case LPSS_BSW_SSP:
1268 return cs - 1;
1269
1270 default:
1271 return cs;
1272 }
1273}
1274
1275static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1276{
1277 return MAX_DMA_LEN;
1278}
1279
1280int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
1281 struct pxa2xx_spi_controller *platform_info)
1282{
1283 struct spi_controller *controller;
1284 struct driver_data *drv_data;
1285 const struct lpss_config *config;
1286 int status;
1287 u32 tmp;
1288
1289 if (platform_info->is_target)
1290 controller = devm_spi_alloc_target(dev, sizeof(*drv_data));
1291 else
1292 controller = devm_spi_alloc_host(dev, sizeof(*drv_data));
1293 if (!controller)
1294 return dev_err_probe(dev, -ENOMEM, "cannot alloc spi_controller\n");
1295
1296 drv_data = spi_controller_get_devdata(controller);
1297 drv_data->controller = controller;
1298 drv_data->controller_info = platform_info;
1299 drv_data->ssp = ssp;
1300
1301 device_set_node(&controller->dev, dev_fwnode(dev));
1302
1303 /* The spi->mode bits understood by this driver: */
1304 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1305
1306 controller->bus_num = ssp->port_id;
1307 controller->dma_alignment = DMA_ALIGNMENT;
1308 controller->cleanup = cleanup;
1309 controller->setup = setup;
1310 controller->set_cs = pxa2xx_spi_set_cs;
1311 controller->transfer_one = pxa2xx_spi_transfer_one;
1312 controller->target_abort = pxa2xx_spi_target_abort;
1313 controller->handle_err = pxa2xx_spi_handle_err;
1314 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1315 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1316 controller->auto_runtime_pm = true;
1317 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1318
1319 drv_data->ssp_type = ssp->type;
1320
1321 if (pxa25x_ssp_comp(drv_data)) {
1322 switch (drv_data->ssp_type) {
1323 case QUARK_X1000_SSP:
1324 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1325 break;
1326 default:
1327 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1328 break;
1329 }
1330
1331 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1332 drv_data->dma_cr1 = 0;
1333 drv_data->clear_sr = SSSR_ROR;
1334 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1335 } else {
1336 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1337 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1338 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1339 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1340 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1341 | SSSR_ROR | SSSR_TUR;
1342 }
1343
1344 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1345 drv_data);
1346 if (status < 0)
1347 return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq);
1348
1349 /* Setup DMA if requested */
1350 if (platform_info->enable_dma) {
1351 status = pxa2xx_spi_dma_setup(drv_data);
1352 if (status) {
1353 dev_warn(dev, "no DMA channels available, using PIO\n");
1354 platform_info->enable_dma = false;
1355 } else {
1356 controller->can_dma = pxa2xx_spi_can_dma;
1357 controller->max_dma_len = MAX_DMA_LEN;
1358 controller->max_transfer_size =
1359 pxa2xx_spi_max_dma_transfer_size;
1360
1361 dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size);
1362 }
1363 }
1364
1365 /* Enable SOC clock */
1366 status = clk_prepare_enable(ssp->clk);
1367 if (status)
1368 goto out_error_dma_irq_alloc;
1369
1370 controller->max_speed_hz = clk_get_rate(ssp->clk);
1371 /*
1372 * Set minimum speed for all other platforms than Intel Quark which is
1373 * able do under 1 Hz transfers.
1374 */
1375 if (!pxa25x_ssp_comp(drv_data))
1376 controller->min_speed_hz =
1377 DIV_ROUND_UP(controller->max_speed_hz, 4096);
1378 else if (!is_quark_x1000_ssp(drv_data))
1379 controller->min_speed_hz =
1380 DIV_ROUND_UP(controller->max_speed_hz, 512);
1381
1382 pxa_ssp_disable(ssp);
1383
1384 /* Load default SSP configuration */
1385 switch (drv_data->ssp_type) {
1386 case QUARK_X1000_SSP:
1387 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1388 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1389 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1390
1391 /* Using the Motorola SPI protocol and use 8 bit frame */
1392 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1393 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1394 break;
1395 case CE4100_SSP:
1396 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1397 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1398 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1399 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1400 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1401 break;
1402 default:
1403
1404 if (spi_controller_is_target(controller)) {
1405 tmp = SSCR1_SCFR |
1406 SSCR1_SCLKDIR |
1407 SSCR1_SFRMDIR |
1408 SSCR1_RxTresh(2) |
1409 SSCR1_TxTresh(1) |
1410 SSCR1_SPH;
1411 } else {
1412 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1413 SSCR1_TxTresh(TX_THRESH_DFLT);
1414 }
1415 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1416 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1417 if (!spi_controller_is_target(controller))
1418 tmp |= SSCR0_SCR(2);
1419 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1420 break;
1421 }
1422
1423 if (!pxa25x_ssp_comp(drv_data))
1424 pxa2xx_spi_write(drv_data, SSTO, 0);
1425
1426 if (!is_quark_x1000_ssp(drv_data))
1427 pxa2xx_spi_write(drv_data, SSPSP, 0);
1428
1429 if (is_lpss_ssp(drv_data)) {
1430 lpss_ssp_setup(drv_data);
1431 config = lpss_get_config(drv_data);
1432 if (config->reg_capabilities >= 0) {
1433 tmp = __lpss_ssp_read_priv(drv_data,
1434 config->reg_capabilities);
1435 tmp &= LPSS_CAPS_CS_EN_MASK;
1436 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1437 platform_info->num_chipselect = ffz(tmp);
1438 }
1439 }
1440 controller->num_chipselect = platform_info->num_chipselect;
1441 controller->use_gpio_descriptors = true;
1442
1443 if (platform_info->is_target) {
1444 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1445 "ready", GPIOD_OUT_LOW);
1446 if (IS_ERR(drv_data->gpiod_ready)) {
1447 status = PTR_ERR(drv_data->gpiod_ready);
1448 goto out_error_clock_enabled;
1449 }
1450 }
1451
1452 /* Register with the SPI framework */
1453 dev_set_drvdata(dev, drv_data);
1454 status = spi_register_controller(controller);
1455 if (status) {
1456 dev_err_probe(dev, status, "problem registering SPI controller\n");
1457 goto out_error_clock_enabled;
1458 }
1459
1460 return status;
1461
1462out_error_clock_enabled:
1463 clk_disable_unprepare(ssp->clk);
1464
1465out_error_dma_irq_alloc:
1466 pxa2xx_spi_dma_release(drv_data);
1467 free_irq(ssp->irq, drv_data);
1468
1469 return status;
1470}
1471EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_probe, "SPI_PXA2xx");
1472
1473void pxa2xx_spi_remove(struct device *dev)
1474{
1475 struct driver_data *drv_data = dev_get_drvdata(dev);
1476 struct ssp_device *ssp = drv_data->ssp;
1477
1478 spi_unregister_controller(drv_data->controller);
1479
1480 /* Disable the SSP at the peripheral and SOC level */
1481 pxa_ssp_disable(ssp);
1482 clk_disable_unprepare(ssp->clk);
1483
1484 /* Release DMA */
1485 if (drv_data->controller_info->enable_dma)
1486 pxa2xx_spi_dma_release(drv_data);
1487
1488 /* Release IRQ */
1489 free_irq(ssp->irq, drv_data);
1490}
1491EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx");
1492
1493static int pxa2xx_spi_suspend(struct device *dev)
1494{
1495 struct driver_data *drv_data = dev_get_drvdata(dev);
1496 struct ssp_device *ssp = drv_data->ssp;
1497 int status;
1498
1499 status = spi_controller_suspend(drv_data->controller);
1500 if (status)
1501 return status;
1502
1503 pxa_ssp_disable(ssp);
1504
1505 if (!pm_runtime_suspended(dev))
1506 clk_disable_unprepare(ssp->clk);
1507
1508 return 0;
1509}
1510
1511static int pxa2xx_spi_resume(struct device *dev)
1512{
1513 struct driver_data *drv_data = dev_get_drvdata(dev);
1514 struct ssp_device *ssp = drv_data->ssp;
1515 int status;
1516
1517 /* Enable the SSP clock */
1518 if (!pm_runtime_suspended(dev)) {
1519 status = clk_prepare_enable(ssp->clk);
1520 if (status)
1521 return status;
1522 }
1523
1524 /* Start the queue running */
1525 return spi_controller_resume(drv_data->controller);
1526}
1527
1528static int pxa2xx_spi_runtime_suspend(struct device *dev)
1529{
1530 struct driver_data *drv_data = dev_get_drvdata(dev);
1531
1532 clk_disable_unprepare(drv_data->ssp->clk);
1533 return 0;
1534}
1535
1536static int pxa2xx_spi_runtime_resume(struct device *dev)
1537{
1538 struct driver_data *drv_data = dev_get_drvdata(dev);
1539
1540 return clk_prepare_enable(drv_data->ssp->clk);
1541}
1542
1543EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) = {
1544 SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1545 RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1546};
1547
1548MODULE_AUTHOR("Stephen Street");
1549MODULE_DESCRIPTION("PXA2xx SSP SPI Controller core driver");
1550MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/bitops.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/ioport.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
25#include <linux/pci.h>
26#include <linux/platform_device.h>
27#include <linux/spi/pxa2xx_spi.h>
28#include <linux/spi/spi.h>
29#include <linux/delay.h>
30#include <linux/gpio.h>
31#include <linux/gpio/consumer.h>
32#include <linux/slab.h>
33#include <linux/clk.h>
34#include <linux/pm_runtime.h>
35#include <linux/acpi.h>
36
37#include "spi-pxa2xx.h"
38
39MODULE_AUTHOR("Stephen Street");
40MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41MODULE_LICENSE("GPL");
42MODULE_ALIAS("platform:pxa2xx-spi");
43
44#define TIMOUT_DFLT 1000
45
46/*
47 * for testing SSCR1 changes that require SSP restart, basically
48 * everything except the service and interrupt enables, the pxa270 developer
49 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
50 * list, but the PXA255 dev man says all bits without really meaning the
51 * service and interrupt enables
52 */
53#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
54 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
55 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
56 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
57 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59
60#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
61 | QUARK_X1000_SSCR1_EFWR \
62 | QUARK_X1000_SSCR1_RFT \
63 | QUARK_X1000_SSCR1_TFT \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65
66#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
67 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
68 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
69 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
70 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
72
73#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
74#define LPSS_CS_CONTROL_SW_MODE BIT(0)
75#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
76#define LPSS_CAPS_CS_EN_SHIFT 9
77#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
78
79struct lpss_config {
80 /* LPSS offset from drv_data->ioaddr */
81 unsigned offset;
82 /* Register offsets from drv_data->lpss_base or -1 */
83 int reg_general;
84 int reg_ssp;
85 int reg_cs_ctrl;
86 int reg_capabilities;
87 /* FIFO thresholds */
88 u32 rx_threshold;
89 u32 tx_threshold_lo;
90 u32 tx_threshold_hi;
91 /* Chip select control */
92 unsigned cs_sel_shift;
93 unsigned cs_sel_mask;
94 unsigned cs_num;
95};
96
97/* Keep these sorted with enum pxa_ssp_type */
98static const struct lpss_config lpss_platforms[] = {
99 { /* LPSS_LPT_SSP */
100 .offset = 0x800,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
109 { /* LPSS_BYT_SSP */
110 .offset = 0x400,
111 .reg_general = 0x08,
112 .reg_ssp = 0x0c,
113 .reg_cs_ctrl = 0x18,
114 .reg_capabilities = -1,
115 .rx_threshold = 64,
116 .tx_threshold_lo = 160,
117 .tx_threshold_hi = 224,
118 },
119 { /* LPSS_BSW_SSP */
120 .offset = 0x400,
121 .reg_general = 0x08,
122 .reg_ssp = 0x0c,
123 .reg_cs_ctrl = 0x18,
124 .reg_capabilities = -1,
125 .rx_threshold = 64,
126 .tx_threshold_lo = 160,
127 .tx_threshold_hi = 224,
128 .cs_sel_shift = 2,
129 .cs_sel_mask = 1 << 2,
130 .cs_num = 2,
131 },
132 { /* LPSS_SPT_SSP */
133 .offset = 0x200,
134 .reg_general = -1,
135 .reg_ssp = 0x20,
136 .reg_cs_ctrl = 0x24,
137 .reg_capabilities = -1,
138 .rx_threshold = 1,
139 .tx_threshold_lo = 32,
140 .tx_threshold_hi = 56,
141 },
142 { /* LPSS_BXT_SSP */
143 .offset = 0x200,
144 .reg_general = -1,
145 .reg_ssp = 0x20,
146 .reg_cs_ctrl = 0x24,
147 .reg_capabilities = 0xfc,
148 .rx_threshold = 1,
149 .tx_threshold_lo = 16,
150 .tx_threshold_hi = 48,
151 .cs_sel_shift = 8,
152 .cs_sel_mask = 3 << 8,
153 },
154 { /* LPSS_CNL_SSP */
155 .offset = 0x200,
156 .reg_general = -1,
157 .reg_ssp = 0x20,
158 .reg_cs_ctrl = 0x24,
159 .reg_capabilities = 0xfc,
160 .rx_threshold = 1,
161 .tx_threshold_lo = 32,
162 .tx_threshold_hi = 56,
163 .cs_sel_shift = 8,
164 .cs_sel_mask = 3 << 8,
165 },
166};
167
168static inline const struct lpss_config
169*lpss_get_config(const struct driver_data *drv_data)
170{
171 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
172}
173
174static bool is_lpss_ssp(const struct driver_data *drv_data)
175{
176 switch (drv_data->ssp_type) {
177 case LPSS_LPT_SSP:
178 case LPSS_BYT_SSP:
179 case LPSS_BSW_SSP:
180 case LPSS_SPT_SSP:
181 case LPSS_BXT_SSP:
182 case LPSS_CNL_SSP:
183 return true;
184 default:
185 return false;
186 }
187}
188
189static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
190{
191 return drv_data->ssp_type == QUARK_X1000_SSP;
192}
193
194static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
195{
196 switch (drv_data->ssp_type) {
197 case QUARK_X1000_SSP:
198 return QUARK_X1000_SSCR1_CHANGE_MASK;
199 case CE4100_SSP:
200 return CE4100_SSCR1_CHANGE_MASK;
201 default:
202 return SSCR1_CHANGE_MASK;
203 }
204}
205
206static u32
207pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
208{
209 switch (drv_data->ssp_type) {
210 case QUARK_X1000_SSP:
211 return RX_THRESH_QUARK_X1000_DFLT;
212 case CE4100_SSP:
213 return RX_THRESH_CE4100_DFLT;
214 default:
215 return RX_THRESH_DFLT;
216 }
217}
218
219static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
220{
221 u32 mask;
222
223 switch (drv_data->ssp_type) {
224 case QUARK_X1000_SSP:
225 mask = QUARK_X1000_SSSR_TFL_MASK;
226 break;
227 case CE4100_SSP:
228 mask = CE4100_SSSR_TFL_MASK;
229 break;
230 default:
231 mask = SSSR_TFL_MASK;
232 break;
233 }
234
235 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
236}
237
238static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
239 u32 *sccr1_reg)
240{
241 u32 mask;
242
243 switch (drv_data->ssp_type) {
244 case QUARK_X1000_SSP:
245 mask = QUARK_X1000_SSCR1_RFT;
246 break;
247 case CE4100_SSP:
248 mask = CE4100_SSCR1_RFT;
249 break;
250 default:
251 mask = SSCR1_RFT;
252 break;
253 }
254 *sccr1_reg &= ~mask;
255}
256
257static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
258 u32 *sccr1_reg, u32 threshold)
259{
260 switch (drv_data->ssp_type) {
261 case QUARK_X1000_SSP:
262 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
263 break;
264 case CE4100_SSP:
265 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
266 break;
267 default:
268 *sccr1_reg |= SSCR1_RxTresh(threshold);
269 break;
270 }
271}
272
273static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
274 u32 clk_div, u8 bits)
275{
276 switch (drv_data->ssp_type) {
277 case QUARK_X1000_SSP:
278 return clk_div
279 | QUARK_X1000_SSCR0_Motorola
280 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
281 | SSCR0_SSE;
282 default:
283 return clk_div
284 | SSCR0_Motorola
285 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
286 | SSCR0_SSE
287 | (bits > 16 ? SSCR0_EDSS : 0);
288 }
289}
290
291/*
292 * Read and write LPSS SSP private registers. Caller must first check that
293 * is_lpss_ssp() returns true before these can be called.
294 */
295static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
296{
297 WARN_ON(!drv_data->lpss_base);
298 return readl(drv_data->lpss_base + offset);
299}
300
301static void __lpss_ssp_write_priv(struct driver_data *drv_data,
302 unsigned offset, u32 value)
303{
304 WARN_ON(!drv_data->lpss_base);
305 writel(value, drv_data->lpss_base + offset);
306}
307
308/*
309 * lpss_ssp_setup - perform LPSS SSP specific setup
310 * @drv_data: pointer to the driver private data
311 *
312 * Perform LPSS SSP specific setup. This function must be called first if
313 * one is going to use LPSS SSP private registers.
314 */
315static void lpss_ssp_setup(struct driver_data *drv_data)
316{
317 const struct lpss_config *config;
318 u32 value;
319
320 config = lpss_get_config(drv_data);
321 drv_data->lpss_base = drv_data->ioaddr + config->offset;
322
323 /* Enable software chip select control */
324 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
325 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
326 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
327 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
328
329 /* Enable multiblock DMA transfers */
330 if (drv_data->master_info->enable_dma) {
331 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
332
333 if (config->reg_general >= 0) {
334 value = __lpss_ssp_read_priv(drv_data,
335 config->reg_general);
336 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
337 __lpss_ssp_write_priv(drv_data,
338 config->reg_general, value);
339 }
340 }
341}
342
343static void lpss_ssp_select_cs(struct driver_data *drv_data,
344 const struct lpss_config *config)
345{
346 u32 value, cs;
347
348 if (!config->cs_sel_mask)
349 return;
350
351 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
352
353 cs = drv_data->master->cur_msg->spi->chip_select;
354 cs <<= config->cs_sel_shift;
355 if (cs != (value & config->cs_sel_mask)) {
356 /*
357 * When switching another chip select output active the
358 * output must be selected first and wait 2 ssp_clk cycles
359 * before changing state to active. Otherwise a short
360 * glitch will occur on the previous chip select since
361 * output select is latched but state control is not.
362 */
363 value &= ~config->cs_sel_mask;
364 value |= cs;
365 __lpss_ssp_write_priv(drv_data,
366 config->reg_cs_ctrl, value);
367 ndelay(1000000000 /
368 (drv_data->master->max_speed_hz / 2));
369 }
370}
371
372static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
373{
374 const struct lpss_config *config;
375 u32 value;
376
377 config = lpss_get_config(drv_data);
378
379 if (enable)
380 lpss_ssp_select_cs(drv_data, config);
381
382 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
383 if (enable)
384 value &= ~LPSS_CS_CONTROL_CS_HIGH;
385 else
386 value |= LPSS_CS_CONTROL_CS_HIGH;
387 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
388}
389
390static void cs_assert(struct driver_data *drv_data)
391{
392 struct chip_data *chip =
393 spi_get_ctldata(drv_data->master->cur_msg->spi);
394
395 if (drv_data->ssp_type == CE4100_SSP) {
396 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
397 return;
398 }
399
400 if (chip->cs_control) {
401 chip->cs_control(PXA2XX_CS_ASSERT);
402 return;
403 }
404
405 if (chip->gpiod_cs) {
406 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
407 return;
408 }
409
410 if (is_lpss_ssp(drv_data))
411 lpss_ssp_cs_control(drv_data, true);
412}
413
414static void cs_deassert(struct driver_data *drv_data)
415{
416 struct chip_data *chip =
417 spi_get_ctldata(drv_data->master->cur_msg->spi);
418 unsigned long timeout;
419
420 if (drv_data->ssp_type == CE4100_SSP)
421 return;
422
423 /* Wait until SSP becomes idle before deasserting the CS */
424 timeout = jiffies + msecs_to_jiffies(10);
425 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
426 !time_after(jiffies, timeout))
427 cpu_relax();
428
429 if (chip->cs_control) {
430 chip->cs_control(PXA2XX_CS_DEASSERT);
431 return;
432 }
433
434 if (chip->gpiod_cs) {
435 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
436 return;
437 }
438
439 if (is_lpss_ssp(drv_data))
440 lpss_ssp_cs_control(drv_data, false);
441}
442
443int pxa2xx_spi_flush(struct driver_data *drv_data)
444{
445 unsigned long limit = loops_per_jiffy << 1;
446
447 do {
448 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
449 pxa2xx_spi_read(drv_data, SSDR);
450 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
451 write_SSSR_CS(drv_data, SSSR_ROR);
452
453 return limit;
454}
455
456static int null_writer(struct driver_data *drv_data)
457{
458 u8 n_bytes = drv_data->n_bytes;
459
460 if (pxa2xx_spi_txfifo_full(drv_data)
461 || (drv_data->tx == drv_data->tx_end))
462 return 0;
463
464 pxa2xx_spi_write(drv_data, SSDR, 0);
465 drv_data->tx += n_bytes;
466
467 return 1;
468}
469
470static int null_reader(struct driver_data *drv_data)
471{
472 u8 n_bytes = drv_data->n_bytes;
473
474 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
475 && (drv_data->rx < drv_data->rx_end)) {
476 pxa2xx_spi_read(drv_data, SSDR);
477 drv_data->rx += n_bytes;
478 }
479
480 return drv_data->rx == drv_data->rx_end;
481}
482
483static int u8_writer(struct driver_data *drv_data)
484{
485 if (pxa2xx_spi_txfifo_full(drv_data)
486 || (drv_data->tx == drv_data->tx_end))
487 return 0;
488
489 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
490 ++drv_data->tx;
491
492 return 1;
493}
494
495static int u8_reader(struct driver_data *drv_data)
496{
497 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
498 && (drv_data->rx < drv_data->rx_end)) {
499 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
500 ++drv_data->rx;
501 }
502
503 return drv_data->rx == drv_data->rx_end;
504}
505
506static int u16_writer(struct driver_data *drv_data)
507{
508 if (pxa2xx_spi_txfifo_full(drv_data)
509 || (drv_data->tx == drv_data->tx_end))
510 return 0;
511
512 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
513 drv_data->tx += 2;
514
515 return 1;
516}
517
518static int u16_reader(struct driver_data *drv_data)
519{
520 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
521 && (drv_data->rx < drv_data->rx_end)) {
522 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
523 drv_data->rx += 2;
524 }
525
526 return drv_data->rx == drv_data->rx_end;
527}
528
529static int u32_writer(struct driver_data *drv_data)
530{
531 if (pxa2xx_spi_txfifo_full(drv_data)
532 || (drv_data->tx == drv_data->tx_end))
533 return 0;
534
535 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
536 drv_data->tx += 4;
537
538 return 1;
539}
540
541static int u32_reader(struct driver_data *drv_data)
542{
543 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
544 && (drv_data->rx < drv_data->rx_end)) {
545 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
546 drv_data->rx += 4;
547 }
548
549 return drv_data->rx == drv_data->rx_end;
550}
551
552void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
553{
554 struct spi_message *msg = drv_data->master->cur_msg;
555 struct spi_transfer *trans = drv_data->cur_transfer;
556
557 /* Move to next transfer */
558 if (trans->transfer_list.next != &msg->transfers) {
559 drv_data->cur_transfer =
560 list_entry(trans->transfer_list.next,
561 struct spi_transfer,
562 transfer_list);
563 return RUNNING_STATE;
564 } else
565 return DONE_STATE;
566}
567
568/* caller already set message->status; dma and pio irqs are blocked */
569static void giveback(struct driver_data *drv_data)
570{
571 struct spi_transfer* last_transfer;
572 struct spi_message *msg;
573
574 msg = drv_data->master->cur_msg;
575 drv_data->cur_transfer = NULL;
576
577 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
578 transfer_list);
579
580 /* Delay if requested before any change in chip select */
581 if (last_transfer->delay_usecs)
582 udelay(last_transfer->delay_usecs);
583
584 /* Drop chip select UNLESS cs_change is true or we are returning
585 * a message with an error, or next message is for another chip
586 */
587 if (!last_transfer->cs_change)
588 cs_deassert(drv_data);
589 else {
590 struct spi_message *next_msg;
591
592 /* Holding of cs was hinted, but we need to make sure
593 * the next message is for the same chip. Don't waste
594 * time with the following tests unless this was hinted.
595 *
596 * We cannot postpone this until pump_messages, because
597 * after calling msg->complete (below) the driver that
598 * sent the current message could be unloaded, which
599 * could invalidate the cs_control() callback...
600 */
601
602 /* get a pointer to the next message, if any */
603 next_msg = spi_get_next_queued_message(drv_data->master);
604
605 /* see if the next and current messages point
606 * to the same chip
607 */
608 if ((next_msg && next_msg->spi != msg->spi) ||
609 msg->state == ERROR_STATE)
610 cs_deassert(drv_data);
611 }
612
613 spi_finalize_current_message(drv_data->master);
614}
615
616static void reset_sccr1(struct driver_data *drv_data)
617{
618 struct chip_data *chip =
619 spi_get_ctldata(drv_data->master->cur_msg->spi);
620 u32 sccr1_reg;
621
622 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
623 switch (drv_data->ssp_type) {
624 case QUARK_X1000_SSP:
625 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
626 break;
627 case CE4100_SSP:
628 sccr1_reg &= ~CE4100_SSCR1_RFT;
629 break;
630 default:
631 sccr1_reg &= ~SSCR1_RFT;
632 break;
633 }
634 sccr1_reg |= chip->threshold;
635 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
636}
637
638static void int_error_stop(struct driver_data *drv_data, const char* msg)
639{
640 /* Stop and reset SSP */
641 write_SSSR_CS(drv_data, drv_data->clear_sr);
642 reset_sccr1(drv_data);
643 if (!pxa25x_ssp_comp(drv_data))
644 pxa2xx_spi_write(drv_data, SSTO, 0);
645 pxa2xx_spi_flush(drv_data);
646 pxa2xx_spi_write(drv_data, SSCR0,
647 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
648
649 dev_err(&drv_data->pdev->dev, "%s\n", msg);
650
651 drv_data->master->cur_msg->state = ERROR_STATE;
652 tasklet_schedule(&drv_data->pump_transfers);
653}
654
655static void int_transfer_complete(struct driver_data *drv_data)
656{
657 /* Clear and disable interrupts */
658 write_SSSR_CS(drv_data, drv_data->clear_sr);
659 reset_sccr1(drv_data);
660 if (!pxa25x_ssp_comp(drv_data))
661 pxa2xx_spi_write(drv_data, SSTO, 0);
662
663 /* Update total byte transferred return count actual bytes read */
664 drv_data->master->cur_msg->actual_length += drv_data->len -
665 (drv_data->rx_end - drv_data->rx);
666
667 /* Transfer delays and chip select release are
668 * handled in pump_transfers or giveback
669 */
670
671 /* Move to next transfer */
672 drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
673
674 /* Schedule transfer tasklet */
675 tasklet_schedule(&drv_data->pump_transfers);
676}
677
678static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
679{
680 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
681 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
682
683 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
684
685 if (irq_status & SSSR_ROR) {
686 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
687 return IRQ_HANDLED;
688 }
689
690 if (irq_status & SSSR_TINT) {
691 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
692 if (drv_data->read(drv_data)) {
693 int_transfer_complete(drv_data);
694 return IRQ_HANDLED;
695 }
696 }
697
698 /* Drain rx fifo, Fill tx fifo and prevent overruns */
699 do {
700 if (drv_data->read(drv_data)) {
701 int_transfer_complete(drv_data);
702 return IRQ_HANDLED;
703 }
704 } while (drv_data->write(drv_data));
705
706 if (drv_data->read(drv_data)) {
707 int_transfer_complete(drv_data);
708 return IRQ_HANDLED;
709 }
710
711 if (drv_data->tx == drv_data->tx_end) {
712 u32 bytes_left;
713 u32 sccr1_reg;
714
715 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
716 sccr1_reg &= ~SSCR1_TIE;
717
718 /*
719 * PXA25x_SSP has no timeout, set up rx threshould for the
720 * remaining RX bytes.
721 */
722 if (pxa25x_ssp_comp(drv_data)) {
723 u32 rx_thre;
724
725 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
726
727 bytes_left = drv_data->rx_end - drv_data->rx;
728 switch (drv_data->n_bytes) {
729 case 4:
730 bytes_left >>= 1;
731 case 2:
732 bytes_left >>= 1;
733 }
734
735 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
736 if (rx_thre > bytes_left)
737 rx_thre = bytes_left;
738
739 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
740 }
741 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
742 }
743
744 /* We did something */
745 return IRQ_HANDLED;
746}
747
748static void handle_bad_msg(struct driver_data *drv_data)
749{
750 pxa2xx_spi_write(drv_data, SSCR0,
751 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
752 pxa2xx_spi_write(drv_data, SSCR1,
753 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
754 if (!pxa25x_ssp_comp(drv_data))
755 pxa2xx_spi_write(drv_data, SSTO, 0);
756 write_SSSR_CS(drv_data, drv_data->clear_sr);
757
758 dev_err(&drv_data->pdev->dev,
759 "bad message state in interrupt handler\n");
760}
761
762static irqreturn_t ssp_int(int irq, void *dev_id)
763{
764 struct driver_data *drv_data = dev_id;
765 u32 sccr1_reg;
766 u32 mask = drv_data->mask_sr;
767 u32 status;
768
769 /*
770 * The IRQ might be shared with other peripherals so we must first
771 * check that are we RPM suspended or not. If we are we assume that
772 * the IRQ was not for us (we shouldn't be RPM suspended when the
773 * interrupt is enabled).
774 */
775 if (pm_runtime_suspended(&drv_data->pdev->dev))
776 return IRQ_NONE;
777
778 /*
779 * If the device is not yet in RPM suspended state and we get an
780 * interrupt that is meant for another device, check if status bits
781 * are all set to one. That means that the device is already
782 * powered off.
783 */
784 status = pxa2xx_spi_read(drv_data, SSSR);
785 if (status == ~0)
786 return IRQ_NONE;
787
788 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
789
790 /* Ignore possible writes if we don't need to write */
791 if (!(sccr1_reg & SSCR1_TIE))
792 mask &= ~SSSR_TFS;
793
794 /* Ignore RX timeout interrupt if it is disabled */
795 if (!(sccr1_reg & SSCR1_TINTE))
796 mask &= ~SSSR_TINT;
797
798 if (!(status & mask))
799 return IRQ_NONE;
800
801 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
802 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
803
804 if (!drv_data->master->cur_msg) {
805 handle_bad_msg(drv_data);
806 /* Never fail */
807 return IRQ_HANDLED;
808 }
809
810 return drv_data->transfer_handler(drv_data);
811}
812
813/*
814 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
815 * input frequency by fractions of 2^24. It also has a divider by 5.
816 *
817 * There are formulas to get baud rate value for given input frequency and
818 * divider parameters, such as DDS_CLK_RATE and SCR:
819 *
820 * Fsys = 200MHz
821 *
822 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
823 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
824 *
825 * DDS_CLK_RATE either 2^n or 2^n / 5.
826 * SCR is in range 0 .. 255
827 *
828 * Divisor = 5^i * 2^j * 2 * k
829 * i = [0, 1] i = 1 iff j = 0 or j > 3
830 * j = [0, 23] j = 0 iff i = 1
831 * k = [1, 256]
832 * Special case: j = 0, i = 1: Divisor = 2 / 5
833 *
834 * Accordingly to the specification the recommended values for DDS_CLK_RATE
835 * are:
836 * Case 1: 2^n, n = [0, 23]
837 * Case 2: 2^24 * 2 / 5 (0x666666)
838 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
839 *
840 * In all cases the lowest possible value is better.
841 *
842 * The function calculates parameters for all cases and chooses the one closest
843 * to the asked baud rate.
844 */
845static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
846{
847 unsigned long xtal = 200000000;
848 unsigned long fref = xtal / 2; /* mandatory division by 2,
849 see (2) */
850 /* case 3 */
851 unsigned long fref1 = fref / 2; /* case 1 */
852 unsigned long fref2 = fref * 2 / 5; /* case 2 */
853 unsigned long scale;
854 unsigned long q, q1, q2;
855 long r, r1, r2;
856 u32 mul;
857
858 /* Case 1 */
859
860 /* Set initial value for DDS_CLK_RATE */
861 mul = (1 << 24) >> 1;
862
863 /* Calculate initial quot */
864 q1 = DIV_ROUND_UP(fref1, rate);
865
866 /* Scale q1 if it's too big */
867 if (q1 > 256) {
868 /* Scale q1 to range [1, 512] */
869 scale = fls_long(q1 - 1);
870 if (scale > 9) {
871 q1 >>= scale - 9;
872 mul >>= scale - 9;
873 }
874
875 /* Round the result if we have a remainder */
876 q1 += q1 & 1;
877 }
878
879 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
880 scale = __ffs(q1);
881 q1 >>= scale;
882 mul >>= scale;
883
884 /* Get the remainder */
885 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
886
887 /* Case 2 */
888
889 q2 = DIV_ROUND_UP(fref2, rate);
890 r2 = abs(fref2 / q2 - rate);
891
892 /*
893 * Choose the best between two: less remainder we have the better. We
894 * can't go case 2 if q2 is greater than 256 since SCR register can
895 * hold only values 0 .. 255.
896 */
897 if (r2 >= r1 || q2 > 256) {
898 /* case 1 is better */
899 r = r1;
900 q = q1;
901 } else {
902 /* case 2 is better */
903 r = r2;
904 q = q2;
905 mul = (1 << 24) * 2 / 5;
906 }
907
908 /* Check case 3 only if the divisor is big enough */
909 if (fref / rate >= 80) {
910 u64 fssp;
911 u32 m;
912
913 /* Calculate initial quot */
914 q1 = DIV_ROUND_UP(fref, rate);
915 m = (1 << 24) / q1;
916
917 /* Get the remainder */
918 fssp = (u64)fref * m;
919 do_div(fssp, 1 << 24);
920 r1 = abs(fssp - rate);
921
922 /* Choose this one if it suits better */
923 if (r1 < r) {
924 /* case 3 is better */
925 q = 1;
926 mul = m;
927 }
928 }
929
930 *dds = mul;
931 return q - 1;
932}
933
934static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
935{
936 unsigned long ssp_clk = drv_data->master->max_speed_hz;
937 const struct ssp_device *ssp = drv_data->ssp;
938
939 rate = min_t(int, ssp_clk, rate);
940
941 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
942 return (ssp_clk / (2 * rate) - 1) & 0xff;
943 else
944 return (ssp_clk / rate - 1) & 0xfff;
945}
946
947static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
948 int rate)
949{
950 struct chip_data *chip =
951 spi_get_ctldata(drv_data->master->cur_msg->spi);
952 unsigned int clk_div;
953
954 switch (drv_data->ssp_type) {
955 case QUARK_X1000_SSP:
956 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
957 break;
958 default:
959 clk_div = ssp_get_clk_div(drv_data, rate);
960 break;
961 }
962 return clk_div << 8;
963}
964
965static bool pxa2xx_spi_can_dma(struct spi_controller *master,
966 struct spi_device *spi,
967 struct spi_transfer *xfer)
968{
969 struct chip_data *chip = spi_get_ctldata(spi);
970
971 return chip->enable_dma &&
972 xfer->len <= MAX_DMA_LEN &&
973 xfer->len >= chip->dma_burst_size;
974}
975
976static void pump_transfers(unsigned long data)
977{
978 struct driver_data *drv_data = (struct driver_data *)data;
979 struct spi_controller *master = drv_data->master;
980 struct spi_message *message = master->cur_msg;
981 struct chip_data *chip = spi_get_ctldata(message->spi);
982 u32 dma_thresh = chip->dma_threshold;
983 u32 dma_burst = chip->dma_burst_size;
984 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
985 struct spi_transfer *transfer;
986 struct spi_transfer *previous;
987 u32 clk_div;
988 u8 bits;
989 u32 speed;
990 u32 cr0;
991 u32 cr1;
992 int err;
993 int dma_mapped;
994
995 /* Get current state information */
996 transfer = drv_data->cur_transfer;
997
998 /* Handle for abort */
999 if (message->state == ERROR_STATE) {
1000 message->status = -EIO;
1001 giveback(drv_data);
1002 return;
1003 }
1004
1005 /* Handle end of message */
1006 if (message->state == DONE_STATE) {
1007 message->status = 0;
1008 giveback(drv_data);
1009 return;
1010 }
1011
1012 /* Delay if requested at end of transfer before CS change */
1013 if (message->state == RUNNING_STATE) {
1014 previous = list_entry(transfer->transfer_list.prev,
1015 struct spi_transfer,
1016 transfer_list);
1017 if (previous->delay_usecs)
1018 udelay(previous->delay_usecs);
1019
1020 /* Drop chip select only if cs_change is requested */
1021 if (previous->cs_change)
1022 cs_deassert(drv_data);
1023 }
1024
1025 /* Check if we can DMA this transfer */
1026 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
1027
1028 /* reject already-mapped transfers; PIO won't always work */
1029 if (message->is_dma_mapped
1030 || transfer->rx_dma || transfer->tx_dma) {
1031 dev_err(&drv_data->pdev->dev,
1032 "pump_transfers: mapped transfer length of "
1033 "%u is greater than %d\n",
1034 transfer->len, MAX_DMA_LEN);
1035 message->status = -EINVAL;
1036 giveback(drv_data);
1037 return;
1038 }
1039
1040 /* warn ... we force this to PIO mode */
1041 dev_warn_ratelimited(&message->spi->dev,
1042 "pump_transfers: DMA disabled for transfer length %ld "
1043 "greater than %d\n",
1044 (long)drv_data->len, MAX_DMA_LEN);
1045 }
1046
1047 /* Setup the transfer state based on the type of transfer */
1048 if (pxa2xx_spi_flush(drv_data) == 0) {
1049 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1050 message->status = -EIO;
1051 giveback(drv_data);
1052 return;
1053 }
1054 drv_data->n_bytes = chip->n_bytes;
1055 drv_data->tx = (void *)transfer->tx_buf;
1056 drv_data->tx_end = drv_data->tx + transfer->len;
1057 drv_data->rx = transfer->rx_buf;
1058 drv_data->rx_end = drv_data->rx + transfer->len;
1059 drv_data->len = transfer->len;
1060 drv_data->write = drv_data->tx ? chip->write : null_writer;
1061 drv_data->read = drv_data->rx ? chip->read : null_reader;
1062
1063 /* Change speed and bit per word on a per transfer */
1064 bits = transfer->bits_per_word;
1065 speed = transfer->speed_hz;
1066
1067 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1068
1069 if (bits <= 8) {
1070 drv_data->n_bytes = 1;
1071 drv_data->read = drv_data->read != null_reader ?
1072 u8_reader : null_reader;
1073 drv_data->write = drv_data->write != null_writer ?
1074 u8_writer : null_writer;
1075 } else if (bits <= 16) {
1076 drv_data->n_bytes = 2;
1077 drv_data->read = drv_data->read != null_reader ?
1078 u16_reader : null_reader;
1079 drv_data->write = drv_data->write != null_writer ?
1080 u16_writer : null_writer;
1081 } else if (bits <= 32) {
1082 drv_data->n_bytes = 4;
1083 drv_data->read = drv_data->read != null_reader ?
1084 u32_reader : null_reader;
1085 drv_data->write = drv_data->write != null_writer ?
1086 u32_writer : null_writer;
1087 }
1088 /*
1089 * if bits/word is changed in dma mode, then must check the
1090 * thresholds and burst also
1091 */
1092 if (chip->enable_dma) {
1093 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1094 message->spi,
1095 bits, &dma_burst,
1096 &dma_thresh))
1097 dev_warn_ratelimited(&message->spi->dev,
1098 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1099 }
1100
1101 message->state = RUNNING_STATE;
1102
1103 dma_mapped = master->can_dma &&
1104 master->can_dma(master, message->spi, transfer) &&
1105 master->cur_msg_mapped;
1106 if (dma_mapped) {
1107
1108 /* Ensure we have the correct interrupt handler */
1109 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1110
1111 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1112 if (err) {
1113 message->status = err;
1114 giveback(drv_data);
1115 return;
1116 }
1117
1118 /* Clear status and start DMA engine */
1119 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1120 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1121
1122 pxa2xx_spi_dma_start(drv_data);
1123 } else {
1124 /* Ensure we have the correct interrupt handler */
1125 drv_data->transfer_handler = interrupt_transfer;
1126
1127 /* Clear status */
1128 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1129 write_SSSR_CS(drv_data, drv_data->clear_sr);
1130 }
1131
1132 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1133 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1134 if (!pxa25x_ssp_comp(drv_data))
1135 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1136 master->max_speed_hz
1137 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1138 dma_mapped ? "DMA" : "PIO");
1139 else
1140 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1141 master->max_speed_hz / 2
1142 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1143 dma_mapped ? "DMA" : "PIO");
1144
1145 if (is_lpss_ssp(drv_data)) {
1146 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1147 != chip->lpss_rx_threshold)
1148 pxa2xx_spi_write(drv_data, SSIRF,
1149 chip->lpss_rx_threshold);
1150 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1151 != chip->lpss_tx_threshold)
1152 pxa2xx_spi_write(drv_data, SSITF,
1153 chip->lpss_tx_threshold);
1154 }
1155
1156 if (is_quark_x1000_ssp(drv_data) &&
1157 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1158 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1159
1160 /* see if we need to reload the config registers */
1161 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1162 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1163 != (cr1 & change_mask)) {
1164 /* stop the SSP, and update the other bits */
1165 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1166 if (!pxa25x_ssp_comp(drv_data))
1167 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1168 /* first set CR1 without interrupt and service enables */
1169 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1170 /* restart the SSP */
1171 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1172
1173 } else {
1174 if (!pxa25x_ssp_comp(drv_data))
1175 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1176 }
1177
1178 cs_assert(drv_data);
1179
1180 /* after chip select, release the data by enabling service
1181 * requests and interrupts, without changing any mode bits */
1182 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1183}
1184
1185static int pxa2xx_spi_transfer_one_message(struct spi_controller *master,
1186 struct spi_message *msg)
1187{
1188 struct driver_data *drv_data = spi_controller_get_devdata(master);
1189
1190 /* Initial message state*/
1191 msg->state = START_STATE;
1192 drv_data->cur_transfer = list_entry(msg->transfers.next,
1193 struct spi_transfer,
1194 transfer_list);
1195
1196 /* Mark as busy and launch transfers */
1197 tasklet_schedule(&drv_data->pump_transfers);
1198 return 0;
1199}
1200
1201static int pxa2xx_spi_unprepare_transfer(struct spi_controller *master)
1202{
1203 struct driver_data *drv_data = spi_controller_get_devdata(master);
1204
1205 /* Disable the SSP now */
1206 pxa2xx_spi_write(drv_data, SSCR0,
1207 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1208
1209 return 0;
1210}
1211
1212static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1213 struct pxa2xx_spi_chip *chip_info)
1214{
1215 struct driver_data *drv_data =
1216 spi_controller_get_devdata(spi->controller);
1217 struct gpio_desc *gpiod;
1218 int err = 0;
1219
1220 if (chip == NULL)
1221 return 0;
1222
1223 if (drv_data->cs_gpiods) {
1224 gpiod = drv_data->cs_gpiods[spi->chip_select];
1225 if (gpiod) {
1226 chip->gpiod_cs = gpiod;
1227 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1228 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1229 }
1230
1231 return 0;
1232 }
1233
1234 if (chip_info == NULL)
1235 return 0;
1236
1237 /* NOTE: setup() can be called multiple times, possibly with
1238 * different chip_info, release previously requested GPIO
1239 */
1240 if (chip->gpiod_cs) {
1241 gpiod_put(chip->gpiod_cs);
1242 chip->gpiod_cs = NULL;
1243 }
1244
1245 /* If (*cs_control) is provided, ignore GPIO chip select */
1246 if (chip_info->cs_control) {
1247 chip->cs_control = chip_info->cs_control;
1248 return 0;
1249 }
1250
1251 if (gpio_is_valid(chip_info->gpio_cs)) {
1252 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1253 if (err) {
1254 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1255 chip_info->gpio_cs);
1256 return err;
1257 }
1258
1259 gpiod = gpio_to_desc(chip_info->gpio_cs);
1260 chip->gpiod_cs = gpiod;
1261 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1262
1263 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1264 }
1265
1266 return err;
1267}
1268
1269static int setup(struct spi_device *spi)
1270{
1271 struct pxa2xx_spi_chip *chip_info;
1272 struct chip_data *chip;
1273 const struct lpss_config *config;
1274 struct driver_data *drv_data =
1275 spi_controller_get_devdata(spi->controller);
1276 uint tx_thres, tx_hi_thres, rx_thres;
1277
1278 switch (drv_data->ssp_type) {
1279 case QUARK_X1000_SSP:
1280 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1281 tx_hi_thres = 0;
1282 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1283 break;
1284 case CE4100_SSP:
1285 tx_thres = TX_THRESH_CE4100_DFLT;
1286 tx_hi_thres = 0;
1287 rx_thres = RX_THRESH_CE4100_DFLT;
1288 break;
1289 case LPSS_LPT_SSP:
1290 case LPSS_BYT_SSP:
1291 case LPSS_BSW_SSP:
1292 case LPSS_SPT_SSP:
1293 case LPSS_BXT_SSP:
1294 case LPSS_CNL_SSP:
1295 config = lpss_get_config(drv_data);
1296 tx_thres = config->tx_threshold_lo;
1297 tx_hi_thres = config->tx_threshold_hi;
1298 rx_thres = config->rx_threshold;
1299 break;
1300 default:
1301 tx_thres = TX_THRESH_DFLT;
1302 tx_hi_thres = 0;
1303 rx_thres = RX_THRESH_DFLT;
1304 break;
1305 }
1306
1307 /* Only alloc on first setup */
1308 chip = spi_get_ctldata(spi);
1309 if (!chip) {
1310 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1311 if (!chip)
1312 return -ENOMEM;
1313
1314 if (drv_data->ssp_type == CE4100_SSP) {
1315 if (spi->chip_select > 4) {
1316 dev_err(&spi->dev,
1317 "failed setup: cs number must not be > 4.\n");
1318 kfree(chip);
1319 return -EINVAL;
1320 }
1321
1322 chip->frm = spi->chip_select;
1323 }
1324 chip->enable_dma = drv_data->master_info->enable_dma;
1325 chip->timeout = TIMOUT_DFLT;
1326 }
1327
1328 /* protocol drivers may change the chip settings, so...
1329 * if chip_info exists, use it */
1330 chip_info = spi->controller_data;
1331
1332 /* chip_info isn't always needed */
1333 chip->cr1 = 0;
1334 if (chip_info) {
1335 if (chip_info->timeout)
1336 chip->timeout = chip_info->timeout;
1337 if (chip_info->tx_threshold)
1338 tx_thres = chip_info->tx_threshold;
1339 if (chip_info->tx_hi_threshold)
1340 tx_hi_thres = chip_info->tx_hi_threshold;
1341 if (chip_info->rx_threshold)
1342 rx_thres = chip_info->rx_threshold;
1343 chip->dma_threshold = 0;
1344 if (chip_info->enable_loopback)
1345 chip->cr1 = SSCR1_LBM;
1346 }
1347
1348 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1349 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1350 | SSITF_TxHiThresh(tx_hi_thres);
1351
1352 /* set dma burst and threshold outside of chip_info path so that if
1353 * chip_info goes away after setting chip->enable_dma, the
1354 * burst and threshold can still respond to changes in bits_per_word */
1355 if (chip->enable_dma) {
1356 /* set up legal burst and threshold for dma */
1357 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1358 spi->bits_per_word,
1359 &chip->dma_burst_size,
1360 &chip->dma_threshold)) {
1361 dev_warn(&spi->dev,
1362 "in setup: DMA burst size reduced to match bits_per_word\n");
1363 }
1364 }
1365
1366 switch (drv_data->ssp_type) {
1367 case QUARK_X1000_SSP:
1368 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1369 & QUARK_X1000_SSCR1_RFT)
1370 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1371 & QUARK_X1000_SSCR1_TFT);
1372 break;
1373 case CE4100_SSP:
1374 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1375 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1376 break;
1377 default:
1378 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1379 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1380 break;
1381 }
1382
1383 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1384 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1385 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1386
1387 if (spi->mode & SPI_LOOP)
1388 chip->cr1 |= SSCR1_LBM;
1389
1390 if (spi->bits_per_word <= 8) {
1391 chip->n_bytes = 1;
1392 chip->read = u8_reader;
1393 chip->write = u8_writer;
1394 } else if (spi->bits_per_word <= 16) {
1395 chip->n_bytes = 2;
1396 chip->read = u16_reader;
1397 chip->write = u16_writer;
1398 } else if (spi->bits_per_word <= 32) {
1399 chip->n_bytes = 4;
1400 chip->read = u32_reader;
1401 chip->write = u32_writer;
1402 }
1403
1404 spi_set_ctldata(spi, chip);
1405
1406 if (drv_data->ssp_type == CE4100_SSP)
1407 return 0;
1408
1409 return setup_cs(spi, chip, chip_info);
1410}
1411
1412static void cleanup(struct spi_device *spi)
1413{
1414 struct chip_data *chip = spi_get_ctldata(spi);
1415 struct driver_data *drv_data =
1416 spi_controller_get_devdata(spi->controller);
1417
1418 if (!chip)
1419 return;
1420
1421 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1422 chip->gpiod_cs)
1423 gpiod_put(chip->gpiod_cs);
1424
1425 kfree(chip);
1426}
1427
1428#ifdef CONFIG_PCI
1429#ifdef CONFIG_ACPI
1430
1431static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1432 { "INT33C0", LPSS_LPT_SSP },
1433 { "INT33C1", LPSS_LPT_SSP },
1434 { "INT3430", LPSS_LPT_SSP },
1435 { "INT3431", LPSS_LPT_SSP },
1436 { "80860F0E", LPSS_BYT_SSP },
1437 { "8086228E", LPSS_BSW_SSP },
1438 { },
1439};
1440MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1441
1442static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1443{
1444 unsigned int devid;
1445 int port_id = -1;
1446
1447 if (adev && adev->pnp.unique_id &&
1448 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1449 port_id = devid;
1450 return port_id;
1451}
1452#else /* !CONFIG_ACPI */
1453static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1454{
1455 return -1;
1456}
1457#endif
1458
1459/*
1460 * PCI IDs of compound devices that integrate both host controller and private
1461 * integrated DMA engine. Please note these are not used in module
1462 * autoloading and probing in this module but matching the LPSS SSP type.
1463 */
1464static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1465 /* SPT-LP */
1466 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1467 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1468 /* SPT-H */
1469 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1470 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1471 /* KBL-H */
1472 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1473 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1474 /* BXT A-Step */
1475 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1476 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1477 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1478 /* BXT B-Step */
1479 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1480 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1481 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1482 /* GLK */
1483 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1484 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1485 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1486 /* APL */
1487 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1488 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1489 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1490 /* CNL-LP */
1491 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1492 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1493 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1494 /* CNL-H */
1495 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1496 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1497 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1498 { },
1499};
1500
1501static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1502{
1503 struct device *dev = param;
1504
1505 if (dev != chan->device->dev->parent)
1506 return false;
1507
1508 return true;
1509}
1510
1511static struct pxa2xx_spi_master *
1512pxa2xx_spi_init_pdata(struct platform_device *pdev)
1513{
1514 struct pxa2xx_spi_master *pdata;
1515 struct acpi_device *adev;
1516 struct ssp_device *ssp;
1517 struct resource *res;
1518 const struct acpi_device_id *adev_id = NULL;
1519 const struct pci_device_id *pcidev_id = NULL;
1520 int type;
1521
1522 adev = ACPI_COMPANION(&pdev->dev);
1523
1524 if (dev_is_pci(pdev->dev.parent))
1525 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1526 to_pci_dev(pdev->dev.parent));
1527 else if (adev)
1528 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1529 &pdev->dev);
1530 else
1531 return NULL;
1532
1533 if (adev_id)
1534 type = (int)adev_id->driver_data;
1535 else if (pcidev_id)
1536 type = (int)pcidev_id->driver_data;
1537 else
1538 return NULL;
1539
1540 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1541 if (!pdata)
1542 return NULL;
1543
1544 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1545 if (!res)
1546 return NULL;
1547
1548 ssp = &pdata->ssp;
1549
1550 ssp->phys_base = res->start;
1551 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1552 if (IS_ERR(ssp->mmio_base))
1553 return NULL;
1554
1555 if (pcidev_id) {
1556 pdata->tx_param = pdev->dev.parent;
1557 pdata->rx_param = pdev->dev.parent;
1558 pdata->dma_filter = pxa2xx_spi_idma_filter;
1559 }
1560
1561 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1562 ssp->irq = platform_get_irq(pdev, 0);
1563 ssp->type = type;
1564 ssp->pdev = pdev;
1565 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1566
1567 pdata->num_chipselect = 1;
1568 pdata->enable_dma = true;
1569
1570 return pdata;
1571}
1572
1573#else /* !CONFIG_PCI */
1574static inline struct pxa2xx_spi_master *
1575pxa2xx_spi_init_pdata(struct platform_device *pdev)
1576{
1577 return NULL;
1578}
1579#endif
1580
1581static int pxa2xx_spi_fw_translate_cs(struct spi_controller *master,
1582 unsigned int cs)
1583{
1584 struct driver_data *drv_data = spi_controller_get_devdata(master);
1585
1586 if (has_acpi_companion(&drv_data->pdev->dev)) {
1587 switch (drv_data->ssp_type) {
1588 /*
1589 * For Atoms the ACPI DeviceSelection used by the Windows
1590 * driver starts from 1 instead of 0 so translate it here
1591 * to match what Linux expects.
1592 */
1593 case LPSS_BYT_SSP:
1594 case LPSS_BSW_SSP:
1595 return cs - 1;
1596
1597 default:
1598 break;
1599 }
1600 }
1601
1602 return cs;
1603}
1604
1605static int pxa2xx_spi_probe(struct platform_device *pdev)
1606{
1607 struct device *dev = &pdev->dev;
1608 struct pxa2xx_spi_master *platform_info;
1609 struct spi_controller *master;
1610 struct driver_data *drv_data;
1611 struct ssp_device *ssp;
1612 const struct lpss_config *config;
1613 int status, count;
1614 u32 tmp;
1615
1616 platform_info = dev_get_platdata(dev);
1617 if (!platform_info) {
1618 platform_info = pxa2xx_spi_init_pdata(pdev);
1619 if (!platform_info) {
1620 dev_err(&pdev->dev, "missing platform data\n");
1621 return -ENODEV;
1622 }
1623 }
1624
1625 ssp = pxa_ssp_request(pdev->id, pdev->name);
1626 if (!ssp)
1627 ssp = &platform_info->ssp;
1628
1629 if (!ssp->mmio_base) {
1630 dev_err(&pdev->dev, "failed to get ssp\n");
1631 return -ENODEV;
1632 }
1633
1634 master = spi_alloc_master(dev, sizeof(struct driver_data));
1635 if (!master) {
1636 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1637 pxa_ssp_free(ssp);
1638 return -ENOMEM;
1639 }
1640 drv_data = spi_controller_get_devdata(master);
1641 drv_data->master = master;
1642 drv_data->master_info = platform_info;
1643 drv_data->pdev = pdev;
1644 drv_data->ssp = ssp;
1645
1646 master->dev.of_node = pdev->dev.of_node;
1647 /* the spi->mode bits understood by this driver: */
1648 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1649
1650 master->bus_num = ssp->port_id;
1651 master->dma_alignment = DMA_ALIGNMENT;
1652 master->cleanup = cleanup;
1653 master->setup = setup;
1654 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1655 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1656 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1657 master->auto_runtime_pm = true;
1658 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1659
1660 drv_data->ssp_type = ssp->type;
1661
1662 drv_data->ioaddr = ssp->mmio_base;
1663 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1664 if (pxa25x_ssp_comp(drv_data)) {
1665 switch (drv_data->ssp_type) {
1666 case QUARK_X1000_SSP:
1667 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1668 break;
1669 default:
1670 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1671 break;
1672 }
1673
1674 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1675 drv_data->dma_cr1 = 0;
1676 drv_data->clear_sr = SSSR_ROR;
1677 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1678 } else {
1679 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1680 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1681 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1682 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1683 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1684 }
1685
1686 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1687 drv_data);
1688 if (status < 0) {
1689 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1690 goto out_error_master_alloc;
1691 }
1692
1693 /* Setup DMA if requested */
1694 if (platform_info->enable_dma) {
1695 status = pxa2xx_spi_dma_setup(drv_data);
1696 if (status) {
1697 dev_dbg(dev, "no DMA channels available, using PIO\n");
1698 platform_info->enable_dma = false;
1699 } else {
1700 master->can_dma = pxa2xx_spi_can_dma;
1701 }
1702 }
1703
1704 /* Enable SOC clock */
1705 clk_prepare_enable(ssp->clk);
1706
1707 master->max_speed_hz = clk_get_rate(ssp->clk);
1708
1709 /* Load default SSP configuration */
1710 pxa2xx_spi_write(drv_data, SSCR0, 0);
1711 switch (drv_data->ssp_type) {
1712 case QUARK_X1000_SSP:
1713 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1714 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1715 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1716
1717 /* using the Motorola SPI protocol and use 8 bit frame */
1718 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1719 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1720 break;
1721 case CE4100_SSP:
1722 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1723 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1724 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1725 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1726 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1727 break;
1728 default:
1729 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1730 SSCR1_TxTresh(TX_THRESH_DFLT);
1731 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1732 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1733 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1734 break;
1735 }
1736
1737 if (!pxa25x_ssp_comp(drv_data))
1738 pxa2xx_spi_write(drv_data, SSTO, 0);
1739
1740 if (!is_quark_x1000_ssp(drv_data))
1741 pxa2xx_spi_write(drv_data, SSPSP, 0);
1742
1743 if (is_lpss_ssp(drv_data)) {
1744 lpss_ssp_setup(drv_data);
1745 config = lpss_get_config(drv_data);
1746 if (config->reg_capabilities >= 0) {
1747 tmp = __lpss_ssp_read_priv(drv_data,
1748 config->reg_capabilities);
1749 tmp &= LPSS_CAPS_CS_EN_MASK;
1750 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1751 platform_info->num_chipselect = ffz(tmp);
1752 } else if (config->cs_num) {
1753 platform_info->num_chipselect = config->cs_num;
1754 }
1755 }
1756 master->num_chipselect = platform_info->num_chipselect;
1757
1758 count = gpiod_count(&pdev->dev, "cs");
1759 if (count > 0) {
1760 int i;
1761
1762 master->num_chipselect = max_t(int, count,
1763 master->num_chipselect);
1764
1765 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1766 master->num_chipselect, sizeof(struct gpio_desc *),
1767 GFP_KERNEL);
1768 if (!drv_data->cs_gpiods) {
1769 status = -ENOMEM;
1770 goto out_error_clock_enabled;
1771 }
1772
1773 for (i = 0; i < master->num_chipselect; i++) {
1774 struct gpio_desc *gpiod;
1775
1776 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1777 if (IS_ERR(gpiod)) {
1778 /* Means use native chip select */
1779 if (PTR_ERR(gpiod) == -ENOENT)
1780 continue;
1781
1782 status = (int)PTR_ERR(gpiod);
1783 goto out_error_clock_enabled;
1784 } else {
1785 drv_data->cs_gpiods[i] = gpiod;
1786 }
1787 }
1788 }
1789
1790 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1791 (unsigned long)drv_data);
1792
1793 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1794 pm_runtime_use_autosuspend(&pdev->dev);
1795 pm_runtime_set_active(&pdev->dev);
1796 pm_runtime_enable(&pdev->dev);
1797
1798 /* Register with the SPI framework */
1799 platform_set_drvdata(pdev, drv_data);
1800 status = devm_spi_register_controller(&pdev->dev, master);
1801 if (status != 0) {
1802 dev_err(&pdev->dev, "problem registering spi master\n");
1803 goto out_error_clock_enabled;
1804 }
1805
1806 return status;
1807
1808out_error_clock_enabled:
1809 pm_runtime_put_noidle(&pdev->dev);
1810 pm_runtime_disable(&pdev->dev);
1811 clk_disable_unprepare(ssp->clk);
1812 pxa2xx_spi_dma_release(drv_data);
1813 free_irq(ssp->irq, drv_data);
1814
1815out_error_master_alloc:
1816 spi_controller_put(master);
1817 pxa_ssp_free(ssp);
1818 return status;
1819}
1820
1821static int pxa2xx_spi_remove(struct platform_device *pdev)
1822{
1823 struct driver_data *drv_data = platform_get_drvdata(pdev);
1824 struct ssp_device *ssp;
1825
1826 if (!drv_data)
1827 return 0;
1828 ssp = drv_data->ssp;
1829
1830 pm_runtime_get_sync(&pdev->dev);
1831
1832 /* Disable the SSP at the peripheral and SOC level */
1833 pxa2xx_spi_write(drv_data, SSCR0, 0);
1834 clk_disable_unprepare(ssp->clk);
1835
1836 /* Release DMA */
1837 if (drv_data->master_info->enable_dma)
1838 pxa2xx_spi_dma_release(drv_data);
1839
1840 pm_runtime_put_noidle(&pdev->dev);
1841 pm_runtime_disable(&pdev->dev);
1842
1843 /* Release IRQ */
1844 free_irq(ssp->irq, drv_data);
1845
1846 /* Release SSP */
1847 pxa_ssp_free(ssp);
1848
1849 return 0;
1850}
1851
1852static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1853{
1854 int status = 0;
1855
1856 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1857 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1858}
1859
1860#ifdef CONFIG_PM_SLEEP
1861static int pxa2xx_spi_suspend(struct device *dev)
1862{
1863 struct driver_data *drv_data = dev_get_drvdata(dev);
1864 struct ssp_device *ssp = drv_data->ssp;
1865 int status;
1866
1867 status = spi_controller_suspend(drv_data->master);
1868 if (status != 0)
1869 return status;
1870 pxa2xx_spi_write(drv_data, SSCR0, 0);
1871
1872 if (!pm_runtime_suspended(dev))
1873 clk_disable_unprepare(ssp->clk);
1874
1875 return 0;
1876}
1877
1878static int pxa2xx_spi_resume(struct device *dev)
1879{
1880 struct driver_data *drv_data = dev_get_drvdata(dev);
1881 struct ssp_device *ssp = drv_data->ssp;
1882 int status;
1883
1884 /* Enable the SSP clock */
1885 if (!pm_runtime_suspended(dev))
1886 clk_prepare_enable(ssp->clk);
1887
1888 /* Restore LPSS private register bits */
1889 if (is_lpss_ssp(drv_data))
1890 lpss_ssp_setup(drv_data);
1891
1892 /* Start the queue running */
1893 status = spi_controller_resume(drv_data->master);
1894 if (status != 0) {
1895 dev_err(dev, "problem starting queue (%d)\n", status);
1896 return status;
1897 }
1898
1899 return 0;
1900}
1901#endif
1902
1903#ifdef CONFIG_PM
1904static int pxa2xx_spi_runtime_suspend(struct device *dev)
1905{
1906 struct driver_data *drv_data = dev_get_drvdata(dev);
1907
1908 clk_disable_unprepare(drv_data->ssp->clk);
1909 return 0;
1910}
1911
1912static int pxa2xx_spi_runtime_resume(struct device *dev)
1913{
1914 struct driver_data *drv_data = dev_get_drvdata(dev);
1915
1916 clk_prepare_enable(drv_data->ssp->clk);
1917 return 0;
1918}
1919#endif
1920
1921static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1922 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1923 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1924 pxa2xx_spi_runtime_resume, NULL)
1925};
1926
1927static struct platform_driver driver = {
1928 .driver = {
1929 .name = "pxa2xx-spi",
1930 .pm = &pxa2xx_spi_pm_ops,
1931 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1932 },
1933 .probe = pxa2xx_spi_probe,
1934 .remove = pxa2xx_spi_remove,
1935 .shutdown = pxa2xx_spi_shutdown,
1936};
1937
1938static int __init pxa2xx_spi_init(void)
1939{
1940 return platform_driver_register(&driver);
1941}
1942subsys_initcall(pxa2xx_spi_init);
1943
1944static void __exit pxa2xx_spi_exit(void)
1945{
1946 platform_driver_unregister(&driver);
1947}
1948module_exit(pxa2xx_spi_exit);