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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI_PPC4XX SPI controller driver.
4 *
5 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
6 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
8 *
9 * Based in part on drivers/spi/spi_s3c24xx.c
10 *
11 * Copyright (c) 2006 Ben Dooks
12 * Copyright (c) 2006 Simtec Electronics
13 * Ben Dooks <ben@simtec.co.uk>
14 */
15
16/*
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
19 * This driver allows platforms to reduce the interrupt load on the CPU
20 * during SPI transfers by setting max_speed_hz via the device tree.
21 */
22
23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <linux/of_address.h>
29#include <linux/of_platform.h>
30#include <linux/platform_device.h>
31#include <linux/sched.h>
32#include <linux/slab.h>
33#include <linux/wait.h>
34
35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37
38#include <asm/dcr.h>
39#include <asm/dcr-regs.h>
40
41/* bits in mode register - bit 0 is MSb */
42
43/*
44 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
45 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
46 * Note: This is the inverse of CPHA.
47 */
48#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
49
50/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
51#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
52
53/*
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
56 * Note: This is identical to SPI_LSB_FIRST.
57 */
58#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
59
60/*
61 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
62 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
63 * Note: This is identical to CPOL.
64 */
65#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
66
67/*
68 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
69 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
70 */
71#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
72
73/* bits in control register */
74/* starts a transfer when set */
75#define SPI_PPC4XX_CR_STR (0x80 >> 7)
76
77/* bits in status register */
78/* port is busy with a transfer */
79#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
80/* RxD ready */
81#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
82
83/* clock settings (SCP and CI) for various SPI modes */
84#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
85#define SPI_CLK_MODE1 (0 | 0)
86#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
87#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
88
89#define DRIVER_NAME "spi_ppc4xx_of"
90
91struct spi_ppc4xx_regs {
92 u8 mode;
93 u8 rxd;
94 u8 txd;
95 u8 cr;
96 u8 sr;
97 u8 dummy;
98 /*
99 * Clock divisor modulus register
100 * This uses the following formula:
101 * SCPClkOut = OPBCLK/(4(CDM + 1))
102 * or
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
104 * bit 0 is the MSb!
105 */
106 u8 cdm;
107};
108
109/* SPI Controller driver's private data. */
110struct ppc4xx_spi {
111 /* bitbang has to be first */
112 struct spi_bitbang bitbang;
113 struct completion done;
114
115 u64 mapbase;
116 u64 mapsize;
117 int irqnum;
118 /* need this to set the SPI clock */
119 unsigned int opb_freq;
120
121 /* for transfers */
122 int len;
123 int count;
124 /* data buffers */
125 const unsigned char *tx;
126 unsigned char *rx;
127
128 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
129 struct spi_controller *host;
130 struct device *dev;
131};
132
133/* need this so we can set the clock in the chipselect routine */
134struct spi_ppc4xx_cs {
135 u8 mode;
136};
137
138static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
139{
140 struct ppc4xx_spi *hw;
141 u8 data;
142
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
144 t->tx_buf, t->rx_buf, t->len);
145
146 hw = spi_controller_get_devdata(spi->controller);
147
148 hw->tx = t->tx_buf;
149 hw->rx = t->rx_buf;
150 hw->len = t->len;
151 hw->count = 0;
152
153 /* send the first byte */
154 data = hw->tx ? hw->tx[0] : 0;
155 out_8(&hw->regs->txd, data);
156 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
157 wait_for_completion(&hw->done);
158
159 return hw->count;
160}
161
162static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
163{
164 struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller);
165 struct spi_ppc4xx_cs *cs = spi->controller_state;
166 int scr;
167 u8 cdm = 0;
168 u32 speed;
169
170 /* Start with the generic configuration for this device. */
171 speed = spi->max_speed_hz;
172
173 /*
174 * Modify the configuration if the transfer overrides it. Do not allow
175 * the transfer to overwrite the generic configuration with zeros.
176 */
177 if (t) {
178 if (t->speed_hz)
179 speed = min(t->speed_hz, spi->max_speed_hz);
180 }
181
182 if (!speed || (speed > spi->max_speed_hz)) {
183 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
184 return -EINVAL;
185 }
186
187 /* Write new configuration */
188 out_8(&hw->regs->mode, cs->mode);
189
190 /* Set the clock */
191 /* opb_freq was already divided by 4 */
192 scr = (hw->opb_freq / speed) - 1;
193 if (scr > 0)
194 cdm = min(scr, 0xff);
195
196 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
197
198 if (in_8(&hw->regs->cdm) != cdm)
199 out_8(&hw->regs->cdm, cdm);
200
201 mutex_lock(&hw->bitbang.lock);
202 if (!hw->bitbang.busy) {
203 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
204 /* Need to ndelay here? */
205 }
206 mutex_unlock(&hw->bitbang.lock);
207
208 return 0;
209}
210
211static int spi_ppc4xx_setup(struct spi_device *spi)
212{
213 struct spi_ppc4xx_cs *cs = spi->controller_state;
214
215 if (!spi->max_speed_hz) {
216 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
217 return -EINVAL;
218 }
219
220 if (cs == NULL) {
221 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
222 if (!cs)
223 return -ENOMEM;
224 spi->controller_state = cs;
225 }
226
227 /*
228 * We set all bits of the SPI0_MODE register, so,
229 * no need to read-modify-write
230 */
231 cs->mode = SPI_PPC4XX_MODE_SPE;
232
233 switch (spi->mode & SPI_MODE_X_MASK) {
234 case SPI_MODE_0:
235 cs->mode |= SPI_CLK_MODE0;
236 break;
237 case SPI_MODE_1:
238 cs->mode |= SPI_CLK_MODE1;
239 break;
240 case SPI_MODE_2:
241 cs->mode |= SPI_CLK_MODE2;
242 break;
243 case SPI_MODE_3:
244 cs->mode |= SPI_CLK_MODE3;
245 break;
246 }
247
248 if (spi->mode & SPI_LSB_FIRST)
249 cs->mode |= SPI_PPC4XX_MODE_RD;
250
251 return 0;
252}
253
254static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
255{
256 struct ppc4xx_spi *hw;
257 u8 status;
258 u8 data;
259 unsigned int count;
260
261 hw = (struct ppc4xx_spi *)dev_id;
262
263 status = in_8(&hw->regs->sr);
264 if (!status)
265 return IRQ_NONE;
266
267 /*
268 * BSY de-asserts one cycle after the transfer is complete. The
269 * interrupt is asserted after the transfer is complete. The exact
270 * relationship is not documented, hence this code.
271 */
272
273 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
274 u8 lstatus;
275 int cnt = 0;
276
277 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
278 do {
279 ndelay(10);
280 lstatus = in_8(&hw->regs->sr);
281 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
282
283 if (cnt >= 100) {
284 dev_err(hw->dev, "busywait: too many loops!\n");
285 complete(&hw->done);
286 return IRQ_HANDLED;
287 } else {
288 /* status is always 1 (RBR) here */
289 status = in_8(&hw->regs->sr);
290 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
291 }
292 }
293
294 count = hw->count;
295 hw->count++;
296
297 /* RBR triggered this interrupt. Therefore, data must be ready. */
298 data = in_8(&hw->regs->rxd);
299 if (hw->rx)
300 hw->rx[count] = data;
301
302 count++;
303
304 if (count < hw->len) {
305 data = hw->tx ? hw->tx[count] : 0;
306 out_8(&hw->regs->txd, data);
307 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
308 } else {
309 complete(&hw->done);
310 }
311
312 return IRQ_HANDLED;
313}
314
315static void spi_ppc4xx_cleanup(struct spi_device *spi)
316{
317 kfree(spi->controller_state);
318}
319
320static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
321{
322 /*
323 * On all 4xx PPC's the SPI bus is shared/multiplexed with
324 * the 2nd I2C bus. We need to enable the SPI bus before
325 * using it.
326 */
327
328 /* need to clear bit 14 to enable SPC */
329 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
330}
331
332/*
333 * platform_device layer stuff...
334 */
335static int spi_ppc4xx_of_probe(struct platform_device *op)
336{
337 struct ppc4xx_spi *hw;
338 struct spi_controller *host;
339 struct spi_bitbang *bbp;
340 struct resource resource;
341 struct device_node *np = op->dev.of_node;
342 struct device *dev = &op->dev;
343 struct device_node *opbnp;
344 int ret;
345 const unsigned int *clk;
346
347 host = spi_alloc_host(dev, sizeof(*hw));
348 if (host == NULL)
349 return -ENOMEM;
350 host->dev.of_node = np;
351 platform_set_drvdata(op, host);
352 hw = spi_controller_get_devdata(host);
353 hw->host = host;
354 hw->dev = dev;
355
356 init_completion(&hw->done);
357
358 /* Setup the state for the bitbang driver */
359 bbp = &hw->bitbang;
360 bbp->ctlr = hw->host;
361 bbp->setup_transfer = spi_ppc4xx_setupxfer;
362 bbp->txrx_bufs = spi_ppc4xx_txrx;
363 bbp->use_dma = 0;
364 bbp->ctlr->setup = spi_ppc4xx_setup;
365 bbp->ctlr->cleanup = spi_ppc4xx_cleanup;
366 bbp->ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
367 bbp->ctlr->use_gpio_descriptors = true;
368 /*
369 * The SPI core will count the number of GPIO descriptors to figure
370 * out the number of chip selects available on the platform.
371 */
372 bbp->ctlr->num_chipselect = 0;
373
374 /* the spi->mode bits understood by this driver: */
375 bbp->ctlr->mode_bits =
376 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
377
378 /* Get the clock for the OPB */
379 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
380 if (opbnp == NULL) {
381 dev_err(dev, "OPB: cannot find node\n");
382 ret = -ENODEV;
383 goto free_host;
384 }
385 /* Get the clock (Hz) for the OPB */
386 clk = of_get_property(opbnp, "clock-frequency", NULL);
387 if (clk == NULL) {
388 dev_err(dev, "OPB: no clock-frequency property set\n");
389 of_node_put(opbnp);
390 ret = -ENODEV;
391 goto free_host;
392 }
393 hw->opb_freq = *clk;
394 hw->opb_freq >>= 2;
395 of_node_put(opbnp);
396
397 ret = of_address_to_resource(np, 0, &resource);
398 if (ret) {
399 dev_err(dev, "error while parsing device node resource\n");
400 goto free_host;
401 }
402 hw->mapbase = resource.start;
403 hw->mapsize = resource_size(&resource);
404
405 /* Sanity check */
406 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
407 dev_err(dev, "too small to map registers\n");
408 ret = -EINVAL;
409 goto free_host;
410 }
411
412 /* Request IRQ */
413 ret = platform_get_irq(op, 0);
414 if (ret < 0)
415 goto free_host;
416 hw->irqnum = ret;
417
418 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
419 0, "spi_ppc4xx_of", (void *)hw);
420 if (ret) {
421 dev_err(dev, "unable to allocate interrupt\n");
422 goto free_host;
423 }
424
425 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
426 dev_err(dev, "resource unavailable\n");
427 ret = -EBUSY;
428 goto request_mem_error;
429 }
430
431 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
432
433 if (!hw->regs) {
434 dev_err(dev, "unable to memory map registers\n");
435 ret = -ENXIO;
436 goto map_io_error;
437 }
438
439 spi_ppc4xx_enable(hw);
440
441 /* Finally register our spi controller */
442 dev->dma_mask = 0;
443 ret = spi_bitbang_start(bbp);
444 if (ret) {
445 dev_err(dev, "failed to register SPI host\n");
446 goto unmap_regs;
447 }
448
449 dev_info(dev, "driver initialized\n");
450
451 return 0;
452
453unmap_regs:
454 iounmap(hw->regs);
455map_io_error:
456 release_mem_region(hw->mapbase, hw->mapsize);
457request_mem_error:
458 free_irq(hw->irqnum, hw);
459free_host:
460 spi_controller_put(host);
461
462 dev_err(dev, "initialization failed\n");
463 return ret;
464}
465
466static void spi_ppc4xx_of_remove(struct platform_device *op)
467{
468 struct spi_controller *host = platform_get_drvdata(op);
469 struct ppc4xx_spi *hw = spi_controller_get_devdata(host);
470
471 spi_bitbang_stop(&hw->bitbang);
472 release_mem_region(hw->mapbase, hw->mapsize);
473 free_irq(hw->irqnum, hw);
474 iounmap(hw->regs);
475 spi_controller_put(host);
476}
477
478static const struct of_device_id spi_ppc4xx_of_match[] = {
479 { .compatible = "ibm,ppc4xx-spi", },
480 {},
481};
482
483MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
484
485static struct platform_driver spi_ppc4xx_of_driver = {
486 .probe = spi_ppc4xx_of_probe,
487 .remove = spi_ppc4xx_of_remove,
488 .driver = {
489 .name = DRIVER_NAME,
490 .of_match_table = spi_ppc4xx_of_match,
491 },
492};
493module_platform_driver(spi_ppc4xx_of_driver);
494
495MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
496MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
497MODULE_LICENSE("GPL");
1/*
2 * SPI_PPC4XX SPI controller driver.
3 *
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
7 *
8 * Based in part on drivers/spi/spi_s3c24xx.c
9 *
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
17 */
18
19/*
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
24 */
25
26#include <linux/module.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/errno.h>
30#include <linux/wait.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_platform.h>
34#include <linux/of_gpio.h>
35#include <linux/interrupt.h>
36#include <linux/delay.h>
37
38#include <linux/gpio.h>
39#include <linux/spi/spi.h>
40#include <linux/spi/spi_bitbang.h>
41
42#include <asm/io.h>
43#include <asm/dcr.h>
44#include <asm/dcr-regs.h>
45
46/* bits in mode register - bit 0 is MSb */
47
48/*
49 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
50 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
51 * Note: This is the inverse of CPHA.
52 */
53#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
54
55/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
56#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
57
58/*
59 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
60 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
61 * Note: This is identical to SPI_LSB_FIRST.
62 */
63#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
64
65/*
66 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
67 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
68 * Note: This is identical to CPOL.
69 */
70#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
71
72/*
73 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
74 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
75 */
76#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
77
78/* bits in control register */
79/* starts a transfer when set */
80#define SPI_PPC4XX_CR_STR (0x80 >> 7)
81
82/* bits in status register */
83/* port is busy with a transfer */
84#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
85/* RxD ready */
86#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
87
88/* clock settings (SCP and CI) for various SPI modes */
89#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
90#define SPI_CLK_MODE1 (0 | 0)
91#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
92#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
93
94#define DRIVER_NAME "spi_ppc4xx_of"
95
96struct spi_ppc4xx_regs {
97 u8 mode;
98 u8 rxd;
99 u8 txd;
100 u8 cr;
101 u8 sr;
102 u8 dummy;
103 /*
104 * Clock divisor modulus register
105 * This uses the following formula:
106 * SCPClkOut = OPBCLK/(4(CDM + 1))
107 * or
108 * CDM = (OPBCLK/4*SCPClkOut) - 1
109 * bit 0 is the MSb!
110 */
111 u8 cdm;
112};
113
114/* SPI Controller driver's private data. */
115struct ppc4xx_spi {
116 /* bitbang has to be first */
117 struct spi_bitbang bitbang;
118 struct completion done;
119
120 u64 mapbase;
121 u64 mapsize;
122 int irqnum;
123 /* need this to set the SPI clock */
124 unsigned int opb_freq;
125
126 /* for transfers */
127 int len;
128 int count;
129 /* data buffers */
130 const unsigned char *tx;
131 unsigned char *rx;
132
133 int *gpios;
134
135 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
136 struct spi_master *master;
137 struct device *dev;
138};
139
140/* need this so we can set the clock in the chipselect routine */
141struct spi_ppc4xx_cs {
142 u8 mode;
143};
144
145static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
146{
147 struct ppc4xx_spi *hw;
148 u8 data;
149
150 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
151 t->tx_buf, t->rx_buf, t->len);
152
153 hw = spi_master_get_devdata(spi->master);
154
155 hw->tx = t->tx_buf;
156 hw->rx = t->rx_buf;
157 hw->len = t->len;
158 hw->count = 0;
159
160 /* send the first byte */
161 data = hw->tx ? hw->tx[0] : 0;
162 out_8(&hw->regs->txd, data);
163 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
164 wait_for_completion(&hw->done);
165
166 return hw->count;
167}
168
169static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
170{
171 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
172 struct spi_ppc4xx_cs *cs = spi->controller_state;
173 int scr;
174 u8 cdm = 0;
175 u32 speed;
176 u8 bits_per_word;
177
178 /* Start with the generic configuration for this device. */
179 bits_per_word = spi->bits_per_word;
180 speed = spi->max_speed_hz;
181
182 /*
183 * Modify the configuration if the transfer overrides it. Do not allow
184 * the transfer to overwrite the generic configuration with zeros.
185 */
186 if (t) {
187 if (t->bits_per_word)
188 bits_per_word = t->bits_per_word;
189
190 if (t->speed_hz)
191 speed = min(t->speed_hz, spi->max_speed_hz);
192 }
193
194 if (!speed || (speed > spi->max_speed_hz)) {
195 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
196 return -EINVAL;
197 }
198
199 /* Write new configuration */
200 out_8(&hw->regs->mode, cs->mode);
201
202 /* Set the clock */
203 /* opb_freq was already divided by 4 */
204 scr = (hw->opb_freq / speed) - 1;
205 if (scr > 0)
206 cdm = min(scr, 0xff);
207
208 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
209
210 if (in_8(&hw->regs->cdm) != cdm)
211 out_8(&hw->regs->cdm, cdm);
212
213 mutex_lock(&hw->bitbang.lock);
214 if (!hw->bitbang.busy) {
215 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
216 /* Need to ndelay here? */
217 }
218 mutex_unlock(&hw->bitbang.lock);
219
220 return 0;
221}
222
223static int spi_ppc4xx_setup(struct spi_device *spi)
224{
225 struct spi_ppc4xx_cs *cs = spi->controller_state;
226
227 if (!spi->max_speed_hz) {
228 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
229 return -EINVAL;
230 }
231
232 if (cs == NULL) {
233 cs = kzalloc(sizeof *cs, GFP_KERNEL);
234 if (!cs)
235 return -ENOMEM;
236 spi->controller_state = cs;
237 }
238
239 /*
240 * We set all bits of the SPI0_MODE register, so,
241 * no need to read-modify-write
242 */
243 cs->mode = SPI_PPC4XX_MODE_SPE;
244
245 switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
246 case SPI_MODE_0:
247 cs->mode |= SPI_CLK_MODE0;
248 break;
249 case SPI_MODE_1:
250 cs->mode |= SPI_CLK_MODE1;
251 break;
252 case SPI_MODE_2:
253 cs->mode |= SPI_CLK_MODE2;
254 break;
255 case SPI_MODE_3:
256 cs->mode |= SPI_CLK_MODE3;
257 break;
258 }
259
260 if (spi->mode & SPI_LSB_FIRST)
261 cs->mode |= SPI_PPC4XX_MODE_RD;
262
263 return 0;
264}
265
266static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
267{
268 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
269 unsigned int cs = spi->chip_select;
270 unsigned int cspol;
271
272 /*
273 * If there are no chip selects at all, or if this is the special
274 * case of a non-existent (dummy) chip select, do nothing.
275 */
276
277 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
278 return;
279
280 cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
281 if (value == BITBANG_CS_INACTIVE)
282 cspol = !cspol;
283
284 gpio_set_value(hw->gpios[cs], cspol);
285}
286
287static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
288{
289 struct ppc4xx_spi *hw;
290 u8 status;
291 u8 data;
292 unsigned int count;
293
294 hw = (struct ppc4xx_spi *)dev_id;
295
296 status = in_8(&hw->regs->sr);
297 if (!status)
298 return IRQ_NONE;
299
300 /*
301 * BSY de-asserts one cycle after the transfer is complete. The
302 * interrupt is asserted after the transfer is complete. The exact
303 * relationship is not documented, hence this code.
304 */
305
306 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
307 u8 lstatus;
308 int cnt = 0;
309
310 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
311 do {
312 ndelay(10);
313 lstatus = in_8(&hw->regs->sr);
314 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
315
316 if (cnt >= 100) {
317 dev_err(hw->dev, "busywait: too many loops!\n");
318 complete(&hw->done);
319 return IRQ_HANDLED;
320 } else {
321 /* status is always 1 (RBR) here */
322 status = in_8(&hw->regs->sr);
323 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
324 }
325 }
326
327 count = hw->count;
328 hw->count++;
329
330 /* RBR triggered this interrupt. Therefore, data must be ready. */
331 data = in_8(&hw->regs->rxd);
332 if (hw->rx)
333 hw->rx[count] = data;
334
335 count++;
336
337 if (count < hw->len) {
338 data = hw->tx ? hw->tx[count] : 0;
339 out_8(&hw->regs->txd, data);
340 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
341 } else {
342 complete(&hw->done);
343 }
344
345 return IRQ_HANDLED;
346}
347
348static void spi_ppc4xx_cleanup(struct spi_device *spi)
349{
350 kfree(spi->controller_state);
351}
352
353static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
354{
355 /*
356 * On all 4xx PPC's the SPI bus is shared/multiplexed with
357 * the 2nd I2C bus. We need to enable the the SPI bus before
358 * using it.
359 */
360
361 /* need to clear bit 14 to enable SPC */
362 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
363}
364
365static void free_gpios(struct ppc4xx_spi *hw)
366{
367 if (hw->master->num_chipselect) {
368 int i;
369 for (i = 0; i < hw->master->num_chipselect; i++)
370 if (gpio_is_valid(hw->gpios[i]))
371 gpio_free(hw->gpios[i]);
372
373 kfree(hw->gpios);
374 hw->gpios = NULL;
375 }
376}
377
378/*
379 * platform_device layer stuff...
380 */
381static int spi_ppc4xx_of_probe(struct platform_device *op)
382{
383 struct ppc4xx_spi *hw;
384 struct spi_master *master;
385 struct spi_bitbang *bbp;
386 struct resource resource;
387 struct device_node *np = op->dev.of_node;
388 struct device *dev = &op->dev;
389 struct device_node *opbnp;
390 int ret;
391 int num_gpios;
392 const unsigned int *clk;
393
394 master = spi_alloc_master(dev, sizeof *hw);
395 if (master == NULL)
396 return -ENOMEM;
397 master->dev.of_node = np;
398 platform_set_drvdata(op, master);
399 hw = spi_master_get_devdata(master);
400 hw->master = master;
401 hw->dev = dev;
402
403 init_completion(&hw->done);
404
405 /*
406 * A count of zero implies a single SPI device without any chip-select.
407 * Note that of_gpio_count counts all gpios assigned to this spi master.
408 * This includes both "null" gpio's and real ones.
409 */
410 num_gpios = of_gpio_count(np);
411 if (num_gpios > 0) {
412 int i;
413
414 hw->gpios = kcalloc(num_gpios, sizeof(*hw->gpios), GFP_KERNEL);
415 if (!hw->gpios) {
416 ret = -ENOMEM;
417 goto free_master;
418 }
419
420 for (i = 0; i < num_gpios; i++) {
421 int gpio;
422 enum of_gpio_flags flags;
423
424 gpio = of_get_gpio_flags(np, i, &flags);
425 hw->gpios[i] = gpio;
426
427 if (gpio_is_valid(gpio)) {
428 /* Real CS - set the initial state. */
429 ret = gpio_request(gpio, np->name);
430 if (ret < 0) {
431 dev_err(dev,
432 "can't request gpio #%d: %d\n",
433 i, ret);
434 goto free_gpios;
435 }
436
437 gpio_direction_output(gpio,
438 !!(flags & OF_GPIO_ACTIVE_LOW));
439 } else if (gpio == -EEXIST) {
440 ; /* No CS, but that's OK. */
441 } else {
442 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
443 ret = -EINVAL;
444 goto free_gpios;
445 }
446 }
447 }
448
449 /* Setup the state for the bitbang driver */
450 bbp = &hw->bitbang;
451 bbp->master = hw->master;
452 bbp->setup_transfer = spi_ppc4xx_setupxfer;
453 bbp->chipselect = spi_ppc4xx_chipsel;
454 bbp->txrx_bufs = spi_ppc4xx_txrx;
455 bbp->use_dma = 0;
456 bbp->master->setup = spi_ppc4xx_setup;
457 bbp->master->cleanup = spi_ppc4xx_cleanup;
458 bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
459
460 /* the spi->mode bits understood by this driver: */
461 bbp->master->mode_bits =
462 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
463
464 /* this many pins in all GPIO controllers */
465 bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0;
466
467 /* Get the clock for the OPB */
468 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
469 if (opbnp == NULL) {
470 dev_err(dev, "OPB: cannot find node\n");
471 ret = -ENODEV;
472 goto free_gpios;
473 }
474 /* Get the clock (Hz) for the OPB */
475 clk = of_get_property(opbnp, "clock-frequency", NULL);
476 if (clk == NULL) {
477 dev_err(dev, "OPB: no clock-frequency property set\n");
478 of_node_put(opbnp);
479 ret = -ENODEV;
480 goto free_gpios;
481 }
482 hw->opb_freq = *clk;
483 hw->opb_freq >>= 2;
484 of_node_put(opbnp);
485
486 ret = of_address_to_resource(np, 0, &resource);
487 if (ret) {
488 dev_err(dev, "error while parsing device node resource\n");
489 goto free_gpios;
490 }
491 hw->mapbase = resource.start;
492 hw->mapsize = resource_size(&resource);
493
494 /* Sanity check */
495 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
496 dev_err(dev, "too small to map registers\n");
497 ret = -EINVAL;
498 goto free_gpios;
499 }
500
501 /* Request IRQ */
502 hw->irqnum = irq_of_parse_and_map(np, 0);
503 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
504 0, "spi_ppc4xx_of", (void *)hw);
505 if (ret) {
506 dev_err(dev, "unable to allocate interrupt\n");
507 goto free_gpios;
508 }
509
510 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
511 dev_err(dev, "resource unavailable\n");
512 ret = -EBUSY;
513 goto request_mem_error;
514 }
515
516 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
517
518 if (!hw->regs) {
519 dev_err(dev, "unable to memory map registers\n");
520 ret = -ENXIO;
521 goto map_io_error;
522 }
523
524 spi_ppc4xx_enable(hw);
525
526 /* Finally register our spi controller */
527 dev->dma_mask = 0;
528 ret = spi_bitbang_start(bbp);
529 if (ret) {
530 dev_err(dev, "failed to register SPI master\n");
531 goto unmap_regs;
532 }
533
534 dev_info(dev, "driver initialized\n");
535
536 return 0;
537
538unmap_regs:
539 iounmap(hw->regs);
540map_io_error:
541 release_mem_region(hw->mapbase, hw->mapsize);
542request_mem_error:
543 free_irq(hw->irqnum, hw);
544free_gpios:
545 free_gpios(hw);
546free_master:
547 spi_master_put(master);
548
549 dev_err(dev, "initialization failed\n");
550 return ret;
551}
552
553static int spi_ppc4xx_of_remove(struct platform_device *op)
554{
555 struct spi_master *master = platform_get_drvdata(op);
556 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
557
558 spi_bitbang_stop(&hw->bitbang);
559 release_mem_region(hw->mapbase, hw->mapsize);
560 free_irq(hw->irqnum, hw);
561 iounmap(hw->regs);
562 free_gpios(hw);
563 spi_master_put(master);
564 return 0;
565}
566
567static const struct of_device_id spi_ppc4xx_of_match[] = {
568 { .compatible = "ibm,ppc4xx-spi", },
569 {},
570};
571
572MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
573
574static struct platform_driver spi_ppc4xx_of_driver = {
575 .probe = spi_ppc4xx_of_probe,
576 .remove = spi_ppc4xx_of_remove,
577 .driver = {
578 .name = DRIVER_NAME,
579 .of_match_table = spi_ppc4xx_of_match,
580 },
581};
582module_platform_driver(spi_ppc4xx_of_driver);
583
584MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
585MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
586MODULE_LICENSE("GPL");