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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Freescale MXS SPI host driver
4//
5// Copyright 2012 DENX Software Engineering, GmbH.
6// Copyright 2012 Freescale Semiconductor, Inc.
7// Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8//
9// Rework and transition to new API by:
10// Marek Vasut <marex@denx.de>
11//
12// Based on previous attempt by:
13// Fabio Estevam <fabio.estevam@freescale.com>
14//
15// Based on code from U-Boot bootloader by:
16// Marek Vasut <marex@denx.de>
17//
18// Based on spi-stmp.c, which is:
19// Author: Dmitry Pervushin <dimka@embeddedalley.com>
20
21#include <linux/kernel.h>
22#include <linux/ioport.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/interrupt.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmaengine.h>
30#include <linux/highmem.h>
31#include <linux/clk.h>
32#include <linux/err.h>
33#include <linux/completion.h>
34#include <linux/pinctrl/consumer.h>
35#include <linux/regulator/consumer.h>
36#include <linux/pm_runtime.h>
37#include <linux/module.h>
38#include <linux/stmp_device.h>
39#include <linux/spi/spi.h>
40#include <linux/spi/mxs-spi.h>
41#include <trace/events/spi.h>
42#include <linux/dma/mxs-dma.h>
43
44#define DRIVER_NAME "mxs-spi"
45
46/* Use 10S timeout for very long transfers, it should suffice. */
47#define SSP_TIMEOUT 10000
48
49#define SG_MAXLEN 0xff00
50
51/*
52 * Flags for txrx functions. More efficient that using an argument register for
53 * each one.
54 */
55#define TXRX_WRITE (1<<0) /* This is a write */
56#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
57
58struct mxs_spi {
59 struct mxs_ssp ssp;
60 struct completion c;
61 unsigned int sck; /* Rate requested (vs actual) */
62};
63
64static int mxs_spi_setup_transfer(struct spi_device *dev,
65 const struct spi_transfer *t)
66{
67 struct mxs_spi *spi = spi_controller_get_devdata(dev->controller);
68 struct mxs_ssp *ssp = &spi->ssp;
69 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
70
71 if (hz == 0) {
72 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
73 return -EINVAL;
74 }
75
76 if (hz != spi->sck) {
77 mxs_ssp_set_clk_rate(ssp, hz);
78 /*
79 * Save requested rate, hz, rather than the actual rate,
80 * ssp->clk_rate. Otherwise we would set the rate every transfer
81 * when the actual rate is not quite the same as requested rate.
82 */
83 spi->sck = hz;
84 /*
85 * Perhaps we should return an error if the actual clock is
86 * nowhere close to what was requested?
87 */
88 }
89
90 writel(BM_SSP_CTRL0_LOCK_CS,
91 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
92
93 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
94 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
95 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
96 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
97 ssp->base + HW_SSP_CTRL1(ssp));
98
99 writel(0x0, ssp->base + HW_SSP_CMD0);
100 writel(0x0, ssp->base + HW_SSP_CMD1);
101
102 return 0;
103}
104
105static u32 mxs_spi_cs_to_reg(unsigned cs)
106{
107 u32 select = 0;
108
109 /*
110 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
111 *
112 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
113 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
114 * the datasheet for further details. In SPI mode, they are used to
115 * toggle the chip-select lines (nCS pins).
116 */
117 if (cs & 1)
118 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
119 if (cs & 2)
120 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
121
122 return select;
123}
124
125static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
126{
127 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
128 struct mxs_ssp *ssp = &spi->ssp;
129 u32 reg;
130
131 do {
132 reg = readl_relaxed(ssp->base + offset);
133
134 if (!set)
135 reg = ~reg;
136
137 reg &= mask;
138
139 if (reg == mask)
140 return 0;
141 } while (time_before(jiffies, timeout));
142
143 return -ETIMEDOUT;
144}
145
146static void mxs_ssp_dma_irq_callback(void *param)
147{
148 struct mxs_spi *spi = param;
149
150 complete(&spi->c);
151}
152
153static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
154{
155 struct mxs_ssp *ssp = dev_id;
156
157 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
158 __func__, __LINE__,
159 readl(ssp->base + HW_SSP_CTRL1(ssp)),
160 readl(ssp->base + HW_SSP_STATUS(ssp)));
161 return IRQ_HANDLED;
162}
163
164static int mxs_spi_txrx_dma(struct mxs_spi *spi,
165 unsigned char *buf, int len,
166 unsigned int flags)
167{
168 struct mxs_ssp *ssp = &spi->ssp;
169 struct dma_async_tx_descriptor *desc = NULL;
170 const bool vmalloced_buf = is_vmalloc_addr(buf);
171 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
172 const int sgs = DIV_ROUND_UP(len, desc_len);
173 int sg_count;
174 int min, ret;
175 u32 ctrl0;
176 struct page *vm_page;
177 struct {
178 u32 pio[4];
179 struct scatterlist sg;
180 } *dma_xfer;
181
182 if (!len)
183 return -EINVAL;
184
185 dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
186 if (!dma_xfer)
187 return -ENOMEM;
188
189 reinit_completion(&spi->c);
190
191 /* Chip select was already programmed into CTRL0 */
192 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
193 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
194 BM_SSP_CTRL0_READ);
195 ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
196
197 if (!(flags & TXRX_WRITE))
198 ctrl0 |= BM_SSP_CTRL0_READ;
199
200 /* Queue the DMA data transfer. */
201 for (sg_count = 0; sg_count < sgs; sg_count++) {
202 /* Prepare the transfer descriptor. */
203 min = min(len, desc_len);
204
205 /*
206 * De-assert CS on last segment if flag is set (i.e., no more
207 * transfers will follow)
208 */
209 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
210 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
211
212 if (ssp->devid == IMX23_SSP) {
213 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
214 ctrl0 |= min;
215 }
216
217 dma_xfer[sg_count].pio[0] = ctrl0;
218 dma_xfer[sg_count].pio[3] = min;
219
220 if (vmalloced_buf) {
221 vm_page = vmalloc_to_page(buf);
222 if (!vm_page) {
223 ret = -ENOMEM;
224 goto err_vmalloc;
225 }
226
227 sg_init_table(&dma_xfer[sg_count].sg, 1);
228 sg_set_page(&dma_xfer[sg_count].sg, vm_page,
229 min, offset_in_page(buf));
230 } else {
231 sg_init_one(&dma_xfer[sg_count].sg, buf, min);
232 }
233
234 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
235 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
236
237 len -= min;
238 buf += min;
239
240 /* Queue the PIO register write transfer. */
241 desc = dmaengine_prep_slave_sg(ssp->dmach,
242 (struct scatterlist *)dma_xfer[sg_count].pio,
243 (ssp->devid == IMX23_SSP) ? 1 : 4,
244 DMA_TRANS_NONE,
245 sg_count ? DMA_PREP_INTERRUPT : 0);
246 if (!desc) {
247 dev_err(ssp->dev,
248 "Failed to get PIO reg. write descriptor.\n");
249 ret = -EINVAL;
250 goto err_mapped;
251 }
252
253 desc = dmaengine_prep_slave_sg(ssp->dmach,
254 &dma_xfer[sg_count].sg, 1,
255 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
256 DMA_PREP_INTERRUPT | MXS_DMA_CTRL_WAIT4END);
257
258 if (!desc) {
259 dev_err(ssp->dev,
260 "Failed to get DMA data write descriptor.\n");
261 ret = -EINVAL;
262 goto err_mapped;
263 }
264 }
265
266 /*
267 * The last descriptor must have this callback,
268 * to finish the DMA transaction.
269 */
270 desc->callback = mxs_ssp_dma_irq_callback;
271 desc->callback_param = spi;
272
273 /* Start the transfer. */
274 dmaengine_submit(desc);
275 dma_async_issue_pending(ssp->dmach);
276
277 if (!wait_for_completion_timeout(&spi->c,
278 msecs_to_jiffies(SSP_TIMEOUT))) {
279 dev_err(ssp->dev, "DMA transfer timeout\n");
280 ret = -ETIMEDOUT;
281 dmaengine_terminate_all(ssp->dmach);
282 goto err_vmalloc;
283 }
284
285 ret = 0;
286
287err_vmalloc:
288 while (--sg_count >= 0) {
289err_mapped:
290 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
291 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
292 }
293
294 kfree(dma_xfer);
295
296 return ret;
297}
298
299static int mxs_spi_txrx_pio(struct mxs_spi *spi,
300 unsigned char *buf, int len,
301 unsigned int flags)
302{
303 struct mxs_ssp *ssp = &spi->ssp;
304
305 writel(BM_SSP_CTRL0_IGNORE_CRC,
306 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
307
308 while (len--) {
309 if (len == 0 && (flags & TXRX_DEASSERT_CS))
310 writel(BM_SSP_CTRL0_IGNORE_CRC,
311 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
312
313 if (ssp->devid == IMX23_SSP) {
314 writel(BM_SSP_CTRL0_XFER_COUNT,
315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
316 writel(1,
317 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
318 } else {
319 writel(1, ssp->base + HW_SSP_XFER_SIZE);
320 }
321
322 if (flags & TXRX_WRITE)
323 writel(BM_SSP_CTRL0_READ,
324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
325 else
326 writel(BM_SSP_CTRL0_READ,
327 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
328
329 writel(BM_SSP_CTRL0_RUN,
330 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
331
332 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
333 return -ETIMEDOUT;
334
335 if (flags & TXRX_WRITE)
336 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
337
338 writel(BM_SSP_CTRL0_DATA_XFER,
339 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
340
341 if (!(flags & TXRX_WRITE)) {
342 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
343 BM_SSP_STATUS_FIFO_EMPTY, 0))
344 return -ETIMEDOUT;
345
346 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
347 }
348
349 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
350 return -ETIMEDOUT;
351
352 buf++;
353 }
354
355 if (len <= 0)
356 return 0;
357
358 return -ETIMEDOUT;
359}
360
361static int mxs_spi_transfer_one(struct spi_controller *host,
362 struct spi_message *m)
363{
364 struct mxs_spi *spi = spi_controller_get_devdata(host);
365 struct mxs_ssp *ssp = &spi->ssp;
366 struct spi_transfer *t;
367 unsigned int flag;
368 int status = 0;
369
370 /* Program CS register bits here, it will be used for all transfers. */
371 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
372 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
373 writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
374 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
375
376 list_for_each_entry(t, &m->transfers, transfer_list) {
377
378 trace_spi_transfer_start(m, t);
379
380 status = mxs_spi_setup_transfer(m->spi, t);
381 if (status)
382 break;
383
384 /* De-assert on last transfer, inverted by cs_change flag */
385 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
386 TXRX_DEASSERT_CS : 0;
387
388 /*
389 * Small blocks can be transfered via PIO.
390 * Measured by empiric means:
391 *
392 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
393 *
394 * DMA only: 2.164808 seconds, 473.0KB/s
395 * Combined: 1.676276 seconds, 610.9KB/s
396 */
397 if (t->len < 32) {
398 writel(BM_SSP_CTRL1_DMA_ENABLE,
399 ssp->base + HW_SSP_CTRL1(ssp) +
400 STMP_OFFSET_REG_CLR);
401
402 if (t->tx_buf)
403 status = mxs_spi_txrx_pio(spi,
404 (void *)t->tx_buf,
405 t->len, flag | TXRX_WRITE);
406 if (t->rx_buf)
407 status = mxs_spi_txrx_pio(spi,
408 t->rx_buf, t->len,
409 flag);
410 } else {
411 writel(BM_SSP_CTRL1_DMA_ENABLE,
412 ssp->base + HW_SSP_CTRL1(ssp) +
413 STMP_OFFSET_REG_SET);
414
415 if (t->tx_buf)
416 status = mxs_spi_txrx_dma(spi,
417 (void *)t->tx_buf, t->len,
418 flag | TXRX_WRITE);
419 if (t->rx_buf)
420 status = mxs_spi_txrx_dma(spi,
421 t->rx_buf, t->len,
422 flag);
423 }
424
425 trace_spi_transfer_stop(m, t);
426
427 if (status) {
428 stmp_reset_block(ssp->base);
429 break;
430 }
431
432 m->actual_length += t->len;
433 }
434
435 m->status = status;
436 spi_finalize_current_message(host);
437
438 return status;
439}
440
441static int mxs_spi_runtime_suspend(struct device *dev)
442{
443 struct spi_controller *host = dev_get_drvdata(dev);
444 struct mxs_spi *spi = spi_controller_get_devdata(host);
445 struct mxs_ssp *ssp = &spi->ssp;
446 int ret;
447
448 clk_disable_unprepare(ssp->clk);
449
450 ret = pinctrl_pm_select_idle_state(dev);
451 if (ret) {
452 int ret2 = clk_prepare_enable(ssp->clk);
453
454 if (ret2)
455 dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
456 ret, ret2);
457 }
458
459 return ret;
460}
461
462static int mxs_spi_runtime_resume(struct device *dev)
463{
464 struct spi_controller *host = dev_get_drvdata(dev);
465 struct mxs_spi *spi = spi_controller_get_devdata(host);
466 struct mxs_ssp *ssp = &spi->ssp;
467 int ret;
468
469 ret = pinctrl_pm_select_default_state(dev);
470 if (ret)
471 return ret;
472
473 ret = clk_prepare_enable(ssp->clk);
474 if (ret)
475 pinctrl_pm_select_idle_state(dev);
476
477 return ret;
478}
479
480static int mxs_spi_suspend(struct device *dev)
481{
482 struct spi_controller *host = dev_get_drvdata(dev);
483 int ret;
484
485 ret = spi_controller_suspend(host);
486 if (ret)
487 return ret;
488
489 if (!pm_runtime_suspended(dev))
490 return mxs_spi_runtime_suspend(dev);
491 else
492 return 0;
493}
494
495static int mxs_spi_resume(struct device *dev)
496{
497 struct spi_controller *host = dev_get_drvdata(dev);
498 int ret;
499
500 if (!pm_runtime_suspended(dev))
501 ret = mxs_spi_runtime_resume(dev);
502 else
503 ret = 0;
504 if (ret)
505 return ret;
506
507 ret = spi_controller_resume(host);
508 if (ret < 0 && !pm_runtime_suspended(dev))
509 mxs_spi_runtime_suspend(dev);
510
511 return ret;
512}
513
514static const struct dev_pm_ops mxs_spi_pm = {
515 RUNTIME_PM_OPS(mxs_spi_runtime_suspend, mxs_spi_runtime_resume, NULL)
516 SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
517};
518
519static const struct of_device_id mxs_spi_dt_ids[] = {
520 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
521 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
522 { /* sentinel */ }
523};
524MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
525
526static int mxs_spi_probe(struct platform_device *pdev)
527{
528 const struct of_device_id *of_id =
529 of_match_device(mxs_spi_dt_ids, &pdev->dev);
530 struct device_node *np = pdev->dev.of_node;
531 struct spi_controller *host;
532 struct mxs_spi *spi;
533 struct mxs_ssp *ssp;
534 struct clk *clk;
535 void __iomem *base;
536 int devid, clk_freq;
537 int ret = 0, irq_err;
538
539 /*
540 * Default clock speed for the SPI core. 160MHz seems to
541 * work reasonably well with most SPI flashes, so use this
542 * as a default. Override with "clock-frequency" DT prop.
543 */
544 const int clk_freq_default = 160000000;
545
546 irq_err = platform_get_irq(pdev, 0);
547 if (irq_err < 0)
548 return irq_err;
549
550 base = devm_platform_ioremap_resource(pdev, 0);
551 if (IS_ERR(base))
552 return PTR_ERR(base);
553
554 clk = devm_clk_get(&pdev->dev, NULL);
555 if (IS_ERR(clk))
556 return PTR_ERR(clk);
557
558 devid = (enum mxs_ssp_id) of_id->data;
559 ret = of_property_read_u32(np, "clock-frequency",
560 &clk_freq);
561 if (ret)
562 clk_freq = clk_freq_default;
563
564 host = spi_alloc_host(&pdev->dev, sizeof(*spi));
565 if (!host)
566 return -ENOMEM;
567
568 platform_set_drvdata(pdev, host);
569
570 host->transfer_one_message = mxs_spi_transfer_one;
571 host->bits_per_word_mask = SPI_BPW_MASK(8);
572 host->mode_bits = SPI_CPOL | SPI_CPHA;
573 host->num_chipselect = 3;
574 host->dev.of_node = np;
575 host->flags = SPI_CONTROLLER_HALF_DUPLEX;
576 host->auto_runtime_pm = true;
577
578 spi = spi_controller_get_devdata(host);
579 ssp = &spi->ssp;
580 ssp->dev = &pdev->dev;
581 ssp->clk = clk;
582 ssp->base = base;
583 ssp->devid = devid;
584
585 init_completion(&spi->c);
586
587 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
588 dev_name(&pdev->dev), ssp);
589 if (ret)
590 goto out_host_free;
591
592 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
593 if (IS_ERR(ssp->dmach)) {
594 dev_err(ssp->dev, "Failed to request DMA\n");
595 ret = PTR_ERR(ssp->dmach);
596 goto out_host_free;
597 }
598
599 pm_runtime_enable(ssp->dev);
600 if (!pm_runtime_enabled(ssp->dev)) {
601 ret = mxs_spi_runtime_resume(ssp->dev);
602 if (ret < 0) {
603 dev_err(ssp->dev, "runtime resume failed\n");
604 goto out_dma_release;
605 }
606 }
607
608 ret = pm_runtime_resume_and_get(ssp->dev);
609 if (ret < 0) {
610 dev_err(ssp->dev, "runtime_get_sync failed\n");
611 goto out_pm_runtime_disable;
612 }
613
614 clk_set_rate(ssp->clk, clk_freq);
615
616 ret = stmp_reset_block(ssp->base);
617 if (ret)
618 goto out_pm_runtime_put;
619
620 ret = devm_spi_register_controller(&pdev->dev, host);
621 if (ret) {
622 dev_err(&pdev->dev, "Cannot register SPI host, %d\n", ret);
623 goto out_pm_runtime_put;
624 }
625
626 pm_runtime_put(ssp->dev);
627
628 return 0;
629
630out_pm_runtime_put:
631 pm_runtime_put(ssp->dev);
632out_pm_runtime_disable:
633 pm_runtime_disable(ssp->dev);
634out_dma_release:
635 dma_release_channel(ssp->dmach);
636out_host_free:
637 spi_controller_put(host);
638 return ret;
639}
640
641static void mxs_spi_remove(struct platform_device *pdev)
642{
643 struct spi_controller *host;
644 struct mxs_spi *spi;
645 struct mxs_ssp *ssp;
646
647 host = platform_get_drvdata(pdev);
648 spi = spi_controller_get_devdata(host);
649 ssp = &spi->ssp;
650
651 pm_runtime_disable(&pdev->dev);
652 if (!pm_runtime_status_suspended(&pdev->dev))
653 mxs_spi_runtime_suspend(&pdev->dev);
654
655 dma_release_channel(ssp->dmach);
656}
657
658static struct platform_driver mxs_spi_driver = {
659 .probe = mxs_spi_probe,
660 .remove = mxs_spi_remove,
661 .driver = {
662 .name = DRIVER_NAME,
663 .of_match_table = mxs_spi_dt_ids,
664 .pm = pm_ptr(&mxs_spi_pm),
665 },
666};
667
668module_platform_driver(mxs_spi_driver);
669
670MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
671MODULE_DESCRIPTION("MXS SPI host driver");
672MODULE_LICENSE("GPL");
673MODULE_ALIAS("platform:mxs-spi");
1/*
2 * Freescale MXS SPI master driver
3 *
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7 *
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
10 *
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
13 *
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
16 *
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 */
30
31#include <linux/kernel.h>
32#include <linux/ioport.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/of_gpio.h>
36#include <linux/platform_device.h>
37#include <linux/delay.h>
38#include <linux/interrupt.h>
39#include <linux/dma-mapping.h>
40#include <linux/dmaengine.h>
41#include <linux/highmem.h>
42#include <linux/clk.h>
43#include <linux/err.h>
44#include <linux/completion.h>
45#include <linux/gpio.h>
46#include <linux/regulator/consumer.h>
47#include <linux/pm_runtime.h>
48#include <linux/module.h>
49#include <linux/stmp_device.h>
50#include <linux/spi/spi.h>
51#include <linux/spi/mxs-spi.h>
52
53#define DRIVER_NAME "mxs-spi"
54
55/* Use 10S timeout for very long transfers, it should suffice. */
56#define SSP_TIMEOUT 10000
57
58#define SG_MAXLEN 0xff00
59
60/*
61 * Flags for txrx functions. More efficient that using an argument register for
62 * each one.
63 */
64#define TXRX_WRITE (1<<0) /* This is a write */
65#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
66
67struct mxs_spi {
68 struct mxs_ssp ssp;
69 struct completion c;
70 unsigned int sck; /* Rate requested (vs actual) */
71};
72
73static int mxs_spi_setup_transfer(struct spi_device *dev,
74 const struct spi_transfer *t)
75{
76 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
77 struct mxs_ssp *ssp = &spi->ssp;
78 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
79
80 if (hz == 0) {
81 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
82 return -EINVAL;
83 }
84
85 if (hz != spi->sck) {
86 mxs_ssp_set_clk_rate(ssp, hz);
87 /*
88 * Save requested rate, hz, rather than the actual rate,
89 * ssp->clk_rate. Otherwise we would set the rate every transfer
90 * when the actual rate is not quite the same as requested rate.
91 */
92 spi->sck = hz;
93 /*
94 * Perhaps we should return an error if the actual clock is
95 * nowhere close to what was requested?
96 */
97 }
98
99 writel(BM_SSP_CTRL0_LOCK_CS,
100 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
101
102 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
103 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
104 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
105 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
106 ssp->base + HW_SSP_CTRL1(ssp));
107
108 writel(0x0, ssp->base + HW_SSP_CMD0);
109 writel(0x0, ssp->base + HW_SSP_CMD1);
110
111 return 0;
112}
113
114static u32 mxs_spi_cs_to_reg(unsigned cs)
115{
116 u32 select = 0;
117
118 /*
119 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
120 *
121 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
122 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
123 * the datasheet for further details. In SPI mode, they are used to
124 * toggle the chip-select lines (nCS pins).
125 */
126 if (cs & 1)
127 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
128 if (cs & 2)
129 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
130
131 return select;
132}
133
134static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
135{
136 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
137 struct mxs_ssp *ssp = &spi->ssp;
138 u32 reg;
139
140 do {
141 reg = readl_relaxed(ssp->base + offset);
142
143 if (!set)
144 reg = ~reg;
145
146 reg &= mask;
147
148 if (reg == mask)
149 return 0;
150 } while (time_before(jiffies, timeout));
151
152 return -ETIMEDOUT;
153}
154
155static void mxs_ssp_dma_irq_callback(void *param)
156{
157 struct mxs_spi *spi = param;
158
159 complete(&spi->c);
160}
161
162static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
163{
164 struct mxs_ssp *ssp = dev_id;
165
166 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
167 __func__, __LINE__,
168 readl(ssp->base + HW_SSP_CTRL1(ssp)),
169 readl(ssp->base + HW_SSP_STATUS(ssp)));
170 return IRQ_HANDLED;
171}
172
173static int mxs_spi_txrx_dma(struct mxs_spi *spi,
174 unsigned char *buf, int len,
175 unsigned int flags)
176{
177 struct mxs_ssp *ssp = &spi->ssp;
178 struct dma_async_tx_descriptor *desc = NULL;
179 const bool vmalloced_buf = is_vmalloc_addr(buf);
180 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
181 const int sgs = DIV_ROUND_UP(len, desc_len);
182 int sg_count;
183 int min, ret;
184 u32 ctrl0;
185 struct page *vm_page;
186 struct {
187 u32 pio[4];
188 struct scatterlist sg;
189 } *dma_xfer;
190
191 if (!len)
192 return -EINVAL;
193
194 dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
195 if (!dma_xfer)
196 return -ENOMEM;
197
198 reinit_completion(&spi->c);
199
200 /* Chip select was already programmed into CTRL0 */
201 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
202 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
203 BM_SSP_CTRL0_READ);
204 ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
205
206 if (!(flags & TXRX_WRITE))
207 ctrl0 |= BM_SSP_CTRL0_READ;
208
209 /* Queue the DMA data transfer. */
210 for (sg_count = 0; sg_count < sgs; sg_count++) {
211 /* Prepare the transfer descriptor. */
212 min = min(len, desc_len);
213
214 /*
215 * De-assert CS on last segment if flag is set (i.e., no more
216 * transfers will follow)
217 */
218 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
219 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
220
221 if (ssp->devid == IMX23_SSP) {
222 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
223 ctrl0 |= min;
224 }
225
226 dma_xfer[sg_count].pio[0] = ctrl0;
227 dma_xfer[sg_count].pio[3] = min;
228
229 if (vmalloced_buf) {
230 vm_page = vmalloc_to_page(buf);
231 if (!vm_page) {
232 ret = -ENOMEM;
233 goto err_vmalloc;
234 }
235
236 sg_init_table(&dma_xfer[sg_count].sg, 1);
237 sg_set_page(&dma_xfer[sg_count].sg, vm_page,
238 min, offset_in_page(buf));
239 } else {
240 sg_init_one(&dma_xfer[sg_count].sg, buf, min);
241 }
242
243 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
244 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
245
246 len -= min;
247 buf += min;
248
249 /* Queue the PIO register write transfer. */
250 desc = dmaengine_prep_slave_sg(ssp->dmach,
251 (struct scatterlist *)dma_xfer[sg_count].pio,
252 (ssp->devid == IMX23_SSP) ? 1 : 4,
253 DMA_TRANS_NONE,
254 sg_count ? DMA_PREP_INTERRUPT : 0);
255 if (!desc) {
256 dev_err(ssp->dev,
257 "Failed to get PIO reg. write descriptor.\n");
258 ret = -EINVAL;
259 goto err_mapped;
260 }
261
262 desc = dmaengine_prep_slave_sg(ssp->dmach,
263 &dma_xfer[sg_count].sg, 1,
264 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
265 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
266
267 if (!desc) {
268 dev_err(ssp->dev,
269 "Failed to get DMA data write descriptor.\n");
270 ret = -EINVAL;
271 goto err_mapped;
272 }
273 }
274
275 /*
276 * The last descriptor must have this callback,
277 * to finish the DMA transaction.
278 */
279 desc->callback = mxs_ssp_dma_irq_callback;
280 desc->callback_param = spi;
281
282 /* Start the transfer. */
283 dmaengine_submit(desc);
284 dma_async_issue_pending(ssp->dmach);
285
286 if (!wait_for_completion_timeout(&spi->c,
287 msecs_to_jiffies(SSP_TIMEOUT))) {
288 dev_err(ssp->dev, "DMA transfer timeout\n");
289 ret = -ETIMEDOUT;
290 dmaengine_terminate_all(ssp->dmach);
291 goto err_vmalloc;
292 }
293
294 ret = 0;
295
296err_vmalloc:
297 while (--sg_count >= 0) {
298err_mapped:
299 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
300 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
301 }
302
303 kfree(dma_xfer);
304
305 return ret;
306}
307
308static int mxs_spi_txrx_pio(struct mxs_spi *spi,
309 unsigned char *buf, int len,
310 unsigned int flags)
311{
312 struct mxs_ssp *ssp = &spi->ssp;
313
314 writel(BM_SSP_CTRL0_IGNORE_CRC,
315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
316
317 while (len--) {
318 if (len == 0 && (flags & TXRX_DEASSERT_CS))
319 writel(BM_SSP_CTRL0_IGNORE_CRC,
320 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
321
322 if (ssp->devid == IMX23_SSP) {
323 writel(BM_SSP_CTRL0_XFER_COUNT,
324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
325 writel(1,
326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
327 } else {
328 writel(1, ssp->base + HW_SSP_XFER_SIZE);
329 }
330
331 if (flags & TXRX_WRITE)
332 writel(BM_SSP_CTRL0_READ,
333 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
334 else
335 writel(BM_SSP_CTRL0_READ,
336 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
337
338 writel(BM_SSP_CTRL0_RUN,
339 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
340
341 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
342 return -ETIMEDOUT;
343
344 if (flags & TXRX_WRITE)
345 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
346
347 writel(BM_SSP_CTRL0_DATA_XFER,
348 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
349
350 if (!(flags & TXRX_WRITE)) {
351 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
352 BM_SSP_STATUS_FIFO_EMPTY, 0))
353 return -ETIMEDOUT;
354
355 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
356 }
357
358 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
359 return -ETIMEDOUT;
360
361 buf++;
362 }
363
364 if (len <= 0)
365 return 0;
366
367 return -ETIMEDOUT;
368}
369
370static int mxs_spi_transfer_one(struct spi_master *master,
371 struct spi_message *m)
372{
373 struct mxs_spi *spi = spi_master_get_devdata(master);
374 struct mxs_ssp *ssp = &spi->ssp;
375 struct spi_transfer *t;
376 unsigned int flag;
377 int status = 0;
378
379 /* Program CS register bits here, it will be used for all transfers. */
380 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
381 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
382 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
383 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
384
385 list_for_each_entry(t, &m->transfers, transfer_list) {
386
387 status = mxs_spi_setup_transfer(m->spi, t);
388 if (status)
389 break;
390
391 /* De-assert on last transfer, inverted by cs_change flag */
392 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
393 TXRX_DEASSERT_CS : 0;
394
395 /*
396 * Small blocks can be transfered via PIO.
397 * Measured by empiric means:
398 *
399 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
400 *
401 * DMA only: 2.164808 seconds, 473.0KB/s
402 * Combined: 1.676276 seconds, 610.9KB/s
403 */
404 if (t->len < 32) {
405 writel(BM_SSP_CTRL1_DMA_ENABLE,
406 ssp->base + HW_SSP_CTRL1(ssp) +
407 STMP_OFFSET_REG_CLR);
408
409 if (t->tx_buf)
410 status = mxs_spi_txrx_pio(spi,
411 (void *)t->tx_buf,
412 t->len, flag | TXRX_WRITE);
413 if (t->rx_buf)
414 status = mxs_spi_txrx_pio(spi,
415 t->rx_buf, t->len,
416 flag);
417 } else {
418 writel(BM_SSP_CTRL1_DMA_ENABLE,
419 ssp->base + HW_SSP_CTRL1(ssp) +
420 STMP_OFFSET_REG_SET);
421
422 if (t->tx_buf)
423 status = mxs_spi_txrx_dma(spi,
424 (void *)t->tx_buf, t->len,
425 flag | TXRX_WRITE);
426 if (t->rx_buf)
427 status = mxs_spi_txrx_dma(spi,
428 t->rx_buf, t->len,
429 flag);
430 }
431
432 if (status) {
433 stmp_reset_block(ssp->base);
434 break;
435 }
436
437 m->actual_length += t->len;
438 }
439
440 m->status = status;
441 spi_finalize_current_message(master);
442
443 return status;
444}
445
446static int mxs_spi_runtime_suspend(struct device *dev)
447{
448 struct spi_master *master = dev_get_drvdata(dev);
449 struct mxs_spi *spi = spi_master_get_devdata(master);
450 struct mxs_ssp *ssp = &spi->ssp;
451 int ret;
452
453 clk_disable_unprepare(ssp->clk);
454
455 ret = pinctrl_pm_select_idle_state(dev);
456 if (ret) {
457 int ret2 = clk_prepare_enable(ssp->clk);
458
459 if (ret2)
460 dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
461 ret, ret2);
462 }
463
464 return ret;
465}
466
467static int mxs_spi_runtime_resume(struct device *dev)
468{
469 struct spi_master *master = dev_get_drvdata(dev);
470 struct mxs_spi *spi = spi_master_get_devdata(master);
471 struct mxs_ssp *ssp = &spi->ssp;
472 int ret;
473
474 ret = pinctrl_pm_select_default_state(dev);
475 if (ret)
476 return ret;
477
478 ret = clk_prepare_enable(ssp->clk);
479 if (ret)
480 pinctrl_pm_select_idle_state(dev);
481
482 return ret;
483}
484
485static int __maybe_unused mxs_spi_suspend(struct device *dev)
486{
487 struct spi_master *master = dev_get_drvdata(dev);
488 int ret;
489
490 ret = spi_master_suspend(master);
491 if (ret)
492 return ret;
493
494 if (!pm_runtime_suspended(dev))
495 return mxs_spi_runtime_suspend(dev);
496 else
497 return 0;
498}
499
500static int __maybe_unused mxs_spi_resume(struct device *dev)
501{
502 struct spi_master *master = dev_get_drvdata(dev);
503 int ret;
504
505 if (!pm_runtime_suspended(dev))
506 ret = mxs_spi_runtime_resume(dev);
507 else
508 ret = 0;
509 if (ret)
510 return ret;
511
512 ret = spi_master_resume(master);
513 if (ret < 0 && !pm_runtime_suspended(dev))
514 mxs_spi_runtime_suspend(dev);
515
516 return ret;
517}
518
519static const struct dev_pm_ops mxs_spi_pm = {
520 SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
521 mxs_spi_runtime_resume, NULL)
522 SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
523};
524
525static const struct of_device_id mxs_spi_dt_ids[] = {
526 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
527 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
528 { /* sentinel */ }
529};
530MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
531
532static int mxs_spi_probe(struct platform_device *pdev)
533{
534 const struct of_device_id *of_id =
535 of_match_device(mxs_spi_dt_ids, &pdev->dev);
536 struct device_node *np = pdev->dev.of_node;
537 struct spi_master *master;
538 struct mxs_spi *spi;
539 struct mxs_ssp *ssp;
540 struct resource *iores;
541 struct clk *clk;
542 void __iomem *base;
543 int devid, clk_freq;
544 int ret = 0, irq_err;
545
546 /*
547 * Default clock speed for the SPI core. 160MHz seems to
548 * work reasonably well with most SPI flashes, so use this
549 * as a default. Override with "clock-frequency" DT prop.
550 */
551 const int clk_freq_default = 160000000;
552
553 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
554 irq_err = platform_get_irq(pdev, 0);
555 if (irq_err < 0)
556 return irq_err;
557
558 base = devm_ioremap_resource(&pdev->dev, iores);
559 if (IS_ERR(base))
560 return PTR_ERR(base);
561
562 clk = devm_clk_get(&pdev->dev, NULL);
563 if (IS_ERR(clk))
564 return PTR_ERR(clk);
565
566 devid = (enum mxs_ssp_id) of_id->data;
567 ret = of_property_read_u32(np, "clock-frequency",
568 &clk_freq);
569 if (ret)
570 clk_freq = clk_freq_default;
571
572 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
573 if (!master)
574 return -ENOMEM;
575
576 platform_set_drvdata(pdev, master);
577
578 master->transfer_one_message = mxs_spi_transfer_one;
579 master->bits_per_word_mask = SPI_BPW_MASK(8);
580 master->mode_bits = SPI_CPOL | SPI_CPHA;
581 master->num_chipselect = 3;
582 master->dev.of_node = np;
583 master->flags = SPI_MASTER_HALF_DUPLEX;
584 master->auto_runtime_pm = true;
585
586 spi = spi_master_get_devdata(master);
587 ssp = &spi->ssp;
588 ssp->dev = &pdev->dev;
589 ssp->clk = clk;
590 ssp->base = base;
591 ssp->devid = devid;
592
593 init_completion(&spi->c);
594
595 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
596 dev_name(&pdev->dev), ssp);
597 if (ret)
598 goto out_master_free;
599
600 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
601 if (!ssp->dmach) {
602 dev_err(ssp->dev, "Failed to request DMA\n");
603 ret = -ENODEV;
604 goto out_master_free;
605 }
606
607 pm_runtime_enable(ssp->dev);
608 if (!pm_runtime_enabled(ssp->dev)) {
609 ret = mxs_spi_runtime_resume(ssp->dev);
610 if (ret < 0) {
611 dev_err(ssp->dev, "runtime resume failed\n");
612 goto out_dma_release;
613 }
614 }
615
616 ret = pm_runtime_get_sync(ssp->dev);
617 if (ret < 0) {
618 dev_err(ssp->dev, "runtime_get_sync failed\n");
619 goto out_pm_runtime_disable;
620 }
621
622 clk_set_rate(ssp->clk, clk_freq);
623
624 ret = stmp_reset_block(ssp->base);
625 if (ret)
626 goto out_pm_runtime_put;
627
628 ret = devm_spi_register_master(&pdev->dev, master);
629 if (ret) {
630 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
631 goto out_pm_runtime_put;
632 }
633
634 pm_runtime_put(ssp->dev);
635
636 return 0;
637
638out_pm_runtime_put:
639 pm_runtime_put(ssp->dev);
640out_pm_runtime_disable:
641 pm_runtime_disable(ssp->dev);
642out_dma_release:
643 dma_release_channel(ssp->dmach);
644out_master_free:
645 spi_master_put(master);
646 return ret;
647}
648
649static int mxs_spi_remove(struct platform_device *pdev)
650{
651 struct spi_master *master;
652 struct mxs_spi *spi;
653 struct mxs_ssp *ssp;
654
655 master = platform_get_drvdata(pdev);
656 spi = spi_master_get_devdata(master);
657 ssp = &spi->ssp;
658
659 pm_runtime_disable(&pdev->dev);
660 if (!pm_runtime_status_suspended(&pdev->dev))
661 mxs_spi_runtime_suspend(&pdev->dev);
662
663 dma_release_channel(ssp->dmach);
664
665 return 0;
666}
667
668static struct platform_driver mxs_spi_driver = {
669 .probe = mxs_spi_probe,
670 .remove = mxs_spi_remove,
671 .driver = {
672 .name = DRIVER_NAME,
673 .of_match_table = mxs_spi_dt_ids,
674 .pm = &mxs_spi_pm,
675 },
676};
677
678module_platform_driver(mxs_spi_driver);
679
680MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
681MODULE_DESCRIPTION("MXS SPI master driver");
682MODULE_LICENSE("GPL");
683MODULE_ALIAS("platform:mxs-spi");