1/*
  2 * Copyright (C) 2014-2016 Rafał Miłecki <rafal@milecki.pl>
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 */
  8
  9#define pr_fmt(fmt)		KBUILD_MODNAME ": " fmt
 10
 11#include <linux/kernel.h>
 12#include <linux/module.h>
 13#include <linux/slab.h>
 14#include <linux/delay.h>
 15#include <linux/bcma/bcma.h>
 16#include <linux/spi/spi.h>
 17
 18#include "spi-bcm53xx.h"
 19
 20#define BCM53XXSPI_MAX_SPI_BAUD	13500000	/* 216 MHz? */
 21#define BCM53XXSPI_FLASH_WINDOW	SZ_32M
 22
 23/* The longest observed required wait was 19 ms */
 24#define BCM53XXSPI_SPE_TIMEOUT_MS	80
 25
 26struct bcm53xxspi {
 27	struct bcma_device *core;
 28	struct spi_master *master;
 29	void __iomem *mmio_base;
 30	bool bspi;				/* Boot SPI mode with memory mapping */
 31};
 32
 33static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
 34{
 35	return bcma_read32(b53spi->core, offset);
 36}
 37
 38static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
 39				    u32 value)
 40{
 41	bcma_write32(b53spi->core, offset, value);
 42}
 43
 44static void bcm53xxspi_disable_bspi(struct bcm53xxspi *b53spi)
 45{
 46	struct device *dev = &b53spi->core->dev;
 47	unsigned long deadline;
 48	u32 tmp;
 49
 50	if (!b53spi->bspi)
 51		return;
 52
 53	tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
 54	if (tmp & 0x1)
 55		return;
 56
 57	deadline = jiffies + usecs_to_jiffies(200);
 58	do {
 59		tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_BUSY_STATUS);
 60		if (!(tmp & 0x1)) {
 61			bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL,
 62					 0x1);
 63			ndelay(200);
 64			b53spi->bspi = false;
 65			return;
 66		}
 67		udelay(1);
 68	} while (!time_after_eq(jiffies, deadline));
 69
 70	dev_warn(dev, "Timeout disabling BSPI\n");
 71}
 72
 73static void bcm53xxspi_enable_bspi(struct bcm53xxspi *b53spi)
 74{
 75	u32 tmp;
 76
 77	if (b53spi->bspi)
 78		return;
 79
 80	tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
 81	if (!(tmp & 0x1))
 82		return;
 83
 84	bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL, 0x0);
 85	b53spi->bspi = true;
 86}
 87
 88static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
 89{
 90	/* Do some magic calculation based on length and buad. Add 10% and 1. */
 91	return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
 92}
 93
 94static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
 95{
 96	unsigned long deadline;
 97	u32 tmp;
 98
 99	/* SPE bit has to be 0 before we read MSPI STATUS */
100	deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS);
101	do {
102		tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
103		if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
104			break;
105		udelay(5);
106	} while (!time_after_eq(jiffies, deadline));
107
108	if (tmp & B53SPI_MSPI_SPCR2_SPE)
109		goto spi_timeout;
110
111	/* Check status */
112	deadline = jiffies + msecs_to_jiffies(timeout_ms);
113	do {
114		tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
115		if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
116			bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
117			return 0;
118		}
119
120		cpu_relax();
121		udelay(100);
122	} while (!time_after_eq(jiffies, deadline));
123
124spi_timeout:
125	bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
126
127	pr_err("Timeout waiting for SPI to be ready!\n");
128
129	return -EBUSY;
130}
131
132static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
133				 size_t len, bool cont)
134{
135	u32 tmp;
136	int i;
137
138	for (i = 0; i < len; i++) {
139		/* Transmit Register File MSB */
140		bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
141				 (unsigned int)w_buf[i]);
142	}
143
144	for (i = 0; i < len; i++) {
145		tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
146		      B53SPI_CDRAM_PCS_DSCK;
147		if (!cont && i == len - 1)
148			tmp &= ~B53SPI_CDRAM_CONT;
149		tmp &= ~0x1;
150		/* Command Register File */
151		bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
152	}
153
154	/* Set queue pointers */
155	bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
156	bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
157
158	if (cont)
159		bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
160
161	/* Start SPI transfer */
162	tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
163	tmp |= B53SPI_MSPI_SPCR2_SPE;
164	if (cont)
165		tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
166	bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
167
168	/* Wait for SPI to finish */
169	bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
170
171	if (!cont)
172		bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
173}
174
175static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
176				size_t len, bool cont)
177{
178	u32 tmp;
179	int i;
180
181	for (i = 0; i < len; i++) {
182		tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
183		      B53SPI_CDRAM_PCS_DSCK;
184		if (!cont && i == len - 1)
185			tmp &= ~B53SPI_CDRAM_CONT;
186		tmp &= ~0x1;
187		/* Command Register File */
188		bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
189	}
190
191	/* Set queue pointers */
192	bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
193	bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
194
195	if (cont)
196		bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
197
198	/* Start SPI transfer */
199	tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
200	tmp |= B53SPI_MSPI_SPCR2_SPE;
201	if (cont)
202		tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
203	bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
204
205	/* Wait for SPI to finish */
206	bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
207
208	if (!cont)
209		bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
210
211	for (i = 0; i < len; ++i) {
212		u16 reg = B53SPI_MSPI_RXRAM + 4 * (1 + i * 2);
213
214		/* Data stored in the transmit register file LSB */
215		r_buf[i] = (u8)bcm53xxspi_read(b53spi, reg);
216	}
217}
218
219static int bcm53xxspi_transfer_one(struct spi_master *master,
220				   struct spi_device *spi,
221				   struct spi_transfer *t)
222{
223	struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
224	u8 *buf;
225	size_t left;
226
227	bcm53xxspi_disable_bspi(b53spi);
228
229	if (t->tx_buf) {
230		buf = (u8 *)t->tx_buf;
231		left = t->len;
232		while (left) {
233			size_t to_write = min_t(size_t, 16, left);
234			bool cont = !spi_transfer_is_last(master, t) ||
235				    left - to_write > 0;
236
237			bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
238			left -= to_write;
239			buf += to_write;
240		}
241	}
242
243	if (t->rx_buf) {
244		buf = (u8 *)t->rx_buf;
245		left = t->len;
246		while (left) {
247			size_t to_read = min_t(size_t, 16, left);
248			bool cont = !spi_transfer_is_last(master, t) ||
249				    left - to_read > 0;
250
251			bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
252			left -= to_read;
253			buf += to_read;
254		}
255	}
256
257	return 0;
258}
259
260static int bcm53xxspi_flash_read(struct spi_device *spi,
261				 struct spi_flash_read_message *msg)
262{
263	struct bcm53xxspi *b53spi = spi_master_get_devdata(spi->master);
264	int ret = 0;
265
266	if (msg->from + msg->len > BCM53XXSPI_FLASH_WINDOW)
267		return -EINVAL;
268
269	bcm53xxspi_enable_bspi(b53spi);
270	memcpy_fromio(msg->buf, b53spi->mmio_base + msg->from, msg->len);
271	msg->retlen = msg->len;
272
273	return ret;
274}
275
276/**************************************************
277 * BCMA
278 **************************************************/
279
280static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
281	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
282	{},
283};
284MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
285
286static int bcm53xxspi_bcma_probe(struct bcma_device *core)
287{
288	struct device *dev = &core->dev;
289	struct bcm53xxspi *b53spi;
290	struct spi_master *master;
291	int err;
292
293	if (core->bus->drv_cc.core->id.rev != 42) {
294		pr_err("SPI on SoC with unsupported ChipCommon rev\n");
295		return -ENOTSUPP;
296	}
297
298	master = spi_alloc_master(dev, sizeof(*b53spi));
299	if (!master)
300		return -ENOMEM;
301
302	b53spi = spi_master_get_devdata(master);
303	b53spi->master = master;
304	b53spi->core = core;
305
306	if (core->addr_s[0])
307		b53spi->mmio_base = devm_ioremap(dev, core->addr_s[0],
308						 BCM53XXSPI_FLASH_WINDOW);
309	b53spi->bspi = true;
310	bcm53xxspi_disable_bspi(b53spi);
311
312	master->dev.of_node = dev->of_node;
313	master->transfer_one = bcm53xxspi_transfer_one;
314	if (b53spi->mmio_base)
315		master->spi_flash_read = bcm53xxspi_flash_read;
316
317	bcma_set_drvdata(core, b53spi);
318
319	err = devm_spi_register_master(dev, master);
320	if (err) {
321		spi_master_put(master);
322		bcma_set_drvdata(core, NULL);
323		return err;
324	}
325
326	return 0;
327}
328
329static struct bcma_driver bcm53xxspi_bcma_driver = {
330	.name		= KBUILD_MODNAME,
331	.id_table	= bcm53xxspi_bcma_tbl,
332	.probe		= bcm53xxspi_bcma_probe,
333};
334
335/**************************************************
336 * Init & exit
337 **************************************************/
338
339static int __init bcm53xxspi_module_init(void)
340{
341	int err = 0;
342
343	err = bcma_driver_register(&bcm53xxspi_bcma_driver);
344	if (err)
345		pr_err("Failed to register bcma driver: %d\n", err);
346
347	return err;
348}
349
350static void __exit bcm53xxspi_module_exit(void)
351{
352	bcma_driver_unregister(&bcm53xxspi_bcma_driver);
353}
354
355module_init(bcm53xxspi_module_init);
356module_exit(bcm53xxspi_module_exit);
357
358MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
359MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
360MODULE_LICENSE("GPL v2");