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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TI OMAP Real Time Clock interface for Linux
4 *
5 * Copyright (C) 2003 MontaVista Software, Inc.
6 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
7 *
8 * Copyright (C) 2006 David Brownell (new RTC framework)
9 * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
10 */
11
12#include <linux/bcd.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinconf-generic.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/property.h>
27#include <linux/rtc.h>
28#include <linux/rtc/rtc-omap.h>
29
30/*
31 * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
32 * with century-range alarm matching, driven by the 32kHz clock.
33 *
34 * The main user-visible ways it differs from PC RTCs are by omitting
35 * "don't care" alarm fields and sub-second periodic IRQs, and having
36 * an autoadjust mechanism to calibrate to the true oscillator rate.
37 *
38 * Board-specific wiring options include using split power mode with
39 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
40 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
41 * low power modes) for OMAP1 boards (OMAP-L138 has this built into
42 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
43 */
44
45/* RTC registers */
46#define OMAP_RTC_SECONDS_REG 0x00
47#define OMAP_RTC_MINUTES_REG 0x04
48#define OMAP_RTC_HOURS_REG 0x08
49#define OMAP_RTC_DAYS_REG 0x0C
50#define OMAP_RTC_MONTHS_REG 0x10
51#define OMAP_RTC_YEARS_REG 0x14
52#define OMAP_RTC_WEEKS_REG 0x18
53
54#define OMAP_RTC_ALARM_SECONDS_REG 0x20
55#define OMAP_RTC_ALARM_MINUTES_REG 0x24
56#define OMAP_RTC_ALARM_HOURS_REG 0x28
57#define OMAP_RTC_ALARM_DAYS_REG 0x2c
58#define OMAP_RTC_ALARM_MONTHS_REG 0x30
59#define OMAP_RTC_ALARM_YEARS_REG 0x34
60
61#define OMAP_RTC_CTRL_REG 0x40
62#define OMAP_RTC_STATUS_REG 0x44
63#define OMAP_RTC_INTERRUPTS_REG 0x48
64
65#define OMAP_RTC_COMP_LSB_REG 0x4c
66#define OMAP_RTC_COMP_MSB_REG 0x50
67#define OMAP_RTC_OSC_REG 0x54
68
69#define OMAP_RTC_SCRATCH0_REG 0x60
70#define OMAP_RTC_SCRATCH1_REG 0x64
71#define OMAP_RTC_SCRATCH2_REG 0x68
72
73#define OMAP_RTC_KICK0_REG 0x6c
74#define OMAP_RTC_KICK1_REG 0x70
75
76#define OMAP_RTC_IRQWAKEEN 0x7c
77
78#define OMAP_RTC_ALARM2_SECONDS_REG 0x80
79#define OMAP_RTC_ALARM2_MINUTES_REG 0x84
80#define OMAP_RTC_ALARM2_HOURS_REG 0x88
81#define OMAP_RTC_ALARM2_DAYS_REG 0x8c
82#define OMAP_RTC_ALARM2_MONTHS_REG 0x90
83#define OMAP_RTC_ALARM2_YEARS_REG 0x94
84
85#define OMAP_RTC_PMIC_REG 0x98
86
87/* OMAP_RTC_CTRL_REG bit fields: */
88#define OMAP_RTC_CTRL_SPLIT BIT(7)
89#define OMAP_RTC_CTRL_DISABLE BIT(6)
90#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
91#define OMAP_RTC_CTRL_TEST BIT(4)
92#define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
93#define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
94#define OMAP_RTC_CTRL_ROUND_30S BIT(1)
95#define OMAP_RTC_CTRL_STOP BIT(0)
96
97/* OMAP_RTC_STATUS_REG bit fields: */
98#define OMAP_RTC_STATUS_POWER_UP BIT(7)
99#define OMAP_RTC_STATUS_ALARM2 BIT(7)
100#define OMAP_RTC_STATUS_ALARM BIT(6)
101#define OMAP_RTC_STATUS_1D_EVENT BIT(5)
102#define OMAP_RTC_STATUS_1H_EVENT BIT(4)
103#define OMAP_RTC_STATUS_1M_EVENT BIT(3)
104#define OMAP_RTC_STATUS_1S_EVENT BIT(2)
105#define OMAP_RTC_STATUS_RUN BIT(1)
106#define OMAP_RTC_STATUS_BUSY BIT(0)
107
108/* OMAP_RTC_INTERRUPTS_REG bit fields: */
109#define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4)
110#define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
111#define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
112
113/* OMAP_RTC_OSC_REG bit fields: */
114#define OMAP_RTC_OSC_32KCLK_EN BIT(6)
115#define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
116#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
117
118/* OMAP_RTC_IRQWAKEEN bit fields: */
119#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
120
121/* OMAP_RTC_PMIC bit fields: */
122#define OMAP_RTC_PMIC_POWER_EN_EN BIT(16)
123#define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x)
124#define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x)
125
126/* OMAP_RTC_KICKER values */
127#define KICK0_VALUE 0x83e70b13
128#define KICK1_VALUE 0x95a4f1e0
129
130struct omap_rtc;
131
132struct omap_rtc_device_type {
133 bool has_32kclk_en;
134 bool has_irqwakeen;
135 bool has_pmic_mode;
136 bool has_power_up_reset;
137 void (*lock)(struct omap_rtc *rtc);
138 void (*unlock)(struct omap_rtc *rtc);
139};
140
141struct omap_rtc {
142 struct rtc_device *rtc;
143 void __iomem *base;
144 struct clk *clk;
145 int irq_alarm;
146 int irq_timer;
147 u8 interrupts_reg;
148 bool is_pmic_controller;
149 bool has_ext_clk;
150 bool is_suspending;
151 const struct omap_rtc_device_type *type;
152 struct pinctrl_dev *pctldev;
153};
154
155static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
156{
157 return readb(rtc->base + reg);
158}
159
160static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
161{
162 return readl(rtc->base + reg);
163}
164
165static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
166{
167 writeb(val, rtc->base + reg);
168}
169
170static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
171{
172 writel(val, rtc->base + reg);
173}
174
175static void am3352_rtc_unlock(struct omap_rtc *rtc)
176{
177 rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
178 rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
179}
180
181static void am3352_rtc_lock(struct omap_rtc *rtc)
182{
183 rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
184 rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
185}
186
187static void default_rtc_unlock(struct omap_rtc *rtc)
188{
189}
190
191static void default_rtc_lock(struct omap_rtc *rtc)
192{
193}
194
195/*
196 * We rely on the rtc framework to handle locking (rtc->ops_lock),
197 * so the only other requirement is that register accesses which
198 * require BUSY to be clear are made with IRQs locally disabled
199 */
200static void rtc_wait_not_busy(struct omap_rtc *rtc)
201{
202 int count;
203 u8 status;
204
205 /* BUSY may stay active for 1/32768 second (~30 usec) */
206 for (count = 0; count < 50; count++) {
207 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
208 if (!(status & OMAP_RTC_STATUS_BUSY))
209 break;
210 udelay(1);
211 }
212 /* now we have ~15 usec to read/write various registers */
213}
214
215static irqreturn_t rtc_irq(int irq, void *dev_id)
216{
217 struct omap_rtc *rtc = dev_id;
218 unsigned long events = 0;
219 u8 irq_data;
220
221 irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
222
223 /* alarm irq? */
224 if (irq_data & OMAP_RTC_STATUS_ALARM) {
225 rtc->type->unlock(rtc);
226 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
227 rtc->type->lock(rtc);
228 events |= RTC_IRQF | RTC_AF;
229 }
230
231 /* 1/sec periodic/update irq? */
232 if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
233 events |= RTC_IRQF | RTC_UF;
234
235 rtc_update_irq(rtc->rtc, 1, events);
236
237 return IRQ_HANDLED;
238}
239
240static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
241{
242 struct omap_rtc *rtc = dev_get_drvdata(dev);
243 u8 reg, irqwake_reg = 0;
244
245 local_irq_disable();
246 rtc_wait_not_busy(rtc);
247 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
248 if (rtc->type->has_irqwakeen)
249 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
250
251 if (enabled) {
252 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
253 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
254 } else {
255 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
256 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
257 }
258 rtc_wait_not_busy(rtc);
259 rtc->type->unlock(rtc);
260 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
261 if (rtc->type->has_irqwakeen)
262 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
263 rtc->type->lock(rtc);
264 local_irq_enable();
265
266 return 0;
267}
268
269/* this hardware doesn't support "don't care" alarm fields */
270static void tm2bcd(struct rtc_time *tm)
271{
272 tm->tm_sec = bin2bcd(tm->tm_sec);
273 tm->tm_min = bin2bcd(tm->tm_min);
274 tm->tm_hour = bin2bcd(tm->tm_hour);
275 tm->tm_mday = bin2bcd(tm->tm_mday);
276
277 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
278 tm->tm_year = bin2bcd(tm->tm_year - 100);
279}
280
281static void bcd2tm(struct rtc_time *tm)
282{
283 tm->tm_sec = bcd2bin(tm->tm_sec);
284 tm->tm_min = bcd2bin(tm->tm_min);
285 tm->tm_hour = bcd2bin(tm->tm_hour);
286 tm->tm_mday = bcd2bin(tm->tm_mday);
287 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
288 /* epoch == 1900 */
289 tm->tm_year = bcd2bin(tm->tm_year) + 100;
290}
291
292static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
293{
294 tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
295 tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
296 tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
297 tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
298 tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
299 tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
300}
301
302static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
303{
304 struct omap_rtc *rtc = dev_get_drvdata(dev);
305
306 /* we don't report wday/yday/isdst ... */
307 local_irq_disable();
308 rtc_wait_not_busy(rtc);
309 omap_rtc_read_time_raw(rtc, tm);
310 local_irq_enable();
311
312 bcd2tm(tm);
313
314 return 0;
315}
316
317static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
318{
319 struct omap_rtc *rtc = dev_get_drvdata(dev);
320
321 tm2bcd(tm);
322
323 local_irq_disable();
324 rtc_wait_not_busy(rtc);
325
326 rtc->type->unlock(rtc);
327 rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
328 rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
329 rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
330 rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
331 rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
332 rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
333 rtc->type->lock(rtc);
334
335 local_irq_enable();
336
337 return 0;
338}
339
340static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
341{
342 struct omap_rtc *rtc = dev_get_drvdata(dev);
343 u8 interrupts;
344
345 local_irq_disable();
346 rtc_wait_not_busy(rtc);
347
348 alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
349 alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
350 alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
351 alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
352 alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
353 alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
354
355 local_irq_enable();
356
357 bcd2tm(&alm->time);
358
359 interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
360 alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
361
362 return 0;
363}
364
365static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
366{
367 struct omap_rtc *rtc = dev_get_drvdata(dev);
368 u8 reg, irqwake_reg = 0;
369
370 tm2bcd(&alm->time);
371
372 local_irq_disable();
373 rtc_wait_not_busy(rtc);
374
375 rtc->type->unlock(rtc);
376 rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
377 rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
378 rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
379 rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
380 rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
381 rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
382
383 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
384 if (rtc->type->has_irqwakeen)
385 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
386
387 if (alm->enabled) {
388 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
389 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
390 } else {
391 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
392 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
393 }
394 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
395 if (rtc->type->has_irqwakeen)
396 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
397 rtc->type->lock(rtc);
398
399 local_irq_enable();
400
401 return 0;
402}
403
404static struct omap_rtc *omap_rtc_power_off_rtc;
405
406/**
407 * omap_rtc_power_off_program: Set the pmic power off sequence. The RTC
408 * generates pmic_pwr_enable control, which can be used to control an external
409 * PMIC.
410 */
411int omap_rtc_power_off_program(struct device *dev)
412{
413 struct omap_rtc *rtc = omap_rtc_power_off_rtc;
414 struct rtc_time tm;
415 unsigned long now;
416 int seconds;
417 u32 val;
418
419 rtc->type->unlock(rtc);
420 /* enable pmic_power_en control */
421 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
422 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
423
424again:
425 /* Clear any existing ALARM2 event */
426 rtc_writel(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM2);
427
428 /* set alarm one second from now */
429 omap_rtc_read_time_raw(rtc, &tm);
430 seconds = tm.tm_sec;
431 bcd2tm(&tm);
432 now = rtc_tm_to_time64(&tm);
433 rtc_time64_to_tm(now + 1, &tm);
434
435 tm2bcd(&tm);
436
437 rtc_wait_not_busy(rtc);
438
439 rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
440 rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
441 rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
442 rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
443 rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
444 rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
445
446 /*
447 * enable ALARM2 interrupt
448 *
449 * NOTE: this fails on AM3352 if rtc_write (writeb) is used
450 */
451 val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
452 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
453 val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
454
455 /* Retry in case roll over happened before alarm was armed. */
456 if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
457 val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
458 if (!(val & OMAP_RTC_STATUS_ALARM2))
459 goto again;
460 }
461
462 rtc->type->lock(rtc);
463
464 return 0;
465}
466EXPORT_SYMBOL(omap_rtc_power_off_program);
467
468/*
469 * omap_rtc_poweroff: RTC-controlled power off
470 *
471 * The RTC can be used to control an external PMIC via the pmic_power_en pin,
472 * which can be configured to transition to OFF on ALARM2 events.
473 *
474 * Notes:
475 * The one-second alarm offset is the shortest offset possible as the alarm
476 * registers must be set before the next timer update and the offset
477 * calculation is too heavy for everything to be done within a single access
478 * period (~15 us).
479 *
480 * Called with local interrupts disabled.
481 */
482static void omap_rtc_power_off(void)
483{
484 struct rtc_device *rtc = omap_rtc_power_off_rtc->rtc;
485 u32 val;
486
487 omap_rtc_power_off_program(rtc->dev.parent);
488
489 /* Set PMIC power enable and EXT_WAKEUP in case PB power on is used */
490 omap_rtc_power_off_rtc->type->unlock(omap_rtc_power_off_rtc);
491 val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG);
492 val |= OMAP_RTC_PMIC_POWER_EN_EN | OMAP_RTC_PMIC_EXT_WKUP_POL(0) |
493 OMAP_RTC_PMIC_EXT_WKUP_EN(0);
494 rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val);
495 omap_rtc_power_off_rtc->type->lock(omap_rtc_power_off_rtc);
496
497 /*
498 * Wait for alarm to trigger (within one second) and external PMIC to
499 * power off the system. Add a 500 ms margin for external latencies
500 * (e.g. debounce circuits).
501 */
502 mdelay(1500);
503}
504
505static const struct rtc_class_ops omap_rtc_ops = {
506 .read_time = omap_rtc_read_time,
507 .set_time = omap_rtc_set_time,
508 .read_alarm = omap_rtc_read_alarm,
509 .set_alarm = omap_rtc_set_alarm,
510 .alarm_irq_enable = omap_rtc_alarm_irq_enable,
511};
512
513static const struct omap_rtc_device_type omap_rtc_default_type = {
514 .has_power_up_reset = true,
515 .lock = default_rtc_lock,
516 .unlock = default_rtc_unlock,
517};
518
519static const struct omap_rtc_device_type omap_rtc_am3352_type = {
520 .has_32kclk_en = true,
521 .has_irqwakeen = true,
522 .has_pmic_mode = true,
523 .lock = am3352_rtc_lock,
524 .unlock = am3352_rtc_unlock,
525};
526
527static const struct omap_rtc_device_type omap_rtc_da830_type = {
528 .lock = am3352_rtc_lock,
529 .unlock = am3352_rtc_unlock,
530};
531
532static const struct platform_device_id omap_rtc_id_table[] = {
533 {
534 .name = "omap_rtc",
535 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
536 }, {
537 .name = "am3352-rtc",
538 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
539 }, {
540 .name = "da830-rtc",
541 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
542 }, {
543 /* sentinel */
544 }
545};
546MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
547
548static const struct of_device_id omap_rtc_of_match[] = {
549 {
550 .compatible = "ti,am3352-rtc",
551 .data = &omap_rtc_am3352_type,
552 }, {
553 .compatible = "ti,da830-rtc",
554 .data = &omap_rtc_da830_type,
555 }, {
556 /* sentinel */
557 }
558};
559MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
560
561static const struct pinctrl_pin_desc rtc_pins_desc[] = {
562 PINCTRL_PIN(0, "ext_wakeup0"),
563 PINCTRL_PIN(1, "ext_wakeup1"),
564 PINCTRL_PIN(2, "ext_wakeup2"),
565 PINCTRL_PIN(3, "ext_wakeup3"),
566};
567
568static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
569{
570 return 0;
571}
572
573static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
574 unsigned int group)
575{
576 return NULL;
577}
578
579static const struct pinctrl_ops rtc_pinctrl_ops = {
580 .get_groups_count = rtc_pinctrl_get_groups_count,
581 .get_group_name = rtc_pinctrl_get_group_name,
582 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
583 .dt_free_map = pinconf_generic_dt_free_map,
584};
585
586#define PIN_CONFIG_ACTIVE_HIGH (PIN_CONFIG_END + 1)
587
588static const struct pinconf_generic_params rtc_params[] = {
589 {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
590};
591
592#ifdef CONFIG_DEBUG_FS
593static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
594 PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
595};
596#endif
597
598static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
599 unsigned int pin, unsigned long *config)
600{
601 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
602 unsigned int param = pinconf_to_config_param(*config);
603 u32 val;
604 u16 arg = 0;
605
606 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
607
608 switch (param) {
609 case PIN_CONFIG_INPUT_ENABLE:
610 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
611 return -EINVAL;
612 break;
613 case PIN_CONFIG_ACTIVE_HIGH:
614 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
615 return -EINVAL;
616 break;
617 default:
618 return -ENOTSUPP;
619 }
620
621 *config = pinconf_to_config_packed(param, arg);
622
623 return 0;
624}
625
626static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
627 unsigned int pin, unsigned long *configs,
628 unsigned int num_configs)
629{
630 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
631 u32 val;
632 unsigned int param;
633 u32 param_val;
634 int i;
635
636 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
637
638 /* active low by default */
639 val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
640
641 for (i = 0; i < num_configs; i++) {
642 param = pinconf_to_config_param(configs[i]);
643 param_val = pinconf_to_config_argument(configs[i]);
644
645 switch (param) {
646 case PIN_CONFIG_INPUT_ENABLE:
647 if (param_val)
648 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
649 else
650 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
651 break;
652 case PIN_CONFIG_ACTIVE_HIGH:
653 val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
654 break;
655 default:
656 dev_err(&rtc->rtc->dev, "Property %u not supported\n",
657 param);
658 return -ENOTSUPP;
659 }
660 }
661
662 rtc->type->unlock(rtc);
663 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
664 rtc->type->lock(rtc);
665
666 return 0;
667}
668
669static const struct pinconf_ops rtc_pinconf_ops = {
670 .is_generic = true,
671 .pin_config_get = rtc_pinconf_get,
672 .pin_config_set = rtc_pinconf_set,
673};
674
675static struct pinctrl_desc rtc_pinctrl_desc = {
676 .pins = rtc_pins_desc,
677 .npins = ARRAY_SIZE(rtc_pins_desc),
678 .pctlops = &rtc_pinctrl_ops,
679 .confops = &rtc_pinconf_ops,
680 .custom_params = rtc_params,
681 .num_custom_params = ARRAY_SIZE(rtc_params),
682#ifdef CONFIG_DEBUG_FS
683 .custom_conf_items = rtc_conf_items,
684#endif
685 .owner = THIS_MODULE,
686};
687
688static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
689 size_t bytes)
690{
691 struct omap_rtc *rtc = priv;
692 u32 *val = _val;
693 int i;
694
695 for (i = 0; i < bytes / 4; i++)
696 val[i] = rtc_readl(rtc,
697 OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
698
699 return 0;
700}
701
702static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
703 size_t bytes)
704{
705 struct omap_rtc *rtc = priv;
706 u32 *val = _val;
707 int i;
708
709 rtc->type->unlock(rtc);
710 for (i = 0; i < bytes / 4; i++)
711 rtc_writel(rtc,
712 OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
713 rtc->type->lock(rtc);
714
715 return 0;
716}
717
718static struct nvmem_config omap_rtc_nvmem_config = {
719 .name = "omap_rtc_scratch",
720 .word_size = 4,
721 .stride = 4,
722 .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
723 .reg_read = omap_rtc_scratch_read,
724 .reg_write = omap_rtc_scratch_write,
725};
726
727static int omap_rtc_probe(struct platform_device *pdev)
728{
729 struct omap_rtc *rtc;
730 u8 reg, mask, new_ctrl;
731 const struct platform_device_id *id_entry;
732 int ret;
733
734 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
735 if (!rtc)
736 return -ENOMEM;
737
738 rtc->type = device_get_match_data(&pdev->dev);
739 if (rtc->type) {
740 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
741 of_device_is_system_power_controller(pdev->dev.of_node);
742 } else {
743 id_entry = platform_get_device_id(pdev);
744 rtc->type = (void *)id_entry->driver_data;
745 }
746
747 rtc->irq_timer = platform_get_irq(pdev, 0);
748 if (rtc->irq_timer < 0)
749 return rtc->irq_timer;
750
751 rtc->irq_alarm = platform_get_irq(pdev, 1);
752 if (rtc->irq_alarm < 0)
753 return rtc->irq_alarm;
754
755 rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
756 if (!IS_ERR(rtc->clk))
757 rtc->has_ext_clk = true;
758 else
759 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
760
761 if (!IS_ERR(rtc->clk))
762 clk_prepare_enable(rtc->clk);
763
764 rtc->base = devm_platform_ioremap_resource(pdev, 0);
765 if (IS_ERR(rtc->base)) {
766 clk_disable_unprepare(rtc->clk);
767 return PTR_ERR(rtc->base);
768 }
769
770 platform_set_drvdata(pdev, rtc);
771
772 /* Enable the clock/module so that we can access the registers */
773 pm_runtime_enable(&pdev->dev);
774 pm_runtime_get_sync(&pdev->dev);
775
776 rtc->type->unlock(rtc);
777
778 /*
779 * disable interrupts
780 *
781 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
782 */
783 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
784
785 /* enable RTC functional clock */
786 if (rtc->type->has_32kclk_en) {
787 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
788 rtc_write(rtc, OMAP_RTC_OSC_REG, reg | OMAP_RTC_OSC_32KCLK_EN);
789 }
790
791 /* clear old status */
792 reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
793
794 mask = OMAP_RTC_STATUS_ALARM;
795
796 if (rtc->type->has_pmic_mode)
797 mask |= OMAP_RTC_STATUS_ALARM2;
798
799 if (rtc->type->has_power_up_reset) {
800 mask |= OMAP_RTC_STATUS_POWER_UP;
801 if (reg & OMAP_RTC_STATUS_POWER_UP)
802 dev_info(&pdev->dev, "RTC power up reset detected\n");
803 }
804
805 if (reg & mask)
806 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
807
808 /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
809 reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
810 if (reg & OMAP_RTC_CTRL_STOP)
811 dev_info(&pdev->dev, "already running\n");
812
813 /* force to 24 hour mode */
814 new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
815 new_ctrl |= OMAP_RTC_CTRL_STOP;
816
817 /*
818 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
819 *
820 * - Device wake-up capability setting should come through chip
821 * init logic. OMAP1 boards should initialize the "wakeup capable"
822 * flag in the platform device if the board is wired right for
823 * being woken up by RTC alarm. For OMAP-L138, this capability
824 * is built into the SoC by the "Deep Sleep" capability.
825 *
826 * - Boards wired so RTC_ON_nOFF is used as the reset signal,
827 * rather than nPWRON_RESET, should forcibly enable split
828 * power mode. (Some chip errata report that RTC_CTRL_SPLIT
829 * is write-only, and always reads as zero...)
830 */
831
832 if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
833 dev_info(&pdev->dev, "split power mode\n");
834
835 if (reg != new_ctrl)
836 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
837
838 /*
839 * If we have the external clock then switch to it so we can keep
840 * ticking across suspend.
841 */
842 if (rtc->has_ext_clk) {
843 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
844 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
845 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
846 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
847 }
848
849 rtc->type->lock(rtc);
850
851 device_init_wakeup(&pdev->dev, true);
852
853 rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
854 if (IS_ERR(rtc->rtc)) {
855 ret = PTR_ERR(rtc->rtc);
856 goto err;
857 }
858
859 rtc->rtc->ops = &omap_rtc_ops;
860 rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
861 rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
862 omap_rtc_nvmem_config.priv = rtc;
863
864 /* handle periodic and alarm irqs */
865 ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
866 dev_name(&rtc->rtc->dev), rtc);
867 if (ret)
868 goto err;
869
870 if (rtc->irq_timer != rtc->irq_alarm) {
871 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
872 dev_name(&rtc->rtc->dev), rtc);
873 if (ret)
874 goto err;
875 }
876
877 /* Support ext_wakeup pinconf */
878 rtc_pinctrl_desc.name = dev_name(&pdev->dev);
879
880 rtc->pctldev = devm_pinctrl_register(&pdev->dev, &rtc_pinctrl_desc, rtc);
881 if (IS_ERR(rtc->pctldev)) {
882 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
883 ret = PTR_ERR(rtc->pctldev);
884 goto err;
885 }
886
887 ret = devm_rtc_register_device(rtc->rtc);
888 if (ret)
889 goto err;
890
891 devm_rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
892
893 if (rtc->is_pmic_controller) {
894 if (!pm_power_off) {
895 omap_rtc_power_off_rtc = rtc;
896 pm_power_off = omap_rtc_power_off;
897 }
898 }
899
900 return 0;
901
902err:
903 clk_disable_unprepare(rtc->clk);
904 device_init_wakeup(&pdev->dev, false);
905 rtc->type->lock(rtc);
906 pm_runtime_put_sync(&pdev->dev);
907 pm_runtime_disable(&pdev->dev);
908
909 return ret;
910}
911
912static void omap_rtc_remove(struct platform_device *pdev)
913{
914 struct omap_rtc *rtc = platform_get_drvdata(pdev);
915 u8 reg;
916
917 if (pm_power_off == omap_rtc_power_off &&
918 omap_rtc_power_off_rtc == rtc) {
919 pm_power_off = NULL;
920 omap_rtc_power_off_rtc = NULL;
921 }
922
923 device_init_wakeup(&pdev->dev, 0);
924
925 if (!IS_ERR(rtc->clk))
926 clk_disable_unprepare(rtc->clk);
927
928 rtc->type->unlock(rtc);
929 /* leave rtc running, but disable irqs */
930 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
931
932 if (rtc->has_ext_clk) {
933 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
934 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
935 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
936 }
937
938 rtc->type->lock(rtc);
939
940 /* Disable the clock/module */
941 pm_runtime_put_sync(&pdev->dev);
942 pm_runtime_disable(&pdev->dev);
943}
944
945static int __maybe_unused omap_rtc_suspend(struct device *dev)
946{
947 struct omap_rtc *rtc = dev_get_drvdata(dev);
948
949 rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
950
951 rtc->type->unlock(rtc);
952 /*
953 * FIXME: the RTC alarm is not currently acting as a wakeup event
954 * source on some platforms, and in fact this enable() call is just
955 * saving a flag that's never used...
956 */
957 if (device_may_wakeup(dev))
958 enable_irq_wake(rtc->irq_alarm);
959 else
960 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
961 rtc->type->lock(rtc);
962
963 rtc->is_suspending = true;
964
965 return 0;
966}
967
968static int __maybe_unused omap_rtc_resume(struct device *dev)
969{
970 struct omap_rtc *rtc = dev_get_drvdata(dev);
971
972 rtc->type->unlock(rtc);
973 if (device_may_wakeup(dev))
974 disable_irq_wake(rtc->irq_alarm);
975 else
976 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
977 rtc->type->lock(rtc);
978
979 rtc->is_suspending = false;
980
981 return 0;
982}
983
984static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
985{
986 struct omap_rtc *rtc = dev_get_drvdata(dev);
987
988 if (rtc->is_suspending && !rtc->has_ext_clk)
989 return -EBUSY;
990
991 return 0;
992}
993
994static const struct dev_pm_ops omap_rtc_pm_ops = {
995 SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
996 SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
997};
998
999static void omap_rtc_shutdown(struct platform_device *pdev)
1000{
1001 struct omap_rtc *rtc = platform_get_drvdata(pdev);
1002 u8 mask;
1003
1004 /*
1005 * Keep the ALARM interrupt enabled to allow the system to power up on
1006 * alarm events.
1007 */
1008 rtc->type->unlock(rtc);
1009 mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
1010 mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
1011 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
1012 rtc->type->lock(rtc);
1013}
1014
1015static struct platform_driver omap_rtc_driver = {
1016 .probe = omap_rtc_probe,
1017 .remove = omap_rtc_remove,
1018 .shutdown = omap_rtc_shutdown,
1019 .driver = {
1020 .name = "omap_rtc",
1021 .pm = &omap_rtc_pm_ops,
1022 .of_match_table = omap_rtc_of_match,
1023 },
1024 .id_table = omap_rtc_id_table,
1025};
1026
1027module_platform_driver(omap_rtc_driver);
1028
1029MODULE_AUTHOR("George G. Davis (and others)");
1030MODULE_DESCRIPTION("TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx RTC driver");
1031MODULE_LICENSE("GPL");
1/*
2 * TI OMAP Real Time Clock interface for Linux
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
6 *
7 * Copyright (C) 2006 David Brownell (new RTC framework)
8 * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <linux/bcd.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/ioport.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinconf-generic.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/rtc.h>
33
34/*
35 * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
36 * with century-range alarm matching, driven by the 32kHz clock.
37 *
38 * The main user-visible ways it differs from PC RTCs are by omitting
39 * "don't care" alarm fields and sub-second periodic IRQs, and having
40 * an autoadjust mechanism to calibrate to the true oscillator rate.
41 *
42 * Board-specific wiring options include using split power mode with
43 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
44 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
45 * low power modes) for OMAP1 boards (OMAP-L138 has this built into
46 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
47 */
48
49/* RTC registers */
50#define OMAP_RTC_SECONDS_REG 0x00
51#define OMAP_RTC_MINUTES_REG 0x04
52#define OMAP_RTC_HOURS_REG 0x08
53#define OMAP_RTC_DAYS_REG 0x0C
54#define OMAP_RTC_MONTHS_REG 0x10
55#define OMAP_RTC_YEARS_REG 0x14
56#define OMAP_RTC_WEEKS_REG 0x18
57
58#define OMAP_RTC_ALARM_SECONDS_REG 0x20
59#define OMAP_RTC_ALARM_MINUTES_REG 0x24
60#define OMAP_RTC_ALARM_HOURS_REG 0x28
61#define OMAP_RTC_ALARM_DAYS_REG 0x2c
62#define OMAP_RTC_ALARM_MONTHS_REG 0x30
63#define OMAP_RTC_ALARM_YEARS_REG 0x34
64
65#define OMAP_RTC_CTRL_REG 0x40
66#define OMAP_RTC_STATUS_REG 0x44
67#define OMAP_RTC_INTERRUPTS_REG 0x48
68
69#define OMAP_RTC_COMP_LSB_REG 0x4c
70#define OMAP_RTC_COMP_MSB_REG 0x50
71#define OMAP_RTC_OSC_REG 0x54
72
73#define OMAP_RTC_SCRATCH0_REG 0x60
74#define OMAP_RTC_SCRATCH1_REG 0x64
75#define OMAP_RTC_SCRATCH2_REG 0x68
76
77#define OMAP_RTC_KICK0_REG 0x6c
78#define OMAP_RTC_KICK1_REG 0x70
79
80#define OMAP_RTC_IRQWAKEEN 0x7c
81
82#define OMAP_RTC_ALARM2_SECONDS_REG 0x80
83#define OMAP_RTC_ALARM2_MINUTES_REG 0x84
84#define OMAP_RTC_ALARM2_HOURS_REG 0x88
85#define OMAP_RTC_ALARM2_DAYS_REG 0x8c
86#define OMAP_RTC_ALARM2_MONTHS_REG 0x90
87#define OMAP_RTC_ALARM2_YEARS_REG 0x94
88
89#define OMAP_RTC_PMIC_REG 0x98
90
91/* OMAP_RTC_CTRL_REG bit fields: */
92#define OMAP_RTC_CTRL_SPLIT BIT(7)
93#define OMAP_RTC_CTRL_DISABLE BIT(6)
94#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
95#define OMAP_RTC_CTRL_TEST BIT(4)
96#define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
97#define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
98#define OMAP_RTC_CTRL_ROUND_30S BIT(1)
99#define OMAP_RTC_CTRL_STOP BIT(0)
100
101/* OMAP_RTC_STATUS_REG bit fields: */
102#define OMAP_RTC_STATUS_POWER_UP BIT(7)
103#define OMAP_RTC_STATUS_ALARM2 BIT(7)
104#define OMAP_RTC_STATUS_ALARM BIT(6)
105#define OMAP_RTC_STATUS_1D_EVENT BIT(5)
106#define OMAP_RTC_STATUS_1H_EVENT BIT(4)
107#define OMAP_RTC_STATUS_1M_EVENT BIT(3)
108#define OMAP_RTC_STATUS_1S_EVENT BIT(2)
109#define OMAP_RTC_STATUS_RUN BIT(1)
110#define OMAP_RTC_STATUS_BUSY BIT(0)
111
112/* OMAP_RTC_INTERRUPTS_REG bit fields: */
113#define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4)
114#define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
115#define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
116
117/* OMAP_RTC_OSC_REG bit fields: */
118#define OMAP_RTC_OSC_32KCLK_EN BIT(6)
119#define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
120#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
121
122/* OMAP_RTC_IRQWAKEEN bit fields: */
123#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
124
125/* OMAP_RTC_PMIC bit fields: */
126#define OMAP_RTC_PMIC_POWER_EN_EN BIT(16)
127#define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x)
128#define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x)
129
130/* OMAP_RTC_KICKER values */
131#define KICK0_VALUE 0x83e70b13
132#define KICK1_VALUE 0x95a4f1e0
133
134struct omap_rtc;
135
136struct omap_rtc_device_type {
137 bool has_32kclk_en;
138 bool has_irqwakeen;
139 bool has_pmic_mode;
140 bool has_power_up_reset;
141 void (*lock)(struct omap_rtc *rtc);
142 void (*unlock)(struct omap_rtc *rtc);
143};
144
145struct omap_rtc {
146 struct rtc_device *rtc;
147 void __iomem *base;
148 struct clk *clk;
149 int irq_alarm;
150 int irq_timer;
151 u8 interrupts_reg;
152 bool is_pmic_controller;
153 bool has_ext_clk;
154 bool is_suspending;
155 const struct omap_rtc_device_type *type;
156 struct pinctrl_dev *pctldev;
157};
158
159static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
160{
161 return readb(rtc->base + reg);
162}
163
164static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
165{
166 return readl(rtc->base + reg);
167}
168
169static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
170{
171 writeb(val, rtc->base + reg);
172}
173
174static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
175{
176 writel(val, rtc->base + reg);
177}
178
179static void am3352_rtc_unlock(struct omap_rtc *rtc)
180{
181 rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
182 rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
183}
184
185static void am3352_rtc_lock(struct omap_rtc *rtc)
186{
187 rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
188 rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
189}
190
191static void default_rtc_unlock(struct omap_rtc *rtc)
192{
193}
194
195static void default_rtc_lock(struct omap_rtc *rtc)
196{
197}
198
199/*
200 * We rely on the rtc framework to handle locking (rtc->ops_lock),
201 * so the only other requirement is that register accesses which
202 * require BUSY to be clear are made with IRQs locally disabled
203 */
204static void rtc_wait_not_busy(struct omap_rtc *rtc)
205{
206 int count;
207 u8 status;
208
209 /* BUSY may stay active for 1/32768 second (~30 usec) */
210 for (count = 0; count < 50; count++) {
211 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
212 if (!(status & OMAP_RTC_STATUS_BUSY))
213 break;
214 udelay(1);
215 }
216 /* now we have ~15 usec to read/write various registers */
217}
218
219static irqreturn_t rtc_irq(int irq, void *dev_id)
220{
221 struct omap_rtc *rtc = dev_id;
222 unsigned long events = 0;
223 u8 irq_data;
224
225 irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
226
227 /* alarm irq? */
228 if (irq_data & OMAP_RTC_STATUS_ALARM) {
229 rtc->type->unlock(rtc);
230 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
231 rtc->type->lock(rtc);
232 events |= RTC_IRQF | RTC_AF;
233 }
234
235 /* 1/sec periodic/update irq? */
236 if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
237 events |= RTC_IRQF | RTC_UF;
238
239 rtc_update_irq(rtc->rtc, 1, events);
240
241 return IRQ_HANDLED;
242}
243
244static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
245{
246 struct omap_rtc *rtc = dev_get_drvdata(dev);
247 u8 reg, irqwake_reg = 0;
248
249 local_irq_disable();
250 rtc_wait_not_busy(rtc);
251 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
252 if (rtc->type->has_irqwakeen)
253 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
254
255 if (enabled) {
256 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
257 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
258 } else {
259 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
260 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
261 }
262 rtc_wait_not_busy(rtc);
263 rtc->type->unlock(rtc);
264 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
265 if (rtc->type->has_irqwakeen)
266 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
267 rtc->type->lock(rtc);
268 local_irq_enable();
269
270 return 0;
271}
272
273/* this hardware doesn't support "don't care" alarm fields */
274static int tm2bcd(struct rtc_time *tm)
275{
276 tm->tm_sec = bin2bcd(tm->tm_sec);
277 tm->tm_min = bin2bcd(tm->tm_min);
278 tm->tm_hour = bin2bcd(tm->tm_hour);
279 tm->tm_mday = bin2bcd(tm->tm_mday);
280
281 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
282
283 /* epoch == 1900 */
284 if (tm->tm_year < 100 || tm->tm_year > 199)
285 return -EINVAL;
286 tm->tm_year = bin2bcd(tm->tm_year - 100);
287
288 return 0;
289}
290
291static void bcd2tm(struct rtc_time *tm)
292{
293 tm->tm_sec = bcd2bin(tm->tm_sec);
294 tm->tm_min = bcd2bin(tm->tm_min);
295 tm->tm_hour = bcd2bin(tm->tm_hour);
296 tm->tm_mday = bcd2bin(tm->tm_mday);
297 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
298 /* epoch == 1900 */
299 tm->tm_year = bcd2bin(tm->tm_year) + 100;
300}
301
302static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
303{
304 tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
305 tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
306 tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
307 tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
308 tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
309 tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
310}
311
312static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
313{
314 struct omap_rtc *rtc = dev_get_drvdata(dev);
315
316 /* we don't report wday/yday/isdst ... */
317 local_irq_disable();
318 rtc_wait_not_busy(rtc);
319 omap_rtc_read_time_raw(rtc, tm);
320 local_irq_enable();
321
322 bcd2tm(tm);
323
324 return 0;
325}
326
327static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
328{
329 struct omap_rtc *rtc = dev_get_drvdata(dev);
330
331 if (tm2bcd(tm) < 0)
332 return -EINVAL;
333
334 local_irq_disable();
335 rtc_wait_not_busy(rtc);
336
337 rtc->type->unlock(rtc);
338 rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
339 rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
340 rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
341 rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
342 rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
343 rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
344 rtc->type->lock(rtc);
345
346 local_irq_enable();
347
348 return 0;
349}
350
351static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
352{
353 struct omap_rtc *rtc = dev_get_drvdata(dev);
354 u8 interrupts;
355
356 local_irq_disable();
357 rtc_wait_not_busy(rtc);
358
359 alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
360 alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
361 alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
362 alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
363 alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
364 alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
365
366 local_irq_enable();
367
368 bcd2tm(&alm->time);
369
370 interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
371 alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
372
373 return 0;
374}
375
376static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
377{
378 struct omap_rtc *rtc = dev_get_drvdata(dev);
379 u8 reg, irqwake_reg = 0;
380
381 if (tm2bcd(&alm->time) < 0)
382 return -EINVAL;
383
384 local_irq_disable();
385 rtc_wait_not_busy(rtc);
386
387 rtc->type->unlock(rtc);
388 rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
389 rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
390 rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
391 rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
392 rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
393 rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
394
395 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
396 if (rtc->type->has_irqwakeen)
397 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
398
399 if (alm->enabled) {
400 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
401 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
402 } else {
403 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
404 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
405 }
406 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
407 if (rtc->type->has_irqwakeen)
408 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
409 rtc->type->lock(rtc);
410
411 local_irq_enable();
412
413 return 0;
414}
415
416static struct omap_rtc *omap_rtc_power_off_rtc;
417
418/*
419 * omap_rtc_poweroff: RTC-controlled power off
420 *
421 * The RTC can be used to control an external PMIC via the pmic_power_en pin,
422 * which can be configured to transition to OFF on ALARM2 events.
423 *
424 * Notes:
425 * The two-second alarm offset is the shortest offset possible as the alarm
426 * registers must be set before the next timer update and the offset
427 * calculation is too heavy for everything to be done within a single access
428 * period (~15 us).
429 *
430 * Called with local interrupts disabled.
431 */
432static void omap_rtc_power_off(void)
433{
434 struct omap_rtc *rtc = omap_rtc_power_off_rtc;
435 struct rtc_time tm;
436 unsigned long now;
437 u32 val;
438
439 rtc->type->unlock(rtc);
440 /* enable pmic_power_en control */
441 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
442 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
443
444 /* set alarm two seconds from now */
445 omap_rtc_read_time_raw(rtc, &tm);
446 bcd2tm(&tm);
447 rtc_tm_to_time(&tm, &now);
448 rtc_time_to_tm(now + 2, &tm);
449
450 if (tm2bcd(&tm) < 0) {
451 dev_err(&rtc->rtc->dev, "power off failed\n");
452 return;
453 }
454
455 rtc_wait_not_busy(rtc);
456
457 rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
458 rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
459 rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
460 rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
461 rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
462 rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
463
464 /*
465 * enable ALARM2 interrupt
466 *
467 * NOTE: this fails on AM3352 if rtc_write (writeb) is used
468 */
469 val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
470 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
471 val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
472 rtc->type->lock(rtc);
473
474 /*
475 * Wait for alarm to trigger (within two seconds) and external PMIC to
476 * power off the system. Add a 500 ms margin for external latencies
477 * (e.g. debounce circuits).
478 */
479 mdelay(2500);
480}
481
482static const struct rtc_class_ops omap_rtc_ops = {
483 .read_time = omap_rtc_read_time,
484 .set_time = omap_rtc_set_time,
485 .read_alarm = omap_rtc_read_alarm,
486 .set_alarm = omap_rtc_set_alarm,
487 .alarm_irq_enable = omap_rtc_alarm_irq_enable,
488};
489
490static const struct omap_rtc_device_type omap_rtc_default_type = {
491 .has_power_up_reset = true,
492 .lock = default_rtc_lock,
493 .unlock = default_rtc_unlock,
494};
495
496static const struct omap_rtc_device_type omap_rtc_am3352_type = {
497 .has_32kclk_en = true,
498 .has_irqwakeen = true,
499 .has_pmic_mode = true,
500 .lock = am3352_rtc_lock,
501 .unlock = am3352_rtc_unlock,
502};
503
504static const struct omap_rtc_device_type omap_rtc_da830_type = {
505 .lock = am3352_rtc_lock,
506 .unlock = am3352_rtc_unlock,
507};
508
509static const struct platform_device_id omap_rtc_id_table[] = {
510 {
511 .name = "omap_rtc",
512 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
513 }, {
514 .name = "am3352-rtc",
515 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
516 }, {
517 .name = "da830-rtc",
518 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
519 }, {
520 /* sentinel */
521 }
522};
523MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
524
525static const struct of_device_id omap_rtc_of_match[] = {
526 {
527 .compatible = "ti,am3352-rtc",
528 .data = &omap_rtc_am3352_type,
529 }, {
530 .compatible = "ti,da830-rtc",
531 .data = &omap_rtc_da830_type,
532 }, {
533 /* sentinel */
534 }
535};
536MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
537
538static const struct pinctrl_pin_desc rtc_pins_desc[] = {
539 PINCTRL_PIN(0, "ext_wakeup0"),
540 PINCTRL_PIN(1, "ext_wakeup1"),
541 PINCTRL_PIN(2, "ext_wakeup2"),
542 PINCTRL_PIN(3, "ext_wakeup3"),
543};
544
545static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
546{
547 return 0;
548}
549
550static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
551 unsigned int group)
552{
553 return NULL;
554}
555
556static const struct pinctrl_ops rtc_pinctrl_ops = {
557 .get_groups_count = rtc_pinctrl_get_groups_count,
558 .get_group_name = rtc_pinctrl_get_group_name,
559 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
560 .dt_free_map = pinconf_generic_dt_free_map,
561};
562
563enum rtc_pin_config_param {
564 PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1,
565};
566
567static const struct pinconf_generic_params rtc_params[] = {
568 {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
569};
570
571#ifdef CONFIG_DEBUG_FS
572static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
573 PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
574};
575#endif
576
577static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
578 unsigned int pin, unsigned long *config)
579{
580 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
581 unsigned int param = pinconf_to_config_param(*config);
582 u32 val;
583 u16 arg = 0;
584
585 rtc->type->unlock(rtc);
586 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
587 rtc->type->lock(rtc);
588
589 switch (param) {
590 case PIN_CONFIG_INPUT_ENABLE:
591 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
592 return -EINVAL;
593 break;
594 case PIN_CONFIG_ACTIVE_HIGH:
595 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
596 return -EINVAL;
597 break;
598 default:
599 return -ENOTSUPP;
600 };
601
602 *config = pinconf_to_config_packed(param, arg);
603
604 return 0;
605}
606
607static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
608 unsigned int pin, unsigned long *configs,
609 unsigned int num_configs)
610{
611 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
612 u32 val;
613 unsigned int param;
614 u32 param_val;
615 int i;
616
617 rtc->type->unlock(rtc);
618 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
619 rtc->type->lock(rtc);
620
621 /* active low by default */
622 val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
623
624 for (i = 0; i < num_configs; i++) {
625 param = pinconf_to_config_param(configs[i]);
626 param_val = pinconf_to_config_argument(configs[i]);
627
628 switch (param) {
629 case PIN_CONFIG_INPUT_ENABLE:
630 if (param_val)
631 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
632 else
633 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
634 break;
635 case PIN_CONFIG_ACTIVE_HIGH:
636 val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
637 break;
638 default:
639 dev_err(&rtc->rtc->dev, "Property %u not supported\n",
640 param);
641 return -ENOTSUPP;
642 }
643 }
644
645 rtc->type->unlock(rtc);
646 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
647 rtc->type->lock(rtc);
648
649 return 0;
650}
651
652static const struct pinconf_ops rtc_pinconf_ops = {
653 .is_generic = true,
654 .pin_config_get = rtc_pinconf_get,
655 .pin_config_set = rtc_pinconf_set,
656};
657
658static struct pinctrl_desc rtc_pinctrl_desc = {
659 .pins = rtc_pins_desc,
660 .npins = ARRAY_SIZE(rtc_pins_desc),
661 .pctlops = &rtc_pinctrl_ops,
662 .confops = &rtc_pinconf_ops,
663 .custom_params = rtc_params,
664 .num_custom_params = ARRAY_SIZE(rtc_params),
665#ifdef CONFIG_DEBUG_FS
666 .custom_conf_items = rtc_conf_items,
667#endif
668 .owner = THIS_MODULE,
669};
670
671static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
672 size_t bytes)
673{
674 struct omap_rtc *rtc = priv;
675 u32 *val = _val;
676 int i;
677
678 for (i = 0; i < bytes / 4; i++)
679 val[i] = rtc_readl(rtc,
680 OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
681
682 return 0;
683}
684
685static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
686 size_t bytes)
687{
688 struct omap_rtc *rtc = priv;
689 u32 *val = _val;
690 int i;
691
692 rtc->type->unlock(rtc);
693 for (i = 0; i < bytes / 4; i++)
694 rtc_writel(rtc,
695 OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
696 rtc->type->lock(rtc);
697
698 return 0;
699}
700
701static struct nvmem_config omap_rtc_nvmem_config = {
702 .name = "omap_rtc_scratch",
703 .word_size = 4,
704 .stride = 4,
705 .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
706 .reg_read = omap_rtc_scratch_read,
707 .reg_write = omap_rtc_scratch_write,
708};
709
710static int omap_rtc_probe(struct platform_device *pdev)
711{
712 struct omap_rtc *rtc;
713 struct resource *res;
714 u8 reg, mask, new_ctrl;
715 const struct platform_device_id *id_entry;
716 const struct of_device_id *of_id;
717 int ret;
718
719 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
720 if (!rtc)
721 return -ENOMEM;
722
723 of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
724 if (of_id) {
725 rtc->type = of_id->data;
726 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
727 of_property_read_bool(pdev->dev.of_node,
728 "system-power-controller");
729 } else {
730 id_entry = platform_get_device_id(pdev);
731 rtc->type = (void *)id_entry->driver_data;
732 }
733
734 rtc->irq_timer = platform_get_irq(pdev, 0);
735 if (rtc->irq_timer <= 0)
736 return -ENOENT;
737
738 rtc->irq_alarm = platform_get_irq(pdev, 1);
739 if (rtc->irq_alarm <= 0)
740 return -ENOENT;
741
742 rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
743 if (!IS_ERR(rtc->clk))
744 rtc->has_ext_clk = true;
745 else
746 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
747
748 if (!IS_ERR(rtc->clk))
749 clk_prepare_enable(rtc->clk);
750
751 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
752 rtc->base = devm_ioremap_resource(&pdev->dev, res);
753 if (IS_ERR(rtc->base)) {
754 clk_disable_unprepare(rtc->clk);
755 return PTR_ERR(rtc->base);
756 }
757
758 platform_set_drvdata(pdev, rtc);
759
760 /* Enable the clock/module so that we can access the registers */
761 pm_runtime_enable(&pdev->dev);
762 pm_runtime_get_sync(&pdev->dev);
763
764 rtc->type->unlock(rtc);
765
766 /*
767 * disable interrupts
768 *
769 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
770 */
771 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
772
773 /* enable RTC functional clock */
774 if (rtc->type->has_32kclk_en) {
775 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
776 rtc_writel(rtc, OMAP_RTC_OSC_REG,
777 reg | OMAP_RTC_OSC_32KCLK_EN);
778 }
779
780 /* clear old status */
781 reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
782
783 mask = OMAP_RTC_STATUS_ALARM;
784
785 if (rtc->type->has_pmic_mode)
786 mask |= OMAP_RTC_STATUS_ALARM2;
787
788 if (rtc->type->has_power_up_reset) {
789 mask |= OMAP_RTC_STATUS_POWER_UP;
790 if (reg & OMAP_RTC_STATUS_POWER_UP)
791 dev_info(&pdev->dev, "RTC power up reset detected\n");
792 }
793
794 if (reg & mask)
795 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
796
797 /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
798 reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
799 if (reg & OMAP_RTC_CTRL_STOP)
800 dev_info(&pdev->dev, "already running\n");
801
802 /* force to 24 hour mode */
803 new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
804 new_ctrl |= OMAP_RTC_CTRL_STOP;
805
806 /*
807 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
808 *
809 * - Device wake-up capability setting should come through chip
810 * init logic. OMAP1 boards should initialize the "wakeup capable"
811 * flag in the platform device if the board is wired right for
812 * being woken up by RTC alarm. For OMAP-L138, this capability
813 * is built into the SoC by the "Deep Sleep" capability.
814 *
815 * - Boards wired so RTC_ON_nOFF is used as the reset signal,
816 * rather than nPWRON_RESET, should forcibly enable split
817 * power mode. (Some chip errata report that RTC_CTRL_SPLIT
818 * is write-only, and always reads as zero...)
819 */
820
821 if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
822 dev_info(&pdev->dev, "split power mode\n");
823
824 if (reg != new_ctrl)
825 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
826
827 /*
828 * If we have the external clock then switch to it so we can keep
829 * ticking across suspend.
830 */
831 if (rtc->has_ext_clk) {
832 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
833 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
834 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
835 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
836 }
837
838 rtc->type->lock(rtc);
839
840 device_init_wakeup(&pdev->dev, true);
841
842 rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
843 if (IS_ERR(rtc->rtc)) {
844 ret = PTR_ERR(rtc->rtc);
845 goto err;
846 }
847
848 rtc->rtc->ops = &omap_rtc_ops;
849 omap_rtc_nvmem_config.priv = rtc;
850
851 /* handle periodic and alarm irqs */
852 ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
853 dev_name(&rtc->rtc->dev), rtc);
854 if (ret)
855 goto err;
856
857 if (rtc->irq_timer != rtc->irq_alarm) {
858 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
859 dev_name(&rtc->rtc->dev), rtc);
860 if (ret)
861 goto err;
862 }
863
864 if (rtc->is_pmic_controller) {
865 if (!pm_power_off) {
866 omap_rtc_power_off_rtc = rtc;
867 pm_power_off = omap_rtc_power_off;
868 }
869 }
870
871 /* Support ext_wakeup pinconf */
872 rtc_pinctrl_desc.name = dev_name(&pdev->dev);
873
874 rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
875 if (IS_ERR(rtc->pctldev)) {
876 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
877 ret = PTR_ERR(rtc->pctldev);
878 goto err;
879 }
880
881 ret = rtc_register_device(rtc->rtc);
882 if (ret)
883 goto err;
884
885 rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
886
887 return 0;
888
889err:
890 clk_disable_unprepare(rtc->clk);
891 device_init_wakeup(&pdev->dev, false);
892 rtc->type->lock(rtc);
893 pm_runtime_put_sync(&pdev->dev);
894 pm_runtime_disable(&pdev->dev);
895
896 return ret;
897}
898
899static int omap_rtc_remove(struct platform_device *pdev)
900{
901 struct omap_rtc *rtc = platform_get_drvdata(pdev);
902 u8 reg;
903
904 if (pm_power_off == omap_rtc_power_off &&
905 omap_rtc_power_off_rtc == rtc) {
906 pm_power_off = NULL;
907 omap_rtc_power_off_rtc = NULL;
908 }
909
910 device_init_wakeup(&pdev->dev, 0);
911
912 if (!IS_ERR(rtc->clk))
913 clk_disable_unprepare(rtc->clk);
914
915 rtc->type->unlock(rtc);
916 /* leave rtc running, but disable irqs */
917 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
918
919 if (rtc->has_ext_clk) {
920 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
921 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
922 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
923 }
924
925 rtc->type->lock(rtc);
926
927 /* Disable the clock/module */
928 pm_runtime_put_sync(&pdev->dev);
929 pm_runtime_disable(&pdev->dev);
930
931 /* Remove ext_wakeup pinconf */
932 pinctrl_unregister(rtc->pctldev);
933
934 return 0;
935}
936
937static int __maybe_unused omap_rtc_suspend(struct device *dev)
938{
939 struct omap_rtc *rtc = dev_get_drvdata(dev);
940
941 rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
942
943 rtc->type->unlock(rtc);
944 /*
945 * FIXME: the RTC alarm is not currently acting as a wakeup event
946 * source on some platforms, and in fact this enable() call is just
947 * saving a flag that's never used...
948 */
949 if (device_may_wakeup(dev))
950 enable_irq_wake(rtc->irq_alarm);
951 else
952 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
953 rtc->type->lock(rtc);
954
955 rtc->is_suspending = true;
956
957 return 0;
958}
959
960static int __maybe_unused omap_rtc_resume(struct device *dev)
961{
962 struct omap_rtc *rtc = dev_get_drvdata(dev);
963
964 rtc->type->unlock(rtc);
965 if (device_may_wakeup(dev))
966 disable_irq_wake(rtc->irq_alarm);
967 else
968 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
969 rtc->type->lock(rtc);
970
971 rtc->is_suspending = false;
972
973 return 0;
974}
975
976static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
977{
978 struct omap_rtc *rtc = dev_get_drvdata(dev);
979
980 if (rtc->is_suspending && !rtc->has_ext_clk)
981 return -EBUSY;
982
983 return 0;
984}
985
986static const struct dev_pm_ops omap_rtc_pm_ops = {
987 SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
988 SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
989};
990
991static void omap_rtc_shutdown(struct platform_device *pdev)
992{
993 struct omap_rtc *rtc = platform_get_drvdata(pdev);
994 u8 mask;
995
996 /*
997 * Keep the ALARM interrupt enabled to allow the system to power up on
998 * alarm events.
999 */
1000 rtc->type->unlock(rtc);
1001 mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
1002 mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
1003 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
1004 rtc->type->lock(rtc);
1005}
1006
1007static struct platform_driver omap_rtc_driver = {
1008 .probe = omap_rtc_probe,
1009 .remove = omap_rtc_remove,
1010 .shutdown = omap_rtc_shutdown,
1011 .driver = {
1012 .name = "omap_rtc",
1013 .pm = &omap_rtc_pm_ops,
1014 .of_match_table = omap_rtc_of_match,
1015 },
1016 .id_table = omap_rtc_id_table,
1017};
1018
1019module_platform_driver(omap_rtc_driver);
1020
1021MODULE_ALIAS("platform:omap_rtc");
1022MODULE_AUTHOR("George G. Davis (and others)");
1023MODULE_LICENSE("GPL");