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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI Driver for Microchip MCP795 RTC
4 *
5 * Copyright (C) Josef Gajdusek <atx@atx.name>
6 *
7 * based on other Linux RTC drivers
8 *
9 * Device datasheet:
10 * https://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/device.h>
16#include <linux/printk.h>
17#include <linux/spi/spi.h>
18#include <linux/rtc.h>
19#include <linux/of.h>
20#include <linux/bcd.h>
21#include <linux/delay.h>
22
23/* MCP795 Instructions, see datasheet table 3-1 */
24#define MCP795_EEREAD 0x03
25#define MCP795_EEWRITE 0x02
26#define MCP795_EEWRDI 0x04
27#define MCP795_EEWREN 0x06
28#define MCP795_SRREAD 0x05
29#define MCP795_SRWRITE 0x01
30#define MCP795_READ 0x13
31#define MCP795_WRITE 0x12
32#define MCP795_UNLOCK 0x14
33#define MCP795_IDWRITE 0x32
34#define MCP795_IDREAD 0x33
35#define MCP795_CLRWDT 0x44
36#define MCP795_CLRRAM 0x54
37
38/* MCP795 RTCC registers, see datasheet table 4-1 */
39#define MCP795_REG_SECONDS 0x01
40#define MCP795_REG_DAY 0x04
41#define MCP795_REG_MONTH 0x06
42#define MCP795_REG_CONTROL 0x08
43#define MCP795_REG_ALM0_SECONDS 0x0C
44#define MCP795_REG_ALM0_DAY 0x0F
45
46#define MCP795_ST_BIT BIT(7)
47#define MCP795_24_BIT BIT(6)
48#define MCP795_LP_BIT BIT(5)
49#define MCP795_EXTOSC_BIT BIT(3)
50#define MCP795_OSCON_BIT BIT(5)
51#define MCP795_ALM0_BIT BIT(4)
52#define MCP795_ALM1_BIT BIT(5)
53#define MCP795_ALM0IF_BIT BIT(3)
54#define MCP795_ALM0C0_BIT BIT(4)
55#define MCP795_ALM0C1_BIT BIT(5)
56#define MCP795_ALM0C2_BIT BIT(6)
57
58#define SEC_PER_DAY (24 * 60 * 60)
59
60static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
61{
62 struct spi_device *spi = to_spi_device(dev);
63 int ret;
64 u8 tx[2];
65
66 tx[0] = MCP795_READ;
67 tx[1] = addr;
68 ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
69
70 if (ret)
71 dev_err(dev, "Failed reading %d bytes from address %x.\n",
72 count, addr);
73
74 return ret;
75}
76
77static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
78{
79 struct spi_device *spi = to_spi_device(dev);
80 int ret;
81 u8 tx[257];
82
83 tx[0] = MCP795_WRITE;
84 tx[1] = addr;
85 memcpy(&tx[2], data, count);
86
87 ret = spi_write(spi, tx, 2 + count);
88
89 if (ret)
90 dev_err(dev, "Failed to write %d bytes to address %x.\n",
91 count, addr);
92
93 return ret;
94}
95
96static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
97{
98 int ret;
99 u8 tmp;
100
101 ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
102 if (ret)
103 return ret;
104
105 if ((tmp & mask) != state) {
106 tmp = (tmp & ~mask) | state;
107 ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
108 }
109
110 return ret;
111}
112
113static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
114{
115 int retries = 5;
116 int ret;
117 u8 data;
118
119 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
120 if (ret)
121 return ret;
122 ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
123 if (ret)
124 return ret;
125 *extosc = !!(data & MCP795_EXTOSC_BIT);
126 ret = mcp795_rtcc_set_bits(
127 dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
128 if (ret)
129 return ret;
130 /* wait for the OSCON bit to clear */
131 do {
132 usleep_range(700, 800);
133 ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
134 if (ret)
135 break;
136 if (!(data & MCP795_OSCON_BIT))
137 break;
138
139 } while (--retries);
140
141 return !retries ? -EIO : ret;
142}
143
144static int mcp795_start_oscillator(struct device *dev, bool *extosc)
145{
146 if (extosc) {
147 u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
148 int ret;
149
150 ret = mcp795_rtcc_set_bits(
151 dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
152 if (ret)
153 return ret;
154 }
155 return mcp795_rtcc_set_bits(
156 dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
157}
158
159/* Enable or disable Alarm 0 in RTC */
160static int mcp795_update_alarm(struct device *dev, bool enable)
161{
162 int ret;
163
164 dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
165
166 if (enable) {
167 /* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
168 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
169 MCP795_ALM0IF_BIT, 0);
170 if (ret)
171 return ret;
172 /* enable alarm 0 */
173 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
174 MCP795_ALM0_BIT, MCP795_ALM0_BIT);
175 } else {
176 /* disable alarm 0 and alarm 1 */
177 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
178 MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
179 }
180 return ret;
181}
182
183static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
184{
185 int ret;
186 u8 data[7];
187 bool extosc;
188
189 /* Stop RTC and store current value of EXTOSC bit */
190 ret = mcp795_stop_oscillator(dev, &extosc);
191 if (ret)
192 return ret;
193
194 /* Read first, so we can leave config bits untouched */
195 ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
196
197 if (ret)
198 return ret;
199
200 data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
201 data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
202 data[2] = bin2bcd(tim->tm_hour);
203 data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
204 data[4] = bin2bcd(tim->tm_mday);
205 data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
206
207 if (tim->tm_year > 100)
208 tim->tm_year -= 100;
209
210 data[6] = bin2bcd(tim->tm_year);
211
212 /* Always write the date and month using a separate Write command.
213 * This is a workaround for a know silicon issue that some combinations
214 * of date and month values may result in the date being reset to 1.
215 */
216 ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
217 if (ret)
218 return ret;
219
220 ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
221 if (ret)
222 return ret;
223
224 /* Start back RTC and restore previous value of EXTOSC bit.
225 * There is no need to clear EXTOSC bit when the previous value was 0
226 * because it was already cleared when stopping the RTC oscillator.
227 */
228 ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
229 if (ret)
230 return ret;
231
232 dev_dbg(dev, "Set mcp795: %ptR\n", tim);
233
234 return 0;
235}
236
237static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
238{
239 int ret;
240 u8 data[7];
241
242 ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
243
244 if (ret)
245 return ret;
246
247 tim->tm_sec = bcd2bin(data[0] & 0x7F);
248 tim->tm_min = bcd2bin(data[1] & 0x7F);
249 tim->tm_hour = bcd2bin(data[2] & 0x3F);
250 tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
251 tim->tm_mday = bcd2bin(data[4] & 0x3F);
252 tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
253 tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
254
255 dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
256
257 return 0;
258}
259
260static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
261{
262 struct rtc_time now_tm;
263 time64_t now;
264 time64_t later;
265 u8 tmp[6];
266 int ret;
267
268 /* Read current time from RTC hardware */
269 ret = mcp795_read_time(dev, &now_tm);
270 if (ret)
271 return ret;
272 /* Get the number of seconds since 1970 */
273 now = rtc_tm_to_time64(&now_tm);
274 later = rtc_tm_to_time64(&alm->time);
275 if (later <= now)
276 return -EINVAL;
277 /* make sure alarm fires within the next one year */
278 if ((later - now) >=
279 (SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
280 return -EDOM;
281 /* disable alarm */
282 ret = mcp795_update_alarm(dev, false);
283 if (ret)
284 return ret;
285 /* Read registers, so we can leave configuration bits untouched */
286 ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
287 if (ret)
288 return ret;
289
290 alm->time.tm_year = -1;
291 alm->time.tm_isdst = -1;
292 alm->time.tm_yday = -1;
293
294 tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
295 tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
296 tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
297 tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
298 /* set alarm match: seconds, minutes, hour, day, date and month */
299 tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
300 tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
301 tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
302
303 ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
304 if (ret)
305 return ret;
306
307 /* enable alarm if requested */
308 if (alm->enabled) {
309 ret = mcp795_update_alarm(dev, true);
310 if (ret)
311 return ret;
312 dev_dbg(dev, "Alarm IRQ armed\n");
313 }
314 dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
315 &alm->time, alm->time.tm_wday, &alm->time);
316 return 0;
317}
318
319static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
320{
321 u8 data[6];
322 int ret;
323
324 ret = mcp795_rtcc_read(
325 dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
326 if (ret)
327 return ret;
328
329 alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
330 alm->time.tm_min = bcd2bin(data[1] & 0x7F);
331 alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
332 alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
333 alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
334 alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
335 alm->time.tm_year = -1;
336 alm->time.tm_isdst = -1;
337 alm->time.tm_yday = -1;
338
339 dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
340 &alm->time, alm->time.tm_wday, &alm->time);
341 return 0;
342}
343
344static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
345{
346 return mcp795_update_alarm(dev, !!enabled);
347}
348
349static irqreturn_t mcp795_irq(int irq, void *data)
350{
351 struct spi_device *spi = data;
352 struct rtc_device *rtc = spi_get_drvdata(spi);
353 int ret;
354
355 rtc_lock(rtc);
356
357 /* Disable alarm.
358 * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
359 * because it is done every time when alarm is enabled.
360 */
361 ret = mcp795_update_alarm(&spi->dev, false);
362 if (ret)
363 dev_err(&spi->dev,
364 "Failed to disable alarm in IRQ (ret=%d)\n", ret);
365 rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
366
367 rtc_unlock(rtc);
368
369 return IRQ_HANDLED;
370}
371
372static const struct rtc_class_ops mcp795_rtc_ops = {
373 .read_time = mcp795_read_time,
374 .set_time = mcp795_set_time,
375 .read_alarm = mcp795_read_alarm,
376 .set_alarm = mcp795_set_alarm,
377 .alarm_irq_enable = mcp795_alarm_irq_enable
378};
379
380static int mcp795_probe(struct spi_device *spi)
381{
382 struct rtc_device *rtc;
383 int ret;
384
385 spi->mode = SPI_MODE_0;
386 spi->bits_per_word = 8;
387 ret = spi_setup(spi);
388 if (ret) {
389 dev_err(&spi->dev, "Unable to setup SPI\n");
390 return ret;
391 }
392
393 /* Start the oscillator but don't set the value of EXTOSC bit */
394 mcp795_start_oscillator(&spi->dev, NULL);
395 /* Clear the 12 hour mode flag*/
396 mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
397
398 rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
399 &mcp795_rtc_ops, THIS_MODULE);
400 if (IS_ERR(rtc))
401 return PTR_ERR(rtc);
402
403 spi_set_drvdata(spi, rtc);
404
405 if (spi->irq > 0) {
406 dev_dbg(&spi->dev, "Alarm support enabled\n");
407
408 /* Clear any pending alarm (ALM0IF bit) before requesting
409 * the interrupt.
410 */
411 mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
412 MCP795_ALM0IF_BIT, 0);
413 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
414 mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
415 dev_name(&rtc->dev), spi);
416 if (ret)
417 dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
418 spi->irq, ret);
419 else
420 device_init_wakeup(&spi->dev, true);
421 }
422 return 0;
423}
424
425#ifdef CONFIG_OF
426static const struct of_device_id mcp795_of_match[] = {
427 { .compatible = "maxim,mcp795" },
428 { }
429};
430MODULE_DEVICE_TABLE(of, mcp795_of_match);
431#endif
432
433static const struct spi_device_id mcp795_spi_ids[] = {
434 { .name = "mcp795" },
435 { }
436};
437MODULE_DEVICE_TABLE(spi, mcp795_spi_ids);
438
439static struct spi_driver mcp795_driver = {
440 .driver = {
441 .name = "rtc-mcp795",
442 .of_match_table = of_match_ptr(mcp795_of_match),
443 },
444 .probe = mcp795_probe,
445 .id_table = mcp795_spi_ids,
446};
447
448module_spi_driver(mcp795_driver);
449
450MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
451MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
452MODULE_LICENSE("GPL");
1/*
2 * SPI Driver for Microchip MCP795 RTC
3 *
4 * Copyright (C) Josef Gajdusek <atx@atx.name>
5 *
6 * based on other Linux RTC drivers
7 *
8 * Device datasheet:
9 * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/printk.h>
21#include <linux/spi/spi.h>
22#include <linux/rtc.h>
23#include <linux/of.h>
24#include <linux/bcd.h>
25#include <linux/delay.h>
26
27/* MCP795 Instructions, see datasheet table 3-1 */
28#define MCP795_EEREAD 0x03
29#define MCP795_EEWRITE 0x02
30#define MCP795_EEWRDI 0x04
31#define MCP795_EEWREN 0x06
32#define MCP795_SRREAD 0x05
33#define MCP795_SRWRITE 0x01
34#define MCP795_READ 0x13
35#define MCP795_WRITE 0x12
36#define MCP795_UNLOCK 0x14
37#define MCP795_IDWRITE 0x32
38#define MCP795_IDREAD 0x33
39#define MCP795_CLRWDT 0x44
40#define MCP795_CLRRAM 0x54
41
42/* MCP795 RTCC registers, see datasheet table 4-1 */
43#define MCP795_REG_SECONDS 0x01
44#define MCP795_REG_DAY 0x04
45#define MCP795_REG_MONTH 0x06
46#define MCP795_REG_CONTROL 0x08
47#define MCP795_REG_ALM0_SECONDS 0x0C
48#define MCP795_REG_ALM0_DAY 0x0F
49
50#define MCP795_ST_BIT BIT(7)
51#define MCP795_24_BIT BIT(6)
52#define MCP795_LP_BIT BIT(5)
53#define MCP795_EXTOSC_BIT BIT(3)
54#define MCP795_OSCON_BIT BIT(5)
55#define MCP795_ALM0_BIT BIT(4)
56#define MCP795_ALM1_BIT BIT(5)
57#define MCP795_ALM0IF_BIT BIT(3)
58#define MCP795_ALM0C0_BIT BIT(4)
59#define MCP795_ALM0C1_BIT BIT(5)
60#define MCP795_ALM0C2_BIT BIT(6)
61
62#define SEC_PER_DAY (24 * 60 * 60)
63
64static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
65{
66 struct spi_device *spi = to_spi_device(dev);
67 int ret;
68 u8 tx[2];
69
70 tx[0] = MCP795_READ;
71 tx[1] = addr;
72 ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
73
74 if (ret)
75 dev_err(dev, "Failed reading %d bytes from address %x.\n",
76 count, addr);
77
78 return ret;
79}
80
81static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
82{
83 struct spi_device *spi = to_spi_device(dev);
84 int ret;
85 u8 tx[257];
86
87 tx[0] = MCP795_WRITE;
88 tx[1] = addr;
89 memcpy(&tx[2], data, count);
90
91 ret = spi_write(spi, tx, 2 + count);
92
93 if (ret)
94 dev_err(dev, "Failed to write %d bytes to address %x.\n",
95 count, addr);
96
97 return ret;
98}
99
100static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
101{
102 int ret;
103 u8 tmp;
104
105 ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
106 if (ret)
107 return ret;
108
109 if ((tmp & mask) != state) {
110 tmp = (tmp & ~mask) | state;
111 ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
112 }
113
114 return ret;
115}
116
117static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
118{
119 int retries = 5;
120 int ret;
121 u8 data;
122
123 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
124 if (ret)
125 return ret;
126 ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
127 if (ret)
128 return ret;
129 *extosc = !!(data & MCP795_EXTOSC_BIT);
130 ret = mcp795_rtcc_set_bits(
131 dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
132 if (ret)
133 return ret;
134 /* wait for the OSCON bit to clear */
135 do {
136 usleep_range(700, 800);
137 ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
138 if (ret)
139 break;
140 if (!(data & MCP795_OSCON_BIT))
141 break;
142
143 } while (--retries);
144
145 return !retries ? -EIO : ret;
146}
147
148static int mcp795_start_oscillator(struct device *dev, bool *extosc)
149{
150 if (extosc) {
151 u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
152 int ret;
153
154 ret = mcp795_rtcc_set_bits(
155 dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
156 if (ret)
157 return ret;
158 }
159 return mcp795_rtcc_set_bits(
160 dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
161}
162
163/* Enable or disable Alarm 0 in RTC */
164static int mcp795_update_alarm(struct device *dev, bool enable)
165{
166 int ret;
167
168 dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
169
170 if (enable) {
171 /* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
172 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
173 MCP795_ALM0IF_BIT, 0);
174 if (ret)
175 return ret;
176 /* enable alarm 0 */
177 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
178 MCP795_ALM0_BIT, MCP795_ALM0_BIT);
179 } else {
180 /* disable alarm 0 and alarm 1 */
181 ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
182 MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
183 }
184 return ret;
185}
186
187static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
188{
189 int ret;
190 u8 data[7];
191 bool extosc;
192
193 /* Stop RTC and store current value of EXTOSC bit */
194 ret = mcp795_stop_oscillator(dev, &extosc);
195 if (ret)
196 return ret;
197
198 /* Read first, so we can leave config bits untouched */
199 ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
200
201 if (ret)
202 return ret;
203
204 data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
205 data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
206 data[2] = bin2bcd(tim->tm_hour);
207 data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
208 data[4] = bin2bcd(tim->tm_mday);
209 data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
210
211 if (tim->tm_year > 100)
212 tim->tm_year -= 100;
213
214 data[6] = bin2bcd(tim->tm_year);
215
216 /* Always write the date and month using a separate Write command.
217 * This is a workaround for a know silicon issue that some combinations
218 * of date and month values may result in the date being reset to 1.
219 */
220 ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
221 if (ret)
222 return ret;
223
224 ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
225 if (ret)
226 return ret;
227
228 /* Start back RTC and restore previous value of EXTOSC bit.
229 * There is no need to clear EXTOSC bit when the previous value was 0
230 * because it was already cleared when stopping the RTC oscillator.
231 */
232 ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
233 if (ret)
234 return ret;
235
236 dev_dbg(dev, "Set mcp795: %04d-%02d-%02d(%d) %02d:%02d:%02d\n",
237 tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
238 tim->tm_wday, tim->tm_hour, tim->tm_min, tim->tm_sec);
239
240 return 0;
241}
242
243static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
244{
245 int ret;
246 u8 data[7];
247
248 ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
249
250 if (ret)
251 return ret;
252
253 tim->tm_sec = bcd2bin(data[0] & 0x7F);
254 tim->tm_min = bcd2bin(data[1] & 0x7F);
255 tim->tm_hour = bcd2bin(data[2] & 0x3F);
256 tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
257 tim->tm_mday = bcd2bin(data[4] & 0x3F);
258 tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
259 tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
260
261 dev_dbg(dev, "Read from mcp795: %04d-%02d-%02d(%d) %02d:%02d:%02d\n",
262 tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
263 tim->tm_wday, tim->tm_hour, tim->tm_min, tim->tm_sec);
264
265 return 0;
266}
267
268static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
269{
270 struct rtc_time now_tm;
271 time64_t now;
272 time64_t later;
273 u8 tmp[6];
274 int ret;
275
276 /* Read current time from RTC hardware */
277 ret = mcp795_read_time(dev, &now_tm);
278 if (ret)
279 return ret;
280 /* Get the number of seconds since 1970 */
281 now = rtc_tm_to_time64(&now_tm);
282 later = rtc_tm_to_time64(&alm->time);
283 if (later <= now)
284 return -EINVAL;
285 /* make sure alarm fires within the next one year */
286 if ((later - now) >=
287 (SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
288 return -EDOM;
289 /* disable alarm */
290 ret = mcp795_update_alarm(dev, false);
291 if (ret)
292 return ret;
293 /* Read registers, so we can leave configuration bits untouched */
294 ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
295 if (ret)
296 return ret;
297
298 alm->time.tm_year = -1;
299 alm->time.tm_isdst = -1;
300 alm->time.tm_yday = -1;
301
302 tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
303 tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
304 tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
305 tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
306 /* set alarm match: seconds, minutes, hour, day, date and month */
307 tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
308 tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
309 tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
310
311 ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
312 if (ret)
313 return ret;
314
315 /* enable alarm if requested */
316 if (alm->enabled) {
317 ret = mcp795_update_alarm(dev, true);
318 if (ret)
319 return ret;
320 dev_dbg(dev, "Alarm IRQ armed\n");
321 }
322 dev_dbg(dev, "Set alarm: %02d-%02d(%d) %02d:%02d:%02d\n",
323 alm->time.tm_mon, alm->time.tm_mday, alm->time.tm_wday,
324 alm->time.tm_hour, alm->time.tm_min, alm->time.tm_sec);
325 return 0;
326}
327
328static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
329{
330 u8 data[6];
331 int ret;
332
333 ret = mcp795_rtcc_read(
334 dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
335 if (ret)
336 return ret;
337
338 alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
339 alm->time.tm_min = bcd2bin(data[1] & 0x7F);
340 alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
341 alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
342 alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
343 alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
344 alm->time.tm_year = -1;
345 alm->time.tm_isdst = -1;
346 alm->time.tm_yday = -1;
347
348 dev_dbg(dev, "Read alarm: %02d-%02d(%d) %02d:%02d:%02d\n",
349 alm->time.tm_mon, alm->time.tm_mday, alm->time.tm_wday,
350 alm->time.tm_hour, alm->time.tm_min, alm->time.tm_sec);
351 return 0;
352}
353
354static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
355{
356 return mcp795_update_alarm(dev, !!enabled);
357}
358
359static irqreturn_t mcp795_irq(int irq, void *data)
360{
361 struct spi_device *spi = data;
362 struct rtc_device *rtc = spi_get_drvdata(spi);
363 struct mutex *lock = &rtc->ops_lock;
364 int ret;
365
366 mutex_lock(lock);
367
368 /* Disable alarm.
369 * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
370 * because it is done every time when alarm is enabled.
371 */
372 ret = mcp795_update_alarm(&spi->dev, false);
373 if (ret)
374 dev_err(&spi->dev,
375 "Failed to disable alarm in IRQ (ret=%d)\n", ret);
376 rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
377
378 mutex_unlock(lock);
379
380 return IRQ_HANDLED;
381}
382
383static const struct rtc_class_ops mcp795_rtc_ops = {
384 .read_time = mcp795_read_time,
385 .set_time = mcp795_set_time,
386 .read_alarm = mcp795_read_alarm,
387 .set_alarm = mcp795_set_alarm,
388 .alarm_irq_enable = mcp795_alarm_irq_enable
389};
390
391static int mcp795_probe(struct spi_device *spi)
392{
393 struct rtc_device *rtc;
394 int ret;
395
396 spi->mode = SPI_MODE_0;
397 spi->bits_per_word = 8;
398 ret = spi_setup(spi);
399 if (ret) {
400 dev_err(&spi->dev, "Unable to setup SPI\n");
401 return ret;
402 }
403
404 /* Start the oscillator but don't set the value of EXTOSC bit */
405 mcp795_start_oscillator(&spi->dev, NULL);
406 /* Clear the 12 hour mode flag*/
407 mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
408
409 rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
410 &mcp795_rtc_ops, THIS_MODULE);
411 if (IS_ERR(rtc))
412 return PTR_ERR(rtc);
413
414 spi_set_drvdata(spi, rtc);
415
416 if (spi->irq > 0) {
417 dev_dbg(&spi->dev, "Alarm support enabled\n");
418
419 /* Clear any pending alarm (ALM0IF bit) before requesting
420 * the interrupt.
421 */
422 mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
423 MCP795_ALM0IF_BIT, 0);
424 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
425 mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
426 dev_name(&rtc->dev), spi);
427 if (ret)
428 dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
429 spi->irq, ret);
430 else
431 device_init_wakeup(&spi->dev, true);
432 }
433 return 0;
434}
435
436#ifdef CONFIG_OF
437static const struct of_device_id mcp795_of_match[] = {
438 { .compatible = "maxim,mcp795" },
439 { }
440};
441MODULE_DEVICE_TABLE(of, mcp795_of_match);
442#endif
443
444static struct spi_driver mcp795_driver = {
445 .driver = {
446 .name = "rtc-mcp795",
447 .of_match_table = of_match_ptr(mcp795_of_match),
448 },
449 .probe = mcp795_probe,
450};
451
452module_spi_driver(mcp795_driver);
453
454MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
455MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
456MODULE_LICENSE("GPL");
457MODULE_ALIAS("spi:mcp795");