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1/*
2 * Intel Running Average Power Limit (RAPL) Driver
3 * Copyright (c) 2013, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.
16 *
17 */
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/types.h>
24#include <linux/device.h>
25#include <linux/slab.h>
26#include <linux/log2.h>
27#include <linux/bitmap.h>
28#include <linux/delay.h>
29#include <linux/sysfs.h>
30#include <linux/cpu.h>
31#include <linux/powercap.h>
32#include <linux/suspend.h>
33#include <asm/iosf_mbi.h>
34
35#include <asm/processor.h>
36#include <asm/cpu_device_id.h>
37#include <asm/intel-family.h>
38
39/* Local defines */
40#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
41
42/* bitmasks for RAPL MSRs, used by primitive access functions */
43#define ENERGY_STATUS_MASK 0xffffffff
44
45#define POWER_LIMIT1_MASK 0x7FFF
46#define POWER_LIMIT1_ENABLE BIT(15)
47#define POWER_LIMIT1_CLAMP BIT(16)
48
49#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
50#define POWER_LIMIT2_ENABLE BIT_ULL(47)
51#define POWER_LIMIT2_CLAMP BIT_ULL(48)
52#define POWER_PACKAGE_LOCK BIT_ULL(63)
53#define POWER_PP_LOCK BIT(31)
54
55#define TIME_WINDOW1_MASK (0x7FULL<<17)
56#define TIME_WINDOW2_MASK (0x7FULL<<49)
57
58#define POWER_UNIT_OFFSET 0
59#define POWER_UNIT_MASK 0x0F
60
61#define ENERGY_UNIT_OFFSET 0x08
62#define ENERGY_UNIT_MASK 0x1F00
63
64#define TIME_UNIT_OFFSET 0x10
65#define TIME_UNIT_MASK 0xF0000
66
67#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
68#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
69#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
70#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
71
72#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
73#define PP_POLICY_MASK 0x1F
74
75/* Non HW constants */
76#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
77#define RAPL_PRIMITIVE_DUMMY BIT(2)
78
79#define TIME_WINDOW_MAX_MSEC 40000
80#define TIME_WINDOW_MIN_MSEC 250
81#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
82enum unit_type {
83 ARBITRARY_UNIT, /* no translation */
84 POWER_UNIT,
85 ENERGY_UNIT,
86 TIME_UNIT,
87};
88
89enum rapl_domain_type {
90 RAPL_DOMAIN_PACKAGE, /* entire package/socket */
91 RAPL_DOMAIN_PP0, /* core power plane */
92 RAPL_DOMAIN_PP1, /* graphics uncore */
93 RAPL_DOMAIN_DRAM,/* DRAM control_type */
94 RAPL_DOMAIN_PLATFORM, /* PSys control_type */
95 RAPL_DOMAIN_MAX,
96};
97
98enum rapl_domain_msr_id {
99 RAPL_DOMAIN_MSR_LIMIT,
100 RAPL_DOMAIN_MSR_STATUS,
101 RAPL_DOMAIN_MSR_PERF,
102 RAPL_DOMAIN_MSR_POLICY,
103 RAPL_DOMAIN_MSR_INFO,
104 RAPL_DOMAIN_MSR_MAX,
105};
106
107/* per domain data, some are optional */
108enum rapl_primitives {
109 ENERGY_COUNTER,
110 POWER_LIMIT1,
111 POWER_LIMIT2,
112 FW_LOCK,
113
114 PL1_ENABLE, /* power limit 1, aka long term */
115 PL1_CLAMP, /* allow frequency to go below OS request */
116 PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
117 PL2_CLAMP,
118
119 TIME_WINDOW1, /* long term */
120 TIME_WINDOW2, /* short term */
121 THERMAL_SPEC_POWER,
122 MAX_POWER,
123
124 MIN_POWER,
125 MAX_TIME_WINDOW,
126 THROTTLED_TIME,
127 PRIORITY_LEVEL,
128
129 /* below are not raw primitive data */
130 AVERAGE_POWER,
131 NR_RAPL_PRIMITIVES,
132};
133
134#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
135
136/* Can be expanded to include events, etc.*/
137struct rapl_domain_data {
138 u64 primitives[NR_RAPL_PRIMITIVES];
139 unsigned long timestamp;
140};
141
142struct msrl_action {
143 u32 msr_no;
144 u64 clear_mask;
145 u64 set_mask;
146 int err;
147};
148
149#define DOMAIN_STATE_INACTIVE BIT(0)
150#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
151#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
152
153#define NR_POWER_LIMITS (2)
154struct rapl_power_limit {
155 struct powercap_zone_constraint *constraint;
156 int prim_id; /* primitive ID used to enable */
157 struct rapl_domain *domain;
158 const char *name;
159 u64 last_power_limit;
160};
161
162static const char pl1_name[] = "long_term";
163static const char pl2_name[] = "short_term";
164
165struct rapl_package;
166struct rapl_domain {
167 const char *name;
168 enum rapl_domain_type id;
169 int msrs[RAPL_DOMAIN_MSR_MAX];
170 struct powercap_zone power_zone;
171 struct rapl_domain_data rdd;
172 struct rapl_power_limit rpl[NR_POWER_LIMITS];
173 u64 attr_map; /* track capabilities */
174 unsigned int state;
175 unsigned int domain_energy_unit;
176 struct rapl_package *rp;
177};
178#define power_zone_to_rapl_domain(_zone) \
179 container_of(_zone, struct rapl_domain, power_zone)
180
181
182/* Each physical package contains multiple domains, these are the common
183 * data across RAPL domains within a package.
184 */
185struct rapl_package {
186 unsigned int id; /* physical package/socket id */
187 unsigned int nr_domains;
188 unsigned long domain_map; /* bit map of active domains */
189 unsigned int power_unit;
190 unsigned int energy_unit;
191 unsigned int time_unit;
192 struct rapl_domain *domains; /* array of domains, sized at runtime */
193 struct powercap_zone *power_zone; /* keep track of parent zone */
194 unsigned long power_limit_irq; /* keep track of package power limit
195 * notify interrupt enable status.
196 */
197 struct list_head plist;
198 int lead_cpu; /* one active cpu per package for access */
199 /* Track active cpus */
200 struct cpumask cpumask;
201};
202
203struct rapl_defaults {
204 u8 floor_freq_reg_addr;
205 int (*check_unit)(struct rapl_package *rp, int cpu);
206 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
207 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
208 bool to_raw);
209 unsigned int dram_domain_energy_unit;
210};
211static struct rapl_defaults *rapl_defaults;
212
213/* Sideband MBI registers */
214#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
215#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
216
217#define PACKAGE_PLN_INT_SAVED BIT(0)
218#define MAX_PRIM_NAME (32)
219
220/* per domain data. used to describe individual knobs such that access function
221 * can be consolidated into one instead of many inline functions.
222 */
223struct rapl_primitive_info {
224 const char *name;
225 u64 mask;
226 int shift;
227 enum rapl_domain_msr_id id;
228 enum unit_type unit;
229 u32 flag;
230};
231
232#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
233 .name = #p, \
234 .mask = m, \
235 .shift = s, \
236 .id = i, \
237 .unit = u, \
238 .flag = f \
239 }
240
241static void rapl_init_domains(struct rapl_package *rp);
242static int rapl_read_data_raw(struct rapl_domain *rd,
243 enum rapl_primitives prim,
244 bool xlate, u64 *data);
245static int rapl_write_data_raw(struct rapl_domain *rd,
246 enum rapl_primitives prim,
247 unsigned long long value);
248static u64 rapl_unit_xlate(struct rapl_domain *rd,
249 enum unit_type type, u64 value,
250 int to_raw);
251static void package_power_limit_irq_save(struct rapl_package *rp);
252
253static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
254
255static const char * const rapl_domain_names[] = {
256 "package",
257 "core",
258 "uncore",
259 "dram",
260 "psys",
261};
262
263static struct powercap_control_type *control_type; /* PowerCap Controller */
264static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
265
266/* caller to ensure CPU hotplug lock is held */
267static struct rapl_package *find_package_by_id(int id)
268{
269 struct rapl_package *rp;
270
271 list_for_each_entry(rp, &rapl_packages, plist) {
272 if (rp->id == id)
273 return rp;
274 }
275
276 return NULL;
277}
278
279static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
280{
281 struct rapl_domain *rd;
282 u64 energy_now;
283
284 /* prevent CPU hotplug, make sure the RAPL domain does not go
285 * away while reading the counter.
286 */
287 get_online_cpus();
288 rd = power_zone_to_rapl_domain(power_zone);
289
290 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
291 *energy_raw = energy_now;
292 put_online_cpus();
293
294 return 0;
295 }
296 put_online_cpus();
297
298 return -EIO;
299}
300
301static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
302{
303 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
304
305 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
306 return 0;
307}
308
309static int release_zone(struct powercap_zone *power_zone)
310{
311 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
312 struct rapl_package *rp = rd->rp;
313
314 /* package zone is the last zone of a package, we can free
315 * memory here since all children has been unregistered.
316 */
317 if (rd->id == RAPL_DOMAIN_PACKAGE) {
318 kfree(rd);
319 rp->domains = NULL;
320 }
321
322 return 0;
323
324}
325
326static int find_nr_power_limit(struct rapl_domain *rd)
327{
328 int i, nr_pl = 0;
329
330 for (i = 0; i < NR_POWER_LIMITS; i++) {
331 if (rd->rpl[i].name)
332 nr_pl++;
333 }
334
335 return nr_pl;
336}
337
338static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
339{
340 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
341
342 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
343 return -EACCES;
344
345 get_online_cpus();
346 rapl_write_data_raw(rd, PL1_ENABLE, mode);
347 if (rapl_defaults->set_floor_freq)
348 rapl_defaults->set_floor_freq(rd, mode);
349 put_online_cpus();
350
351 return 0;
352}
353
354static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
355{
356 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
357 u64 val;
358
359 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
360 *mode = false;
361 return 0;
362 }
363 get_online_cpus();
364 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
365 put_online_cpus();
366 return -EIO;
367 }
368 *mode = val;
369 put_online_cpus();
370
371 return 0;
372}
373
374/* per RAPL domain ops, in the order of rapl_domain_type */
375static const struct powercap_zone_ops zone_ops[] = {
376 /* RAPL_DOMAIN_PACKAGE */
377 {
378 .get_energy_uj = get_energy_counter,
379 .get_max_energy_range_uj = get_max_energy_counter,
380 .release = release_zone,
381 .set_enable = set_domain_enable,
382 .get_enable = get_domain_enable,
383 },
384 /* RAPL_DOMAIN_PP0 */
385 {
386 .get_energy_uj = get_energy_counter,
387 .get_max_energy_range_uj = get_max_energy_counter,
388 .release = release_zone,
389 .set_enable = set_domain_enable,
390 .get_enable = get_domain_enable,
391 },
392 /* RAPL_DOMAIN_PP1 */
393 {
394 .get_energy_uj = get_energy_counter,
395 .get_max_energy_range_uj = get_max_energy_counter,
396 .release = release_zone,
397 .set_enable = set_domain_enable,
398 .get_enable = get_domain_enable,
399 },
400 /* RAPL_DOMAIN_DRAM */
401 {
402 .get_energy_uj = get_energy_counter,
403 .get_max_energy_range_uj = get_max_energy_counter,
404 .release = release_zone,
405 .set_enable = set_domain_enable,
406 .get_enable = get_domain_enable,
407 },
408 /* RAPL_DOMAIN_PLATFORM */
409 {
410 .get_energy_uj = get_energy_counter,
411 .get_max_energy_range_uj = get_max_energy_counter,
412 .release = release_zone,
413 .set_enable = set_domain_enable,
414 .get_enable = get_domain_enable,
415 },
416};
417
418
419/*
420 * Constraint index used by powercap can be different than power limit (PL)
421 * index in that some PLs maybe missing due to non-existant MSRs. So we
422 * need to convert here by finding the valid PLs only (name populated).
423 */
424static int contraint_to_pl(struct rapl_domain *rd, int cid)
425{
426 int i, j;
427
428 for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) {
429 if ((rd->rpl[i].name) && j++ == cid) {
430 pr_debug("%s: index %d\n", __func__, i);
431 return i;
432 }
433 }
434 pr_err("Cannot find matching power limit for constraint %d\n", cid);
435
436 return -EINVAL;
437}
438
439static int set_power_limit(struct powercap_zone *power_zone, int cid,
440 u64 power_limit)
441{
442 struct rapl_domain *rd;
443 struct rapl_package *rp;
444 int ret = 0;
445 int id;
446
447 get_online_cpus();
448 rd = power_zone_to_rapl_domain(power_zone);
449 id = contraint_to_pl(rd, cid);
450 if (id < 0) {
451 ret = id;
452 goto set_exit;
453 }
454
455 rp = rd->rp;
456
457 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
458 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
459 rd->name);
460 ret = -EACCES;
461 goto set_exit;
462 }
463
464 switch (rd->rpl[id].prim_id) {
465 case PL1_ENABLE:
466 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
467 break;
468 case PL2_ENABLE:
469 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
470 break;
471 default:
472 ret = -EINVAL;
473 }
474 if (!ret)
475 package_power_limit_irq_save(rp);
476set_exit:
477 put_online_cpus();
478 return ret;
479}
480
481static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
482 u64 *data)
483{
484 struct rapl_domain *rd;
485 u64 val;
486 int prim;
487 int ret = 0;
488 int id;
489
490 get_online_cpus();
491 rd = power_zone_to_rapl_domain(power_zone);
492 id = contraint_to_pl(rd, cid);
493 if (id < 0) {
494 ret = id;
495 goto get_exit;
496 }
497
498 switch (rd->rpl[id].prim_id) {
499 case PL1_ENABLE:
500 prim = POWER_LIMIT1;
501 break;
502 case PL2_ENABLE:
503 prim = POWER_LIMIT2;
504 break;
505 default:
506 put_online_cpus();
507 return -EINVAL;
508 }
509 if (rapl_read_data_raw(rd, prim, true, &val))
510 ret = -EIO;
511 else
512 *data = val;
513
514get_exit:
515 put_online_cpus();
516
517 return ret;
518}
519
520static int set_time_window(struct powercap_zone *power_zone, int cid,
521 u64 window)
522{
523 struct rapl_domain *rd;
524 int ret = 0;
525 int id;
526
527 get_online_cpus();
528 rd = power_zone_to_rapl_domain(power_zone);
529 id = contraint_to_pl(rd, cid);
530 if (id < 0) {
531 ret = id;
532 goto set_time_exit;
533 }
534
535 switch (rd->rpl[id].prim_id) {
536 case PL1_ENABLE:
537 rapl_write_data_raw(rd, TIME_WINDOW1, window);
538 break;
539 case PL2_ENABLE:
540 rapl_write_data_raw(rd, TIME_WINDOW2, window);
541 break;
542 default:
543 ret = -EINVAL;
544 }
545
546set_time_exit:
547 put_online_cpus();
548 return ret;
549}
550
551static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data)
552{
553 struct rapl_domain *rd;
554 u64 val;
555 int ret = 0;
556 int id;
557
558 get_online_cpus();
559 rd = power_zone_to_rapl_domain(power_zone);
560 id = contraint_to_pl(rd, cid);
561 if (id < 0) {
562 ret = id;
563 goto get_time_exit;
564 }
565
566 switch (rd->rpl[id].prim_id) {
567 case PL1_ENABLE:
568 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
569 break;
570 case PL2_ENABLE:
571 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
572 break;
573 default:
574 put_online_cpus();
575 return -EINVAL;
576 }
577 if (!ret)
578 *data = val;
579
580get_time_exit:
581 put_online_cpus();
582
583 return ret;
584}
585
586static const char *get_constraint_name(struct powercap_zone *power_zone, int cid)
587{
588 struct rapl_domain *rd;
589 int id;
590
591 rd = power_zone_to_rapl_domain(power_zone);
592 id = contraint_to_pl(rd, cid);
593 if (id >= 0)
594 return rd->rpl[id].name;
595
596 return NULL;
597}
598
599
600static int get_max_power(struct powercap_zone *power_zone, int id,
601 u64 *data)
602{
603 struct rapl_domain *rd;
604 u64 val;
605 int prim;
606 int ret = 0;
607
608 get_online_cpus();
609 rd = power_zone_to_rapl_domain(power_zone);
610 switch (rd->rpl[id].prim_id) {
611 case PL1_ENABLE:
612 prim = THERMAL_SPEC_POWER;
613 break;
614 case PL2_ENABLE:
615 prim = MAX_POWER;
616 break;
617 default:
618 put_online_cpus();
619 return -EINVAL;
620 }
621 if (rapl_read_data_raw(rd, prim, true, &val))
622 ret = -EIO;
623 else
624 *data = val;
625
626 put_online_cpus();
627
628 return ret;
629}
630
631static const struct powercap_zone_constraint_ops constraint_ops = {
632 .set_power_limit_uw = set_power_limit,
633 .get_power_limit_uw = get_current_power_limit,
634 .set_time_window_us = set_time_window,
635 .get_time_window_us = get_time_window,
636 .get_max_power_uw = get_max_power,
637 .get_name = get_constraint_name,
638};
639
640/* called after domain detection and package level data are set */
641static void rapl_init_domains(struct rapl_package *rp)
642{
643 int i;
644 struct rapl_domain *rd = rp->domains;
645
646 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
647 unsigned int mask = rp->domain_map & (1 << i);
648 switch (mask) {
649 case BIT(RAPL_DOMAIN_PACKAGE):
650 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
651 rd->id = RAPL_DOMAIN_PACKAGE;
652 rd->msrs[0] = MSR_PKG_POWER_LIMIT;
653 rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
654 rd->msrs[2] = MSR_PKG_PERF_STATUS;
655 rd->msrs[3] = 0;
656 rd->msrs[4] = MSR_PKG_POWER_INFO;
657 rd->rpl[0].prim_id = PL1_ENABLE;
658 rd->rpl[0].name = pl1_name;
659 rd->rpl[1].prim_id = PL2_ENABLE;
660 rd->rpl[1].name = pl2_name;
661 break;
662 case BIT(RAPL_DOMAIN_PP0):
663 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
664 rd->id = RAPL_DOMAIN_PP0;
665 rd->msrs[0] = MSR_PP0_POWER_LIMIT;
666 rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
667 rd->msrs[2] = 0;
668 rd->msrs[3] = MSR_PP0_POLICY;
669 rd->msrs[4] = 0;
670 rd->rpl[0].prim_id = PL1_ENABLE;
671 rd->rpl[0].name = pl1_name;
672 break;
673 case BIT(RAPL_DOMAIN_PP1):
674 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
675 rd->id = RAPL_DOMAIN_PP1;
676 rd->msrs[0] = MSR_PP1_POWER_LIMIT;
677 rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
678 rd->msrs[2] = 0;
679 rd->msrs[3] = MSR_PP1_POLICY;
680 rd->msrs[4] = 0;
681 rd->rpl[0].prim_id = PL1_ENABLE;
682 rd->rpl[0].name = pl1_name;
683 break;
684 case BIT(RAPL_DOMAIN_DRAM):
685 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
686 rd->id = RAPL_DOMAIN_DRAM;
687 rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
688 rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
689 rd->msrs[2] = MSR_DRAM_PERF_STATUS;
690 rd->msrs[3] = 0;
691 rd->msrs[4] = MSR_DRAM_POWER_INFO;
692 rd->rpl[0].prim_id = PL1_ENABLE;
693 rd->rpl[0].name = pl1_name;
694 rd->domain_energy_unit =
695 rapl_defaults->dram_domain_energy_unit;
696 if (rd->domain_energy_unit)
697 pr_info("DRAM domain energy unit %dpj\n",
698 rd->domain_energy_unit);
699 break;
700 }
701 if (mask) {
702 rd->rp = rp;
703 rd++;
704 }
705 }
706}
707
708static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
709 u64 value, int to_raw)
710{
711 u64 units = 1;
712 struct rapl_package *rp = rd->rp;
713 u64 scale = 1;
714
715 switch (type) {
716 case POWER_UNIT:
717 units = rp->power_unit;
718 break;
719 case ENERGY_UNIT:
720 scale = ENERGY_UNIT_SCALE;
721 /* per domain unit takes precedence */
722 if (rd->domain_energy_unit)
723 units = rd->domain_energy_unit;
724 else
725 units = rp->energy_unit;
726 break;
727 case TIME_UNIT:
728 return rapl_defaults->compute_time_window(rp, value, to_raw);
729 case ARBITRARY_UNIT:
730 default:
731 return value;
732 };
733
734 if (to_raw)
735 return div64_u64(value, units) * scale;
736
737 value *= units;
738
739 return div64_u64(value, scale);
740}
741
742/* in the order of enum rapl_primitives */
743static struct rapl_primitive_info rpi[] = {
744 /* name, mask, shift, msr index, unit divisor */
745 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
746 RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
747 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
748 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
749 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
750 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
751 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
752 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
753 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
754 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
755 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
756 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
757 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
758 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
759 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
760 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
761 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
762 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
763 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
764 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
765 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
766 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
767 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
768 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
769 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
770 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
771 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
772 RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
773 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
774 RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
775 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
776 RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
777 /* non-hardware */
778 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
779 RAPL_PRIMITIVE_DERIVED),
780 {NULL, 0, 0, 0},
781};
782
783/* Read primitive data based on its related struct rapl_primitive_info.
784 * if xlate flag is set, return translated data based on data units, i.e.
785 * time, energy, and power.
786 * RAPL MSRs are non-architectual and are laid out not consistently across
787 * domains. Here we use primitive info to allow writing consolidated access
788 * functions.
789 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
790 * is pre-assigned based on RAPL unit MSRs read at init time.
791 * 63-------------------------- 31--------------------------- 0
792 * | xxxxx (mask) |
793 * | |<- shift ----------------|
794 * 63-------------------------- 31--------------------------- 0
795 */
796static int rapl_read_data_raw(struct rapl_domain *rd,
797 enum rapl_primitives prim,
798 bool xlate, u64 *data)
799{
800 u64 value, final;
801 u32 msr;
802 struct rapl_primitive_info *rp = &rpi[prim];
803 int cpu;
804
805 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
806 return -EINVAL;
807
808 msr = rd->msrs[rp->id];
809 if (!msr)
810 return -EINVAL;
811
812 cpu = rd->rp->lead_cpu;
813
814 /* special-case package domain, which uses a different bit*/
815 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
816 rp->mask = POWER_PACKAGE_LOCK;
817 rp->shift = 63;
818 }
819 /* non-hardware data are collected by the polling thread */
820 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
821 *data = rd->rdd.primitives[prim];
822 return 0;
823 }
824
825 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
826 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
827 return -EIO;
828 }
829
830 final = value & rp->mask;
831 final = final >> rp->shift;
832 if (xlate)
833 *data = rapl_unit_xlate(rd, rp->unit, final, 0);
834 else
835 *data = final;
836
837 return 0;
838}
839
840
841static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
842{
843 int err;
844 u64 val;
845
846 err = rdmsrl_safe(msr_no, &val);
847 if (err)
848 goto out;
849
850 val &= ~clear_mask;
851 val |= set_mask;
852
853 err = wrmsrl_safe(msr_no, val);
854
855out:
856 return err;
857}
858
859static void msrl_update_func(void *info)
860{
861 struct msrl_action *ma = info;
862
863 ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
864}
865
866/* Similar use of primitive info in the read counterpart */
867static int rapl_write_data_raw(struct rapl_domain *rd,
868 enum rapl_primitives prim,
869 unsigned long long value)
870{
871 struct rapl_primitive_info *rp = &rpi[prim];
872 int cpu;
873 u64 bits;
874 struct msrl_action ma;
875 int ret;
876
877 cpu = rd->rp->lead_cpu;
878 bits = rapl_unit_xlate(rd, rp->unit, value, 1);
879 bits <<= rp->shift;
880 bits &= rp->mask;
881
882 memset(&ma, 0, sizeof(ma));
883
884 ma.msr_no = rd->msrs[rp->id];
885 ma.clear_mask = rp->mask;
886 ma.set_mask = bits;
887
888 ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
889 if (ret)
890 WARN_ON_ONCE(ret);
891 else
892 ret = ma.err;
893
894 return ret;
895}
896
897/*
898 * Raw RAPL data stored in MSRs are in certain scales. We need to
899 * convert them into standard units based on the units reported in
900 * the RAPL unit MSRs. This is specific to CPUs as the method to
901 * calculate units differ on different CPUs.
902 * We convert the units to below format based on CPUs.
903 * i.e.
904 * energy unit: picoJoules : Represented in picoJoules by default
905 * power unit : microWatts : Represented in milliWatts by default
906 * time unit : microseconds: Represented in seconds by default
907 */
908static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
909{
910 u64 msr_val;
911 u32 value;
912
913 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
914 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
915 MSR_RAPL_POWER_UNIT, cpu);
916 return -ENODEV;
917 }
918
919 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
920 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
921
922 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
923 rp->power_unit = 1000000 / (1 << value);
924
925 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
926 rp->time_unit = 1000000 / (1 << value);
927
928 pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
929 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
930
931 return 0;
932}
933
934static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
935{
936 u64 msr_val;
937 u32 value;
938
939 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
940 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
941 MSR_RAPL_POWER_UNIT, cpu);
942 return -ENODEV;
943 }
944 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
945 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
946
947 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
948 rp->power_unit = (1 << value) * 1000;
949
950 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
951 rp->time_unit = 1000000 / (1 << value);
952
953 pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
954 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
955
956 return 0;
957}
958
959static void power_limit_irq_save_cpu(void *info)
960{
961 u32 l, h = 0;
962 struct rapl_package *rp = (struct rapl_package *)info;
963
964 /* save the state of PLN irq mask bit before disabling it */
965 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
966 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
967 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
968 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
969 }
970 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
971 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
972}
973
974
975/* REVISIT:
976 * When package power limit is set artificially low by RAPL, LVT
977 * thermal interrupt for package power limit should be ignored
978 * since we are not really exceeding the real limit. The intention
979 * is to avoid excessive interrupts while we are trying to save power.
980 * A useful feature might be routing the package_power_limit interrupt
981 * to userspace via eventfd. once we have a usecase, this is simple
982 * to do by adding an atomic notifier.
983 */
984
985static void package_power_limit_irq_save(struct rapl_package *rp)
986{
987 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
988 return;
989
990 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
991}
992
993/*
994 * Restore per package power limit interrupt enable state. Called from cpu
995 * hotplug code on package removal.
996 */
997static void package_power_limit_irq_restore(struct rapl_package *rp)
998{
999 u32 l, h;
1000
1001 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
1002 return;
1003
1004 /* irq enable state not saved, nothing to restore */
1005 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
1006 return;
1007
1008 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
1009
1010 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
1011 l |= PACKAGE_THERM_INT_PLN_ENABLE;
1012 else
1013 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
1014
1015 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
1016}
1017
1018static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
1019{
1020 int nr_powerlimit = find_nr_power_limit(rd);
1021
1022 /* always enable clamp such that p-state can go below OS requested
1023 * range. power capping priority over guranteed frequency.
1024 */
1025 rapl_write_data_raw(rd, PL1_CLAMP, mode);
1026
1027 /* some domains have pl2 */
1028 if (nr_powerlimit > 1) {
1029 rapl_write_data_raw(rd, PL2_ENABLE, mode);
1030 rapl_write_data_raw(rd, PL2_CLAMP, mode);
1031 }
1032}
1033
1034static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
1035{
1036 static u32 power_ctrl_orig_val;
1037 u32 mdata;
1038
1039 if (!rapl_defaults->floor_freq_reg_addr) {
1040 pr_err("Invalid floor frequency config register\n");
1041 return;
1042 }
1043
1044 if (!power_ctrl_orig_val)
1045 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
1046 rapl_defaults->floor_freq_reg_addr,
1047 &power_ctrl_orig_val);
1048 mdata = power_ctrl_orig_val;
1049 if (enable) {
1050 mdata &= ~(0x7f << 8);
1051 mdata |= 1 << 8;
1052 }
1053 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
1054 rapl_defaults->floor_freq_reg_addr, mdata);
1055}
1056
1057static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
1058 bool to_raw)
1059{
1060 u64 f, y; /* fraction and exp. used for time unit */
1061
1062 /*
1063 * Special processing based on 2^Y*(1+F/4), refer
1064 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
1065 */
1066 if (!to_raw) {
1067 f = (value & 0x60) >> 5;
1068 y = value & 0x1f;
1069 value = (1 << y) * (4 + f) * rp->time_unit / 4;
1070 } else {
1071 do_div(value, rp->time_unit);
1072 y = ilog2(value);
1073 f = div64_u64(4 * (value - (1 << y)), 1 << y);
1074 value = (y & 0x1f) | ((f & 0x3) << 5);
1075 }
1076 return value;
1077}
1078
1079static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
1080 bool to_raw)
1081{
1082 /*
1083 * Atom time unit encoding is straight forward val * time_unit,
1084 * where time_unit is default to 1 sec. Never 0.
1085 */
1086 if (!to_raw)
1087 return (value) ? value *= rp->time_unit : rp->time_unit;
1088 else
1089 value = div64_u64(value, rp->time_unit);
1090
1091 return value;
1092}
1093
1094static const struct rapl_defaults rapl_defaults_core = {
1095 .floor_freq_reg_addr = 0,
1096 .check_unit = rapl_check_unit_core,
1097 .set_floor_freq = set_floor_freq_default,
1098 .compute_time_window = rapl_compute_time_window_core,
1099};
1100
1101static const struct rapl_defaults rapl_defaults_hsw_server = {
1102 .check_unit = rapl_check_unit_core,
1103 .set_floor_freq = set_floor_freq_default,
1104 .compute_time_window = rapl_compute_time_window_core,
1105 .dram_domain_energy_unit = 15300,
1106};
1107
1108static const struct rapl_defaults rapl_defaults_byt = {
1109 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1110 .check_unit = rapl_check_unit_atom,
1111 .set_floor_freq = set_floor_freq_atom,
1112 .compute_time_window = rapl_compute_time_window_atom,
1113};
1114
1115static const struct rapl_defaults rapl_defaults_tng = {
1116 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
1117 .check_unit = rapl_check_unit_atom,
1118 .set_floor_freq = set_floor_freq_atom,
1119 .compute_time_window = rapl_compute_time_window_atom,
1120};
1121
1122static const struct rapl_defaults rapl_defaults_ann = {
1123 .floor_freq_reg_addr = 0,
1124 .check_unit = rapl_check_unit_atom,
1125 .set_floor_freq = NULL,
1126 .compute_time_window = rapl_compute_time_window_atom,
1127};
1128
1129static const struct rapl_defaults rapl_defaults_cht = {
1130 .floor_freq_reg_addr = 0,
1131 .check_unit = rapl_check_unit_atom,
1132 .set_floor_freq = NULL,
1133 .compute_time_window = rapl_compute_time_window_atom,
1134};
1135
1136#define RAPL_CPU(_model, _ops) { \
1137 .vendor = X86_VENDOR_INTEL, \
1138 .family = 6, \
1139 .model = _model, \
1140 .driver_data = (kernel_ulong_t)&_ops, \
1141 }
1142
1143static const struct x86_cpu_id rapl_ids[] __initconst = {
1144 RAPL_CPU(INTEL_FAM6_SANDYBRIDGE, rapl_defaults_core),
1145 RAPL_CPU(INTEL_FAM6_SANDYBRIDGE_X, rapl_defaults_core),
1146
1147 RAPL_CPU(INTEL_FAM6_IVYBRIDGE, rapl_defaults_core),
1148 RAPL_CPU(INTEL_FAM6_IVYBRIDGE_X, rapl_defaults_core),
1149
1150 RAPL_CPU(INTEL_FAM6_HASWELL_CORE, rapl_defaults_core),
1151 RAPL_CPU(INTEL_FAM6_HASWELL_ULT, rapl_defaults_core),
1152 RAPL_CPU(INTEL_FAM6_HASWELL_GT3E, rapl_defaults_core),
1153 RAPL_CPU(INTEL_FAM6_HASWELL_X, rapl_defaults_hsw_server),
1154
1155 RAPL_CPU(INTEL_FAM6_BROADWELL_CORE, rapl_defaults_core),
1156 RAPL_CPU(INTEL_FAM6_BROADWELL_GT3E, rapl_defaults_core),
1157 RAPL_CPU(INTEL_FAM6_BROADWELL_XEON_D, rapl_defaults_core),
1158 RAPL_CPU(INTEL_FAM6_BROADWELL_X, rapl_defaults_hsw_server),
1159
1160 RAPL_CPU(INTEL_FAM6_SKYLAKE_DESKTOP, rapl_defaults_core),
1161 RAPL_CPU(INTEL_FAM6_SKYLAKE_MOBILE, rapl_defaults_core),
1162 RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
1163 RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
1164 RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
1165 RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
1166
1167 RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
1168 RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
1169 RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD, rapl_defaults_tng),
1170 RAPL_CPU(INTEL_FAM6_ATOM_MOOREFIELD, rapl_defaults_ann),
1171 RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core),
1172 RAPL_CPU(INTEL_FAM6_ATOM_GEMINI_LAKE, rapl_defaults_core),
1173 RAPL_CPU(INTEL_FAM6_ATOM_DENVERTON, rapl_defaults_core),
1174
1175 RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server),
1176 RAPL_CPU(INTEL_FAM6_XEON_PHI_KNM, rapl_defaults_hsw_server),
1177 {}
1178};
1179MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1180
1181/* Read once for all raw primitive data for domains */
1182static void rapl_update_domain_data(struct rapl_package *rp)
1183{
1184 int dmn, prim;
1185 u64 val;
1186
1187 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1188 pr_debug("update package %d domain %s data\n", rp->id,
1189 rp->domains[dmn].name);
1190 /* exclude non-raw primitives */
1191 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
1192 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1193 rpi[prim].unit, &val))
1194 rp->domains[dmn].rdd.primitives[prim] = val;
1195 }
1196 }
1197
1198}
1199
1200static void rapl_unregister_powercap(void)
1201{
1202 if (platform_rapl_domain) {
1203 powercap_unregister_zone(control_type,
1204 &platform_rapl_domain->power_zone);
1205 kfree(platform_rapl_domain);
1206 }
1207 powercap_unregister_control_type(control_type);
1208}
1209
1210static int rapl_package_register_powercap(struct rapl_package *rp)
1211{
1212 struct rapl_domain *rd;
1213 char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
1214 struct powercap_zone *power_zone = NULL;
1215 int nr_pl, ret;
1216
1217 /* Update the domain data of the new package */
1218 rapl_update_domain_data(rp);
1219
1220 /* first we register package domain as the parent zone*/
1221 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1222 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1223 nr_pl = find_nr_power_limit(rd);
1224 pr_debug("register socket %d package domain %s\n",
1225 rp->id, rd->name);
1226 memset(dev_name, 0, sizeof(dev_name));
1227 snprintf(dev_name, sizeof(dev_name), "%s-%d",
1228 rd->name, rp->id);
1229 power_zone = powercap_register_zone(&rd->power_zone,
1230 control_type,
1231 dev_name, NULL,
1232 &zone_ops[rd->id],
1233 nr_pl,
1234 &constraint_ops);
1235 if (IS_ERR(power_zone)) {
1236 pr_debug("failed to register package, %d\n",
1237 rp->id);
1238 return PTR_ERR(power_zone);
1239 }
1240 /* track parent zone in per package/socket data */
1241 rp->power_zone = power_zone;
1242 /* done, only one package domain per socket */
1243 break;
1244 }
1245 }
1246 if (!power_zone) {
1247 pr_err("no package domain found, unknown topology!\n");
1248 return -ENODEV;
1249 }
1250 /* now register domains as children of the socket/package*/
1251 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1252 if (rd->id == RAPL_DOMAIN_PACKAGE)
1253 continue;
1254 /* number of power limits per domain varies */
1255 nr_pl = find_nr_power_limit(rd);
1256 power_zone = powercap_register_zone(&rd->power_zone,
1257 control_type, rd->name,
1258 rp->power_zone,
1259 &zone_ops[rd->id], nr_pl,
1260 &constraint_ops);
1261
1262 if (IS_ERR(power_zone)) {
1263 pr_debug("failed to register power_zone, %d:%s:%s\n",
1264 rp->id, rd->name, dev_name);
1265 ret = PTR_ERR(power_zone);
1266 goto err_cleanup;
1267 }
1268 }
1269 return 0;
1270
1271err_cleanup:
1272 /*
1273 * Clean up previously initialized domains within the package if we
1274 * failed after the first domain setup.
1275 */
1276 while (--rd >= rp->domains) {
1277 pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
1278 powercap_unregister_zone(control_type, &rd->power_zone);
1279 }
1280
1281 return ret;
1282}
1283
1284static int __init rapl_register_psys(void)
1285{
1286 struct rapl_domain *rd;
1287 struct powercap_zone *power_zone;
1288 u64 val;
1289
1290 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
1291 return -ENODEV;
1292
1293 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
1294 return -ENODEV;
1295
1296 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
1297 if (!rd)
1298 return -ENOMEM;
1299
1300 rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
1301 rd->id = RAPL_DOMAIN_PLATFORM;
1302 rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
1303 rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
1304 rd->rpl[0].prim_id = PL1_ENABLE;
1305 rd->rpl[0].name = pl1_name;
1306 rd->rpl[1].prim_id = PL2_ENABLE;
1307 rd->rpl[1].name = pl2_name;
1308 rd->rp = find_package_by_id(0);
1309
1310 power_zone = powercap_register_zone(&rd->power_zone, control_type,
1311 "psys", NULL,
1312 &zone_ops[RAPL_DOMAIN_PLATFORM],
1313 2, &constraint_ops);
1314
1315 if (IS_ERR(power_zone)) {
1316 kfree(rd);
1317 return PTR_ERR(power_zone);
1318 }
1319
1320 platform_rapl_domain = rd;
1321
1322 return 0;
1323}
1324
1325static int __init rapl_register_powercap(void)
1326{
1327 control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1328 if (IS_ERR(control_type)) {
1329 pr_debug("failed to register powercap control_type.\n");
1330 return PTR_ERR(control_type);
1331 }
1332 return 0;
1333}
1334
1335static int rapl_check_domain(int cpu, int domain)
1336{
1337 unsigned msr;
1338 u64 val = 0;
1339
1340 switch (domain) {
1341 case RAPL_DOMAIN_PACKAGE:
1342 msr = MSR_PKG_ENERGY_STATUS;
1343 break;
1344 case RAPL_DOMAIN_PP0:
1345 msr = MSR_PP0_ENERGY_STATUS;
1346 break;
1347 case RAPL_DOMAIN_PP1:
1348 msr = MSR_PP1_ENERGY_STATUS;
1349 break;
1350 case RAPL_DOMAIN_DRAM:
1351 msr = MSR_DRAM_ENERGY_STATUS;
1352 break;
1353 case RAPL_DOMAIN_PLATFORM:
1354 /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
1355 return -EINVAL;
1356 default:
1357 pr_err("invalid domain id %d\n", domain);
1358 return -EINVAL;
1359 }
1360 /* make sure domain counters are available and contains non-zero
1361 * values, otherwise skip it.
1362 */
1363 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
1364 return -ENODEV;
1365
1366 return 0;
1367}
1368
1369
1370/*
1371 * Check if power limits are available. Two cases when they are not available:
1372 * 1. Locked by BIOS, in this case we still provide read-only access so that
1373 * users can see what limit is set by the BIOS.
1374 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not
1375 * exist at all. In this case, we do not show the contraints in powercap.
1376 *
1377 * Called after domains are detected and initialized.
1378 */
1379static void rapl_detect_powerlimit(struct rapl_domain *rd)
1380{
1381 u64 val64;
1382 int i;
1383
1384 /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */
1385 if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) {
1386 if (val64) {
1387 pr_info("RAPL package %d domain %s locked by BIOS\n",
1388 rd->rp->id, rd->name);
1389 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
1390 }
1391 }
1392 /* check if power limit MSRs exists, otherwise domain is monitoring only */
1393 for (i = 0; i < NR_POWER_LIMITS; i++) {
1394 int prim = rd->rpl[i].prim_id;
1395 if (rapl_read_data_raw(rd, prim, false, &val64))
1396 rd->rpl[i].name = NULL;
1397 }
1398}
1399
1400/* Detect active and valid domains for the given CPU, caller must
1401 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1402 */
1403static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1404{
1405 struct rapl_domain *rd;
1406 int i;
1407
1408 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1409 /* use physical package id to read counters */
1410 if (!rapl_check_domain(cpu, i)) {
1411 rp->domain_map |= 1 << i;
1412 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1413 }
1414 }
1415 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1416 if (!rp->nr_domains) {
1417 pr_debug("no valid rapl domains found in package %d\n", rp->id);
1418 return -ENODEV;
1419 }
1420 pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
1421
1422 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1423 GFP_KERNEL);
1424 if (!rp->domains)
1425 return -ENOMEM;
1426
1427 rapl_init_domains(rp);
1428
1429 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++)
1430 rapl_detect_powerlimit(rd);
1431
1432 return 0;
1433}
1434
1435/* called from CPU hotplug notifier, hotplug lock held */
1436static void rapl_remove_package(struct rapl_package *rp)
1437{
1438 struct rapl_domain *rd, *rd_package = NULL;
1439
1440 package_power_limit_irq_restore(rp);
1441
1442 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1443 rapl_write_data_raw(rd, PL1_ENABLE, 0);
1444 rapl_write_data_raw(rd, PL1_CLAMP, 0);
1445 if (find_nr_power_limit(rd) > 1) {
1446 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1447 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1448 }
1449 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1450 rd_package = rd;
1451 continue;
1452 }
1453 pr_debug("remove package, undo power limit on %d: %s\n",
1454 rp->id, rd->name);
1455 powercap_unregister_zone(control_type, &rd->power_zone);
1456 }
1457 /* do parent zone last */
1458 powercap_unregister_zone(control_type, &rd_package->power_zone);
1459 list_del(&rp->plist);
1460 kfree(rp);
1461}
1462
1463/* called from CPU hotplug notifier, hotplug lock held */
1464static struct rapl_package *rapl_add_package(int cpu, int pkgid)
1465{
1466 struct rapl_package *rp;
1467 int ret;
1468
1469 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1470 if (!rp)
1471 return ERR_PTR(-ENOMEM);
1472
1473 /* add the new package to the list */
1474 rp->id = pkgid;
1475 rp->lead_cpu = cpu;
1476
1477 /* check if the package contains valid domains */
1478 if (rapl_detect_domains(rp, cpu) ||
1479 rapl_defaults->check_unit(rp, cpu)) {
1480 ret = -ENODEV;
1481 goto err_free_package;
1482 }
1483 ret = rapl_package_register_powercap(rp);
1484 if (!ret) {
1485 INIT_LIST_HEAD(&rp->plist);
1486 list_add(&rp->plist, &rapl_packages);
1487 return rp;
1488 }
1489
1490err_free_package:
1491 kfree(rp->domains);
1492 kfree(rp);
1493 return ERR_PTR(ret);
1494}
1495
1496/* Handles CPU hotplug on multi-socket systems.
1497 * If a CPU goes online as the first CPU of the physical package
1498 * we add the RAPL package to the system. Similarly, when the last
1499 * CPU of the package is removed, we remove the RAPL package and its
1500 * associated domains. Cooling devices are handled accordingly at
1501 * per-domain level.
1502 */
1503static int rapl_cpu_online(unsigned int cpu)
1504{
1505 int pkgid = topology_physical_package_id(cpu);
1506 struct rapl_package *rp;
1507
1508 rp = find_package_by_id(pkgid);
1509 if (!rp) {
1510 rp = rapl_add_package(cpu, pkgid);
1511 if (IS_ERR(rp))
1512 return PTR_ERR(rp);
1513 }
1514 cpumask_set_cpu(cpu, &rp->cpumask);
1515 return 0;
1516}
1517
1518static int rapl_cpu_down_prep(unsigned int cpu)
1519{
1520 int pkgid = topology_physical_package_id(cpu);
1521 struct rapl_package *rp;
1522 int lead_cpu;
1523
1524 rp = find_package_by_id(pkgid);
1525 if (!rp)
1526 return 0;
1527
1528 cpumask_clear_cpu(cpu, &rp->cpumask);
1529 lead_cpu = cpumask_first(&rp->cpumask);
1530 if (lead_cpu >= nr_cpu_ids)
1531 rapl_remove_package(rp);
1532 else if (rp->lead_cpu == cpu)
1533 rp->lead_cpu = lead_cpu;
1534 return 0;
1535}
1536
1537static enum cpuhp_state pcap_rapl_online;
1538
1539static void power_limit_state_save(void)
1540{
1541 struct rapl_package *rp;
1542 struct rapl_domain *rd;
1543 int nr_pl, ret, i;
1544
1545 get_online_cpus();
1546 list_for_each_entry(rp, &rapl_packages, plist) {
1547 if (!rp->power_zone)
1548 continue;
1549 rd = power_zone_to_rapl_domain(rp->power_zone);
1550 nr_pl = find_nr_power_limit(rd);
1551 for (i = 0; i < nr_pl; i++) {
1552 switch (rd->rpl[i].prim_id) {
1553 case PL1_ENABLE:
1554 ret = rapl_read_data_raw(rd,
1555 POWER_LIMIT1,
1556 true,
1557 &rd->rpl[i].last_power_limit);
1558 if (ret)
1559 rd->rpl[i].last_power_limit = 0;
1560 break;
1561 case PL2_ENABLE:
1562 ret = rapl_read_data_raw(rd,
1563 POWER_LIMIT2,
1564 true,
1565 &rd->rpl[i].last_power_limit);
1566 if (ret)
1567 rd->rpl[i].last_power_limit = 0;
1568 break;
1569 }
1570 }
1571 }
1572 put_online_cpus();
1573}
1574
1575static void power_limit_state_restore(void)
1576{
1577 struct rapl_package *rp;
1578 struct rapl_domain *rd;
1579 int nr_pl, i;
1580
1581 get_online_cpus();
1582 list_for_each_entry(rp, &rapl_packages, plist) {
1583 if (!rp->power_zone)
1584 continue;
1585 rd = power_zone_to_rapl_domain(rp->power_zone);
1586 nr_pl = find_nr_power_limit(rd);
1587 for (i = 0; i < nr_pl; i++) {
1588 switch (rd->rpl[i].prim_id) {
1589 case PL1_ENABLE:
1590 if (rd->rpl[i].last_power_limit)
1591 rapl_write_data_raw(rd,
1592 POWER_LIMIT1,
1593 rd->rpl[i].last_power_limit);
1594 break;
1595 case PL2_ENABLE:
1596 if (rd->rpl[i].last_power_limit)
1597 rapl_write_data_raw(rd,
1598 POWER_LIMIT2,
1599 rd->rpl[i].last_power_limit);
1600 break;
1601 }
1602 }
1603 }
1604 put_online_cpus();
1605}
1606
1607static int rapl_pm_callback(struct notifier_block *nb,
1608 unsigned long mode, void *_unused)
1609{
1610 switch (mode) {
1611 case PM_SUSPEND_PREPARE:
1612 power_limit_state_save();
1613 break;
1614 case PM_POST_SUSPEND:
1615 power_limit_state_restore();
1616 break;
1617 }
1618 return NOTIFY_OK;
1619}
1620
1621static struct notifier_block rapl_pm_notifier = {
1622 .notifier_call = rapl_pm_callback,
1623};
1624
1625static int __init rapl_init(void)
1626{
1627 const struct x86_cpu_id *id;
1628 int ret;
1629
1630 id = x86_match_cpu(rapl_ids);
1631 if (!id) {
1632 pr_err("driver does not support CPU family %d model %d\n",
1633 boot_cpu_data.x86, boot_cpu_data.x86_model);
1634
1635 return -ENODEV;
1636 }
1637
1638 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1639
1640 ret = rapl_register_powercap();
1641 if (ret)
1642 return ret;
1643
1644 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
1645 rapl_cpu_online, rapl_cpu_down_prep);
1646 if (ret < 0)
1647 goto err_unreg;
1648 pcap_rapl_online = ret;
1649
1650 /* Don't bail out if PSys is not supported */
1651 rapl_register_psys();
1652
1653 ret = register_pm_notifier(&rapl_pm_notifier);
1654 if (ret)
1655 goto err_unreg_all;
1656
1657 return 0;
1658
1659err_unreg_all:
1660 cpuhp_remove_state(pcap_rapl_online);
1661
1662err_unreg:
1663 rapl_unregister_powercap();
1664 return ret;
1665}
1666
1667static void __exit rapl_exit(void)
1668{
1669 unregister_pm_notifier(&rapl_pm_notifier);
1670 cpuhp_remove_state(pcap_rapl_online);
1671 rapl_unregister_powercap();
1672}
1673
1674module_init(rapl_init);
1675module_exit(rapl_exit);
1676
1677MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1678MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1679MODULE_LICENSE("GPL v2");