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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * QLogic QLA3xxx NIC HBA Driver
4 * Copyright (c) 2003-2006 QLogic Corporation
5 */
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
25#include <linux/in.h>
26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
34#include <linux/delay.h>
35#include <linux/mm.h>
36#include <linux/prefetch.h>
37
38#include "qla3xxx.h"
39
40#define DRV_NAME "qla3xxx"
41#define DRV_STRING "QLogic ISP3XXX Network Driver"
42#define DRV_VERSION "v2.03.00-k5"
43
44static const char ql3xxx_driver_name[] = DRV_NAME;
45static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47#define TIMED_OUT_MSG \
48"Timed out waiting for management port to get free before issuing command\n"
49
50MODULE_AUTHOR("QLogic Corporation");
51MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
52MODULE_LICENSE("GPL");
53MODULE_VERSION(DRV_VERSION);
54
55static const u32 default_msg
56 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
57 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
58
59static int debug = -1; /* defaults above */
60module_param(debug, int, 0);
61MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
62
63static int msi;
64module_param(msi, int, 0);
65MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
66
67static const struct pci_device_id ql3xxx_pci_tbl[] = {
68 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
69 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
70 /* required last entry */
71 {0,}
72};
73
74MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
75
76/*
77 * These are the known PHY's which are used
78 */
79enum PHY_DEVICE_TYPE {
80 PHY_TYPE_UNKNOWN = 0,
81 PHY_VITESSE_VSC8211,
82 PHY_AGERE_ET1011C,
83 MAX_PHY_DEV_TYPES
84};
85
86struct PHY_DEVICE_INFO {
87 const enum PHY_DEVICE_TYPE phyDevice;
88 const u32 phyIdOUI;
89 const u16 phyIdModel;
90 const char *name;
91};
92
93static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
94 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
95 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
96 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
97};
98
99
100/*
101 * Caller must take hw_lock.
102 */
103static int ql_sem_spinlock(struct ql3_adapter *qdev,
104 u32 sem_mask, u32 sem_bits)
105{
106 struct ql3xxx_port_registers __iomem *port_regs =
107 qdev->mem_map_registers;
108 u32 value;
109 unsigned int seconds = 3;
110
111 do {
112 writel((sem_mask | sem_bits),
113 &port_regs->CommonRegs.semaphoreReg);
114 value = readl(&port_regs->CommonRegs.semaphoreReg);
115 if ((value & (sem_mask >> 16)) == sem_bits)
116 return 0;
117 mdelay(1000);
118 } while (--seconds);
119 return -1;
120}
121
122static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
123{
124 struct ql3xxx_port_registers __iomem *port_regs =
125 qdev->mem_map_registers;
126 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
127 readl(&port_regs->CommonRegs.semaphoreReg);
128}
129
130static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
131{
132 struct ql3xxx_port_registers __iomem *port_regs =
133 qdev->mem_map_registers;
134 u32 value;
135
136 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
137 value = readl(&port_regs->CommonRegs.semaphoreReg);
138 return ((value & (sem_mask >> 16)) == sem_bits);
139}
140
141/*
142 * Caller holds hw_lock.
143 */
144static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
145{
146 int i = 0;
147
148 do {
149 if (ql_sem_lock(qdev,
150 QL_DRVR_SEM_MASK,
151 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
152 * 2) << 1)) {
153 netdev_printk(KERN_DEBUG, qdev->ndev,
154 "driver lock acquired\n");
155 return 1;
156 }
157 mdelay(1000);
158 } while (++i < 10);
159
160 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
161 return 0;
162}
163
164static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
165{
166 struct ql3xxx_port_registers __iomem *port_regs =
167 qdev->mem_map_registers;
168
169 writel(((ISP_CONTROL_NP_MASK << 16) | page),
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
172 qdev->current_page = page;
173}
174
175static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
176{
177 u32 value;
178 unsigned long hw_flags;
179
180 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
181 value = readl(reg);
182 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183
184 return value;
185}
186
187static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
188{
189 return readl(reg);
190}
191
192static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
193{
194 u32 value;
195 unsigned long hw_flags;
196
197 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
198
199 if (qdev->current_page != 0)
200 ql_set_register_page(qdev, 0);
201 value = readl(reg);
202
203 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
204 return value;
205}
206
207static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
208{
209 if (qdev->current_page != 0)
210 ql_set_register_page(qdev, 0);
211 return readl(reg);
212}
213
214static void ql_write_common_reg_l(struct ql3_adapter *qdev,
215 u32 __iomem *reg, u32 value)
216{
217 unsigned long hw_flags;
218
219 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
220 writel(value, reg);
221 readl(reg);
222 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
223}
224
225static void ql_write_common_reg(struct ql3_adapter *qdev,
226 u32 __iomem *reg, u32 value)
227{
228 writel(value, reg);
229 readl(reg);
230}
231
232static void ql_write_nvram_reg(struct ql3_adapter *qdev,
233 u32 __iomem *reg, u32 value)
234{
235 writel(value, reg);
236 readl(reg);
237 udelay(1);
238}
239
240static void ql_write_page0_reg(struct ql3_adapter *qdev,
241 u32 __iomem *reg, u32 value)
242{
243 if (qdev->current_page != 0)
244 ql_set_register_page(qdev, 0);
245 writel(value, reg);
246 readl(reg);
247}
248
249/*
250 * Caller holds hw_lock. Only called during init.
251 */
252static void ql_write_page1_reg(struct ql3_adapter *qdev,
253 u32 __iomem *reg, u32 value)
254{
255 if (qdev->current_page != 1)
256 ql_set_register_page(qdev, 1);
257 writel(value, reg);
258 readl(reg);
259}
260
261/*
262 * Caller holds hw_lock. Only called during init.
263 */
264static void ql_write_page2_reg(struct ql3_adapter *qdev,
265 u32 __iomem *reg, u32 value)
266{
267 if (qdev->current_page != 2)
268 ql_set_register_page(qdev, 2);
269 writel(value, reg);
270 readl(reg);
271}
272
273static void ql_disable_interrupts(struct ql3_adapter *qdev)
274{
275 struct ql3xxx_port_registers __iomem *port_regs =
276 qdev->mem_map_registers;
277
278 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
279 (ISP_IMR_ENABLE_INT << 16));
280
281}
282
283static void ql_enable_interrupts(struct ql3_adapter *qdev)
284{
285 struct ql3xxx_port_registers __iomem *port_regs =
286 qdev->mem_map_registers;
287
288 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
289 ((0xff << 16) | ISP_IMR_ENABLE_INT));
290
291}
292
293static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
294 struct ql_rcv_buf_cb *lrg_buf_cb)
295{
296 dma_addr_t map;
297 int err;
298 lrg_buf_cb->next = NULL;
299
300 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
301 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
302 } else {
303 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
304 qdev->lrg_buf_free_tail = lrg_buf_cb;
305 }
306
307 if (!lrg_buf_cb->skb) {
308 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
309 qdev->lrg_buffer_len);
310 if (unlikely(!lrg_buf_cb->skb)) {
311 qdev->lrg_buf_skb_check++;
312 } else {
313 /*
314 * We save some space to copy the ethhdr from first
315 * buffer
316 */
317 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
318 map = dma_map_single(&qdev->pdev->dev,
319 lrg_buf_cb->skb->data,
320 qdev->lrg_buffer_len - QL_HEADER_SPACE,
321 DMA_FROM_DEVICE);
322 err = dma_mapping_error(&qdev->pdev->dev, map);
323 if (err) {
324 netdev_err(qdev->ndev,
325 "PCI mapping failed with error: %d\n",
326 err);
327 dev_kfree_skb(lrg_buf_cb->skb);
328 lrg_buf_cb->skb = NULL;
329
330 qdev->lrg_buf_skb_check++;
331 return;
332 }
333
334 lrg_buf_cb->buf_phy_addr_low =
335 cpu_to_le32(LS_64BITS(map));
336 lrg_buf_cb->buf_phy_addr_high =
337 cpu_to_le32(MS_64BITS(map));
338 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
339 dma_unmap_len_set(lrg_buf_cb, maplen,
340 qdev->lrg_buffer_len -
341 QL_HEADER_SPACE);
342 }
343 }
344
345 qdev->lrg_buf_free_count++;
346}
347
348static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
349 *qdev)
350{
351 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
352
353 if (lrg_buf_cb != NULL) {
354 qdev->lrg_buf_free_head = lrg_buf_cb->next;
355 if (qdev->lrg_buf_free_head == NULL)
356 qdev->lrg_buf_free_tail = NULL;
357 qdev->lrg_buf_free_count--;
358 }
359
360 return lrg_buf_cb;
361}
362
363static u32 addrBits = EEPROM_NO_ADDR_BITS;
364static u32 dataBits = EEPROM_NO_DATA_BITS;
365
366static void fm93c56a_deselect(struct ql3_adapter *qdev);
367static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
368 unsigned short *value);
369
370/*
371 * Caller holds hw_lock.
372 */
373static void fm93c56a_select(struct ql3_adapter *qdev)
374{
375 struct ql3xxx_port_registers __iomem *port_regs =
376 qdev->mem_map_registers;
377 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
378
379 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
380 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
381}
382
383/*
384 * Caller holds hw_lock.
385 */
386static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
387{
388 int i;
389 u32 mask;
390 u32 dataBit;
391 u32 previousBit;
392 struct ql3xxx_port_registers __iomem *port_regs =
393 qdev->mem_map_registers;
394 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
395
396 /* Clock in a zero, then do the start bit */
397 ql_write_nvram_reg(qdev, spir,
398 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
399 AUBURN_EEPROM_DO_1));
400 ql_write_nvram_reg(qdev, spir,
401 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
402 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
403 ql_write_nvram_reg(qdev, spir,
404 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
405 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
406
407 mask = 1 << (FM93C56A_CMD_BITS - 1);
408 /* Force the previous data bit to be different */
409 previousBit = 0xffff;
410 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
411 dataBit = (cmd & mask)
412 ? AUBURN_EEPROM_DO_1
413 : AUBURN_EEPROM_DO_0;
414 if (previousBit != dataBit) {
415 /* If the bit changed, change the DO state to match */
416 ql_write_nvram_reg(qdev, spir,
417 (ISP_NVRAM_MASK |
418 qdev->eeprom_cmd_data | dataBit));
419 previousBit = dataBit;
420 }
421 ql_write_nvram_reg(qdev, spir,
422 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
423 dataBit | AUBURN_EEPROM_CLK_RISE));
424 ql_write_nvram_reg(qdev, spir,
425 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
426 dataBit | AUBURN_EEPROM_CLK_FALL));
427 cmd = cmd << 1;
428 }
429
430 mask = 1 << (addrBits - 1);
431 /* Force the previous data bit to be different */
432 previousBit = 0xffff;
433 for (i = 0; i < addrBits; i++) {
434 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
435 : AUBURN_EEPROM_DO_0;
436 if (previousBit != dataBit) {
437 /*
438 * If the bit changed, then change the DO state to
439 * match
440 */
441 ql_write_nvram_reg(qdev, spir,
442 (ISP_NVRAM_MASK |
443 qdev->eeprom_cmd_data | dataBit));
444 previousBit = dataBit;
445 }
446 ql_write_nvram_reg(qdev, spir,
447 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
448 dataBit | AUBURN_EEPROM_CLK_RISE));
449 ql_write_nvram_reg(qdev, spir,
450 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
451 dataBit | AUBURN_EEPROM_CLK_FALL));
452 eepromAddr = eepromAddr << 1;
453 }
454}
455
456/*
457 * Caller holds hw_lock.
458 */
459static void fm93c56a_deselect(struct ql3_adapter *qdev)
460{
461 struct ql3xxx_port_registers __iomem *port_regs =
462 qdev->mem_map_registers;
463 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
464
465 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
466 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
467}
468
469/*
470 * Caller holds hw_lock.
471 */
472static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
473{
474 int i;
475 u32 data = 0;
476 u32 dataBit;
477 struct ql3xxx_port_registers __iomem *port_regs =
478 qdev->mem_map_registers;
479 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
480
481 /* Read the data bits */
482 /* The first bit is a dummy. Clock right over it. */
483 for (i = 0; i < dataBits; i++) {
484 ql_write_nvram_reg(qdev, spir,
485 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
486 AUBURN_EEPROM_CLK_RISE);
487 ql_write_nvram_reg(qdev, spir,
488 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
489 AUBURN_EEPROM_CLK_FALL);
490 dataBit = (ql_read_common_reg(qdev, spir) &
491 AUBURN_EEPROM_DI_1) ? 1 : 0;
492 data = (data << 1) | dataBit;
493 }
494 *value = (u16)data;
495}
496
497/*
498 * Caller holds hw_lock.
499 */
500static void eeprom_readword(struct ql3_adapter *qdev,
501 u32 eepromAddr, unsigned short *value)
502{
503 fm93c56a_select(qdev);
504 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
505 fm93c56a_datain(qdev, value);
506 fm93c56a_deselect(qdev);
507}
508
509static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
510{
511 __le16 buf[ETH_ALEN / 2];
512
513 buf[0] = cpu_to_le16(addr[0]);
514 buf[1] = cpu_to_le16(addr[1]);
515 buf[2] = cpu_to_le16(addr[2]);
516 eth_hw_addr_set(ndev, (u8 *)buf);
517}
518
519static int ql_get_nvram_params(struct ql3_adapter *qdev)
520{
521 u16 *pEEPROMData;
522 u16 checksum = 0;
523 u32 index;
524 unsigned long hw_flags;
525
526 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
527
528 pEEPROMData = (u16 *)&qdev->nvram_data;
529 qdev->eeprom_cmd_data = 0;
530 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
531 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
532 2) << 10)) {
533 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
534 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
535 return -1;
536 }
537
538 for (index = 0; index < EEPROM_SIZE; index++) {
539 eeprom_readword(qdev, index, pEEPROMData);
540 checksum += *pEEPROMData;
541 pEEPROMData++;
542 }
543 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
544
545 if (checksum != 0) {
546 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
547 checksum);
548 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
549 return -1;
550 }
551
552 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
553 return checksum;
554}
555
556static const u32 PHYAddr[2] = {
557 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
558};
559
560static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
561{
562 struct ql3xxx_port_registers __iomem *port_regs =
563 qdev->mem_map_registers;
564 u32 temp;
565 int count = 1000;
566
567 while (count) {
568 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
569 if (!(temp & MAC_MII_STATUS_BSY))
570 return 0;
571 udelay(10);
572 count--;
573 }
574 return -1;
575}
576
577static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
578{
579 struct ql3xxx_port_registers __iomem *port_regs =
580 qdev->mem_map_registers;
581 u32 scanControl;
582
583 if (qdev->numPorts > 1) {
584 /* Auto scan will cycle through multiple ports */
585 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
586 } else {
587 scanControl = MAC_MII_CONTROL_SC;
588 }
589
590 /*
591 * Scan register 1 of PHY/PETBI,
592 * Set up to scan both devices
593 * The autoscan starts from the first register, completes
594 * the last one before rolling over to the first
595 */
596 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
597 PHYAddr[0] | MII_SCAN_REGISTER);
598
599 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
600 (scanControl) |
601 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
602}
603
604static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
605{
606 u8 ret;
607 struct ql3xxx_port_registers __iomem *port_regs =
608 qdev->mem_map_registers;
609
610 /* See if scan mode is enabled before we turn it off */
611 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
612 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
613 /* Scan is enabled */
614 ret = 1;
615 } else {
616 /* Scan is disabled */
617 ret = 0;
618 }
619
620 /*
621 * When disabling scan mode you must first change the MII register
622 * address
623 */
624 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
625 PHYAddr[0] | MII_SCAN_REGISTER);
626
627 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
628 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
629 MAC_MII_CONTROL_RC) << 16));
630
631 return ret;
632}
633
634static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
635 u16 regAddr, u16 value, u32 phyAddr)
636{
637 struct ql3xxx_port_registers __iomem *port_regs =
638 qdev->mem_map_registers;
639 u8 scanWasEnabled;
640
641 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
642
643 if (ql_wait_for_mii_ready(qdev)) {
644 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
645 return -1;
646 }
647
648 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
649 phyAddr | regAddr);
650
651 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
652
653 /* Wait for write to complete 9/10/04 SJP */
654 if (ql_wait_for_mii_ready(qdev)) {
655 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
656 return -1;
657 }
658
659 if (scanWasEnabled)
660 ql_mii_enable_scan_mode(qdev);
661
662 return 0;
663}
664
665static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
666 u16 *value, u32 phyAddr)
667{
668 struct ql3xxx_port_registers __iomem *port_regs =
669 qdev->mem_map_registers;
670 u8 scanWasEnabled;
671 u32 temp;
672
673 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
674
675 if (ql_wait_for_mii_ready(qdev)) {
676 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
677 return -1;
678 }
679
680 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
681 phyAddr | regAddr);
682
683 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
684 (MAC_MII_CONTROL_RC << 16));
685
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
687 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
688
689 /* Wait for the read to complete */
690 if (ql_wait_for_mii_ready(qdev)) {
691 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
692 return -1;
693 }
694
695 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
696 *value = (u16) temp;
697
698 if (scanWasEnabled)
699 ql_mii_enable_scan_mode(qdev);
700
701 return 0;
702}
703
704static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
705{
706 struct ql3xxx_port_registers __iomem *port_regs =
707 qdev->mem_map_registers;
708
709 ql_mii_disable_scan_mode(qdev);
710
711 if (ql_wait_for_mii_ready(qdev)) {
712 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
713 return -1;
714 }
715
716 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
717 qdev->PHYAddr | regAddr);
718
719 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
720
721 /* Wait for write to complete. */
722 if (ql_wait_for_mii_ready(qdev)) {
723 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
724 return -1;
725 }
726
727 ql_mii_enable_scan_mode(qdev);
728
729 return 0;
730}
731
732static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
733{
734 u32 temp;
735 struct ql3xxx_port_registers __iomem *port_regs =
736 qdev->mem_map_registers;
737
738 ql_mii_disable_scan_mode(qdev);
739
740 if (ql_wait_for_mii_ready(qdev)) {
741 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
742 return -1;
743 }
744
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
746 qdev->PHYAddr | regAddr);
747
748 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
749 (MAC_MII_CONTROL_RC << 16));
750
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
752 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
753
754 /* Wait for the read to complete */
755 if (ql_wait_for_mii_ready(qdev)) {
756 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
757 return -1;
758 }
759
760 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
761 *value = (u16) temp;
762
763 ql_mii_enable_scan_mode(qdev);
764
765 return 0;
766}
767
768static void ql_petbi_reset(struct ql3_adapter *qdev)
769{
770 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
771}
772
773static void ql_petbi_start_neg(struct ql3_adapter *qdev)
774{
775 u16 reg;
776
777 /* Enable Auto-negotiation sense */
778 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
779 reg |= PETBI_TBI_AUTO_SENSE;
780 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
781
782 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
783 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
784
785 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
786 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
787 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
788
789}
790
791static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
792{
793 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
794 PHYAddr[qdev->mac_index]);
795}
796
797static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
798{
799 u16 reg;
800
801 /* Enable Auto-negotiation sense */
802 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
803 PHYAddr[qdev->mac_index]);
804 reg |= PETBI_TBI_AUTO_SENSE;
805 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
806 PHYAddr[qdev->mac_index]);
807
808 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
809 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
810 PHYAddr[qdev->mac_index]);
811
812 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
813 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
814 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
815 PHYAddr[qdev->mac_index]);
816}
817
818static void ql_petbi_init(struct ql3_adapter *qdev)
819{
820 ql_petbi_reset(qdev);
821 ql_petbi_start_neg(qdev);
822}
823
824static void ql_petbi_init_ex(struct ql3_adapter *qdev)
825{
826 ql_petbi_reset_ex(qdev);
827 ql_petbi_start_neg_ex(qdev);
828}
829
830static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
831{
832 u16 reg;
833
834 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
835 return 0;
836
837 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
838}
839
840static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
841{
842 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
843 /* power down device bit 11 = 1 */
844 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
845 /* enable diagnostic mode bit 2 = 1 */
846 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
847 /* 1000MB amplitude adjust (see Agere errata) */
848 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
849 /* 1000MB amplitude adjust (see Agere errata) */
850 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
851 /* 100MB amplitude adjust (see Agere errata) */
852 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
853 /* 100MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
855 /* 10MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
857 /* 10MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
859 /* point to hidden reg 0x2806 */
860 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
861 /* Write new PHYAD w/bit 5 set */
862 ql_mii_write_reg_ex(qdev, 0x11,
863 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
864 /*
865 * Disable diagnostic mode bit 2 = 0
866 * Power up device bit 11 = 0
867 * Link up (on) and activity (blink)
868 */
869 ql_mii_write_reg(qdev, 0x12, 0x840a);
870 ql_mii_write_reg(qdev, 0x00, 0x1140);
871 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
872}
873
874static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
875 u16 phyIdReg0, u16 phyIdReg1)
876{
877 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
878 u32 oui;
879 u16 model;
880 int i;
881
882 if (phyIdReg0 == 0xffff)
883 return result;
884
885 if (phyIdReg1 == 0xffff)
886 return result;
887
888 /* oui is split between two registers */
889 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
890
891 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
892
893 /* Scan table for this PHY */
894 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
895 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
896 (model == PHY_DEVICES[i].phyIdModel)) {
897 netdev_info(qdev->ndev, "Phy: %s\n",
898 PHY_DEVICES[i].name);
899 result = PHY_DEVICES[i].phyDevice;
900 break;
901 }
902 }
903
904 return result;
905}
906
907static int ql_phy_get_speed(struct ql3_adapter *qdev)
908{
909 u16 reg;
910
911 switch (qdev->phyType) {
912 case PHY_AGERE_ET1011C: {
913 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
914 return 0;
915
916 reg = (reg >> 8) & 3;
917 break;
918 }
919 default:
920 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
921 return 0;
922
923 reg = (((reg & 0x18) >> 3) & 3);
924 }
925
926 switch (reg) {
927 case 2:
928 return SPEED_1000;
929 case 1:
930 return SPEED_100;
931 case 0:
932 return SPEED_10;
933 default:
934 return -1;
935 }
936}
937
938static int ql_is_full_dup(struct ql3_adapter *qdev)
939{
940 u16 reg;
941
942 switch (qdev->phyType) {
943 case PHY_AGERE_ET1011C: {
944 if (ql_mii_read_reg(qdev, 0x1A, ®))
945 return 0;
946
947 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
948 }
949 case PHY_VITESSE_VSC8211:
950 default: {
951 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
952 return 0;
953 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
954 }
955 }
956}
957
958static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
959{
960 u16 reg;
961
962 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
963 return 0;
964
965 return (reg & PHY_NEG_PAUSE) != 0;
966}
967
968static int PHY_Setup(struct ql3_adapter *qdev)
969{
970 u16 reg1;
971 u16 reg2;
972 bool agereAddrChangeNeeded = false;
973 u32 miiAddr = 0;
974 int err;
975
976 /* Determine the PHY we are using by reading the ID's */
977 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
978 if (err != 0) {
979 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
980 return err;
981 }
982
983 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
984 if (err != 0) {
985 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
986 return err;
987 }
988
989 /* Check if we have a Agere PHY */
990 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
991
992 /* Determine which MII address we should be using
993 determined by the index of the card */
994 if (qdev->mac_index == 0)
995 miiAddr = MII_AGERE_ADDR_1;
996 else
997 miiAddr = MII_AGERE_ADDR_2;
998
999 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1000 if (err != 0) {
1001 netdev_err(qdev->ndev,
1002 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1003 return err;
1004 }
1005
1006 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1007 if (err != 0) {
1008 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1009 return err;
1010 }
1011
1012 /* We need to remember to initialize the Agere PHY */
1013 agereAddrChangeNeeded = true;
1014 }
1015
1016 /* Determine the particular PHY we have on board to apply
1017 PHY specific initializations */
1018 qdev->phyType = getPhyType(qdev, reg1, reg2);
1019
1020 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1021 /* need this here so address gets changed */
1022 phyAgereSpecificInit(qdev, miiAddr);
1023 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1024 netdev_err(qdev->ndev, "PHY is unknown\n");
1025 return -EIO;
1026 }
1027
1028 return 0;
1029}
1030
1031/*
1032 * Caller holds hw_lock.
1033 */
1034static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1035{
1036 struct ql3xxx_port_registers __iomem *port_regs =
1037 qdev->mem_map_registers;
1038 u32 value;
1039
1040 if (enable)
1041 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1042 else
1043 value = (MAC_CONFIG_REG_PE << 16);
1044
1045 if (qdev->mac_index)
1046 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1047 else
1048 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1049}
1050
1051/*
1052 * Caller holds hw_lock.
1053 */
1054static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1055{
1056 struct ql3xxx_port_registers __iomem *port_regs =
1057 qdev->mem_map_registers;
1058 u32 value;
1059
1060 if (enable)
1061 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1062 else
1063 value = (MAC_CONFIG_REG_SR << 16);
1064
1065 if (qdev->mac_index)
1066 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1067 else
1068 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1069}
1070
1071/*
1072 * Caller holds hw_lock.
1073 */
1074static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1075{
1076 struct ql3xxx_port_registers __iomem *port_regs =
1077 qdev->mem_map_registers;
1078 u32 value;
1079
1080 if (enable)
1081 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1082 else
1083 value = (MAC_CONFIG_REG_GM << 16);
1084
1085 if (qdev->mac_index)
1086 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1087 else
1088 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1089}
1090
1091/*
1092 * Caller holds hw_lock.
1093 */
1094static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1095{
1096 struct ql3xxx_port_registers __iomem *port_regs =
1097 qdev->mem_map_registers;
1098 u32 value;
1099
1100 if (enable)
1101 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1102 else
1103 value = (MAC_CONFIG_REG_FD << 16);
1104
1105 if (qdev->mac_index)
1106 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1107 else
1108 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1109}
1110
1111/*
1112 * Caller holds hw_lock.
1113 */
1114static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1115{
1116 struct ql3xxx_port_registers __iomem *port_regs =
1117 qdev->mem_map_registers;
1118 u32 value;
1119
1120 if (enable)
1121 value =
1122 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1123 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1124 else
1125 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1126
1127 if (qdev->mac_index)
1128 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1129 else
1130 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1131}
1132
1133/*
1134 * Caller holds hw_lock.
1135 */
1136static int ql_is_fiber(struct ql3_adapter *qdev)
1137{
1138 struct ql3xxx_port_registers __iomem *port_regs =
1139 qdev->mem_map_registers;
1140 u32 bitToCheck = 0;
1141 u32 temp;
1142
1143 switch (qdev->mac_index) {
1144 case 0:
1145 bitToCheck = PORT_STATUS_SM0;
1146 break;
1147 case 1:
1148 bitToCheck = PORT_STATUS_SM1;
1149 break;
1150 }
1151
1152 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1153 return (temp & bitToCheck) != 0;
1154}
1155
1156static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1157{
1158 u16 reg;
1159 ql_mii_read_reg(qdev, 0x00, ®);
1160 return (reg & 0x1000) != 0;
1161}
1162
1163/*
1164 * Caller holds hw_lock.
1165 */
1166static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1167{
1168 struct ql3xxx_port_registers __iomem *port_regs =
1169 qdev->mem_map_registers;
1170 u32 bitToCheck = 0;
1171 u32 temp;
1172
1173 switch (qdev->mac_index) {
1174 case 0:
1175 bitToCheck = PORT_STATUS_AC0;
1176 break;
1177 case 1:
1178 bitToCheck = PORT_STATUS_AC1;
1179 break;
1180 }
1181
1182 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1183 if (temp & bitToCheck) {
1184 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1185 return 1;
1186 }
1187 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1188 return 0;
1189}
1190
1191/*
1192 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1193 */
1194static int ql_is_neg_pause(struct ql3_adapter *qdev)
1195{
1196 if (ql_is_fiber(qdev))
1197 return ql_is_petbi_neg_pause(qdev);
1198 else
1199 return ql_is_phy_neg_pause(qdev);
1200}
1201
1202static int ql_auto_neg_error(struct ql3_adapter *qdev)
1203{
1204 struct ql3xxx_port_registers __iomem *port_regs =
1205 qdev->mem_map_registers;
1206 u32 bitToCheck = 0;
1207 u32 temp;
1208
1209 switch (qdev->mac_index) {
1210 case 0:
1211 bitToCheck = PORT_STATUS_AE0;
1212 break;
1213 case 1:
1214 bitToCheck = PORT_STATUS_AE1;
1215 break;
1216 }
1217 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1218 return (temp & bitToCheck) != 0;
1219}
1220
1221static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1222{
1223 if (ql_is_fiber(qdev))
1224 return SPEED_1000;
1225 else
1226 return ql_phy_get_speed(qdev);
1227}
1228
1229static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1230{
1231 if (ql_is_fiber(qdev))
1232 return 1;
1233 else
1234 return ql_is_full_dup(qdev);
1235}
1236
1237/*
1238 * Caller holds hw_lock.
1239 */
1240static int ql_link_down_detect(struct ql3_adapter *qdev)
1241{
1242 struct ql3xxx_port_registers __iomem *port_regs =
1243 qdev->mem_map_registers;
1244 u32 bitToCheck = 0;
1245 u32 temp;
1246
1247 switch (qdev->mac_index) {
1248 case 0:
1249 bitToCheck = ISP_CONTROL_LINK_DN_0;
1250 break;
1251 case 1:
1252 bitToCheck = ISP_CONTROL_LINK_DN_1;
1253 break;
1254 }
1255
1256 temp =
1257 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1258 return (temp & bitToCheck) != 0;
1259}
1260
1261/*
1262 * Caller holds hw_lock.
1263 */
1264static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1265{
1266 struct ql3xxx_port_registers __iomem *port_regs =
1267 qdev->mem_map_registers;
1268
1269 switch (qdev->mac_index) {
1270 case 0:
1271 ql_write_common_reg(qdev,
1272 &port_regs->CommonRegs.ispControlStatus,
1273 (ISP_CONTROL_LINK_DN_0) |
1274 (ISP_CONTROL_LINK_DN_0 << 16));
1275 break;
1276
1277 case 1:
1278 ql_write_common_reg(qdev,
1279 &port_regs->CommonRegs.ispControlStatus,
1280 (ISP_CONTROL_LINK_DN_1) |
1281 (ISP_CONTROL_LINK_DN_1 << 16));
1282 break;
1283
1284 default:
1285 return 1;
1286 }
1287
1288 return 0;
1289}
1290
1291/*
1292 * Caller holds hw_lock.
1293 */
1294static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1295{
1296 struct ql3xxx_port_registers __iomem *port_regs =
1297 qdev->mem_map_registers;
1298 u32 bitToCheck = 0;
1299 u32 temp;
1300
1301 switch (qdev->mac_index) {
1302 case 0:
1303 bitToCheck = PORT_STATUS_F1_ENABLED;
1304 break;
1305 case 1:
1306 bitToCheck = PORT_STATUS_F3_ENABLED;
1307 break;
1308 default:
1309 break;
1310 }
1311
1312 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1313 if (temp & bitToCheck) {
1314 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1315 "not link master\n");
1316 return 0;
1317 }
1318
1319 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1320 return 1;
1321}
1322
1323static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1324{
1325 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1326 PHYAddr[qdev->mac_index]);
1327}
1328
1329static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1330{
1331 u16 reg;
1332 u16 portConfiguration;
1333
1334 if (qdev->phyType == PHY_AGERE_ET1011C)
1335 ql_mii_write_reg(qdev, 0x13, 0x0000);
1336 /* turn off external loopback */
1337
1338 if (qdev->mac_index == 0)
1339 portConfiguration =
1340 qdev->nvram_data.macCfg_port0.portConfiguration;
1341 else
1342 portConfiguration =
1343 qdev->nvram_data.macCfg_port1.portConfiguration;
1344
1345 /* Some HBA's in the field are set to 0 and they need to
1346 be reinterpreted with a default value */
1347 if (portConfiguration == 0)
1348 portConfiguration = PORT_CONFIG_DEFAULT;
1349
1350 /* Set the 1000 advertisements */
1351 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1352 PHYAddr[qdev->mac_index]);
1353 reg &= ~PHY_GIG_ALL_PARAMS;
1354
1355 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1356 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1357 reg |= PHY_GIG_ADV_1000F;
1358 else
1359 reg |= PHY_GIG_ADV_1000H;
1360 }
1361
1362 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1363 PHYAddr[qdev->mac_index]);
1364
1365 /* Set the 10/100 & pause negotiation advertisements */
1366 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1367 PHYAddr[qdev->mac_index]);
1368 reg &= ~PHY_NEG_ALL_PARAMS;
1369
1370 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1371 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1372
1373 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1374 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1375 reg |= PHY_NEG_ADV_100F;
1376
1377 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1378 reg |= PHY_NEG_ADV_10F;
1379 }
1380
1381 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1382 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1383 reg |= PHY_NEG_ADV_100H;
1384
1385 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1386 reg |= PHY_NEG_ADV_10H;
1387 }
1388
1389 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1390 reg |= 1;
1391
1392 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1393 PHYAddr[qdev->mac_index]);
1394
1395 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1396
1397 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1398 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1399 PHYAddr[qdev->mac_index]);
1400}
1401
1402static void ql_phy_init_ex(struct ql3_adapter *qdev)
1403{
1404 ql_phy_reset_ex(qdev);
1405 PHY_Setup(qdev);
1406 ql_phy_start_neg_ex(qdev);
1407}
1408
1409/*
1410 * Caller holds hw_lock.
1411 */
1412static u32 ql_get_link_state(struct ql3_adapter *qdev)
1413{
1414 struct ql3xxx_port_registers __iomem *port_regs =
1415 qdev->mem_map_registers;
1416 u32 bitToCheck = 0;
1417 u32 temp, linkState;
1418
1419 switch (qdev->mac_index) {
1420 case 0:
1421 bitToCheck = PORT_STATUS_UP0;
1422 break;
1423 case 1:
1424 bitToCheck = PORT_STATUS_UP1;
1425 break;
1426 }
1427
1428 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1429 if (temp & bitToCheck)
1430 linkState = LS_UP;
1431 else
1432 linkState = LS_DOWN;
1433
1434 return linkState;
1435}
1436
1437static int ql_port_start(struct ql3_adapter *qdev)
1438{
1439 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1440 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1441 2) << 7)) {
1442 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1443 return -1;
1444 }
1445
1446 if (ql_is_fiber(qdev)) {
1447 ql_petbi_init(qdev);
1448 } else {
1449 /* Copper port */
1450 ql_phy_init_ex(qdev);
1451 }
1452
1453 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1454 return 0;
1455}
1456
1457static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1458{
1459
1460 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1461 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1462 2) << 7))
1463 return -1;
1464
1465 if (!ql_auto_neg_error(qdev)) {
1466 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1467 /* configure the MAC */
1468 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1469 "Configuring link\n");
1470 ql_mac_cfg_soft_reset(qdev, 1);
1471 ql_mac_cfg_gig(qdev,
1472 (ql_get_link_speed
1473 (qdev) ==
1474 SPEED_1000));
1475 ql_mac_cfg_full_dup(qdev,
1476 ql_is_link_full_dup
1477 (qdev));
1478 ql_mac_cfg_pause(qdev,
1479 ql_is_neg_pause
1480 (qdev));
1481 ql_mac_cfg_soft_reset(qdev, 0);
1482
1483 /* enable the MAC */
1484 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1485 "Enabling mac\n");
1486 ql_mac_enable(qdev, 1);
1487 }
1488
1489 qdev->port_link_state = LS_UP;
1490 netif_start_queue(qdev->ndev);
1491 netif_carrier_on(qdev->ndev);
1492 netif_info(qdev, link, qdev->ndev,
1493 "Link is up at %d Mbps, %s duplex\n",
1494 ql_get_link_speed(qdev),
1495 ql_is_link_full_dup(qdev) ? "full" : "half");
1496
1497 } else { /* Remote error detected */
1498
1499 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1500 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1501 "Remote error detected. Calling ql_port_start()\n");
1502 /*
1503 * ql_port_start() is shared code and needs
1504 * to lock the PHY on it's own.
1505 */
1506 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1507 if (ql_port_start(qdev)) /* Restart port */
1508 return -1;
1509 return 0;
1510 }
1511 }
1512 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1513 return 0;
1514}
1515
1516static void ql_link_state_machine_work(struct work_struct *work)
1517{
1518 struct ql3_adapter *qdev =
1519 container_of(work, struct ql3_adapter, link_state_work.work);
1520
1521 u32 curr_link_state;
1522 unsigned long hw_flags;
1523
1524 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1525
1526 curr_link_state = ql_get_link_state(qdev);
1527
1528 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1529 netif_info(qdev, link, qdev->ndev,
1530 "Reset in progress, skip processing link state\n");
1531
1532 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1533
1534 /* Restart timer on 2 second interval. */
1535 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1536
1537 return;
1538 }
1539
1540 switch (qdev->port_link_state) {
1541 default:
1542 if (test_bit(QL_LINK_MASTER, &qdev->flags))
1543 ql_port_start(qdev);
1544 qdev->port_link_state = LS_DOWN;
1545 fallthrough;
1546
1547 case LS_DOWN:
1548 if (curr_link_state == LS_UP) {
1549 netif_info(qdev, link, qdev->ndev, "Link is up\n");
1550 if (ql_is_auto_neg_complete(qdev))
1551 ql_finish_auto_neg(qdev);
1552
1553 if (qdev->port_link_state == LS_UP)
1554 ql_link_down_detect_clear(qdev);
1555
1556 qdev->port_link_state = LS_UP;
1557 }
1558 break;
1559
1560 case LS_UP:
1561 /*
1562 * See if the link is currently down or went down and came
1563 * back up
1564 */
1565 if (curr_link_state == LS_DOWN) {
1566 netif_info(qdev, link, qdev->ndev, "Link is down\n");
1567 qdev->port_link_state = LS_DOWN;
1568 }
1569 if (ql_link_down_detect(qdev))
1570 qdev->port_link_state = LS_DOWN;
1571 break;
1572 }
1573 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1574
1575 /* Restart timer on 2 second interval. */
1576 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1577}
1578
1579/*
1580 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1581 */
1582static void ql_get_phy_owner(struct ql3_adapter *qdev)
1583{
1584 if (ql_this_adapter_controls_port(qdev))
1585 set_bit(QL_LINK_MASTER, &qdev->flags);
1586 else
1587 clear_bit(QL_LINK_MASTER, &qdev->flags);
1588}
1589
1590/*
1591 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1592 */
1593static void ql_init_scan_mode(struct ql3_adapter *qdev)
1594{
1595 ql_mii_enable_scan_mode(qdev);
1596
1597 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1598 if (ql_this_adapter_controls_port(qdev))
1599 ql_petbi_init_ex(qdev);
1600 } else {
1601 if (ql_this_adapter_controls_port(qdev))
1602 ql_phy_init_ex(qdev);
1603 }
1604}
1605
1606/*
1607 * MII_Setup needs to be called before taking the PHY out of reset
1608 * so that the management interface clock speed can be set properly.
1609 * It would be better if we had a way to disable MDC until after the
1610 * PHY is out of reset, but we don't have that capability.
1611 */
1612static int ql_mii_setup(struct ql3_adapter *qdev)
1613{
1614 u32 reg;
1615 struct ql3xxx_port_registers __iomem *port_regs =
1616 qdev->mem_map_registers;
1617
1618 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1619 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1620 2) << 7))
1621 return -1;
1622
1623 if (qdev->device_id == QL3032_DEVICE_ID)
1624 ql_write_page0_reg(qdev,
1625 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1626
1627 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1628 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1629
1630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1631 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1632
1633 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1634 return 0;
1635}
1636
1637#define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1638 SUPPORTED_FIBRE | \
1639 SUPPORTED_Autoneg)
1640#define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1641 SUPPORTED_10baseT_Full | \
1642 SUPPORTED_100baseT_Half | \
1643 SUPPORTED_100baseT_Full | \
1644 SUPPORTED_1000baseT_Half | \
1645 SUPPORTED_1000baseT_Full | \
1646 SUPPORTED_Autoneg | \
1647 SUPPORTED_TP) \
1648
1649static u32 ql_supported_modes(struct ql3_adapter *qdev)
1650{
1651 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1652 return SUPPORTED_OPTICAL_MODES;
1653
1654 return SUPPORTED_TP_MODES;
1655}
1656
1657static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1658{
1659 int status;
1660 unsigned long hw_flags;
1661 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1662 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1663 (QL_RESOURCE_BITS_BASE_CODE |
1664 (qdev->mac_index) * 2) << 7)) {
1665 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1666 return 0;
1667 }
1668 status = ql_is_auto_cfg(qdev);
1669 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1670 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1671 return status;
1672}
1673
1674static u32 ql_get_speed(struct ql3_adapter *qdev)
1675{
1676 u32 status;
1677 unsigned long hw_flags;
1678 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1679 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1680 (QL_RESOURCE_BITS_BASE_CODE |
1681 (qdev->mac_index) * 2) << 7)) {
1682 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1683 return 0;
1684 }
1685 status = ql_get_link_speed(qdev);
1686 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1687 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1688 return status;
1689}
1690
1691static int ql_get_full_dup(struct ql3_adapter *qdev)
1692{
1693 int status;
1694 unsigned long hw_flags;
1695 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1696 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1697 (QL_RESOURCE_BITS_BASE_CODE |
1698 (qdev->mac_index) * 2) << 7)) {
1699 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1700 return 0;
1701 }
1702 status = ql_is_link_full_dup(qdev);
1703 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1704 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1705 return status;
1706}
1707
1708static int ql_get_link_ksettings(struct net_device *ndev,
1709 struct ethtool_link_ksettings *cmd)
1710{
1711 struct ql3_adapter *qdev = netdev_priv(ndev);
1712 u32 supported, advertising;
1713
1714 supported = ql_supported_modes(qdev);
1715
1716 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1717 cmd->base.port = PORT_FIBRE;
1718 } else {
1719 cmd->base.port = PORT_TP;
1720 cmd->base.phy_address = qdev->PHYAddr;
1721 }
1722 advertising = ql_supported_modes(qdev);
1723 cmd->base.autoneg = ql_get_auto_cfg_status(qdev);
1724 cmd->base.speed = ql_get_speed(qdev);
1725 cmd->base.duplex = ql_get_full_dup(qdev);
1726
1727 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1728 supported);
1729 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1730 advertising);
1731
1732 return 0;
1733}
1734
1735static void ql_get_drvinfo(struct net_device *ndev,
1736 struct ethtool_drvinfo *drvinfo)
1737{
1738 struct ql3_adapter *qdev = netdev_priv(ndev);
1739 strscpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1740 strscpy(drvinfo->version, ql3xxx_driver_version,
1741 sizeof(drvinfo->version));
1742 strscpy(drvinfo->bus_info, pci_name(qdev->pdev),
1743 sizeof(drvinfo->bus_info));
1744}
1745
1746static u32 ql_get_msglevel(struct net_device *ndev)
1747{
1748 struct ql3_adapter *qdev = netdev_priv(ndev);
1749 return qdev->msg_enable;
1750}
1751
1752static void ql_set_msglevel(struct net_device *ndev, u32 value)
1753{
1754 struct ql3_adapter *qdev = netdev_priv(ndev);
1755 qdev->msg_enable = value;
1756}
1757
1758static void ql_get_pauseparam(struct net_device *ndev,
1759 struct ethtool_pauseparam *pause)
1760{
1761 struct ql3_adapter *qdev = netdev_priv(ndev);
1762 struct ql3xxx_port_registers __iomem *port_regs =
1763 qdev->mem_map_registers;
1764
1765 u32 reg;
1766 if (qdev->mac_index == 0)
1767 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1768 else
1769 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1770
1771 pause->autoneg = ql_get_auto_cfg_status(qdev);
1772 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1773 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1774}
1775
1776static const struct ethtool_ops ql3xxx_ethtool_ops = {
1777 .get_drvinfo = ql_get_drvinfo,
1778 .get_link = ethtool_op_get_link,
1779 .get_msglevel = ql_get_msglevel,
1780 .set_msglevel = ql_set_msglevel,
1781 .get_pauseparam = ql_get_pauseparam,
1782 .get_link_ksettings = ql_get_link_ksettings,
1783};
1784
1785static int ql_populate_free_queue(struct ql3_adapter *qdev)
1786{
1787 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1788 dma_addr_t map;
1789 int err;
1790
1791 while (lrg_buf_cb) {
1792 if (!lrg_buf_cb->skb) {
1793 lrg_buf_cb->skb =
1794 netdev_alloc_skb(qdev->ndev,
1795 qdev->lrg_buffer_len);
1796 if (unlikely(!lrg_buf_cb->skb)) {
1797 netdev_printk(KERN_DEBUG, qdev->ndev,
1798 "Failed netdev_alloc_skb()\n");
1799 break;
1800 } else {
1801 /*
1802 * We save some space to copy the ethhdr from
1803 * first buffer
1804 */
1805 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1806 map = dma_map_single(&qdev->pdev->dev,
1807 lrg_buf_cb->skb->data,
1808 qdev->lrg_buffer_len - QL_HEADER_SPACE,
1809 DMA_FROM_DEVICE);
1810
1811 err = dma_mapping_error(&qdev->pdev->dev, map);
1812 if (err) {
1813 netdev_err(qdev->ndev,
1814 "PCI mapping failed with error: %d\n",
1815 err);
1816 dev_kfree_skb(lrg_buf_cb->skb);
1817 lrg_buf_cb->skb = NULL;
1818 break;
1819 }
1820
1821
1822 lrg_buf_cb->buf_phy_addr_low =
1823 cpu_to_le32(LS_64BITS(map));
1824 lrg_buf_cb->buf_phy_addr_high =
1825 cpu_to_le32(MS_64BITS(map));
1826 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1827 dma_unmap_len_set(lrg_buf_cb, maplen,
1828 qdev->lrg_buffer_len -
1829 QL_HEADER_SPACE);
1830 --qdev->lrg_buf_skb_check;
1831 if (!qdev->lrg_buf_skb_check)
1832 return 1;
1833 }
1834 }
1835 lrg_buf_cb = lrg_buf_cb->next;
1836 }
1837 return 0;
1838}
1839
1840/*
1841 * Caller holds hw_lock.
1842 */
1843static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1844{
1845 struct ql3xxx_port_registers __iomem *port_regs =
1846 qdev->mem_map_registers;
1847
1848 if (qdev->small_buf_release_cnt >= 16) {
1849 while (qdev->small_buf_release_cnt >= 16) {
1850 qdev->small_buf_q_producer_index++;
1851
1852 if (qdev->small_buf_q_producer_index ==
1853 NUM_SBUFQ_ENTRIES)
1854 qdev->small_buf_q_producer_index = 0;
1855 qdev->small_buf_release_cnt -= 8;
1856 }
1857 wmb();
1858 writel_relaxed(qdev->small_buf_q_producer_index,
1859 &port_regs->CommonRegs.rxSmallQProducerIndex);
1860 }
1861}
1862
1863/*
1864 * Caller holds hw_lock.
1865 */
1866static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1867{
1868 struct bufq_addr_element *lrg_buf_q_ele;
1869 int i;
1870 struct ql_rcv_buf_cb *lrg_buf_cb;
1871 struct ql3xxx_port_registers __iomem *port_regs =
1872 qdev->mem_map_registers;
1873
1874 if ((qdev->lrg_buf_free_count >= 8) &&
1875 (qdev->lrg_buf_release_cnt >= 16)) {
1876
1877 if (qdev->lrg_buf_skb_check)
1878 if (!ql_populate_free_queue(qdev))
1879 return;
1880
1881 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1882
1883 while ((qdev->lrg_buf_release_cnt >= 16) &&
1884 (qdev->lrg_buf_free_count >= 8)) {
1885
1886 for (i = 0; i < 8; i++) {
1887 lrg_buf_cb =
1888 ql_get_from_lrg_buf_free_list(qdev);
1889 lrg_buf_q_ele->addr_high =
1890 lrg_buf_cb->buf_phy_addr_high;
1891 lrg_buf_q_ele->addr_low =
1892 lrg_buf_cb->buf_phy_addr_low;
1893 lrg_buf_q_ele++;
1894
1895 qdev->lrg_buf_release_cnt--;
1896 }
1897
1898 qdev->lrg_buf_q_producer_index++;
1899
1900 if (qdev->lrg_buf_q_producer_index ==
1901 qdev->num_lbufq_entries)
1902 qdev->lrg_buf_q_producer_index = 0;
1903
1904 if (qdev->lrg_buf_q_producer_index ==
1905 (qdev->num_lbufq_entries - 1)) {
1906 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1907 }
1908 }
1909 wmb();
1910 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1911 writel(qdev->lrg_buf_q_producer_index,
1912 &port_regs->CommonRegs.rxLargeQProducerIndex);
1913 }
1914}
1915
1916static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1917 struct ob_mac_iocb_rsp *mac_rsp)
1918{
1919 struct ql_tx_buf_cb *tx_cb;
1920 int i;
1921
1922 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1923 netdev_warn(qdev->ndev,
1924 "Frame too short but it was padded and sent\n");
1925 }
1926
1927 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1928
1929 /* Check the transmit response flags for any errors */
1930 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1931 netdev_err(qdev->ndev,
1932 "Frame too short to be legal, frame not sent\n");
1933
1934 qdev->ndev->stats.tx_errors++;
1935 goto frame_not_sent;
1936 }
1937
1938 if (tx_cb->seg_count == 0) {
1939 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1940 mac_rsp->transaction_id);
1941
1942 qdev->ndev->stats.tx_errors++;
1943 goto invalid_seg_count;
1944 }
1945
1946 dma_unmap_single(&qdev->pdev->dev,
1947 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1948 dma_unmap_len(&tx_cb->map[0], maplen), DMA_TO_DEVICE);
1949 tx_cb->seg_count--;
1950 if (tx_cb->seg_count) {
1951 for (i = 1; i < tx_cb->seg_count; i++) {
1952 dma_unmap_page(&qdev->pdev->dev,
1953 dma_unmap_addr(&tx_cb->map[i], mapaddr),
1954 dma_unmap_len(&tx_cb->map[i], maplen),
1955 DMA_TO_DEVICE);
1956 }
1957 }
1958 qdev->ndev->stats.tx_packets++;
1959 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1960
1961frame_not_sent:
1962 dev_kfree_skb_irq(tx_cb->skb);
1963 tx_cb->skb = NULL;
1964
1965invalid_seg_count:
1966 atomic_inc(&qdev->tx_count);
1967}
1968
1969static void ql_get_sbuf(struct ql3_adapter *qdev)
1970{
1971 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1972 qdev->small_buf_index = 0;
1973 qdev->small_buf_release_cnt++;
1974}
1975
1976static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1977{
1978 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1979 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1980 qdev->lrg_buf_release_cnt++;
1981 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1982 qdev->lrg_buf_index = 0;
1983 return lrg_buf_cb;
1984}
1985
1986/*
1987 * The difference between 3022 and 3032 for inbound completions:
1988 * 3022 uses two buffers per completion. The first buffer contains
1989 * (some) header info, the second the remainder of the headers plus
1990 * the data. For this chip we reserve some space at the top of the
1991 * receive buffer so that the header info in buffer one can be
1992 * prepended to the buffer two. Buffer two is the sent up while
1993 * buffer one is returned to the hardware to be reused.
1994 * 3032 receives all of it's data and headers in one buffer for a
1995 * simpler process. 3032 also supports checksum verification as
1996 * can be seen in ql_process_macip_rx_intr().
1997 */
1998static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1999 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2000{
2001 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2002 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2003 struct sk_buff *skb;
2004 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2005
2006 /*
2007 * Get the inbound address list (small buffer).
2008 */
2009 ql_get_sbuf(qdev);
2010
2011 if (qdev->device_id == QL3022_DEVICE_ID)
2012 lrg_buf_cb1 = ql_get_lbuf(qdev);
2013
2014 /* start of second buffer */
2015 lrg_buf_cb2 = ql_get_lbuf(qdev);
2016 skb = lrg_buf_cb2->skb;
2017
2018 qdev->ndev->stats.rx_packets++;
2019 qdev->ndev->stats.rx_bytes += length;
2020
2021 skb_put(skb, length);
2022 dma_unmap_single(&qdev->pdev->dev,
2023 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2024 dma_unmap_len(lrg_buf_cb2, maplen), DMA_FROM_DEVICE);
2025 prefetch(skb->data);
2026 skb_checksum_none_assert(skb);
2027 skb->protocol = eth_type_trans(skb, qdev->ndev);
2028
2029 napi_gro_receive(&qdev->napi, skb);
2030 lrg_buf_cb2->skb = NULL;
2031
2032 if (qdev->device_id == QL3022_DEVICE_ID)
2033 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2034 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2035}
2036
2037static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2038 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2039{
2040 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2041 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2042 struct sk_buff *skb1 = NULL, *skb2;
2043 struct net_device *ndev = qdev->ndev;
2044 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2045 u16 size = 0;
2046
2047 /*
2048 * Get the inbound address list (small buffer).
2049 */
2050
2051 ql_get_sbuf(qdev);
2052
2053 if (qdev->device_id == QL3022_DEVICE_ID) {
2054 /* start of first buffer on 3022 */
2055 lrg_buf_cb1 = ql_get_lbuf(qdev);
2056 skb1 = lrg_buf_cb1->skb;
2057 size = ETH_HLEN;
2058 if (*((u16 *) skb1->data) != 0xFFFF)
2059 size += VLAN_ETH_HLEN - ETH_HLEN;
2060 }
2061
2062 /* start of second buffer */
2063 lrg_buf_cb2 = ql_get_lbuf(qdev);
2064 skb2 = lrg_buf_cb2->skb;
2065
2066 skb_put(skb2, length); /* Just the second buffer length here. */
2067 dma_unmap_single(&qdev->pdev->dev,
2068 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2069 dma_unmap_len(lrg_buf_cb2, maplen), DMA_FROM_DEVICE);
2070 prefetch(skb2->data);
2071
2072 skb_checksum_none_assert(skb2);
2073 if (qdev->device_id == QL3022_DEVICE_ID) {
2074 /*
2075 * Copy the ethhdr from first buffer to second. This
2076 * is necessary for 3022 IP completions.
2077 */
2078 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2079 skb_push(skb2, size), size);
2080 } else {
2081 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2082 if (checksum &
2083 (IB_IP_IOCB_RSP_3032_ICE |
2084 IB_IP_IOCB_RSP_3032_CE)) {
2085 netdev_err(ndev,
2086 "%s: Bad checksum for this %s packet, checksum = %x\n",
2087 __func__,
2088 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2089 "TCP" : "UDP"), checksum);
2090 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2091 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2092 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2093 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2094 }
2095 }
2096 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2097
2098 napi_gro_receive(&qdev->napi, skb2);
2099 ndev->stats.rx_packets++;
2100 ndev->stats.rx_bytes += length;
2101 lrg_buf_cb2->skb = NULL;
2102
2103 if (qdev->device_id == QL3022_DEVICE_ID)
2104 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2105 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2106}
2107
2108static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget)
2109{
2110 struct net_rsp_iocb *net_rsp;
2111 struct net_device *ndev = qdev->ndev;
2112 int work_done = 0;
2113
2114 /* While there are entries in the completion queue. */
2115 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2116 qdev->rsp_consumer_index) && (work_done < budget)) {
2117
2118 net_rsp = qdev->rsp_current;
2119 rmb();
2120 /*
2121 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2122 * if the inbound completion is for a VLAN.
2123 */
2124 if (qdev->device_id == QL3032_DEVICE_ID)
2125 net_rsp->opcode &= 0x7f;
2126 switch (net_rsp->opcode) {
2127
2128 case OPCODE_OB_MAC_IOCB_FN0:
2129 case OPCODE_OB_MAC_IOCB_FN2:
2130 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2131 net_rsp);
2132 break;
2133
2134 case OPCODE_IB_MAC_IOCB:
2135 case OPCODE_IB_3032_MAC_IOCB:
2136 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2137 net_rsp);
2138 work_done++;
2139 break;
2140
2141 case OPCODE_IB_IP_IOCB:
2142 case OPCODE_IB_3032_IP_IOCB:
2143 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2144 net_rsp);
2145 work_done++;
2146 break;
2147 default: {
2148 u32 *tmp = (u32 *)net_rsp;
2149 netdev_err(ndev,
2150 "Hit default case, not handled!\n"
2151 " dropping the packet, opcode = %x\n"
2152 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2153 net_rsp->opcode,
2154 (unsigned long int)tmp[0],
2155 (unsigned long int)tmp[1],
2156 (unsigned long int)tmp[2],
2157 (unsigned long int)tmp[3]);
2158 }
2159 }
2160
2161 qdev->rsp_consumer_index++;
2162
2163 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2164 qdev->rsp_consumer_index = 0;
2165 qdev->rsp_current = qdev->rsp_q_virt_addr;
2166 } else {
2167 qdev->rsp_current++;
2168 }
2169
2170 }
2171
2172 return work_done;
2173}
2174
2175static int ql_poll(struct napi_struct *napi, int budget)
2176{
2177 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2178 struct ql3xxx_port_registers __iomem *port_regs =
2179 qdev->mem_map_registers;
2180 int work_done;
2181
2182 work_done = ql_tx_rx_clean(qdev, budget);
2183
2184 if (work_done < budget && napi_complete_done(napi, work_done)) {
2185 unsigned long flags;
2186
2187 spin_lock_irqsave(&qdev->hw_lock, flags);
2188 ql_update_small_bufq_prod_index(qdev);
2189 ql_update_lrg_bufq_prod_index(qdev);
2190 writel(qdev->rsp_consumer_index,
2191 &port_regs->CommonRegs.rspQConsumerIndex);
2192 spin_unlock_irqrestore(&qdev->hw_lock, flags);
2193
2194 ql_enable_interrupts(qdev);
2195 }
2196 return work_done;
2197}
2198
2199static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2200{
2201
2202 struct net_device *ndev = dev_id;
2203 struct ql3_adapter *qdev = netdev_priv(ndev);
2204 struct ql3xxx_port_registers __iomem *port_regs =
2205 qdev->mem_map_registers;
2206 u32 value;
2207 int handled = 1;
2208 u32 var;
2209
2210 value = ql_read_common_reg_l(qdev,
2211 &port_regs->CommonRegs.ispControlStatus);
2212
2213 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2214 spin_lock(&qdev->adapter_lock);
2215 netif_stop_queue(qdev->ndev);
2216 netif_carrier_off(qdev->ndev);
2217 ql_disable_interrupts(qdev);
2218 qdev->port_link_state = LS_DOWN;
2219 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2220
2221 if (value & ISP_CONTROL_FE) {
2222 /*
2223 * Chip Fatal Error.
2224 */
2225 var =
2226 ql_read_page0_reg_l(qdev,
2227 &port_regs->PortFatalErrStatus);
2228 netdev_warn(ndev,
2229 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2230 var);
2231 set_bit(QL_RESET_START, &qdev->flags) ;
2232 } else {
2233 /*
2234 * Soft Reset Requested.
2235 */
2236 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2237 netdev_err(ndev,
2238 "Another function issued a reset to the chip. ISR value = %x\n",
2239 value);
2240 }
2241 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2242 spin_unlock(&qdev->adapter_lock);
2243 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2244 ql_disable_interrupts(qdev);
2245 if (likely(napi_schedule_prep(&qdev->napi)))
2246 __napi_schedule(&qdev->napi);
2247 } else
2248 return IRQ_NONE;
2249
2250 return IRQ_RETVAL(handled);
2251}
2252
2253/*
2254 * Get the total number of segments needed for the given number of fragments.
2255 * This is necessary because outbound address lists (OAL) will be used when
2256 * more than two frags are given. Each address list has 5 addr/len pairs.
2257 * The 5th pair in each OAL is used to point to the next OAL if more frags
2258 * are coming. That is why the frags:segment count ratio is not linear.
2259 */
2260static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2261{
2262 if (qdev->device_id == QL3022_DEVICE_ID)
2263 return 1;
2264
2265 if (frags <= 2)
2266 return frags + 1;
2267 else if (frags <= 6)
2268 return frags + 2;
2269 else if (frags <= 10)
2270 return frags + 3;
2271 else if (frags <= 14)
2272 return frags + 4;
2273 else if (frags <= 18)
2274 return frags + 5;
2275 return -1;
2276}
2277
2278static void ql_hw_csum_setup(const struct sk_buff *skb,
2279 struct ob_mac_iocb_req *mac_iocb_ptr)
2280{
2281 const struct iphdr *ip = ip_hdr(skb);
2282
2283 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2284 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2285
2286 if (ip->protocol == IPPROTO_TCP) {
2287 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2288 OB_3032MAC_IOCB_REQ_IC;
2289 } else {
2290 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2291 OB_3032MAC_IOCB_REQ_IC;
2292 }
2293
2294}
2295
2296/*
2297 * Map the buffers for this transmit.
2298 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2299 */
2300static int ql_send_map(struct ql3_adapter *qdev,
2301 struct ob_mac_iocb_req *mac_iocb_ptr,
2302 struct ql_tx_buf_cb *tx_cb,
2303 struct sk_buff *skb)
2304{
2305 struct oal *oal;
2306 struct oal_entry *oal_entry;
2307 int len = skb_headlen(skb);
2308 dma_addr_t map;
2309 int err;
2310 int completed_segs, i;
2311 int seg_cnt, seg = 0;
2312 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2313
2314 seg_cnt = tx_cb->seg_count;
2315 /*
2316 * Map the skb buffer first.
2317 */
2318 map = dma_map_single(&qdev->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2319
2320 err = dma_mapping_error(&qdev->pdev->dev, map);
2321 if (err) {
2322 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2323 err);
2324
2325 return NETDEV_TX_BUSY;
2326 }
2327
2328 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2329 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2330 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2331 oal_entry->len = cpu_to_le32(len);
2332 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2333 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2334 seg++;
2335
2336 if (seg_cnt == 1) {
2337 /* Terminate the last segment. */
2338 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2339 return NETDEV_TX_OK;
2340 }
2341 oal = tx_cb->oal;
2342 for (completed_segs = 0;
2343 completed_segs < frag_cnt;
2344 completed_segs++, seg++) {
2345 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2346 oal_entry++;
2347 /*
2348 * Check for continuation requirements.
2349 * It's strange but necessary.
2350 * Continuation entry points to outbound address list.
2351 */
2352 if ((seg == 2 && seg_cnt > 3) ||
2353 (seg == 7 && seg_cnt > 8) ||
2354 (seg == 12 && seg_cnt > 13) ||
2355 (seg == 17 && seg_cnt > 18)) {
2356 map = dma_map_single(&qdev->pdev->dev, oal,
2357 sizeof(struct oal),
2358 DMA_TO_DEVICE);
2359
2360 err = dma_mapping_error(&qdev->pdev->dev, map);
2361 if (err) {
2362 netdev_err(qdev->ndev,
2363 "PCI mapping outbound address list with error: %d\n",
2364 err);
2365 goto map_error;
2366 }
2367
2368 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2369 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2370 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2371 OAL_CONT_ENTRY);
2372 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2373 dma_unmap_len_set(&tx_cb->map[seg], maplen,
2374 sizeof(struct oal));
2375 oal_entry = (struct oal_entry *)oal;
2376 oal++;
2377 seg++;
2378 }
2379
2380 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2381 DMA_TO_DEVICE);
2382
2383 err = dma_mapping_error(&qdev->pdev->dev, map);
2384 if (err) {
2385 netdev_err(qdev->ndev,
2386 "PCI mapping frags failed with error: %d\n",
2387 err);
2388 goto map_error;
2389 }
2390
2391 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2392 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2393 oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2394 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2395 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2396 }
2397 /* Terminate the last segment. */
2398 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2399 return NETDEV_TX_OK;
2400
2401map_error:
2402 /* A PCI mapping failed and now we will need to back out
2403 * We need to traverse through the oal's and associated pages which
2404 * have been mapped and now we must unmap them to clean up properly
2405 */
2406
2407 seg = 1;
2408 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2409 oal = tx_cb->oal;
2410 for (i = 0; i < completed_segs; i++, seg++) {
2411 oal_entry++;
2412
2413 /*
2414 * Check for continuation requirements.
2415 * It's strange but necessary.
2416 */
2417
2418 if ((seg == 2 && seg_cnt > 3) ||
2419 (seg == 7 && seg_cnt > 8) ||
2420 (seg == 12 && seg_cnt > 13) ||
2421 (seg == 17 && seg_cnt > 18)) {
2422 dma_unmap_single(&qdev->pdev->dev,
2423 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2424 dma_unmap_len(&tx_cb->map[seg], maplen),
2425 DMA_TO_DEVICE);
2426 oal++;
2427 seg++;
2428 }
2429
2430 dma_unmap_page(&qdev->pdev->dev,
2431 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2432 dma_unmap_len(&tx_cb->map[seg], maplen),
2433 DMA_TO_DEVICE);
2434 }
2435
2436 dma_unmap_single(&qdev->pdev->dev,
2437 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2438 dma_unmap_addr(&tx_cb->map[0], maplen),
2439 DMA_TO_DEVICE);
2440
2441 return NETDEV_TX_BUSY;
2442
2443}
2444
2445/*
2446 * The difference between 3022 and 3032 sends:
2447 * 3022 only supports a simple single segment transmission.
2448 * 3032 supports checksumming and scatter/gather lists (fragments).
2449 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2450 * in the IOCB plus a chain of outbound address lists (OAL) that
2451 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2452 * will be used to point to an OAL when more ALP entries are required.
2453 * The IOCB is always the top of the chain followed by one or more
2454 * OALs (when necessary).
2455 */
2456static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2457 struct net_device *ndev)
2458{
2459 struct ql3_adapter *qdev = netdev_priv(ndev);
2460 struct ql3xxx_port_registers __iomem *port_regs =
2461 qdev->mem_map_registers;
2462 struct ql_tx_buf_cb *tx_cb;
2463 u32 tot_len = skb->len;
2464 struct ob_mac_iocb_req *mac_iocb_ptr;
2465
2466 if (unlikely(atomic_read(&qdev->tx_count) < 2))
2467 return NETDEV_TX_BUSY;
2468
2469 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2470 tx_cb->seg_count = ql_get_seg_count(qdev,
2471 skb_shinfo(skb)->nr_frags);
2472 if (tx_cb->seg_count == -1) {
2473 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2474 dev_kfree_skb_any(skb);
2475 return NETDEV_TX_OK;
2476 }
2477
2478 mac_iocb_ptr = tx_cb->queue_entry;
2479 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2480 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2481 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2482 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2483 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2484 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2485 tx_cb->skb = skb;
2486 if (qdev->device_id == QL3032_DEVICE_ID &&
2487 skb->ip_summed == CHECKSUM_PARTIAL)
2488 ql_hw_csum_setup(skb, mac_iocb_ptr);
2489
2490 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2491 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2492 return NETDEV_TX_BUSY;
2493 }
2494
2495 wmb();
2496 qdev->req_producer_index++;
2497 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2498 qdev->req_producer_index = 0;
2499 wmb();
2500 ql_write_common_reg_l(qdev,
2501 &port_regs->CommonRegs.reqQProducerIndex,
2502 qdev->req_producer_index);
2503
2504 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2505 "tx queued, slot %d, len %d\n",
2506 qdev->req_producer_index, skb->len);
2507
2508 atomic_dec(&qdev->tx_count);
2509 return NETDEV_TX_OK;
2510}
2511
2512static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2513{
2514 qdev->req_q_size =
2515 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2516
2517 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2518
2519 /* The barrier is required to ensure request and response queue
2520 * addr writes to the registers.
2521 */
2522 wmb();
2523
2524 qdev->req_q_virt_addr =
2525 dma_alloc_coherent(&qdev->pdev->dev, (size_t)qdev->req_q_size,
2526 &qdev->req_q_phy_addr, GFP_KERNEL);
2527
2528 if ((qdev->req_q_virt_addr == NULL) ||
2529 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2530 netdev_err(qdev->ndev, "reqQ failed\n");
2531 return -ENOMEM;
2532 }
2533
2534 qdev->rsp_q_virt_addr =
2535 dma_alloc_coherent(&qdev->pdev->dev, (size_t)qdev->rsp_q_size,
2536 &qdev->rsp_q_phy_addr, GFP_KERNEL);
2537
2538 if ((qdev->rsp_q_virt_addr == NULL) ||
2539 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2540 netdev_err(qdev->ndev, "rspQ allocation failed\n");
2541 dma_free_coherent(&qdev->pdev->dev, (size_t)qdev->req_q_size,
2542 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2543 return -ENOMEM;
2544 }
2545
2546 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2547
2548 return 0;
2549}
2550
2551static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2552{
2553 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2554 netdev_info(qdev->ndev, "Already done\n");
2555 return;
2556 }
2557
2558 dma_free_coherent(&qdev->pdev->dev, qdev->req_q_size,
2559 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2560
2561 qdev->req_q_virt_addr = NULL;
2562
2563 dma_free_coherent(&qdev->pdev->dev, qdev->rsp_q_size,
2564 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2565
2566 qdev->rsp_q_virt_addr = NULL;
2567
2568 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2569}
2570
2571static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2572{
2573 /* Create Large Buffer Queue */
2574 qdev->lrg_buf_q_size =
2575 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2576 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2577 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2578 else
2579 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2580
2581 qdev->lrg_buf = kmalloc_array(qdev->num_large_buffers,
2582 sizeof(struct ql_rcv_buf_cb),
2583 GFP_KERNEL);
2584 if (qdev->lrg_buf == NULL)
2585 return -ENOMEM;
2586
2587 qdev->lrg_buf_q_alloc_virt_addr =
2588 dma_alloc_coherent(&qdev->pdev->dev,
2589 qdev->lrg_buf_q_alloc_size,
2590 &qdev->lrg_buf_q_alloc_phy_addr, GFP_KERNEL);
2591
2592 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2593 netdev_err(qdev->ndev, "lBufQ failed\n");
2594 kfree(qdev->lrg_buf);
2595 return -ENOMEM;
2596 }
2597 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2598 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2599
2600 /* Create Small Buffer Queue */
2601 qdev->small_buf_q_size =
2602 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2603 if (qdev->small_buf_q_size < PAGE_SIZE)
2604 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2605 else
2606 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2607
2608 qdev->small_buf_q_alloc_virt_addr =
2609 dma_alloc_coherent(&qdev->pdev->dev,
2610 qdev->small_buf_q_alloc_size,
2611 &qdev->small_buf_q_alloc_phy_addr, GFP_KERNEL);
2612
2613 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2614 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2615 dma_free_coherent(&qdev->pdev->dev,
2616 qdev->lrg_buf_q_alloc_size,
2617 qdev->lrg_buf_q_alloc_virt_addr,
2618 qdev->lrg_buf_q_alloc_phy_addr);
2619 kfree(qdev->lrg_buf);
2620 return -ENOMEM;
2621 }
2622
2623 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2624 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2625 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2626 return 0;
2627}
2628
2629static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2630{
2631 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2632 netdev_info(qdev->ndev, "Already done\n");
2633 return;
2634 }
2635 kfree(qdev->lrg_buf);
2636 dma_free_coherent(&qdev->pdev->dev, qdev->lrg_buf_q_alloc_size,
2637 qdev->lrg_buf_q_alloc_virt_addr,
2638 qdev->lrg_buf_q_alloc_phy_addr);
2639
2640 qdev->lrg_buf_q_virt_addr = NULL;
2641
2642 dma_free_coherent(&qdev->pdev->dev, qdev->small_buf_q_alloc_size,
2643 qdev->small_buf_q_alloc_virt_addr,
2644 qdev->small_buf_q_alloc_phy_addr);
2645
2646 qdev->small_buf_q_virt_addr = NULL;
2647
2648 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2649}
2650
2651static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2652{
2653 int i;
2654 struct bufq_addr_element *small_buf_q_entry;
2655
2656 /* Currently we allocate on one of memory and use it for smallbuffers */
2657 qdev->small_buf_total_size =
2658 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2659 QL_SMALL_BUFFER_SIZE);
2660
2661 qdev->small_buf_virt_addr =
2662 dma_alloc_coherent(&qdev->pdev->dev,
2663 qdev->small_buf_total_size,
2664 &qdev->small_buf_phy_addr, GFP_KERNEL);
2665
2666 if (qdev->small_buf_virt_addr == NULL) {
2667 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2668 return -ENOMEM;
2669 }
2670
2671 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2672 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2673
2674 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2675
2676 /* Initialize the small buffer queue. */
2677 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2678 small_buf_q_entry->addr_high =
2679 cpu_to_le32(qdev->small_buf_phy_addr_high);
2680 small_buf_q_entry->addr_low =
2681 cpu_to_le32(qdev->small_buf_phy_addr_low +
2682 (i * QL_SMALL_BUFFER_SIZE));
2683 small_buf_q_entry++;
2684 }
2685 qdev->small_buf_index = 0;
2686 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2687 return 0;
2688}
2689
2690static void ql_free_small_buffers(struct ql3_adapter *qdev)
2691{
2692 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2693 netdev_info(qdev->ndev, "Already done\n");
2694 return;
2695 }
2696 if (qdev->small_buf_virt_addr != NULL) {
2697 dma_free_coherent(&qdev->pdev->dev,
2698 qdev->small_buf_total_size,
2699 qdev->small_buf_virt_addr,
2700 qdev->small_buf_phy_addr);
2701
2702 qdev->small_buf_virt_addr = NULL;
2703 }
2704}
2705
2706static void ql_free_large_buffers(struct ql3_adapter *qdev)
2707{
2708 int i = 0;
2709 struct ql_rcv_buf_cb *lrg_buf_cb;
2710
2711 for (i = 0; i < qdev->num_large_buffers; i++) {
2712 lrg_buf_cb = &qdev->lrg_buf[i];
2713 if (lrg_buf_cb->skb) {
2714 dev_kfree_skb(lrg_buf_cb->skb);
2715 dma_unmap_single(&qdev->pdev->dev,
2716 dma_unmap_addr(lrg_buf_cb, mapaddr),
2717 dma_unmap_len(lrg_buf_cb, maplen),
2718 DMA_FROM_DEVICE);
2719 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2720 } else {
2721 break;
2722 }
2723 }
2724}
2725
2726static void ql_init_large_buffers(struct ql3_adapter *qdev)
2727{
2728 int i;
2729 struct ql_rcv_buf_cb *lrg_buf_cb;
2730 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2731
2732 for (i = 0; i < qdev->num_large_buffers; i++) {
2733 lrg_buf_cb = &qdev->lrg_buf[i];
2734 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2735 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2736 buf_addr_ele++;
2737 }
2738 qdev->lrg_buf_index = 0;
2739 qdev->lrg_buf_skb_check = 0;
2740}
2741
2742static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2743{
2744 int i;
2745 struct ql_rcv_buf_cb *lrg_buf_cb;
2746 struct sk_buff *skb;
2747 dma_addr_t map;
2748 int err;
2749
2750 for (i = 0; i < qdev->num_large_buffers; i++) {
2751 lrg_buf_cb = &qdev->lrg_buf[i];
2752 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2753
2754 skb = netdev_alloc_skb(qdev->ndev,
2755 qdev->lrg_buffer_len);
2756 if (unlikely(!skb)) {
2757 /* Better luck next round */
2758 netdev_err(qdev->ndev,
2759 "large buff alloc failed for %d bytes at index %d\n",
2760 qdev->lrg_buffer_len * 2, i);
2761 ql_free_large_buffers(qdev);
2762 return -ENOMEM;
2763 } else {
2764 lrg_buf_cb->index = i;
2765 /*
2766 * We save some space to copy the ethhdr from first
2767 * buffer
2768 */
2769 skb_reserve(skb, QL_HEADER_SPACE);
2770 map = dma_map_single(&qdev->pdev->dev, skb->data,
2771 qdev->lrg_buffer_len - QL_HEADER_SPACE,
2772 DMA_FROM_DEVICE);
2773
2774 err = dma_mapping_error(&qdev->pdev->dev, map);
2775 if (err) {
2776 netdev_err(qdev->ndev,
2777 "PCI mapping failed with error: %d\n",
2778 err);
2779 dev_kfree_skb_irq(skb);
2780 ql_free_large_buffers(qdev);
2781 return -ENOMEM;
2782 }
2783
2784 lrg_buf_cb->skb = skb;
2785 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2786 dma_unmap_len_set(lrg_buf_cb, maplen,
2787 qdev->lrg_buffer_len -
2788 QL_HEADER_SPACE);
2789 lrg_buf_cb->buf_phy_addr_low =
2790 cpu_to_le32(LS_64BITS(map));
2791 lrg_buf_cb->buf_phy_addr_high =
2792 cpu_to_le32(MS_64BITS(map));
2793 }
2794 }
2795 return 0;
2796}
2797
2798static void ql_free_send_free_list(struct ql3_adapter *qdev)
2799{
2800 struct ql_tx_buf_cb *tx_cb;
2801 int i;
2802
2803 tx_cb = &qdev->tx_buf[0];
2804 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2805 kfree(tx_cb->oal);
2806 tx_cb->oal = NULL;
2807 tx_cb++;
2808 }
2809}
2810
2811static int ql_create_send_free_list(struct ql3_adapter *qdev)
2812{
2813 struct ql_tx_buf_cb *tx_cb;
2814 int i;
2815 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2816
2817 /* Create free list of transmit buffers */
2818 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2819
2820 tx_cb = &qdev->tx_buf[i];
2821 tx_cb->skb = NULL;
2822 tx_cb->queue_entry = req_q_curr;
2823 req_q_curr++;
2824 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2825 if (tx_cb->oal == NULL)
2826 return -ENOMEM;
2827 }
2828 return 0;
2829}
2830
2831static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2832{
2833 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2834 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2835 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2836 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2837 /*
2838 * Bigger buffers, so less of them.
2839 */
2840 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2841 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2842 } else {
2843 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2844 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2845 return -ENOMEM;
2846 }
2847 qdev->num_large_buffers =
2848 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2849 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2850 qdev->max_frame_size =
2851 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2852
2853 /*
2854 * First allocate a page of shared memory and use it for shadow
2855 * locations of Network Request Queue Consumer Address Register and
2856 * Network Completion Queue Producer Index Register
2857 */
2858 qdev->shadow_reg_virt_addr =
2859 dma_alloc_coherent(&qdev->pdev->dev, PAGE_SIZE,
2860 &qdev->shadow_reg_phy_addr, GFP_KERNEL);
2861
2862 if (qdev->shadow_reg_virt_addr != NULL) {
2863 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2864 qdev->req_consumer_index_phy_addr_high =
2865 MS_64BITS(qdev->shadow_reg_phy_addr);
2866 qdev->req_consumer_index_phy_addr_low =
2867 LS_64BITS(qdev->shadow_reg_phy_addr);
2868
2869 qdev->prsp_producer_index =
2870 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2871 qdev->rsp_producer_index_phy_addr_high =
2872 qdev->req_consumer_index_phy_addr_high;
2873 qdev->rsp_producer_index_phy_addr_low =
2874 qdev->req_consumer_index_phy_addr_low + 8;
2875 } else {
2876 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2877 return -ENOMEM;
2878 }
2879
2880 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2881 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2882 goto err_req_rsp;
2883 }
2884
2885 if (ql_alloc_buffer_queues(qdev) != 0) {
2886 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2887 goto err_buffer_queues;
2888 }
2889
2890 if (ql_alloc_small_buffers(qdev) != 0) {
2891 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2892 goto err_small_buffers;
2893 }
2894
2895 if (ql_alloc_large_buffers(qdev) != 0) {
2896 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2897 goto err_small_buffers;
2898 }
2899
2900 /* Initialize the large buffer queue. */
2901 ql_init_large_buffers(qdev);
2902 if (ql_create_send_free_list(qdev))
2903 goto err_free_list;
2904
2905 qdev->rsp_current = qdev->rsp_q_virt_addr;
2906
2907 return 0;
2908err_free_list:
2909 ql_free_send_free_list(qdev);
2910err_small_buffers:
2911 ql_free_buffer_queues(qdev);
2912err_buffer_queues:
2913 ql_free_net_req_rsp_queues(qdev);
2914err_req_rsp:
2915 dma_free_coherent(&qdev->pdev->dev, PAGE_SIZE,
2916 qdev->shadow_reg_virt_addr,
2917 qdev->shadow_reg_phy_addr);
2918
2919 return -ENOMEM;
2920}
2921
2922static void ql_free_mem_resources(struct ql3_adapter *qdev)
2923{
2924 ql_free_send_free_list(qdev);
2925 ql_free_large_buffers(qdev);
2926 ql_free_small_buffers(qdev);
2927 ql_free_buffer_queues(qdev);
2928 ql_free_net_req_rsp_queues(qdev);
2929 if (qdev->shadow_reg_virt_addr != NULL) {
2930 dma_free_coherent(&qdev->pdev->dev, PAGE_SIZE,
2931 qdev->shadow_reg_virt_addr,
2932 qdev->shadow_reg_phy_addr);
2933 qdev->shadow_reg_virt_addr = NULL;
2934 }
2935}
2936
2937static int ql_init_misc_registers(struct ql3_adapter *qdev)
2938{
2939 struct ql3xxx_local_ram_registers __iomem *local_ram =
2940 (void __iomem *)qdev->mem_map_registers;
2941
2942 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2943 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2944 2) << 4))
2945 return -1;
2946
2947 ql_write_page2_reg(qdev,
2948 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2949
2950 ql_write_page2_reg(qdev,
2951 &local_ram->maxBufletCount,
2952 qdev->nvram_data.bufletCount);
2953
2954 ql_write_page2_reg(qdev,
2955 &local_ram->freeBufletThresholdLow,
2956 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2957 (qdev->nvram_data.tcpWindowThreshold0));
2958
2959 ql_write_page2_reg(qdev,
2960 &local_ram->freeBufletThresholdHigh,
2961 qdev->nvram_data.tcpWindowThreshold50);
2962
2963 ql_write_page2_reg(qdev,
2964 &local_ram->ipHashTableBase,
2965 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2966 qdev->nvram_data.ipHashTableBaseLo);
2967 ql_write_page2_reg(qdev,
2968 &local_ram->ipHashTableCount,
2969 qdev->nvram_data.ipHashTableSize);
2970 ql_write_page2_reg(qdev,
2971 &local_ram->tcpHashTableBase,
2972 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2973 qdev->nvram_data.tcpHashTableBaseLo);
2974 ql_write_page2_reg(qdev,
2975 &local_ram->tcpHashTableCount,
2976 qdev->nvram_data.tcpHashTableSize);
2977 ql_write_page2_reg(qdev,
2978 &local_ram->ncbBase,
2979 (qdev->nvram_data.ncbTableBaseHi << 16) |
2980 qdev->nvram_data.ncbTableBaseLo);
2981 ql_write_page2_reg(qdev,
2982 &local_ram->maxNcbCount,
2983 qdev->nvram_data.ncbTableSize);
2984 ql_write_page2_reg(qdev,
2985 &local_ram->drbBase,
2986 (qdev->nvram_data.drbTableBaseHi << 16) |
2987 qdev->nvram_data.drbTableBaseLo);
2988 ql_write_page2_reg(qdev,
2989 &local_ram->maxDrbCount,
2990 qdev->nvram_data.drbTableSize);
2991 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2992 return 0;
2993}
2994
2995static int ql_adapter_initialize(struct ql3_adapter *qdev)
2996{
2997 u32 value;
2998 struct ql3xxx_port_registers __iomem *port_regs =
2999 qdev->mem_map_registers;
3000 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3001 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3002 (void __iomem *)port_regs;
3003 u32 delay = 10;
3004 int status = 0;
3005
3006 if (ql_mii_setup(qdev))
3007 return -1;
3008
3009 /* Bring out PHY out of reset */
3010 ql_write_common_reg(qdev, spir,
3011 (ISP_SERIAL_PORT_IF_WE |
3012 (ISP_SERIAL_PORT_IF_WE << 16)));
3013 /* Give the PHY time to come out of reset. */
3014 mdelay(100);
3015 qdev->port_link_state = LS_DOWN;
3016 netif_carrier_off(qdev->ndev);
3017
3018 /* V2 chip fix for ARS-39168. */
3019 ql_write_common_reg(qdev, spir,
3020 (ISP_SERIAL_PORT_IF_SDE |
3021 (ISP_SERIAL_PORT_IF_SDE << 16)));
3022
3023 /* Request Queue Registers */
3024 *((u32 *)(qdev->preq_consumer_index)) = 0;
3025 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3026 qdev->req_producer_index = 0;
3027
3028 ql_write_page1_reg(qdev,
3029 &hmem_regs->reqConsumerIndexAddrHigh,
3030 qdev->req_consumer_index_phy_addr_high);
3031 ql_write_page1_reg(qdev,
3032 &hmem_regs->reqConsumerIndexAddrLow,
3033 qdev->req_consumer_index_phy_addr_low);
3034
3035 ql_write_page1_reg(qdev,
3036 &hmem_regs->reqBaseAddrHigh,
3037 MS_64BITS(qdev->req_q_phy_addr));
3038 ql_write_page1_reg(qdev,
3039 &hmem_regs->reqBaseAddrLow,
3040 LS_64BITS(qdev->req_q_phy_addr));
3041 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3042
3043 /* Response Queue Registers */
3044 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3045 qdev->rsp_consumer_index = 0;
3046 qdev->rsp_current = qdev->rsp_q_virt_addr;
3047
3048 ql_write_page1_reg(qdev,
3049 &hmem_regs->rspProducerIndexAddrHigh,
3050 qdev->rsp_producer_index_phy_addr_high);
3051
3052 ql_write_page1_reg(qdev,
3053 &hmem_regs->rspProducerIndexAddrLow,
3054 qdev->rsp_producer_index_phy_addr_low);
3055
3056 ql_write_page1_reg(qdev,
3057 &hmem_regs->rspBaseAddrHigh,
3058 MS_64BITS(qdev->rsp_q_phy_addr));
3059
3060 ql_write_page1_reg(qdev,
3061 &hmem_regs->rspBaseAddrLow,
3062 LS_64BITS(qdev->rsp_q_phy_addr));
3063
3064 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3065
3066 /* Large Buffer Queue */
3067 ql_write_page1_reg(qdev,
3068 &hmem_regs->rxLargeQBaseAddrHigh,
3069 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3070
3071 ql_write_page1_reg(qdev,
3072 &hmem_regs->rxLargeQBaseAddrLow,
3073 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3074
3075 ql_write_page1_reg(qdev,
3076 &hmem_regs->rxLargeQLength,
3077 qdev->num_lbufq_entries);
3078
3079 ql_write_page1_reg(qdev,
3080 &hmem_regs->rxLargeBufferLength,
3081 qdev->lrg_buffer_len);
3082
3083 /* Small Buffer Queue */
3084 ql_write_page1_reg(qdev,
3085 &hmem_regs->rxSmallQBaseAddrHigh,
3086 MS_64BITS(qdev->small_buf_q_phy_addr));
3087
3088 ql_write_page1_reg(qdev,
3089 &hmem_regs->rxSmallQBaseAddrLow,
3090 LS_64BITS(qdev->small_buf_q_phy_addr));
3091
3092 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3093 ql_write_page1_reg(qdev,
3094 &hmem_regs->rxSmallBufferLength,
3095 QL_SMALL_BUFFER_SIZE);
3096
3097 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3098 qdev->small_buf_release_cnt = 8;
3099 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3100 qdev->lrg_buf_release_cnt = 8;
3101 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3102 qdev->small_buf_index = 0;
3103 qdev->lrg_buf_index = 0;
3104 qdev->lrg_buf_free_count = 0;
3105 qdev->lrg_buf_free_head = NULL;
3106 qdev->lrg_buf_free_tail = NULL;
3107
3108 ql_write_common_reg(qdev,
3109 &port_regs->CommonRegs.
3110 rxSmallQProducerIndex,
3111 qdev->small_buf_q_producer_index);
3112 ql_write_common_reg(qdev,
3113 &port_regs->CommonRegs.
3114 rxLargeQProducerIndex,
3115 qdev->lrg_buf_q_producer_index);
3116
3117 /*
3118 * Find out if the chip has already been initialized. If it has, then
3119 * we skip some of the initialization.
3120 */
3121 clear_bit(QL_LINK_MASTER, &qdev->flags);
3122 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3123 if ((value & PORT_STATUS_IC) == 0) {
3124
3125 /* Chip has not been configured yet, so let it rip. */
3126 if (ql_init_misc_registers(qdev)) {
3127 status = -1;
3128 goto out;
3129 }
3130
3131 value = qdev->nvram_data.tcpMaxWindowSize;
3132 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3133
3134 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3135
3136 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3137 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3138 * 2) << 13)) {
3139 status = -1;
3140 goto out;
3141 }
3142 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3143 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3144 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3145 16) | (INTERNAL_CHIP_SD |
3146 INTERNAL_CHIP_WE)));
3147 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3148 }
3149
3150 if (qdev->mac_index)
3151 ql_write_page0_reg(qdev,
3152 &port_regs->mac1MaxFrameLengthReg,
3153 qdev->max_frame_size);
3154 else
3155 ql_write_page0_reg(qdev,
3156 &port_regs->mac0MaxFrameLengthReg,
3157 qdev->max_frame_size);
3158
3159 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3160 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3161 2) << 7)) {
3162 status = -1;
3163 goto out;
3164 }
3165
3166 PHY_Setup(qdev);
3167 ql_init_scan_mode(qdev);
3168 ql_get_phy_owner(qdev);
3169
3170 /* Load the MAC Configuration */
3171
3172 /* Program lower 32 bits of the MAC address */
3173 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3174 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3175 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3176 ((qdev->ndev->dev_addr[2] << 24)
3177 | (qdev->ndev->dev_addr[3] << 16)
3178 | (qdev->ndev->dev_addr[4] << 8)
3179 | qdev->ndev->dev_addr[5]));
3180
3181 /* Program top 16 bits of the MAC address */
3182 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3183 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3184 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3185 ((qdev->ndev->dev_addr[0] << 8)
3186 | qdev->ndev->dev_addr[1]));
3187
3188 /* Enable Primary MAC */
3189 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3190 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3191 MAC_ADDR_INDIRECT_PTR_REG_PE));
3192
3193 /* Clear Primary and Secondary IP addresses */
3194 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3195 ((IP_ADDR_INDEX_REG_MASK << 16) |
3196 (qdev->mac_index << 2)));
3197 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3198
3199 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3200 ((IP_ADDR_INDEX_REG_MASK << 16) |
3201 ((qdev->mac_index << 2) + 1)));
3202 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3203
3204 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3205
3206 /* Indicate Configuration Complete */
3207 ql_write_page0_reg(qdev,
3208 &port_regs->portControl,
3209 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3210
3211 do {
3212 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3213 if (value & PORT_STATUS_IC)
3214 break;
3215 spin_unlock_irq(&qdev->hw_lock);
3216 msleep(500);
3217 spin_lock_irq(&qdev->hw_lock);
3218 } while (--delay);
3219
3220 if (delay == 0) {
3221 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3222 status = -1;
3223 goto out;
3224 }
3225
3226 /* Enable Ethernet Function */
3227 if (qdev->device_id == QL3032_DEVICE_ID) {
3228 value =
3229 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3230 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3231 QL3032_PORT_CONTROL_ET);
3232 ql_write_page0_reg(qdev, &port_regs->functionControl,
3233 ((value << 16) | value));
3234 } else {
3235 value =
3236 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3237 PORT_CONTROL_HH);
3238 ql_write_page0_reg(qdev, &port_regs->portControl,
3239 ((value << 16) | value));
3240 }
3241
3242
3243out:
3244 return status;
3245}
3246
3247/*
3248 * Caller holds hw_lock.
3249 */
3250static int ql_adapter_reset(struct ql3_adapter *qdev)
3251{
3252 struct ql3xxx_port_registers __iomem *port_regs =
3253 qdev->mem_map_registers;
3254 int status = 0;
3255 u16 value;
3256 int max_wait_time;
3257
3258 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3259 clear_bit(QL_RESET_DONE, &qdev->flags);
3260
3261 /*
3262 * Issue soft reset to chip.
3263 */
3264 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3265 ql_write_common_reg(qdev,
3266 &port_regs->CommonRegs.ispControlStatus,
3267 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3268
3269 /* Wait 3 seconds for reset to complete. */
3270 netdev_printk(KERN_DEBUG, qdev->ndev,
3271 "Wait 10 milliseconds for reset to complete\n");
3272
3273 /* Wait until the firmware tells us the Soft Reset is done */
3274 max_wait_time = 5;
3275 do {
3276 value =
3277 ql_read_common_reg(qdev,
3278 &port_regs->CommonRegs.ispControlStatus);
3279 if ((value & ISP_CONTROL_SR) == 0)
3280 break;
3281
3282 mdelay(1000);
3283 } while ((--max_wait_time));
3284
3285 /*
3286 * Also, make sure that the Network Reset Interrupt bit has been
3287 * cleared after the soft reset has taken place.
3288 */
3289 value =
3290 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3291 if (value & ISP_CONTROL_RI) {
3292 netdev_printk(KERN_DEBUG, qdev->ndev,
3293 "clearing RI after reset\n");
3294 ql_write_common_reg(qdev,
3295 &port_regs->CommonRegs.
3296 ispControlStatus,
3297 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3298 }
3299
3300 if (max_wait_time == 0) {
3301 /* Issue Force Soft Reset */
3302 ql_write_common_reg(qdev,
3303 &port_regs->CommonRegs.
3304 ispControlStatus,
3305 ((ISP_CONTROL_FSR << 16) |
3306 ISP_CONTROL_FSR));
3307 /*
3308 * Wait until the firmware tells us the Force Soft Reset is
3309 * done
3310 */
3311 max_wait_time = 5;
3312 do {
3313 value = ql_read_common_reg(qdev,
3314 &port_regs->CommonRegs.
3315 ispControlStatus);
3316 if ((value & ISP_CONTROL_FSR) == 0)
3317 break;
3318 mdelay(1000);
3319 } while ((--max_wait_time));
3320 }
3321 if (max_wait_time == 0)
3322 status = 1;
3323
3324 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3325 set_bit(QL_RESET_DONE, &qdev->flags);
3326 return status;
3327}
3328
3329static void ql_set_mac_info(struct ql3_adapter *qdev)
3330{
3331 struct ql3xxx_port_registers __iomem *port_regs =
3332 qdev->mem_map_registers;
3333 u32 value, port_status;
3334 u8 func_number;
3335
3336 /* Get the function number */
3337 value =
3338 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3339 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3340 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3341 switch (value & ISP_CONTROL_FN_MASK) {
3342 case ISP_CONTROL_FN0_NET:
3343 qdev->mac_index = 0;
3344 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3345 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3346 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3347 if (port_status & PORT_STATUS_SM0)
3348 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3349 else
3350 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3351 break;
3352
3353 case ISP_CONTROL_FN1_NET:
3354 qdev->mac_index = 1;
3355 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3356 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3357 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3358 if (port_status & PORT_STATUS_SM1)
3359 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3360 else
3361 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3362 break;
3363
3364 case ISP_CONTROL_FN0_SCSI:
3365 case ISP_CONTROL_FN1_SCSI:
3366 default:
3367 netdev_printk(KERN_DEBUG, qdev->ndev,
3368 "Invalid function number, ispControlStatus = 0x%x\n",
3369 value);
3370 break;
3371 }
3372 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3373}
3374
3375static void ql_display_dev_info(struct net_device *ndev)
3376{
3377 struct ql3_adapter *qdev = netdev_priv(ndev);
3378 struct pci_dev *pdev = qdev->pdev;
3379
3380 netdev_info(ndev,
3381 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3382 DRV_NAME, qdev->index, qdev->chip_rev_id,
3383 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3384 qdev->pci_slot);
3385 netdev_info(ndev, "%s Interface\n",
3386 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3387
3388 /*
3389 * Print PCI bus width/type.
3390 */
3391 netdev_info(ndev, "Bus interface is %s %s\n",
3392 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3393 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3394
3395 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3396 qdev->mem_map_registers);
3397 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3398
3399 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3400}
3401
3402static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3403{
3404 struct net_device *ndev = qdev->ndev;
3405 int retval = 0;
3406
3407 netif_stop_queue(ndev);
3408 netif_carrier_off(ndev);
3409
3410 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3411 clear_bit(QL_LINK_MASTER, &qdev->flags);
3412
3413 ql_disable_interrupts(qdev);
3414
3415 free_irq(qdev->pdev->irq, ndev);
3416
3417 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3418 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3419 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3420 pci_disable_msi(qdev->pdev);
3421 }
3422
3423 del_timer_sync(&qdev->adapter_timer);
3424
3425 napi_disable(&qdev->napi);
3426
3427 if (do_reset) {
3428 int soft_reset;
3429 unsigned long hw_flags;
3430
3431 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3432 if (ql_wait_for_drvr_lock(qdev)) {
3433 soft_reset = ql_adapter_reset(qdev);
3434 if (soft_reset) {
3435 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3436 qdev->index);
3437 }
3438 netdev_err(ndev,
3439 "Releasing driver lock via chip reset\n");
3440 } else {
3441 netdev_err(ndev,
3442 "Could not acquire driver lock to do reset!\n");
3443 retval = -1;
3444 }
3445 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3446 }
3447 ql_free_mem_resources(qdev);
3448 return retval;
3449}
3450
3451static int ql_adapter_up(struct ql3_adapter *qdev)
3452{
3453 struct net_device *ndev = qdev->ndev;
3454 int err;
3455 unsigned long irq_flags = IRQF_SHARED;
3456 unsigned long hw_flags;
3457
3458 if (ql_alloc_mem_resources(qdev)) {
3459 netdev_err(ndev, "Unable to allocate buffers\n");
3460 return -ENOMEM;
3461 }
3462
3463 if (qdev->msi) {
3464 if (pci_enable_msi(qdev->pdev)) {
3465 netdev_err(ndev,
3466 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3467 qdev->msi = 0;
3468 } else {
3469 netdev_info(ndev, "MSI Enabled...\n");
3470 set_bit(QL_MSI_ENABLED, &qdev->flags);
3471 irq_flags &= ~IRQF_SHARED;
3472 }
3473 }
3474
3475 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3476 irq_flags, ndev->name, ndev);
3477 if (err) {
3478 netdev_err(ndev,
3479 "Failed to reserve interrupt %d - already in use\n",
3480 qdev->pdev->irq);
3481 goto err_irq;
3482 }
3483
3484 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3485
3486 if (!ql_wait_for_drvr_lock(qdev)) {
3487 netdev_err(ndev, "Could not acquire driver lock\n");
3488 err = -ENODEV;
3489 goto err_lock;
3490 }
3491
3492 err = ql_adapter_initialize(qdev);
3493 if (err) {
3494 netdev_err(ndev, "Unable to initialize adapter\n");
3495 goto err_init;
3496 }
3497 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3498
3499 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3500
3501 set_bit(QL_ADAPTER_UP, &qdev->flags);
3502
3503 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3504
3505 napi_enable(&qdev->napi);
3506 ql_enable_interrupts(qdev);
3507 return 0;
3508
3509err_init:
3510 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3511err_lock:
3512 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3513 free_irq(qdev->pdev->irq, ndev);
3514err_irq:
3515 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3516 netdev_info(ndev, "calling pci_disable_msi()\n");
3517 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3518 pci_disable_msi(qdev->pdev);
3519 }
3520 return err;
3521}
3522
3523static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3524{
3525 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3526 netdev_err(qdev->ndev,
3527 "Driver up/down cycle failed, closing device\n");
3528 rtnl_lock();
3529 dev_close(qdev->ndev);
3530 rtnl_unlock();
3531 return -1;
3532 }
3533 return 0;
3534}
3535
3536static int ql3xxx_close(struct net_device *ndev)
3537{
3538 struct ql3_adapter *qdev = netdev_priv(ndev);
3539
3540 /*
3541 * Wait for device to recover from a reset.
3542 * (Rarely happens, but possible.)
3543 */
3544 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3545 msleep(50);
3546
3547 ql_adapter_down(qdev, QL_DO_RESET);
3548 return 0;
3549}
3550
3551static int ql3xxx_open(struct net_device *ndev)
3552{
3553 struct ql3_adapter *qdev = netdev_priv(ndev);
3554 return ql_adapter_up(qdev);
3555}
3556
3557static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3558{
3559 struct ql3_adapter *qdev = netdev_priv(ndev);
3560 struct ql3xxx_port_registers __iomem *port_regs =
3561 qdev->mem_map_registers;
3562 struct sockaddr *addr = p;
3563 unsigned long hw_flags;
3564
3565 if (netif_running(ndev))
3566 return -EBUSY;
3567
3568 if (!is_valid_ether_addr(addr->sa_data))
3569 return -EADDRNOTAVAIL;
3570
3571 eth_hw_addr_set(ndev, addr->sa_data);
3572
3573 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3574 /* Program lower 32 bits of the MAC address */
3575 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3576 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3577 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3578 ((ndev->dev_addr[2] << 24) | (ndev->
3579 dev_addr[3] << 16) |
3580 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3581
3582 /* Program top 16 bits of the MAC address */
3583 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3584 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3585 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3586 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3587 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3588
3589 return 0;
3590}
3591
3592static void ql3xxx_tx_timeout(struct net_device *ndev, unsigned int txqueue)
3593{
3594 struct ql3_adapter *qdev = netdev_priv(ndev);
3595
3596 netdev_err(ndev, "Resetting...\n");
3597 /*
3598 * Stop the queues, we've got a problem.
3599 */
3600 netif_stop_queue(ndev);
3601
3602 /*
3603 * Wake up the worker to process this event.
3604 */
3605 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3606}
3607
3608static void ql_reset_work(struct work_struct *work)
3609{
3610 struct ql3_adapter *qdev =
3611 container_of(work, struct ql3_adapter, reset_work.work);
3612 struct net_device *ndev = qdev->ndev;
3613 u32 value;
3614 struct ql_tx_buf_cb *tx_cb;
3615 int max_wait_time, i;
3616 struct ql3xxx_port_registers __iomem *port_regs =
3617 qdev->mem_map_registers;
3618 unsigned long hw_flags;
3619
3620 if (test_bit(QL_RESET_PER_SCSI, &qdev->flags) ||
3621 test_bit(QL_RESET_START, &qdev->flags)) {
3622 clear_bit(QL_LINK_MASTER, &qdev->flags);
3623
3624 /*
3625 * Loop through the active list and return the skb.
3626 */
3627 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3628 int j;
3629 tx_cb = &qdev->tx_buf[i];
3630 if (tx_cb->skb) {
3631 netdev_printk(KERN_DEBUG, ndev,
3632 "Freeing lost SKB\n");
3633 dma_unmap_single(&qdev->pdev->dev,
3634 dma_unmap_addr(&tx_cb->map[0], mapaddr),
3635 dma_unmap_len(&tx_cb->map[0], maplen),
3636 DMA_TO_DEVICE);
3637 for (j = 1; j < tx_cb->seg_count; j++) {
3638 dma_unmap_page(&qdev->pdev->dev,
3639 dma_unmap_addr(&tx_cb->map[j], mapaddr),
3640 dma_unmap_len(&tx_cb->map[j], maplen),
3641 DMA_TO_DEVICE);
3642 }
3643 dev_kfree_skb(tx_cb->skb);
3644 tx_cb->skb = NULL;
3645 }
3646 }
3647
3648 netdev_err(ndev, "Clearing NRI after reset\n");
3649 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3650 ql_write_common_reg(qdev,
3651 &port_regs->CommonRegs.
3652 ispControlStatus,
3653 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3654 /*
3655 * Wait the for Soft Reset to Complete.
3656 */
3657 max_wait_time = 10;
3658 do {
3659 value = ql_read_common_reg(qdev,
3660 &port_regs->CommonRegs.
3661
3662 ispControlStatus);
3663 if ((value & ISP_CONTROL_SR) == 0) {
3664 netdev_printk(KERN_DEBUG, ndev,
3665 "reset completed\n");
3666 break;
3667 }
3668
3669 if (value & ISP_CONTROL_RI) {
3670 netdev_printk(KERN_DEBUG, ndev,
3671 "clearing NRI after reset\n");
3672 ql_write_common_reg(qdev,
3673 &port_regs->
3674 CommonRegs.
3675 ispControlStatus,
3676 ((ISP_CONTROL_RI <<
3677 16) | ISP_CONTROL_RI));
3678 }
3679
3680 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3681 ssleep(1);
3682 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3683 } while (--max_wait_time);
3684 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3685
3686 if (value & ISP_CONTROL_SR) {
3687
3688 /*
3689 * Set the reset flags and clear the board again.
3690 * Nothing else to do...
3691 */
3692 netdev_err(ndev,
3693 "Timed out waiting for reset to complete\n");
3694 netdev_err(ndev, "Do a reset\n");
3695 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3696 clear_bit(QL_RESET_START, &qdev->flags);
3697 ql_cycle_adapter(qdev, QL_DO_RESET);
3698 return;
3699 }
3700
3701 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3702 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3703 clear_bit(QL_RESET_START, &qdev->flags);
3704 ql_cycle_adapter(qdev, QL_NO_RESET);
3705 }
3706}
3707
3708static void ql_tx_timeout_work(struct work_struct *work)
3709{
3710 struct ql3_adapter *qdev =
3711 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3712
3713 ql_cycle_adapter(qdev, QL_DO_RESET);
3714}
3715
3716static void ql_get_board_info(struct ql3_adapter *qdev)
3717{
3718 struct ql3xxx_port_registers __iomem *port_regs =
3719 qdev->mem_map_registers;
3720 u32 value;
3721
3722 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3723
3724 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3725 if (value & PORT_STATUS_64)
3726 qdev->pci_width = 64;
3727 else
3728 qdev->pci_width = 32;
3729 if (value & PORT_STATUS_X)
3730 qdev->pci_x = 1;
3731 else
3732 qdev->pci_x = 0;
3733 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3734}
3735
3736static void ql3xxx_timer(struct timer_list *t)
3737{
3738 struct ql3_adapter *qdev = from_timer(qdev, t, adapter_timer);
3739 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3740}
3741
3742static const struct net_device_ops ql3xxx_netdev_ops = {
3743 .ndo_open = ql3xxx_open,
3744 .ndo_start_xmit = ql3xxx_send,
3745 .ndo_stop = ql3xxx_close,
3746 .ndo_validate_addr = eth_validate_addr,
3747 .ndo_set_mac_address = ql3xxx_set_mac_address,
3748 .ndo_tx_timeout = ql3xxx_tx_timeout,
3749};
3750
3751static int ql3xxx_probe(struct pci_dev *pdev,
3752 const struct pci_device_id *pci_entry)
3753{
3754 struct net_device *ndev = NULL;
3755 struct ql3_adapter *qdev = NULL;
3756 static int cards_found;
3757 int err;
3758
3759 err = pci_enable_device(pdev);
3760 if (err) {
3761 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3762 goto err_out;
3763 }
3764
3765 err = pci_request_regions(pdev, DRV_NAME);
3766 if (err) {
3767 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3768 goto err_out_disable_pdev;
3769 }
3770
3771 pci_set_master(pdev);
3772
3773 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3774 if (err) {
3775 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3776 goto err_out_free_regions;
3777 }
3778
3779 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3780 if (!ndev) {
3781 err = -ENOMEM;
3782 goto err_out_free_regions;
3783 }
3784
3785 SET_NETDEV_DEV(ndev, &pdev->dev);
3786
3787 pci_set_drvdata(pdev, ndev);
3788
3789 qdev = netdev_priv(ndev);
3790 qdev->index = cards_found;
3791 qdev->ndev = ndev;
3792 qdev->pdev = pdev;
3793 qdev->device_id = pci_entry->device;
3794 qdev->port_link_state = LS_DOWN;
3795 if (msi)
3796 qdev->msi = 1;
3797
3798 qdev->msg_enable = netif_msg_init(debug, default_msg);
3799
3800 ndev->features |= NETIF_F_HIGHDMA;
3801 if (qdev->device_id == QL3032_DEVICE_ID)
3802 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3803
3804 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3805 if (!qdev->mem_map_registers) {
3806 pr_err("%s: cannot map device registers\n", pci_name(pdev));
3807 err = -EIO;
3808 goto err_out_free_ndev;
3809 }
3810
3811 spin_lock_init(&qdev->adapter_lock);
3812 spin_lock_init(&qdev->hw_lock);
3813
3814 /* Set driver entry points */
3815 ndev->netdev_ops = &ql3xxx_netdev_ops;
3816 ndev->ethtool_ops = &ql3xxx_ethtool_ops;
3817 ndev->watchdog_timeo = 5 * HZ;
3818
3819 netif_napi_add(ndev, &qdev->napi, ql_poll);
3820
3821 ndev->irq = pdev->irq;
3822
3823 /* make sure the EEPROM is good */
3824 if (ql_get_nvram_params(qdev)) {
3825 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3826 __func__, qdev->index);
3827 err = -EIO;
3828 goto err_out_iounmap;
3829 }
3830
3831 ql_set_mac_info(qdev);
3832
3833 /* Validate and set parameters */
3834 if (qdev->mac_index) {
3835 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3836 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3837 } else {
3838 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3839 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3840 }
3841
3842 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3843
3844 /* Record PCI bus information. */
3845 ql_get_board_info(qdev);
3846
3847 /*
3848 * Set the Maximum Memory Read Byte Count value. We do this to handle
3849 * jumbo frames.
3850 */
3851 if (qdev->pci_x)
3852 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3853
3854 err = register_netdev(ndev);
3855 if (err) {
3856 pr_err("%s: cannot register net device\n", pci_name(pdev));
3857 goto err_out_iounmap;
3858 }
3859
3860 /* we're going to reset, so assume we have no link for now */
3861
3862 netif_carrier_off(ndev);
3863 netif_stop_queue(ndev);
3864
3865 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3866 if (!qdev->workqueue) {
3867 unregister_netdev(ndev);
3868 err = -ENOMEM;
3869 goto err_out_iounmap;
3870 }
3871
3872 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3873 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3874 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3875
3876 timer_setup(&qdev->adapter_timer, ql3xxx_timer, 0);
3877 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3878
3879 if (!cards_found) {
3880 pr_alert("%s\n", DRV_STRING);
3881 pr_alert("Driver name: %s, Version: %s\n",
3882 DRV_NAME, DRV_VERSION);
3883 }
3884 ql_display_dev_info(ndev);
3885
3886 cards_found++;
3887 return 0;
3888
3889err_out_iounmap:
3890 iounmap(qdev->mem_map_registers);
3891err_out_free_ndev:
3892 free_netdev(ndev);
3893err_out_free_regions:
3894 pci_release_regions(pdev);
3895err_out_disable_pdev:
3896 pci_disable_device(pdev);
3897err_out:
3898 return err;
3899}
3900
3901static void ql3xxx_remove(struct pci_dev *pdev)
3902{
3903 struct net_device *ndev = pci_get_drvdata(pdev);
3904 struct ql3_adapter *qdev = netdev_priv(ndev);
3905
3906 unregister_netdev(ndev);
3907
3908 ql_disable_interrupts(qdev);
3909
3910 if (qdev->workqueue) {
3911 cancel_delayed_work(&qdev->reset_work);
3912 cancel_delayed_work(&qdev->tx_timeout_work);
3913 destroy_workqueue(qdev->workqueue);
3914 qdev->workqueue = NULL;
3915 }
3916
3917 iounmap(qdev->mem_map_registers);
3918 pci_release_regions(pdev);
3919 free_netdev(ndev);
3920}
3921
3922static struct pci_driver ql3xxx_driver = {
3923
3924 .name = DRV_NAME,
3925 .id_table = ql3xxx_pci_tbl,
3926 .probe = ql3xxx_probe,
3927 .remove = ql3xxx_remove,
3928};
3929
3930module_pci_driver(ql3xxx_driver);
1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/list.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/ip.h>
26#include <linux/in.h>
27#include <linux/if_arp.h>
28#include <linux/if_ether.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/skbuff.h>
33#include <linux/rtnetlink.h>
34#include <linux/if_vlan.h>
35#include <linux/delay.h>
36#include <linux/mm.h>
37#include <linux/prefetch.h>
38
39#include "qla3xxx.h"
40
41#define DRV_NAME "qla3xxx"
42#define DRV_STRING "QLogic ISP3XXX Network Driver"
43#define DRV_VERSION "v2.03.00-k5"
44
45static const char ql3xxx_driver_name[] = DRV_NAME;
46static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48#define TIMED_OUT_MSG \
49"Timed out waiting for management port to get free before issuing command\n"
50
51MODULE_AUTHOR("QLogic Corporation");
52MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
53MODULE_LICENSE("GPL");
54MODULE_VERSION(DRV_VERSION);
55
56static const u32 default_msg
57 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
58 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
59
60static int debug = -1; /* defaults above */
61module_param(debug, int, 0);
62MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
63
64static int msi;
65module_param(msi, int, 0);
66MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
67
68static const struct pci_device_id ql3xxx_pci_tbl[] = {
69 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
70 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
71 /* required last entry */
72 {0,}
73};
74
75MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
76
77/*
78 * These are the known PHY's which are used
79 */
80enum PHY_DEVICE_TYPE {
81 PHY_TYPE_UNKNOWN = 0,
82 PHY_VITESSE_VSC8211,
83 PHY_AGERE_ET1011C,
84 MAX_PHY_DEV_TYPES
85};
86
87struct PHY_DEVICE_INFO {
88 const enum PHY_DEVICE_TYPE phyDevice;
89 const u32 phyIdOUI;
90 const u16 phyIdModel;
91 const char *name;
92};
93
94static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
95 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
96 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
97 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
98};
99
100
101/*
102 * Caller must take hw_lock.
103 */
104static int ql_sem_spinlock(struct ql3_adapter *qdev,
105 u32 sem_mask, u32 sem_bits)
106{
107 struct ql3xxx_port_registers __iomem *port_regs =
108 qdev->mem_map_registers;
109 u32 value;
110 unsigned int seconds = 3;
111
112 do {
113 writel((sem_mask | sem_bits),
114 &port_regs->CommonRegs.semaphoreReg);
115 value = readl(&port_regs->CommonRegs.semaphoreReg);
116 if ((value & (sem_mask >> 16)) == sem_bits)
117 return 0;
118 ssleep(1);
119 } while (--seconds);
120 return -1;
121}
122
123static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
124{
125 struct ql3xxx_port_registers __iomem *port_regs =
126 qdev->mem_map_registers;
127 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
128 readl(&port_regs->CommonRegs.semaphoreReg);
129}
130
131static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
132{
133 struct ql3xxx_port_registers __iomem *port_regs =
134 qdev->mem_map_registers;
135 u32 value;
136
137 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
138 value = readl(&port_regs->CommonRegs.semaphoreReg);
139 return ((value & (sem_mask >> 16)) == sem_bits);
140}
141
142/*
143 * Caller holds hw_lock.
144 */
145static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
146{
147 int i = 0;
148
149 do {
150 if (ql_sem_lock(qdev,
151 QL_DRVR_SEM_MASK,
152 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
153 * 2) << 1)) {
154 netdev_printk(KERN_DEBUG, qdev->ndev,
155 "driver lock acquired\n");
156 return 1;
157 }
158 ssleep(1);
159 } while (++i < 10);
160
161 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
162 return 0;
163}
164
165static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
166{
167 struct ql3xxx_port_registers __iomem *port_regs =
168 qdev->mem_map_registers;
169
170 writel(((ISP_CONTROL_NP_MASK << 16) | page),
171 &port_regs->CommonRegs.ispControlStatus);
172 readl(&port_regs->CommonRegs.ispControlStatus);
173 qdev->current_page = page;
174}
175
176static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
177{
178 u32 value;
179 unsigned long hw_flags;
180
181 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
182 value = readl(reg);
183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
184
185 return value;
186}
187
188static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
189{
190 return readl(reg);
191}
192
193static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
194{
195 u32 value;
196 unsigned long hw_flags;
197
198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
199
200 if (qdev->current_page != 0)
201 ql_set_register_page(qdev, 0);
202 value = readl(reg);
203
204 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
205 return value;
206}
207
208static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
209{
210 if (qdev->current_page != 0)
211 ql_set_register_page(qdev, 0);
212 return readl(reg);
213}
214
215static void ql_write_common_reg_l(struct ql3_adapter *qdev,
216 u32 __iomem *reg, u32 value)
217{
218 unsigned long hw_flags;
219
220 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
221 writel(value, reg);
222 readl(reg);
223 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
224}
225
226static void ql_write_common_reg(struct ql3_adapter *qdev,
227 u32 __iomem *reg, u32 value)
228{
229 writel(value, reg);
230 readl(reg);
231}
232
233static void ql_write_nvram_reg(struct ql3_adapter *qdev,
234 u32 __iomem *reg, u32 value)
235{
236 writel(value, reg);
237 readl(reg);
238 udelay(1);
239}
240
241static void ql_write_page0_reg(struct ql3_adapter *qdev,
242 u32 __iomem *reg, u32 value)
243{
244 if (qdev->current_page != 0)
245 ql_set_register_page(qdev, 0);
246 writel(value, reg);
247 readl(reg);
248}
249
250/*
251 * Caller holds hw_lock. Only called during init.
252 */
253static void ql_write_page1_reg(struct ql3_adapter *qdev,
254 u32 __iomem *reg, u32 value)
255{
256 if (qdev->current_page != 1)
257 ql_set_register_page(qdev, 1);
258 writel(value, reg);
259 readl(reg);
260}
261
262/*
263 * Caller holds hw_lock. Only called during init.
264 */
265static void ql_write_page2_reg(struct ql3_adapter *qdev,
266 u32 __iomem *reg, u32 value)
267{
268 if (qdev->current_page != 2)
269 ql_set_register_page(qdev, 2);
270 writel(value, reg);
271 readl(reg);
272}
273
274static void ql_disable_interrupts(struct ql3_adapter *qdev)
275{
276 struct ql3xxx_port_registers __iomem *port_regs =
277 qdev->mem_map_registers;
278
279 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
280 (ISP_IMR_ENABLE_INT << 16));
281
282}
283
284static void ql_enable_interrupts(struct ql3_adapter *qdev)
285{
286 struct ql3xxx_port_registers __iomem *port_regs =
287 qdev->mem_map_registers;
288
289 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
290 ((0xff << 16) | ISP_IMR_ENABLE_INT));
291
292}
293
294static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
295 struct ql_rcv_buf_cb *lrg_buf_cb)
296{
297 dma_addr_t map;
298 int err;
299 lrg_buf_cb->next = NULL;
300
301 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
302 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
303 } else {
304 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
305 qdev->lrg_buf_free_tail = lrg_buf_cb;
306 }
307
308 if (!lrg_buf_cb->skb) {
309 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
310 qdev->lrg_buffer_len);
311 if (unlikely(!lrg_buf_cb->skb)) {
312 qdev->lrg_buf_skb_check++;
313 } else {
314 /*
315 * We save some space to copy the ethhdr from first
316 * buffer
317 */
318 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
319 map = pci_map_single(qdev->pdev,
320 lrg_buf_cb->skb->data,
321 qdev->lrg_buffer_len -
322 QL_HEADER_SPACE,
323 PCI_DMA_FROMDEVICE);
324 err = pci_dma_mapping_error(qdev->pdev, map);
325 if (err) {
326 netdev_err(qdev->ndev,
327 "PCI mapping failed with error: %d\n",
328 err);
329 dev_kfree_skb(lrg_buf_cb->skb);
330 lrg_buf_cb->skb = NULL;
331
332 qdev->lrg_buf_skb_check++;
333 return;
334 }
335
336 lrg_buf_cb->buf_phy_addr_low =
337 cpu_to_le32(LS_64BITS(map));
338 lrg_buf_cb->buf_phy_addr_high =
339 cpu_to_le32(MS_64BITS(map));
340 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
341 dma_unmap_len_set(lrg_buf_cb, maplen,
342 qdev->lrg_buffer_len -
343 QL_HEADER_SPACE);
344 }
345 }
346
347 qdev->lrg_buf_free_count++;
348}
349
350static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
351 *qdev)
352{
353 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
354
355 if (lrg_buf_cb != NULL) {
356 qdev->lrg_buf_free_head = lrg_buf_cb->next;
357 if (qdev->lrg_buf_free_head == NULL)
358 qdev->lrg_buf_free_tail = NULL;
359 qdev->lrg_buf_free_count--;
360 }
361
362 return lrg_buf_cb;
363}
364
365static u32 addrBits = EEPROM_NO_ADDR_BITS;
366static u32 dataBits = EEPROM_NO_DATA_BITS;
367
368static void fm93c56a_deselect(struct ql3_adapter *qdev);
369static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
370 unsigned short *value);
371
372/*
373 * Caller holds hw_lock.
374 */
375static void fm93c56a_select(struct ql3_adapter *qdev)
376{
377 struct ql3xxx_port_registers __iomem *port_regs =
378 qdev->mem_map_registers;
379 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
380
381 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
382 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
383 ql_write_nvram_reg(qdev, spir,
384 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
385}
386
387/*
388 * Caller holds hw_lock.
389 */
390static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
391{
392 int i;
393 u32 mask;
394 u32 dataBit;
395 u32 previousBit;
396 struct ql3xxx_port_registers __iomem *port_regs =
397 qdev->mem_map_registers;
398 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
399
400 /* Clock in a zero, then do the start bit */
401 ql_write_nvram_reg(qdev, spir,
402 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
403 AUBURN_EEPROM_DO_1));
404 ql_write_nvram_reg(qdev, spir,
405 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
406 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
407 ql_write_nvram_reg(qdev, spir,
408 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
409 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
410
411 mask = 1 << (FM93C56A_CMD_BITS - 1);
412 /* Force the previous data bit to be different */
413 previousBit = 0xffff;
414 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
415 dataBit = (cmd & mask)
416 ? AUBURN_EEPROM_DO_1
417 : AUBURN_EEPROM_DO_0;
418 if (previousBit != dataBit) {
419 /* If the bit changed, change the DO state to match */
420 ql_write_nvram_reg(qdev, spir,
421 (ISP_NVRAM_MASK |
422 qdev->eeprom_cmd_data | dataBit));
423 previousBit = dataBit;
424 }
425 ql_write_nvram_reg(qdev, spir,
426 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
427 dataBit | AUBURN_EEPROM_CLK_RISE));
428 ql_write_nvram_reg(qdev, spir,
429 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
430 dataBit | AUBURN_EEPROM_CLK_FALL));
431 cmd = cmd << 1;
432 }
433
434 mask = 1 << (addrBits - 1);
435 /* Force the previous data bit to be different */
436 previousBit = 0xffff;
437 for (i = 0; i < addrBits; i++) {
438 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
439 : AUBURN_EEPROM_DO_0;
440 if (previousBit != dataBit) {
441 /*
442 * If the bit changed, then change the DO state to
443 * match
444 */
445 ql_write_nvram_reg(qdev, spir,
446 (ISP_NVRAM_MASK |
447 qdev->eeprom_cmd_data | dataBit));
448 previousBit = dataBit;
449 }
450 ql_write_nvram_reg(qdev, spir,
451 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
452 dataBit | AUBURN_EEPROM_CLK_RISE));
453 ql_write_nvram_reg(qdev, spir,
454 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
455 dataBit | AUBURN_EEPROM_CLK_FALL));
456 eepromAddr = eepromAddr << 1;
457 }
458}
459
460/*
461 * Caller holds hw_lock.
462 */
463static void fm93c56a_deselect(struct ql3_adapter *qdev)
464{
465 struct ql3xxx_port_registers __iomem *port_regs =
466 qdev->mem_map_registers;
467 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
468
469 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
470 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
471}
472
473/*
474 * Caller holds hw_lock.
475 */
476static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
477{
478 int i;
479 u32 data = 0;
480 u32 dataBit;
481 struct ql3xxx_port_registers __iomem *port_regs =
482 qdev->mem_map_registers;
483 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
484
485 /* Read the data bits */
486 /* The first bit is a dummy. Clock right over it. */
487 for (i = 0; i < dataBits; i++) {
488 ql_write_nvram_reg(qdev, spir,
489 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
490 AUBURN_EEPROM_CLK_RISE);
491 ql_write_nvram_reg(qdev, spir,
492 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
493 AUBURN_EEPROM_CLK_FALL);
494 dataBit = (ql_read_common_reg(qdev, spir) &
495 AUBURN_EEPROM_DI_1) ? 1 : 0;
496 data = (data << 1) | dataBit;
497 }
498 *value = (u16)data;
499}
500
501/*
502 * Caller holds hw_lock.
503 */
504static void eeprom_readword(struct ql3_adapter *qdev,
505 u32 eepromAddr, unsigned short *value)
506{
507 fm93c56a_select(qdev);
508 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
509 fm93c56a_datain(qdev, value);
510 fm93c56a_deselect(qdev);
511}
512
513static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
514{
515 __le16 *p = (__le16 *)ndev->dev_addr;
516 p[0] = cpu_to_le16(addr[0]);
517 p[1] = cpu_to_le16(addr[1]);
518 p[2] = cpu_to_le16(addr[2]);
519}
520
521static int ql_get_nvram_params(struct ql3_adapter *qdev)
522{
523 u16 *pEEPROMData;
524 u16 checksum = 0;
525 u32 index;
526 unsigned long hw_flags;
527
528 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
529
530 pEEPROMData = (u16 *)&qdev->nvram_data;
531 qdev->eeprom_cmd_data = 0;
532 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
533 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
534 2) << 10)) {
535 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
536 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
537 return -1;
538 }
539
540 for (index = 0; index < EEPROM_SIZE; index++) {
541 eeprom_readword(qdev, index, pEEPROMData);
542 checksum += *pEEPROMData;
543 pEEPROMData++;
544 }
545 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
546
547 if (checksum != 0) {
548 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
549 checksum);
550 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
551 return -1;
552 }
553
554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
555 return checksum;
556}
557
558static const u32 PHYAddr[2] = {
559 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
560};
561
562static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
563{
564 struct ql3xxx_port_registers __iomem *port_regs =
565 qdev->mem_map_registers;
566 u32 temp;
567 int count = 1000;
568
569 while (count) {
570 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
571 if (!(temp & MAC_MII_STATUS_BSY))
572 return 0;
573 udelay(10);
574 count--;
575 }
576 return -1;
577}
578
579static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
580{
581 struct ql3xxx_port_registers __iomem *port_regs =
582 qdev->mem_map_registers;
583 u32 scanControl;
584
585 if (qdev->numPorts > 1) {
586 /* Auto scan will cycle through multiple ports */
587 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
588 } else {
589 scanControl = MAC_MII_CONTROL_SC;
590 }
591
592 /*
593 * Scan register 1 of PHY/PETBI,
594 * Set up to scan both devices
595 * The autoscan starts from the first register, completes
596 * the last one before rolling over to the first
597 */
598 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
599 PHYAddr[0] | MII_SCAN_REGISTER);
600
601 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
602 (scanControl) |
603 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
604}
605
606static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
607{
608 u8 ret;
609 struct ql3xxx_port_registers __iomem *port_regs =
610 qdev->mem_map_registers;
611
612 /* See if scan mode is enabled before we turn it off */
613 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
614 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
615 /* Scan is enabled */
616 ret = 1;
617 } else {
618 /* Scan is disabled */
619 ret = 0;
620 }
621
622 /*
623 * When disabling scan mode you must first change the MII register
624 * address
625 */
626 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627 PHYAddr[0] | MII_SCAN_REGISTER);
628
629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
630 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
631 MAC_MII_CONTROL_RC) << 16));
632
633 return ret;
634}
635
636static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
637 u16 regAddr, u16 value, u32 phyAddr)
638{
639 struct ql3xxx_port_registers __iomem *port_regs =
640 qdev->mem_map_registers;
641 u8 scanWasEnabled;
642
643 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
644
645 if (ql_wait_for_mii_ready(qdev)) {
646 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
647 return -1;
648 }
649
650 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651 phyAddr | regAddr);
652
653 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
654
655 /* Wait for write to complete 9/10/04 SJP */
656 if (ql_wait_for_mii_ready(qdev)) {
657 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
658 return -1;
659 }
660
661 if (scanWasEnabled)
662 ql_mii_enable_scan_mode(qdev);
663
664 return 0;
665}
666
667static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
668 u16 *value, u32 phyAddr)
669{
670 struct ql3xxx_port_registers __iomem *port_regs =
671 qdev->mem_map_registers;
672 u8 scanWasEnabled;
673 u32 temp;
674
675 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
676
677 if (ql_wait_for_mii_ready(qdev)) {
678 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
679 return -1;
680 }
681
682 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 phyAddr | regAddr);
684
685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
686 (MAC_MII_CONTROL_RC << 16));
687
688 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
689 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
690
691 /* Wait for the read to complete */
692 if (ql_wait_for_mii_ready(qdev)) {
693 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
694 return -1;
695 }
696
697 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
698 *value = (u16) temp;
699
700 if (scanWasEnabled)
701 ql_mii_enable_scan_mode(qdev);
702
703 return 0;
704}
705
706static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
707{
708 struct ql3xxx_port_registers __iomem *port_regs =
709 qdev->mem_map_registers;
710
711 ql_mii_disable_scan_mode(qdev);
712
713 if (ql_wait_for_mii_ready(qdev)) {
714 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
715 return -1;
716 }
717
718 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
719 qdev->PHYAddr | regAddr);
720
721 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
722
723 /* Wait for write to complete. */
724 if (ql_wait_for_mii_ready(qdev)) {
725 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
726 return -1;
727 }
728
729 ql_mii_enable_scan_mode(qdev);
730
731 return 0;
732}
733
734static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
735{
736 u32 temp;
737 struct ql3xxx_port_registers __iomem *port_regs =
738 qdev->mem_map_registers;
739
740 ql_mii_disable_scan_mode(qdev);
741
742 if (ql_wait_for_mii_ready(qdev)) {
743 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
744 return -1;
745 }
746
747 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
748 qdev->PHYAddr | regAddr);
749
750 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
751 (MAC_MII_CONTROL_RC << 16));
752
753 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
754 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
755
756 /* Wait for the read to complete */
757 if (ql_wait_for_mii_ready(qdev)) {
758 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
759 return -1;
760 }
761
762 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
763 *value = (u16) temp;
764
765 ql_mii_enable_scan_mode(qdev);
766
767 return 0;
768}
769
770static void ql_petbi_reset(struct ql3_adapter *qdev)
771{
772 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
773}
774
775static void ql_petbi_start_neg(struct ql3_adapter *qdev)
776{
777 u16 reg;
778
779 /* Enable Auto-negotiation sense */
780 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
781 reg |= PETBI_TBI_AUTO_SENSE;
782 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
783
784 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
785 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
786
787 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
788 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
789 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
790
791}
792
793static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
794{
795 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
796 PHYAddr[qdev->mac_index]);
797}
798
799static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
800{
801 u16 reg;
802
803 /* Enable Auto-negotiation sense */
804 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
805 PHYAddr[qdev->mac_index]);
806 reg |= PETBI_TBI_AUTO_SENSE;
807 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
808 PHYAddr[qdev->mac_index]);
809
810 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
811 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
812 PHYAddr[qdev->mac_index]);
813
814 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
815 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
816 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
817 PHYAddr[qdev->mac_index]);
818}
819
820static void ql_petbi_init(struct ql3_adapter *qdev)
821{
822 ql_petbi_reset(qdev);
823 ql_petbi_start_neg(qdev);
824}
825
826static void ql_petbi_init_ex(struct ql3_adapter *qdev)
827{
828 ql_petbi_reset_ex(qdev);
829 ql_petbi_start_neg_ex(qdev);
830}
831
832static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
833{
834 u16 reg;
835
836 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
837 return 0;
838
839 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
840}
841
842static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
843{
844 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
845 /* power down device bit 11 = 1 */
846 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
847 /* enable diagnostic mode bit 2 = 1 */
848 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
849 /* 1000MB amplitude adjust (see Agere errata) */
850 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
851 /* 1000MB amplitude adjust (see Agere errata) */
852 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
853 /* 100MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
855 /* 100MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
857 /* 10MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
859 /* 10MB amplitude adjust (see Agere errata) */
860 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
861 /* point to hidden reg 0x2806 */
862 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
863 /* Write new PHYAD w/bit 5 set */
864 ql_mii_write_reg_ex(qdev, 0x11,
865 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
866 /*
867 * Disable diagnostic mode bit 2 = 0
868 * Power up device bit 11 = 0
869 * Link up (on) and activity (blink)
870 */
871 ql_mii_write_reg(qdev, 0x12, 0x840a);
872 ql_mii_write_reg(qdev, 0x00, 0x1140);
873 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
874}
875
876static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
877 u16 phyIdReg0, u16 phyIdReg1)
878{
879 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
880 u32 oui;
881 u16 model;
882 int i;
883
884 if (phyIdReg0 == 0xffff)
885 return result;
886
887 if (phyIdReg1 == 0xffff)
888 return result;
889
890 /* oui is split between two registers */
891 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
892
893 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
894
895 /* Scan table for this PHY */
896 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
897 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
898 (model == PHY_DEVICES[i].phyIdModel)) {
899 netdev_info(qdev->ndev, "Phy: %s\n",
900 PHY_DEVICES[i].name);
901 result = PHY_DEVICES[i].phyDevice;
902 break;
903 }
904 }
905
906 return result;
907}
908
909static int ql_phy_get_speed(struct ql3_adapter *qdev)
910{
911 u16 reg;
912
913 switch (qdev->phyType) {
914 case PHY_AGERE_ET1011C: {
915 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
916 return 0;
917
918 reg = (reg >> 8) & 3;
919 break;
920 }
921 default:
922 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
923 return 0;
924
925 reg = (((reg & 0x18) >> 3) & 3);
926 }
927
928 switch (reg) {
929 case 2:
930 return SPEED_1000;
931 case 1:
932 return SPEED_100;
933 case 0:
934 return SPEED_10;
935 default:
936 return -1;
937 }
938}
939
940static int ql_is_full_dup(struct ql3_adapter *qdev)
941{
942 u16 reg;
943
944 switch (qdev->phyType) {
945 case PHY_AGERE_ET1011C: {
946 if (ql_mii_read_reg(qdev, 0x1A, ®))
947 return 0;
948
949 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
950 }
951 case PHY_VITESSE_VSC8211:
952 default: {
953 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
954 return 0;
955 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
956 }
957 }
958}
959
960static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
961{
962 u16 reg;
963
964 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
965 return 0;
966
967 return (reg & PHY_NEG_PAUSE) != 0;
968}
969
970static int PHY_Setup(struct ql3_adapter *qdev)
971{
972 u16 reg1;
973 u16 reg2;
974 bool agereAddrChangeNeeded = false;
975 u32 miiAddr = 0;
976 int err;
977
978 /* Determine the PHY we are using by reading the ID's */
979 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
980 if (err != 0) {
981 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
982 return err;
983 }
984
985 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
986 if (err != 0) {
987 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
988 return err;
989 }
990
991 /* Check if we have a Agere PHY */
992 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
993
994 /* Determine which MII address we should be using
995 determined by the index of the card */
996 if (qdev->mac_index == 0)
997 miiAddr = MII_AGERE_ADDR_1;
998 else
999 miiAddr = MII_AGERE_ADDR_2;
1000
1001 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1002 if (err != 0) {
1003 netdev_err(qdev->ndev,
1004 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1005 return err;
1006 }
1007
1008 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1009 if (err != 0) {
1010 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1011 return err;
1012 }
1013
1014 /* We need to remember to initialize the Agere PHY */
1015 agereAddrChangeNeeded = true;
1016 }
1017
1018 /* Determine the particular PHY we have on board to apply
1019 PHY specific initializations */
1020 qdev->phyType = getPhyType(qdev, reg1, reg2);
1021
1022 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1023 /* need this here so address gets changed */
1024 phyAgereSpecificInit(qdev, miiAddr);
1025 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1026 netdev_err(qdev->ndev, "PHY is unknown\n");
1027 return -EIO;
1028 }
1029
1030 return 0;
1031}
1032
1033/*
1034 * Caller holds hw_lock.
1035 */
1036static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1037{
1038 struct ql3xxx_port_registers __iomem *port_regs =
1039 qdev->mem_map_registers;
1040 u32 value;
1041
1042 if (enable)
1043 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1044 else
1045 value = (MAC_CONFIG_REG_PE << 16);
1046
1047 if (qdev->mac_index)
1048 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1049 else
1050 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1051}
1052
1053/*
1054 * Caller holds hw_lock.
1055 */
1056static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1057{
1058 struct ql3xxx_port_registers __iomem *port_regs =
1059 qdev->mem_map_registers;
1060 u32 value;
1061
1062 if (enable)
1063 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1064 else
1065 value = (MAC_CONFIG_REG_SR << 16);
1066
1067 if (qdev->mac_index)
1068 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1069 else
1070 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1071}
1072
1073/*
1074 * Caller holds hw_lock.
1075 */
1076static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1077{
1078 struct ql3xxx_port_registers __iomem *port_regs =
1079 qdev->mem_map_registers;
1080 u32 value;
1081
1082 if (enable)
1083 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1084 else
1085 value = (MAC_CONFIG_REG_GM << 16);
1086
1087 if (qdev->mac_index)
1088 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1089 else
1090 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1091}
1092
1093/*
1094 * Caller holds hw_lock.
1095 */
1096static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1097{
1098 struct ql3xxx_port_registers __iomem *port_regs =
1099 qdev->mem_map_registers;
1100 u32 value;
1101
1102 if (enable)
1103 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1104 else
1105 value = (MAC_CONFIG_REG_FD << 16);
1106
1107 if (qdev->mac_index)
1108 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1109 else
1110 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1111}
1112
1113/*
1114 * Caller holds hw_lock.
1115 */
1116static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1117{
1118 struct ql3xxx_port_registers __iomem *port_regs =
1119 qdev->mem_map_registers;
1120 u32 value;
1121
1122 if (enable)
1123 value =
1124 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1125 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1126 else
1127 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1128
1129 if (qdev->mac_index)
1130 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1131 else
1132 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1133}
1134
1135/*
1136 * Caller holds hw_lock.
1137 */
1138static int ql_is_fiber(struct ql3_adapter *qdev)
1139{
1140 struct ql3xxx_port_registers __iomem *port_regs =
1141 qdev->mem_map_registers;
1142 u32 bitToCheck = 0;
1143 u32 temp;
1144
1145 switch (qdev->mac_index) {
1146 case 0:
1147 bitToCheck = PORT_STATUS_SM0;
1148 break;
1149 case 1:
1150 bitToCheck = PORT_STATUS_SM1;
1151 break;
1152 }
1153
1154 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1155 return (temp & bitToCheck) != 0;
1156}
1157
1158static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1159{
1160 u16 reg;
1161 ql_mii_read_reg(qdev, 0x00, ®);
1162 return (reg & 0x1000) != 0;
1163}
1164
1165/*
1166 * Caller holds hw_lock.
1167 */
1168static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1169{
1170 struct ql3xxx_port_registers __iomem *port_regs =
1171 qdev->mem_map_registers;
1172 u32 bitToCheck = 0;
1173 u32 temp;
1174
1175 switch (qdev->mac_index) {
1176 case 0:
1177 bitToCheck = PORT_STATUS_AC0;
1178 break;
1179 case 1:
1180 bitToCheck = PORT_STATUS_AC1;
1181 break;
1182 }
1183
1184 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1185 if (temp & bitToCheck) {
1186 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1187 return 1;
1188 }
1189 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1190 return 0;
1191}
1192
1193/*
1194 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1195 */
1196static int ql_is_neg_pause(struct ql3_adapter *qdev)
1197{
1198 if (ql_is_fiber(qdev))
1199 return ql_is_petbi_neg_pause(qdev);
1200 else
1201 return ql_is_phy_neg_pause(qdev);
1202}
1203
1204static int ql_auto_neg_error(struct ql3_adapter *qdev)
1205{
1206 struct ql3xxx_port_registers __iomem *port_regs =
1207 qdev->mem_map_registers;
1208 u32 bitToCheck = 0;
1209 u32 temp;
1210
1211 switch (qdev->mac_index) {
1212 case 0:
1213 bitToCheck = PORT_STATUS_AE0;
1214 break;
1215 case 1:
1216 bitToCheck = PORT_STATUS_AE1;
1217 break;
1218 }
1219 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1220 return (temp & bitToCheck) != 0;
1221}
1222
1223static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1224{
1225 if (ql_is_fiber(qdev))
1226 return SPEED_1000;
1227 else
1228 return ql_phy_get_speed(qdev);
1229}
1230
1231static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1232{
1233 if (ql_is_fiber(qdev))
1234 return 1;
1235 else
1236 return ql_is_full_dup(qdev);
1237}
1238
1239/*
1240 * Caller holds hw_lock.
1241 */
1242static int ql_link_down_detect(struct ql3_adapter *qdev)
1243{
1244 struct ql3xxx_port_registers __iomem *port_regs =
1245 qdev->mem_map_registers;
1246 u32 bitToCheck = 0;
1247 u32 temp;
1248
1249 switch (qdev->mac_index) {
1250 case 0:
1251 bitToCheck = ISP_CONTROL_LINK_DN_0;
1252 break;
1253 case 1:
1254 bitToCheck = ISP_CONTROL_LINK_DN_1;
1255 break;
1256 }
1257
1258 temp =
1259 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1260 return (temp & bitToCheck) != 0;
1261}
1262
1263/*
1264 * Caller holds hw_lock.
1265 */
1266static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1267{
1268 struct ql3xxx_port_registers __iomem *port_regs =
1269 qdev->mem_map_registers;
1270
1271 switch (qdev->mac_index) {
1272 case 0:
1273 ql_write_common_reg(qdev,
1274 &port_regs->CommonRegs.ispControlStatus,
1275 (ISP_CONTROL_LINK_DN_0) |
1276 (ISP_CONTROL_LINK_DN_0 << 16));
1277 break;
1278
1279 case 1:
1280 ql_write_common_reg(qdev,
1281 &port_regs->CommonRegs.ispControlStatus,
1282 (ISP_CONTROL_LINK_DN_1) |
1283 (ISP_CONTROL_LINK_DN_1 << 16));
1284 break;
1285
1286 default:
1287 return 1;
1288 }
1289
1290 return 0;
1291}
1292
1293/*
1294 * Caller holds hw_lock.
1295 */
1296static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1297{
1298 struct ql3xxx_port_registers __iomem *port_regs =
1299 qdev->mem_map_registers;
1300 u32 bitToCheck = 0;
1301 u32 temp;
1302
1303 switch (qdev->mac_index) {
1304 case 0:
1305 bitToCheck = PORT_STATUS_F1_ENABLED;
1306 break;
1307 case 1:
1308 bitToCheck = PORT_STATUS_F3_ENABLED;
1309 break;
1310 default:
1311 break;
1312 }
1313
1314 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1315 if (temp & bitToCheck) {
1316 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1317 "not link master\n");
1318 return 0;
1319 }
1320
1321 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1322 return 1;
1323}
1324
1325static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1326{
1327 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1328 PHYAddr[qdev->mac_index]);
1329}
1330
1331static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1332{
1333 u16 reg;
1334 u16 portConfiguration;
1335
1336 if (qdev->phyType == PHY_AGERE_ET1011C)
1337 ql_mii_write_reg(qdev, 0x13, 0x0000);
1338 /* turn off external loopback */
1339
1340 if (qdev->mac_index == 0)
1341 portConfiguration =
1342 qdev->nvram_data.macCfg_port0.portConfiguration;
1343 else
1344 portConfiguration =
1345 qdev->nvram_data.macCfg_port1.portConfiguration;
1346
1347 /* Some HBA's in the field are set to 0 and they need to
1348 be reinterpreted with a default value */
1349 if (portConfiguration == 0)
1350 portConfiguration = PORT_CONFIG_DEFAULT;
1351
1352 /* Set the 1000 advertisements */
1353 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1354 PHYAddr[qdev->mac_index]);
1355 reg &= ~PHY_GIG_ALL_PARAMS;
1356
1357 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1358 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1359 reg |= PHY_GIG_ADV_1000F;
1360 else
1361 reg |= PHY_GIG_ADV_1000H;
1362 }
1363
1364 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1365 PHYAddr[qdev->mac_index]);
1366
1367 /* Set the 10/100 & pause negotiation advertisements */
1368 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1369 PHYAddr[qdev->mac_index]);
1370 reg &= ~PHY_NEG_ALL_PARAMS;
1371
1372 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1373 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1374
1375 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1376 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1377 reg |= PHY_NEG_ADV_100F;
1378
1379 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1380 reg |= PHY_NEG_ADV_10F;
1381 }
1382
1383 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1384 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1385 reg |= PHY_NEG_ADV_100H;
1386
1387 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1388 reg |= PHY_NEG_ADV_10H;
1389 }
1390
1391 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1392 reg |= 1;
1393
1394 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1395 PHYAddr[qdev->mac_index]);
1396
1397 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1398
1399 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1400 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1401 PHYAddr[qdev->mac_index]);
1402}
1403
1404static void ql_phy_init_ex(struct ql3_adapter *qdev)
1405{
1406 ql_phy_reset_ex(qdev);
1407 PHY_Setup(qdev);
1408 ql_phy_start_neg_ex(qdev);
1409}
1410
1411/*
1412 * Caller holds hw_lock.
1413 */
1414static u32 ql_get_link_state(struct ql3_adapter *qdev)
1415{
1416 struct ql3xxx_port_registers __iomem *port_regs =
1417 qdev->mem_map_registers;
1418 u32 bitToCheck = 0;
1419 u32 temp, linkState;
1420
1421 switch (qdev->mac_index) {
1422 case 0:
1423 bitToCheck = PORT_STATUS_UP0;
1424 break;
1425 case 1:
1426 bitToCheck = PORT_STATUS_UP1;
1427 break;
1428 }
1429
1430 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1431 if (temp & bitToCheck)
1432 linkState = LS_UP;
1433 else
1434 linkState = LS_DOWN;
1435
1436 return linkState;
1437}
1438
1439static int ql_port_start(struct ql3_adapter *qdev)
1440{
1441 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1442 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1443 2) << 7)) {
1444 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1445 return -1;
1446 }
1447
1448 if (ql_is_fiber(qdev)) {
1449 ql_petbi_init(qdev);
1450 } else {
1451 /* Copper port */
1452 ql_phy_init_ex(qdev);
1453 }
1454
1455 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1456 return 0;
1457}
1458
1459static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1460{
1461
1462 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1463 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1464 2) << 7))
1465 return -1;
1466
1467 if (!ql_auto_neg_error(qdev)) {
1468 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1469 /* configure the MAC */
1470 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1471 "Configuring link\n");
1472 ql_mac_cfg_soft_reset(qdev, 1);
1473 ql_mac_cfg_gig(qdev,
1474 (ql_get_link_speed
1475 (qdev) ==
1476 SPEED_1000));
1477 ql_mac_cfg_full_dup(qdev,
1478 ql_is_link_full_dup
1479 (qdev));
1480 ql_mac_cfg_pause(qdev,
1481 ql_is_neg_pause
1482 (qdev));
1483 ql_mac_cfg_soft_reset(qdev, 0);
1484
1485 /* enable the MAC */
1486 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1487 "Enabling mac\n");
1488 ql_mac_enable(qdev, 1);
1489 }
1490
1491 qdev->port_link_state = LS_UP;
1492 netif_start_queue(qdev->ndev);
1493 netif_carrier_on(qdev->ndev);
1494 netif_info(qdev, link, qdev->ndev,
1495 "Link is up at %d Mbps, %s duplex\n",
1496 ql_get_link_speed(qdev),
1497 ql_is_link_full_dup(qdev) ? "full" : "half");
1498
1499 } else { /* Remote error detected */
1500
1501 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1502 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1503 "Remote error detected. Calling ql_port_start()\n");
1504 /*
1505 * ql_port_start() is shared code and needs
1506 * to lock the PHY on it's own.
1507 */
1508 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1509 if (ql_port_start(qdev)) /* Restart port */
1510 return -1;
1511 return 0;
1512 }
1513 }
1514 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1515 return 0;
1516}
1517
1518static void ql_link_state_machine_work(struct work_struct *work)
1519{
1520 struct ql3_adapter *qdev =
1521 container_of(work, struct ql3_adapter, link_state_work.work);
1522
1523 u32 curr_link_state;
1524 unsigned long hw_flags;
1525
1526 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1527
1528 curr_link_state = ql_get_link_state(qdev);
1529
1530 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1531 netif_info(qdev, link, qdev->ndev,
1532 "Reset in progress, skip processing link state\n");
1533
1534 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1535
1536 /* Restart timer on 2 second interval. */
1537 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1538
1539 return;
1540 }
1541
1542 switch (qdev->port_link_state) {
1543 default:
1544 if (test_bit(QL_LINK_MASTER, &qdev->flags))
1545 ql_port_start(qdev);
1546 qdev->port_link_state = LS_DOWN;
1547 /* Fall Through */
1548
1549 case LS_DOWN:
1550 if (curr_link_state == LS_UP) {
1551 netif_info(qdev, link, qdev->ndev, "Link is up\n");
1552 if (ql_is_auto_neg_complete(qdev))
1553 ql_finish_auto_neg(qdev);
1554
1555 if (qdev->port_link_state == LS_UP)
1556 ql_link_down_detect_clear(qdev);
1557
1558 qdev->port_link_state = LS_UP;
1559 }
1560 break;
1561
1562 case LS_UP:
1563 /*
1564 * See if the link is currently down or went down and came
1565 * back up
1566 */
1567 if (curr_link_state == LS_DOWN) {
1568 netif_info(qdev, link, qdev->ndev, "Link is down\n");
1569 qdev->port_link_state = LS_DOWN;
1570 }
1571 if (ql_link_down_detect(qdev))
1572 qdev->port_link_state = LS_DOWN;
1573 break;
1574 }
1575 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1576
1577 /* Restart timer on 2 second interval. */
1578 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1579}
1580
1581/*
1582 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1583 */
1584static void ql_get_phy_owner(struct ql3_adapter *qdev)
1585{
1586 if (ql_this_adapter_controls_port(qdev))
1587 set_bit(QL_LINK_MASTER, &qdev->flags);
1588 else
1589 clear_bit(QL_LINK_MASTER, &qdev->flags);
1590}
1591
1592/*
1593 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1594 */
1595static void ql_init_scan_mode(struct ql3_adapter *qdev)
1596{
1597 ql_mii_enable_scan_mode(qdev);
1598
1599 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1600 if (ql_this_adapter_controls_port(qdev))
1601 ql_petbi_init_ex(qdev);
1602 } else {
1603 if (ql_this_adapter_controls_port(qdev))
1604 ql_phy_init_ex(qdev);
1605 }
1606}
1607
1608/*
1609 * MII_Setup needs to be called before taking the PHY out of reset
1610 * so that the management interface clock speed can be set properly.
1611 * It would be better if we had a way to disable MDC until after the
1612 * PHY is out of reset, but we don't have that capability.
1613 */
1614static int ql_mii_setup(struct ql3_adapter *qdev)
1615{
1616 u32 reg;
1617 struct ql3xxx_port_registers __iomem *port_regs =
1618 qdev->mem_map_registers;
1619
1620 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1621 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1622 2) << 7))
1623 return -1;
1624
1625 if (qdev->device_id == QL3032_DEVICE_ID)
1626 ql_write_page0_reg(qdev,
1627 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1628
1629 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1630 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1631
1632 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1633 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1634
1635 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1636 return 0;
1637}
1638
1639#define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1640 SUPPORTED_FIBRE | \
1641 SUPPORTED_Autoneg)
1642#define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1643 SUPPORTED_10baseT_Full | \
1644 SUPPORTED_100baseT_Half | \
1645 SUPPORTED_100baseT_Full | \
1646 SUPPORTED_1000baseT_Half | \
1647 SUPPORTED_1000baseT_Full | \
1648 SUPPORTED_Autoneg | \
1649 SUPPORTED_TP) \
1650
1651static u32 ql_supported_modes(struct ql3_adapter *qdev)
1652{
1653 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1654 return SUPPORTED_OPTICAL_MODES;
1655
1656 return SUPPORTED_TP_MODES;
1657}
1658
1659static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1660{
1661 int status;
1662 unsigned long hw_flags;
1663 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1664 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1665 (QL_RESOURCE_BITS_BASE_CODE |
1666 (qdev->mac_index) * 2) << 7)) {
1667 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1668 return 0;
1669 }
1670 status = ql_is_auto_cfg(qdev);
1671 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1672 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1673 return status;
1674}
1675
1676static u32 ql_get_speed(struct ql3_adapter *qdev)
1677{
1678 u32 status;
1679 unsigned long hw_flags;
1680 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1681 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1682 (QL_RESOURCE_BITS_BASE_CODE |
1683 (qdev->mac_index) * 2) << 7)) {
1684 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1685 return 0;
1686 }
1687 status = ql_get_link_speed(qdev);
1688 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1689 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1690 return status;
1691}
1692
1693static int ql_get_full_dup(struct ql3_adapter *qdev)
1694{
1695 int status;
1696 unsigned long hw_flags;
1697 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1698 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1699 (QL_RESOURCE_BITS_BASE_CODE |
1700 (qdev->mac_index) * 2) << 7)) {
1701 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1702 return 0;
1703 }
1704 status = ql_is_link_full_dup(qdev);
1705 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1706 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1707 return status;
1708}
1709
1710static int ql_get_link_ksettings(struct net_device *ndev,
1711 struct ethtool_link_ksettings *cmd)
1712{
1713 struct ql3_adapter *qdev = netdev_priv(ndev);
1714 u32 supported, advertising;
1715
1716 supported = ql_supported_modes(qdev);
1717
1718 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1719 cmd->base.port = PORT_FIBRE;
1720 } else {
1721 cmd->base.port = PORT_TP;
1722 cmd->base.phy_address = qdev->PHYAddr;
1723 }
1724 advertising = ql_supported_modes(qdev);
1725 cmd->base.autoneg = ql_get_auto_cfg_status(qdev);
1726 cmd->base.speed = ql_get_speed(qdev);
1727 cmd->base.duplex = ql_get_full_dup(qdev);
1728
1729 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1730 supported);
1731 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1732 advertising);
1733
1734 return 0;
1735}
1736
1737static void ql_get_drvinfo(struct net_device *ndev,
1738 struct ethtool_drvinfo *drvinfo)
1739{
1740 struct ql3_adapter *qdev = netdev_priv(ndev);
1741 strlcpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1742 strlcpy(drvinfo->version, ql3xxx_driver_version,
1743 sizeof(drvinfo->version));
1744 strlcpy(drvinfo->bus_info, pci_name(qdev->pdev),
1745 sizeof(drvinfo->bus_info));
1746}
1747
1748static u32 ql_get_msglevel(struct net_device *ndev)
1749{
1750 struct ql3_adapter *qdev = netdev_priv(ndev);
1751 return qdev->msg_enable;
1752}
1753
1754static void ql_set_msglevel(struct net_device *ndev, u32 value)
1755{
1756 struct ql3_adapter *qdev = netdev_priv(ndev);
1757 qdev->msg_enable = value;
1758}
1759
1760static void ql_get_pauseparam(struct net_device *ndev,
1761 struct ethtool_pauseparam *pause)
1762{
1763 struct ql3_adapter *qdev = netdev_priv(ndev);
1764 struct ql3xxx_port_registers __iomem *port_regs =
1765 qdev->mem_map_registers;
1766
1767 u32 reg;
1768 if (qdev->mac_index == 0)
1769 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1770 else
1771 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1772
1773 pause->autoneg = ql_get_auto_cfg_status(qdev);
1774 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1775 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1776}
1777
1778static const struct ethtool_ops ql3xxx_ethtool_ops = {
1779 .get_drvinfo = ql_get_drvinfo,
1780 .get_link = ethtool_op_get_link,
1781 .get_msglevel = ql_get_msglevel,
1782 .set_msglevel = ql_set_msglevel,
1783 .get_pauseparam = ql_get_pauseparam,
1784 .get_link_ksettings = ql_get_link_ksettings,
1785};
1786
1787static int ql_populate_free_queue(struct ql3_adapter *qdev)
1788{
1789 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1790 dma_addr_t map;
1791 int err;
1792
1793 while (lrg_buf_cb) {
1794 if (!lrg_buf_cb->skb) {
1795 lrg_buf_cb->skb =
1796 netdev_alloc_skb(qdev->ndev,
1797 qdev->lrg_buffer_len);
1798 if (unlikely(!lrg_buf_cb->skb)) {
1799 netdev_printk(KERN_DEBUG, qdev->ndev,
1800 "Failed netdev_alloc_skb()\n");
1801 break;
1802 } else {
1803 /*
1804 * We save some space to copy the ethhdr from
1805 * first buffer
1806 */
1807 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1808 map = pci_map_single(qdev->pdev,
1809 lrg_buf_cb->skb->data,
1810 qdev->lrg_buffer_len -
1811 QL_HEADER_SPACE,
1812 PCI_DMA_FROMDEVICE);
1813
1814 err = pci_dma_mapping_error(qdev->pdev, map);
1815 if (err) {
1816 netdev_err(qdev->ndev,
1817 "PCI mapping failed with error: %d\n",
1818 err);
1819 dev_kfree_skb(lrg_buf_cb->skb);
1820 lrg_buf_cb->skb = NULL;
1821 break;
1822 }
1823
1824
1825 lrg_buf_cb->buf_phy_addr_low =
1826 cpu_to_le32(LS_64BITS(map));
1827 lrg_buf_cb->buf_phy_addr_high =
1828 cpu_to_le32(MS_64BITS(map));
1829 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1830 dma_unmap_len_set(lrg_buf_cb, maplen,
1831 qdev->lrg_buffer_len -
1832 QL_HEADER_SPACE);
1833 --qdev->lrg_buf_skb_check;
1834 if (!qdev->lrg_buf_skb_check)
1835 return 1;
1836 }
1837 }
1838 lrg_buf_cb = lrg_buf_cb->next;
1839 }
1840 return 0;
1841}
1842
1843/*
1844 * Caller holds hw_lock.
1845 */
1846static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1847{
1848 struct ql3xxx_port_registers __iomem *port_regs =
1849 qdev->mem_map_registers;
1850
1851 if (qdev->small_buf_release_cnt >= 16) {
1852 while (qdev->small_buf_release_cnt >= 16) {
1853 qdev->small_buf_q_producer_index++;
1854
1855 if (qdev->small_buf_q_producer_index ==
1856 NUM_SBUFQ_ENTRIES)
1857 qdev->small_buf_q_producer_index = 0;
1858 qdev->small_buf_release_cnt -= 8;
1859 }
1860 wmb();
1861 writel_relaxed(qdev->small_buf_q_producer_index,
1862 &port_regs->CommonRegs.rxSmallQProducerIndex);
1863 mmiowb();
1864 }
1865}
1866
1867/*
1868 * Caller holds hw_lock.
1869 */
1870static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1871{
1872 struct bufq_addr_element *lrg_buf_q_ele;
1873 int i;
1874 struct ql_rcv_buf_cb *lrg_buf_cb;
1875 struct ql3xxx_port_registers __iomem *port_regs =
1876 qdev->mem_map_registers;
1877
1878 if ((qdev->lrg_buf_free_count >= 8) &&
1879 (qdev->lrg_buf_release_cnt >= 16)) {
1880
1881 if (qdev->lrg_buf_skb_check)
1882 if (!ql_populate_free_queue(qdev))
1883 return;
1884
1885 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1886
1887 while ((qdev->lrg_buf_release_cnt >= 16) &&
1888 (qdev->lrg_buf_free_count >= 8)) {
1889
1890 for (i = 0; i < 8; i++) {
1891 lrg_buf_cb =
1892 ql_get_from_lrg_buf_free_list(qdev);
1893 lrg_buf_q_ele->addr_high =
1894 lrg_buf_cb->buf_phy_addr_high;
1895 lrg_buf_q_ele->addr_low =
1896 lrg_buf_cb->buf_phy_addr_low;
1897 lrg_buf_q_ele++;
1898
1899 qdev->lrg_buf_release_cnt--;
1900 }
1901
1902 qdev->lrg_buf_q_producer_index++;
1903
1904 if (qdev->lrg_buf_q_producer_index ==
1905 qdev->num_lbufq_entries)
1906 qdev->lrg_buf_q_producer_index = 0;
1907
1908 if (qdev->lrg_buf_q_producer_index ==
1909 (qdev->num_lbufq_entries - 1)) {
1910 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1911 }
1912 }
1913 wmb();
1914 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1915 writel(qdev->lrg_buf_q_producer_index,
1916 &port_regs->CommonRegs.rxLargeQProducerIndex);
1917 }
1918}
1919
1920static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1921 struct ob_mac_iocb_rsp *mac_rsp)
1922{
1923 struct ql_tx_buf_cb *tx_cb;
1924 int i;
1925
1926 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1927 netdev_warn(qdev->ndev,
1928 "Frame too short but it was padded and sent\n");
1929 }
1930
1931 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1932
1933 /* Check the transmit response flags for any errors */
1934 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1935 netdev_err(qdev->ndev,
1936 "Frame too short to be legal, frame not sent\n");
1937
1938 qdev->ndev->stats.tx_errors++;
1939 goto frame_not_sent;
1940 }
1941
1942 if (tx_cb->seg_count == 0) {
1943 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1944 mac_rsp->transaction_id);
1945
1946 qdev->ndev->stats.tx_errors++;
1947 goto invalid_seg_count;
1948 }
1949
1950 pci_unmap_single(qdev->pdev,
1951 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1952 dma_unmap_len(&tx_cb->map[0], maplen),
1953 PCI_DMA_TODEVICE);
1954 tx_cb->seg_count--;
1955 if (tx_cb->seg_count) {
1956 for (i = 1; i < tx_cb->seg_count; i++) {
1957 pci_unmap_page(qdev->pdev,
1958 dma_unmap_addr(&tx_cb->map[i],
1959 mapaddr),
1960 dma_unmap_len(&tx_cb->map[i], maplen),
1961 PCI_DMA_TODEVICE);
1962 }
1963 }
1964 qdev->ndev->stats.tx_packets++;
1965 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1966
1967frame_not_sent:
1968 dev_kfree_skb_irq(tx_cb->skb);
1969 tx_cb->skb = NULL;
1970
1971invalid_seg_count:
1972 atomic_inc(&qdev->tx_count);
1973}
1974
1975static void ql_get_sbuf(struct ql3_adapter *qdev)
1976{
1977 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1978 qdev->small_buf_index = 0;
1979 qdev->small_buf_release_cnt++;
1980}
1981
1982static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1983{
1984 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1985 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1986 qdev->lrg_buf_release_cnt++;
1987 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1988 qdev->lrg_buf_index = 0;
1989 return lrg_buf_cb;
1990}
1991
1992/*
1993 * The difference between 3022 and 3032 for inbound completions:
1994 * 3022 uses two buffers per completion. The first buffer contains
1995 * (some) header info, the second the remainder of the headers plus
1996 * the data. For this chip we reserve some space at the top of the
1997 * receive buffer so that the header info in buffer one can be
1998 * prepended to the buffer two. Buffer two is the sent up while
1999 * buffer one is returned to the hardware to be reused.
2000 * 3032 receives all of it's data and headers in one buffer for a
2001 * simpler process. 3032 also supports checksum verification as
2002 * can be seen in ql_process_macip_rx_intr().
2003 */
2004static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2005 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2006{
2007 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2008 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2009 struct sk_buff *skb;
2010 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2011
2012 /*
2013 * Get the inbound address list (small buffer).
2014 */
2015 ql_get_sbuf(qdev);
2016
2017 if (qdev->device_id == QL3022_DEVICE_ID)
2018 lrg_buf_cb1 = ql_get_lbuf(qdev);
2019
2020 /* start of second buffer */
2021 lrg_buf_cb2 = ql_get_lbuf(qdev);
2022 skb = lrg_buf_cb2->skb;
2023
2024 qdev->ndev->stats.rx_packets++;
2025 qdev->ndev->stats.rx_bytes += length;
2026
2027 skb_put(skb, length);
2028 pci_unmap_single(qdev->pdev,
2029 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2030 dma_unmap_len(lrg_buf_cb2, maplen),
2031 PCI_DMA_FROMDEVICE);
2032 prefetch(skb->data);
2033 skb_checksum_none_assert(skb);
2034 skb->protocol = eth_type_trans(skb, qdev->ndev);
2035
2036 napi_gro_receive(&qdev->napi, skb);
2037 lrg_buf_cb2->skb = NULL;
2038
2039 if (qdev->device_id == QL3022_DEVICE_ID)
2040 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2041 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2042}
2043
2044static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2045 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2046{
2047 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2048 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2049 struct sk_buff *skb1 = NULL, *skb2;
2050 struct net_device *ndev = qdev->ndev;
2051 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2052 u16 size = 0;
2053
2054 /*
2055 * Get the inbound address list (small buffer).
2056 */
2057
2058 ql_get_sbuf(qdev);
2059
2060 if (qdev->device_id == QL3022_DEVICE_ID) {
2061 /* start of first buffer on 3022 */
2062 lrg_buf_cb1 = ql_get_lbuf(qdev);
2063 skb1 = lrg_buf_cb1->skb;
2064 size = ETH_HLEN;
2065 if (*((u16 *) skb1->data) != 0xFFFF)
2066 size += VLAN_ETH_HLEN - ETH_HLEN;
2067 }
2068
2069 /* start of second buffer */
2070 lrg_buf_cb2 = ql_get_lbuf(qdev);
2071 skb2 = lrg_buf_cb2->skb;
2072
2073 skb_put(skb2, length); /* Just the second buffer length here. */
2074 pci_unmap_single(qdev->pdev,
2075 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2076 dma_unmap_len(lrg_buf_cb2, maplen),
2077 PCI_DMA_FROMDEVICE);
2078 prefetch(skb2->data);
2079
2080 skb_checksum_none_assert(skb2);
2081 if (qdev->device_id == QL3022_DEVICE_ID) {
2082 /*
2083 * Copy the ethhdr from first buffer to second. This
2084 * is necessary for 3022 IP completions.
2085 */
2086 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2087 skb_push(skb2, size), size);
2088 } else {
2089 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2090 if (checksum &
2091 (IB_IP_IOCB_RSP_3032_ICE |
2092 IB_IP_IOCB_RSP_3032_CE)) {
2093 netdev_err(ndev,
2094 "%s: Bad checksum for this %s packet, checksum = %x\n",
2095 __func__,
2096 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2097 "TCP" : "UDP"), checksum);
2098 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2099 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2100 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2101 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2102 }
2103 }
2104 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2105
2106 napi_gro_receive(&qdev->napi, skb2);
2107 ndev->stats.rx_packets++;
2108 ndev->stats.rx_bytes += length;
2109 lrg_buf_cb2->skb = NULL;
2110
2111 if (qdev->device_id == QL3022_DEVICE_ID)
2112 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2113 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2114}
2115
2116static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget)
2117{
2118 struct net_rsp_iocb *net_rsp;
2119 struct net_device *ndev = qdev->ndev;
2120 int work_done = 0;
2121
2122 /* While there are entries in the completion queue. */
2123 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2124 qdev->rsp_consumer_index) && (work_done < budget)) {
2125
2126 net_rsp = qdev->rsp_current;
2127 rmb();
2128 /*
2129 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2130 * if the inbound completion is for a VLAN.
2131 */
2132 if (qdev->device_id == QL3032_DEVICE_ID)
2133 net_rsp->opcode &= 0x7f;
2134 switch (net_rsp->opcode) {
2135
2136 case OPCODE_OB_MAC_IOCB_FN0:
2137 case OPCODE_OB_MAC_IOCB_FN2:
2138 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2139 net_rsp);
2140 break;
2141
2142 case OPCODE_IB_MAC_IOCB:
2143 case OPCODE_IB_3032_MAC_IOCB:
2144 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2145 net_rsp);
2146 work_done++;
2147 break;
2148
2149 case OPCODE_IB_IP_IOCB:
2150 case OPCODE_IB_3032_IP_IOCB:
2151 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2152 net_rsp);
2153 work_done++;
2154 break;
2155 default: {
2156 u32 *tmp = (u32 *)net_rsp;
2157 netdev_err(ndev,
2158 "Hit default case, not handled!\n"
2159 " dropping the packet, opcode = %x\n"
2160 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2161 net_rsp->opcode,
2162 (unsigned long int)tmp[0],
2163 (unsigned long int)tmp[1],
2164 (unsigned long int)tmp[2],
2165 (unsigned long int)tmp[3]);
2166 }
2167 }
2168
2169 qdev->rsp_consumer_index++;
2170
2171 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2172 qdev->rsp_consumer_index = 0;
2173 qdev->rsp_current = qdev->rsp_q_virt_addr;
2174 } else {
2175 qdev->rsp_current++;
2176 }
2177
2178 }
2179
2180 return work_done;
2181}
2182
2183static int ql_poll(struct napi_struct *napi, int budget)
2184{
2185 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2186 struct ql3xxx_port_registers __iomem *port_regs =
2187 qdev->mem_map_registers;
2188 int work_done;
2189
2190 work_done = ql_tx_rx_clean(qdev, budget);
2191
2192 if (work_done < budget && napi_complete_done(napi, work_done)) {
2193 unsigned long flags;
2194
2195 spin_lock_irqsave(&qdev->hw_lock, flags);
2196 ql_update_small_bufq_prod_index(qdev);
2197 ql_update_lrg_bufq_prod_index(qdev);
2198 writel(qdev->rsp_consumer_index,
2199 &port_regs->CommonRegs.rspQConsumerIndex);
2200 spin_unlock_irqrestore(&qdev->hw_lock, flags);
2201
2202 ql_enable_interrupts(qdev);
2203 }
2204 return work_done;
2205}
2206
2207static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2208{
2209
2210 struct net_device *ndev = dev_id;
2211 struct ql3_adapter *qdev = netdev_priv(ndev);
2212 struct ql3xxx_port_registers __iomem *port_regs =
2213 qdev->mem_map_registers;
2214 u32 value;
2215 int handled = 1;
2216 u32 var;
2217
2218 value = ql_read_common_reg_l(qdev,
2219 &port_regs->CommonRegs.ispControlStatus);
2220
2221 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2222 spin_lock(&qdev->adapter_lock);
2223 netif_stop_queue(qdev->ndev);
2224 netif_carrier_off(qdev->ndev);
2225 ql_disable_interrupts(qdev);
2226 qdev->port_link_state = LS_DOWN;
2227 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2228
2229 if (value & ISP_CONTROL_FE) {
2230 /*
2231 * Chip Fatal Error.
2232 */
2233 var =
2234 ql_read_page0_reg_l(qdev,
2235 &port_regs->PortFatalErrStatus);
2236 netdev_warn(ndev,
2237 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2238 var);
2239 set_bit(QL_RESET_START, &qdev->flags) ;
2240 } else {
2241 /*
2242 * Soft Reset Requested.
2243 */
2244 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2245 netdev_err(ndev,
2246 "Another function issued a reset to the chip. ISR value = %x\n",
2247 value);
2248 }
2249 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2250 spin_unlock(&qdev->adapter_lock);
2251 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2252 ql_disable_interrupts(qdev);
2253 if (likely(napi_schedule_prep(&qdev->napi)))
2254 __napi_schedule(&qdev->napi);
2255 } else
2256 return IRQ_NONE;
2257
2258 return IRQ_RETVAL(handled);
2259}
2260
2261/*
2262 * Get the total number of segments needed for the given number of fragments.
2263 * This is necessary because outbound address lists (OAL) will be used when
2264 * more than two frags are given. Each address list has 5 addr/len pairs.
2265 * The 5th pair in each OAL is used to point to the next OAL if more frags
2266 * are coming. That is why the frags:segment count ratio is not linear.
2267 */
2268static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2269{
2270 if (qdev->device_id == QL3022_DEVICE_ID)
2271 return 1;
2272
2273 if (frags <= 2)
2274 return frags + 1;
2275 else if (frags <= 6)
2276 return frags + 2;
2277 else if (frags <= 10)
2278 return frags + 3;
2279 else if (frags <= 14)
2280 return frags + 4;
2281 else if (frags <= 18)
2282 return frags + 5;
2283 return -1;
2284}
2285
2286static void ql_hw_csum_setup(const struct sk_buff *skb,
2287 struct ob_mac_iocb_req *mac_iocb_ptr)
2288{
2289 const struct iphdr *ip = ip_hdr(skb);
2290
2291 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2292 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2293
2294 if (ip->protocol == IPPROTO_TCP) {
2295 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2296 OB_3032MAC_IOCB_REQ_IC;
2297 } else {
2298 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2299 OB_3032MAC_IOCB_REQ_IC;
2300 }
2301
2302}
2303
2304/*
2305 * Map the buffers for this transmit.
2306 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2307 */
2308static int ql_send_map(struct ql3_adapter *qdev,
2309 struct ob_mac_iocb_req *mac_iocb_ptr,
2310 struct ql_tx_buf_cb *tx_cb,
2311 struct sk_buff *skb)
2312{
2313 struct oal *oal;
2314 struct oal_entry *oal_entry;
2315 int len = skb_headlen(skb);
2316 dma_addr_t map;
2317 int err;
2318 int completed_segs, i;
2319 int seg_cnt, seg = 0;
2320 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2321
2322 seg_cnt = tx_cb->seg_count;
2323 /*
2324 * Map the skb buffer first.
2325 */
2326 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2327
2328 err = pci_dma_mapping_error(qdev->pdev, map);
2329 if (err) {
2330 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2331 err);
2332
2333 return NETDEV_TX_BUSY;
2334 }
2335
2336 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2337 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2338 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2339 oal_entry->len = cpu_to_le32(len);
2340 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2341 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2342 seg++;
2343
2344 if (seg_cnt == 1) {
2345 /* Terminate the last segment. */
2346 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2347 return NETDEV_TX_OK;
2348 }
2349 oal = tx_cb->oal;
2350 for (completed_segs = 0;
2351 completed_segs < frag_cnt;
2352 completed_segs++, seg++) {
2353 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2354 oal_entry++;
2355 /*
2356 * Check for continuation requirements.
2357 * It's strange but necessary.
2358 * Continuation entry points to outbound address list.
2359 */
2360 if ((seg == 2 && seg_cnt > 3) ||
2361 (seg == 7 && seg_cnt > 8) ||
2362 (seg == 12 && seg_cnt > 13) ||
2363 (seg == 17 && seg_cnt > 18)) {
2364 map = pci_map_single(qdev->pdev, oal,
2365 sizeof(struct oal),
2366 PCI_DMA_TODEVICE);
2367
2368 err = pci_dma_mapping_error(qdev->pdev, map);
2369 if (err) {
2370 netdev_err(qdev->ndev,
2371 "PCI mapping outbound address list with error: %d\n",
2372 err);
2373 goto map_error;
2374 }
2375
2376 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2377 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2378 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2379 OAL_CONT_ENTRY);
2380 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2381 dma_unmap_len_set(&tx_cb->map[seg], maplen,
2382 sizeof(struct oal));
2383 oal_entry = (struct oal_entry *)oal;
2384 oal++;
2385 seg++;
2386 }
2387
2388 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2389 DMA_TO_DEVICE);
2390
2391 err = dma_mapping_error(&qdev->pdev->dev, map);
2392 if (err) {
2393 netdev_err(qdev->ndev,
2394 "PCI mapping frags failed with error: %d\n",
2395 err);
2396 goto map_error;
2397 }
2398
2399 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2400 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2401 oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2402 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2403 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2404 }
2405 /* Terminate the last segment. */
2406 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2407 return NETDEV_TX_OK;
2408
2409map_error:
2410 /* A PCI mapping failed and now we will need to back out
2411 * We need to traverse through the oal's and associated pages which
2412 * have been mapped and now we must unmap them to clean up properly
2413 */
2414
2415 seg = 1;
2416 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2417 oal = tx_cb->oal;
2418 for (i = 0; i < completed_segs; i++, seg++) {
2419 oal_entry++;
2420
2421 /*
2422 * Check for continuation requirements.
2423 * It's strange but necessary.
2424 */
2425
2426 if ((seg == 2 && seg_cnt > 3) ||
2427 (seg == 7 && seg_cnt > 8) ||
2428 (seg == 12 && seg_cnt > 13) ||
2429 (seg == 17 && seg_cnt > 18)) {
2430 pci_unmap_single(qdev->pdev,
2431 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2432 dma_unmap_len(&tx_cb->map[seg], maplen),
2433 PCI_DMA_TODEVICE);
2434 oal++;
2435 seg++;
2436 }
2437
2438 pci_unmap_page(qdev->pdev,
2439 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2440 dma_unmap_len(&tx_cb->map[seg], maplen),
2441 PCI_DMA_TODEVICE);
2442 }
2443
2444 pci_unmap_single(qdev->pdev,
2445 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2446 dma_unmap_addr(&tx_cb->map[0], maplen),
2447 PCI_DMA_TODEVICE);
2448
2449 return NETDEV_TX_BUSY;
2450
2451}
2452
2453/*
2454 * The difference between 3022 and 3032 sends:
2455 * 3022 only supports a simple single segment transmission.
2456 * 3032 supports checksumming and scatter/gather lists (fragments).
2457 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2458 * in the IOCB plus a chain of outbound address lists (OAL) that
2459 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2460 * will be used to point to an OAL when more ALP entries are required.
2461 * The IOCB is always the top of the chain followed by one or more
2462 * OALs (when necessary).
2463 */
2464static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2465 struct net_device *ndev)
2466{
2467 struct ql3_adapter *qdev = netdev_priv(ndev);
2468 struct ql3xxx_port_registers __iomem *port_regs =
2469 qdev->mem_map_registers;
2470 struct ql_tx_buf_cb *tx_cb;
2471 u32 tot_len = skb->len;
2472 struct ob_mac_iocb_req *mac_iocb_ptr;
2473
2474 if (unlikely(atomic_read(&qdev->tx_count) < 2))
2475 return NETDEV_TX_BUSY;
2476
2477 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2478 tx_cb->seg_count = ql_get_seg_count(qdev,
2479 skb_shinfo(skb)->nr_frags);
2480 if (tx_cb->seg_count == -1) {
2481 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2482 return NETDEV_TX_OK;
2483 }
2484
2485 mac_iocb_ptr = tx_cb->queue_entry;
2486 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2487 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2488 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2489 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2490 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2491 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2492 tx_cb->skb = skb;
2493 if (qdev->device_id == QL3032_DEVICE_ID &&
2494 skb->ip_summed == CHECKSUM_PARTIAL)
2495 ql_hw_csum_setup(skb, mac_iocb_ptr);
2496
2497 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2498 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2499 return NETDEV_TX_BUSY;
2500 }
2501
2502 wmb();
2503 qdev->req_producer_index++;
2504 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2505 qdev->req_producer_index = 0;
2506 wmb();
2507 ql_write_common_reg_l(qdev,
2508 &port_regs->CommonRegs.reqQProducerIndex,
2509 qdev->req_producer_index);
2510
2511 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2512 "tx queued, slot %d, len %d\n",
2513 qdev->req_producer_index, skb->len);
2514
2515 atomic_dec(&qdev->tx_count);
2516 return NETDEV_TX_OK;
2517}
2518
2519static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2520{
2521 qdev->req_q_size =
2522 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2523
2524 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2525
2526 /* The barrier is required to ensure request and response queue
2527 * addr writes to the registers.
2528 */
2529 wmb();
2530
2531 qdev->req_q_virt_addr =
2532 pci_alloc_consistent(qdev->pdev,
2533 (size_t) qdev->req_q_size,
2534 &qdev->req_q_phy_addr);
2535
2536 if ((qdev->req_q_virt_addr == NULL) ||
2537 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2538 netdev_err(qdev->ndev, "reqQ failed\n");
2539 return -ENOMEM;
2540 }
2541
2542 qdev->rsp_q_virt_addr =
2543 pci_alloc_consistent(qdev->pdev,
2544 (size_t) qdev->rsp_q_size,
2545 &qdev->rsp_q_phy_addr);
2546
2547 if ((qdev->rsp_q_virt_addr == NULL) ||
2548 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2549 netdev_err(qdev->ndev, "rspQ allocation failed\n");
2550 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2551 qdev->req_q_virt_addr,
2552 qdev->req_q_phy_addr);
2553 return -ENOMEM;
2554 }
2555
2556 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2557
2558 return 0;
2559}
2560
2561static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2562{
2563 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2564 netdev_info(qdev->ndev, "Already done\n");
2565 return;
2566 }
2567
2568 pci_free_consistent(qdev->pdev,
2569 qdev->req_q_size,
2570 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2571
2572 qdev->req_q_virt_addr = NULL;
2573
2574 pci_free_consistent(qdev->pdev,
2575 qdev->rsp_q_size,
2576 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2577
2578 qdev->rsp_q_virt_addr = NULL;
2579
2580 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2581}
2582
2583static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2584{
2585 /* Create Large Buffer Queue */
2586 qdev->lrg_buf_q_size =
2587 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2588 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2589 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2590 else
2591 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2592
2593 qdev->lrg_buf = kmalloc_array(qdev->num_large_buffers,
2594 sizeof(struct ql_rcv_buf_cb),
2595 GFP_KERNEL);
2596 if (qdev->lrg_buf == NULL)
2597 return -ENOMEM;
2598
2599 qdev->lrg_buf_q_alloc_virt_addr =
2600 pci_alloc_consistent(qdev->pdev,
2601 qdev->lrg_buf_q_alloc_size,
2602 &qdev->lrg_buf_q_alloc_phy_addr);
2603
2604 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2605 netdev_err(qdev->ndev, "lBufQ failed\n");
2606 return -ENOMEM;
2607 }
2608 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2609 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2610
2611 /* Create Small Buffer Queue */
2612 qdev->small_buf_q_size =
2613 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2614 if (qdev->small_buf_q_size < PAGE_SIZE)
2615 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2616 else
2617 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2618
2619 qdev->small_buf_q_alloc_virt_addr =
2620 pci_alloc_consistent(qdev->pdev,
2621 qdev->small_buf_q_alloc_size,
2622 &qdev->small_buf_q_alloc_phy_addr);
2623
2624 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2625 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2626 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2627 qdev->lrg_buf_q_alloc_virt_addr,
2628 qdev->lrg_buf_q_alloc_phy_addr);
2629 return -ENOMEM;
2630 }
2631
2632 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2633 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2634 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2635 return 0;
2636}
2637
2638static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2639{
2640 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2641 netdev_info(qdev->ndev, "Already done\n");
2642 return;
2643 }
2644 kfree(qdev->lrg_buf);
2645 pci_free_consistent(qdev->pdev,
2646 qdev->lrg_buf_q_alloc_size,
2647 qdev->lrg_buf_q_alloc_virt_addr,
2648 qdev->lrg_buf_q_alloc_phy_addr);
2649
2650 qdev->lrg_buf_q_virt_addr = NULL;
2651
2652 pci_free_consistent(qdev->pdev,
2653 qdev->small_buf_q_alloc_size,
2654 qdev->small_buf_q_alloc_virt_addr,
2655 qdev->small_buf_q_alloc_phy_addr);
2656
2657 qdev->small_buf_q_virt_addr = NULL;
2658
2659 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2660}
2661
2662static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2663{
2664 int i;
2665 struct bufq_addr_element *small_buf_q_entry;
2666
2667 /* Currently we allocate on one of memory and use it for smallbuffers */
2668 qdev->small_buf_total_size =
2669 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2670 QL_SMALL_BUFFER_SIZE);
2671
2672 qdev->small_buf_virt_addr =
2673 pci_alloc_consistent(qdev->pdev,
2674 qdev->small_buf_total_size,
2675 &qdev->small_buf_phy_addr);
2676
2677 if (qdev->small_buf_virt_addr == NULL) {
2678 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2679 return -ENOMEM;
2680 }
2681
2682 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2683 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2684
2685 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2686
2687 /* Initialize the small buffer queue. */
2688 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2689 small_buf_q_entry->addr_high =
2690 cpu_to_le32(qdev->small_buf_phy_addr_high);
2691 small_buf_q_entry->addr_low =
2692 cpu_to_le32(qdev->small_buf_phy_addr_low +
2693 (i * QL_SMALL_BUFFER_SIZE));
2694 small_buf_q_entry++;
2695 }
2696 qdev->small_buf_index = 0;
2697 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2698 return 0;
2699}
2700
2701static void ql_free_small_buffers(struct ql3_adapter *qdev)
2702{
2703 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2704 netdev_info(qdev->ndev, "Already done\n");
2705 return;
2706 }
2707 if (qdev->small_buf_virt_addr != NULL) {
2708 pci_free_consistent(qdev->pdev,
2709 qdev->small_buf_total_size,
2710 qdev->small_buf_virt_addr,
2711 qdev->small_buf_phy_addr);
2712
2713 qdev->small_buf_virt_addr = NULL;
2714 }
2715}
2716
2717static void ql_free_large_buffers(struct ql3_adapter *qdev)
2718{
2719 int i = 0;
2720 struct ql_rcv_buf_cb *lrg_buf_cb;
2721
2722 for (i = 0; i < qdev->num_large_buffers; i++) {
2723 lrg_buf_cb = &qdev->lrg_buf[i];
2724 if (lrg_buf_cb->skb) {
2725 dev_kfree_skb(lrg_buf_cb->skb);
2726 pci_unmap_single(qdev->pdev,
2727 dma_unmap_addr(lrg_buf_cb, mapaddr),
2728 dma_unmap_len(lrg_buf_cb, maplen),
2729 PCI_DMA_FROMDEVICE);
2730 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2731 } else {
2732 break;
2733 }
2734 }
2735}
2736
2737static void ql_init_large_buffers(struct ql3_adapter *qdev)
2738{
2739 int i;
2740 struct ql_rcv_buf_cb *lrg_buf_cb;
2741 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2742
2743 for (i = 0; i < qdev->num_large_buffers; i++) {
2744 lrg_buf_cb = &qdev->lrg_buf[i];
2745 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2746 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2747 buf_addr_ele++;
2748 }
2749 qdev->lrg_buf_index = 0;
2750 qdev->lrg_buf_skb_check = 0;
2751}
2752
2753static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2754{
2755 int i;
2756 struct ql_rcv_buf_cb *lrg_buf_cb;
2757 struct sk_buff *skb;
2758 dma_addr_t map;
2759 int err;
2760
2761 for (i = 0; i < qdev->num_large_buffers; i++) {
2762 skb = netdev_alloc_skb(qdev->ndev,
2763 qdev->lrg_buffer_len);
2764 if (unlikely(!skb)) {
2765 /* Better luck next round */
2766 netdev_err(qdev->ndev,
2767 "large buff alloc failed for %d bytes at index %d\n",
2768 qdev->lrg_buffer_len * 2, i);
2769 ql_free_large_buffers(qdev);
2770 return -ENOMEM;
2771 } else {
2772
2773 lrg_buf_cb = &qdev->lrg_buf[i];
2774 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2775 lrg_buf_cb->index = i;
2776 lrg_buf_cb->skb = skb;
2777 /*
2778 * We save some space to copy the ethhdr from first
2779 * buffer
2780 */
2781 skb_reserve(skb, QL_HEADER_SPACE);
2782 map = pci_map_single(qdev->pdev,
2783 skb->data,
2784 qdev->lrg_buffer_len -
2785 QL_HEADER_SPACE,
2786 PCI_DMA_FROMDEVICE);
2787
2788 err = pci_dma_mapping_error(qdev->pdev, map);
2789 if (err) {
2790 netdev_err(qdev->ndev,
2791 "PCI mapping failed with error: %d\n",
2792 err);
2793 ql_free_large_buffers(qdev);
2794 return -ENOMEM;
2795 }
2796
2797 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2798 dma_unmap_len_set(lrg_buf_cb, maplen,
2799 qdev->lrg_buffer_len -
2800 QL_HEADER_SPACE);
2801 lrg_buf_cb->buf_phy_addr_low =
2802 cpu_to_le32(LS_64BITS(map));
2803 lrg_buf_cb->buf_phy_addr_high =
2804 cpu_to_le32(MS_64BITS(map));
2805 }
2806 }
2807 return 0;
2808}
2809
2810static void ql_free_send_free_list(struct ql3_adapter *qdev)
2811{
2812 struct ql_tx_buf_cb *tx_cb;
2813 int i;
2814
2815 tx_cb = &qdev->tx_buf[0];
2816 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2817 kfree(tx_cb->oal);
2818 tx_cb->oal = NULL;
2819 tx_cb++;
2820 }
2821}
2822
2823static int ql_create_send_free_list(struct ql3_adapter *qdev)
2824{
2825 struct ql_tx_buf_cb *tx_cb;
2826 int i;
2827 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2828
2829 /* Create free list of transmit buffers */
2830 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2831
2832 tx_cb = &qdev->tx_buf[i];
2833 tx_cb->skb = NULL;
2834 tx_cb->queue_entry = req_q_curr;
2835 req_q_curr++;
2836 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2837 if (tx_cb->oal == NULL)
2838 return -ENOMEM;
2839 }
2840 return 0;
2841}
2842
2843static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2844{
2845 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2846 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2847 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2848 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2849 /*
2850 * Bigger buffers, so less of them.
2851 */
2852 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2853 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2854 } else {
2855 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2856 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2857 return -ENOMEM;
2858 }
2859 qdev->num_large_buffers =
2860 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2861 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2862 qdev->max_frame_size =
2863 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2864
2865 /*
2866 * First allocate a page of shared memory and use it for shadow
2867 * locations of Network Request Queue Consumer Address Register and
2868 * Network Completion Queue Producer Index Register
2869 */
2870 qdev->shadow_reg_virt_addr =
2871 pci_alloc_consistent(qdev->pdev,
2872 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2873
2874 if (qdev->shadow_reg_virt_addr != NULL) {
2875 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2876 qdev->req_consumer_index_phy_addr_high =
2877 MS_64BITS(qdev->shadow_reg_phy_addr);
2878 qdev->req_consumer_index_phy_addr_low =
2879 LS_64BITS(qdev->shadow_reg_phy_addr);
2880
2881 qdev->prsp_producer_index =
2882 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2883 qdev->rsp_producer_index_phy_addr_high =
2884 qdev->req_consumer_index_phy_addr_high;
2885 qdev->rsp_producer_index_phy_addr_low =
2886 qdev->req_consumer_index_phy_addr_low + 8;
2887 } else {
2888 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2889 return -ENOMEM;
2890 }
2891
2892 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2893 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2894 goto err_req_rsp;
2895 }
2896
2897 if (ql_alloc_buffer_queues(qdev) != 0) {
2898 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2899 goto err_buffer_queues;
2900 }
2901
2902 if (ql_alloc_small_buffers(qdev) != 0) {
2903 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2904 goto err_small_buffers;
2905 }
2906
2907 if (ql_alloc_large_buffers(qdev) != 0) {
2908 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2909 goto err_small_buffers;
2910 }
2911
2912 /* Initialize the large buffer queue. */
2913 ql_init_large_buffers(qdev);
2914 if (ql_create_send_free_list(qdev))
2915 goto err_free_list;
2916
2917 qdev->rsp_current = qdev->rsp_q_virt_addr;
2918
2919 return 0;
2920err_free_list:
2921 ql_free_send_free_list(qdev);
2922err_small_buffers:
2923 ql_free_buffer_queues(qdev);
2924err_buffer_queues:
2925 ql_free_net_req_rsp_queues(qdev);
2926err_req_rsp:
2927 pci_free_consistent(qdev->pdev,
2928 PAGE_SIZE,
2929 qdev->shadow_reg_virt_addr,
2930 qdev->shadow_reg_phy_addr);
2931
2932 return -ENOMEM;
2933}
2934
2935static void ql_free_mem_resources(struct ql3_adapter *qdev)
2936{
2937 ql_free_send_free_list(qdev);
2938 ql_free_large_buffers(qdev);
2939 ql_free_small_buffers(qdev);
2940 ql_free_buffer_queues(qdev);
2941 ql_free_net_req_rsp_queues(qdev);
2942 if (qdev->shadow_reg_virt_addr != NULL) {
2943 pci_free_consistent(qdev->pdev,
2944 PAGE_SIZE,
2945 qdev->shadow_reg_virt_addr,
2946 qdev->shadow_reg_phy_addr);
2947 qdev->shadow_reg_virt_addr = NULL;
2948 }
2949}
2950
2951static int ql_init_misc_registers(struct ql3_adapter *qdev)
2952{
2953 struct ql3xxx_local_ram_registers __iomem *local_ram =
2954 (void __iomem *)qdev->mem_map_registers;
2955
2956 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2957 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2958 2) << 4))
2959 return -1;
2960
2961 ql_write_page2_reg(qdev,
2962 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2963
2964 ql_write_page2_reg(qdev,
2965 &local_ram->maxBufletCount,
2966 qdev->nvram_data.bufletCount);
2967
2968 ql_write_page2_reg(qdev,
2969 &local_ram->freeBufletThresholdLow,
2970 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2971 (qdev->nvram_data.tcpWindowThreshold0));
2972
2973 ql_write_page2_reg(qdev,
2974 &local_ram->freeBufletThresholdHigh,
2975 qdev->nvram_data.tcpWindowThreshold50);
2976
2977 ql_write_page2_reg(qdev,
2978 &local_ram->ipHashTableBase,
2979 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2980 qdev->nvram_data.ipHashTableBaseLo);
2981 ql_write_page2_reg(qdev,
2982 &local_ram->ipHashTableCount,
2983 qdev->nvram_data.ipHashTableSize);
2984 ql_write_page2_reg(qdev,
2985 &local_ram->tcpHashTableBase,
2986 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2987 qdev->nvram_data.tcpHashTableBaseLo);
2988 ql_write_page2_reg(qdev,
2989 &local_ram->tcpHashTableCount,
2990 qdev->nvram_data.tcpHashTableSize);
2991 ql_write_page2_reg(qdev,
2992 &local_ram->ncbBase,
2993 (qdev->nvram_data.ncbTableBaseHi << 16) |
2994 qdev->nvram_data.ncbTableBaseLo);
2995 ql_write_page2_reg(qdev,
2996 &local_ram->maxNcbCount,
2997 qdev->nvram_data.ncbTableSize);
2998 ql_write_page2_reg(qdev,
2999 &local_ram->drbBase,
3000 (qdev->nvram_data.drbTableBaseHi << 16) |
3001 qdev->nvram_data.drbTableBaseLo);
3002 ql_write_page2_reg(qdev,
3003 &local_ram->maxDrbCount,
3004 qdev->nvram_data.drbTableSize);
3005 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3006 return 0;
3007}
3008
3009static int ql_adapter_initialize(struct ql3_adapter *qdev)
3010{
3011 u32 value;
3012 struct ql3xxx_port_registers __iomem *port_regs =
3013 qdev->mem_map_registers;
3014 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3015 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3016 (void __iomem *)port_regs;
3017 u32 delay = 10;
3018 int status = 0;
3019
3020 if (ql_mii_setup(qdev))
3021 return -1;
3022
3023 /* Bring out PHY out of reset */
3024 ql_write_common_reg(qdev, spir,
3025 (ISP_SERIAL_PORT_IF_WE |
3026 (ISP_SERIAL_PORT_IF_WE << 16)));
3027 /* Give the PHY time to come out of reset. */
3028 mdelay(100);
3029 qdev->port_link_state = LS_DOWN;
3030 netif_carrier_off(qdev->ndev);
3031
3032 /* V2 chip fix for ARS-39168. */
3033 ql_write_common_reg(qdev, spir,
3034 (ISP_SERIAL_PORT_IF_SDE |
3035 (ISP_SERIAL_PORT_IF_SDE << 16)));
3036
3037 /* Request Queue Registers */
3038 *((u32 *)(qdev->preq_consumer_index)) = 0;
3039 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3040 qdev->req_producer_index = 0;
3041
3042 ql_write_page1_reg(qdev,
3043 &hmem_regs->reqConsumerIndexAddrHigh,
3044 qdev->req_consumer_index_phy_addr_high);
3045 ql_write_page1_reg(qdev,
3046 &hmem_regs->reqConsumerIndexAddrLow,
3047 qdev->req_consumer_index_phy_addr_low);
3048
3049 ql_write_page1_reg(qdev,
3050 &hmem_regs->reqBaseAddrHigh,
3051 MS_64BITS(qdev->req_q_phy_addr));
3052 ql_write_page1_reg(qdev,
3053 &hmem_regs->reqBaseAddrLow,
3054 LS_64BITS(qdev->req_q_phy_addr));
3055 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3056
3057 /* Response Queue Registers */
3058 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3059 qdev->rsp_consumer_index = 0;
3060 qdev->rsp_current = qdev->rsp_q_virt_addr;
3061
3062 ql_write_page1_reg(qdev,
3063 &hmem_regs->rspProducerIndexAddrHigh,
3064 qdev->rsp_producer_index_phy_addr_high);
3065
3066 ql_write_page1_reg(qdev,
3067 &hmem_regs->rspProducerIndexAddrLow,
3068 qdev->rsp_producer_index_phy_addr_low);
3069
3070 ql_write_page1_reg(qdev,
3071 &hmem_regs->rspBaseAddrHigh,
3072 MS_64BITS(qdev->rsp_q_phy_addr));
3073
3074 ql_write_page1_reg(qdev,
3075 &hmem_regs->rspBaseAddrLow,
3076 LS_64BITS(qdev->rsp_q_phy_addr));
3077
3078 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3079
3080 /* Large Buffer Queue */
3081 ql_write_page1_reg(qdev,
3082 &hmem_regs->rxLargeQBaseAddrHigh,
3083 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3084
3085 ql_write_page1_reg(qdev,
3086 &hmem_regs->rxLargeQBaseAddrLow,
3087 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3088
3089 ql_write_page1_reg(qdev,
3090 &hmem_regs->rxLargeQLength,
3091 qdev->num_lbufq_entries);
3092
3093 ql_write_page1_reg(qdev,
3094 &hmem_regs->rxLargeBufferLength,
3095 qdev->lrg_buffer_len);
3096
3097 /* Small Buffer Queue */
3098 ql_write_page1_reg(qdev,
3099 &hmem_regs->rxSmallQBaseAddrHigh,
3100 MS_64BITS(qdev->small_buf_q_phy_addr));
3101
3102 ql_write_page1_reg(qdev,
3103 &hmem_regs->rxSmallQBaseAddrLow,
3104 LS_64BITS(qdev->small_buf_q_phy_addr));
3105
3106 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3107 ql_write_page1_reg(qdev,
3108 &hmem_regs->rxSmallBufferLength,
3109 QL_SMALL_BUFFER_SIZE);
3110
3111 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3112 qdev->small_buf_release_cnt = 8;
3113 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3114 qdev->lrg_buf_release_cnt = 8;
3115 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3116 qdev->small_buf_index = 0;
3117 qdev->lrg_buf_index = 0;
3118 qdev->lrg_buf_free_count = 0;
3119 qdev->lrg_buf_free_head = NULL;
3120 qdev->lrg_buf_free_tail = NULL;
3121
3122 ql_write_common_reg(qdev,
3123 &port_regs->CommonRegs.
3124 rxSmallQProducerIndex,
3125 qdev->small_buf_q_producer_index);
3126 ql_write_common_reg(qdev,
3127 &port_regs->CommonRegs.
3128 rxLargeQProducerIndex,
3129 qdev->lrg_buf_q_producer_index);
3130
3131 /*
3132 * Find out if the chip has already been initialized. If it has, then
3133 * we skip some of the initialization.
3134 */
3135 clear_bit(QL_LINK_MASTER, &qdev->flags);
3136 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3137 if ((value & PORT_STATUS_IC) == 0) {
3138
3139 /* Chip has not been configured yet, so let it rip. */
3140 if (ql_init_misc_registers(qdev)) {
3141 status = -1;
3142 goto out;
3143 }
3144
3145 value = qdev->nvram_data.tcpMaxWindowSize;
3146 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3147
3148 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3149
3150 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3151 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3152 * 2) << 13)) {
3153 status = -1;
3154 goto out;
3155 }
3156 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3157 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3158 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3159 16) | (INTERNAL_CHIP_SD |
3160 INTERNAL_CHIP_WE)));
3161 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3162 }
3163
3164 if (qdev->mac_index)
3165 ql_write_page0_reg(qdev,
3166 &port_regs->mac1MaxFrameLengthReg,
3167 qdev->max_frame_size);
3168 else
3169 ql_write_page0_reg(qdev,
3170 &port_regs->mac0MaxFrameLengthReg,
3171 qdev->max_frame_size);
3172
3173 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3174 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3175 2) << 7)) {
3176 status = -1;
3177 goto out;
3178 }
3179
3180 PHY_Setup(qdev);
3181 ql_init_scan_mode(qdev);
3182 ql_get_phy_owner(qdev);
3183
3184 /* Load the MAC Configuration */
3185
3186 /* Program lower 32 bits of the MAC address */
3187 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3188 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3189 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3190 ((qdev->ndev->dev_addr[2] << 24)
3191 | (qdev->ndev->dev_addr[3] << 16)
3192 | (qdev->ndev->dev_addr[4] << 8)
3193 | qdev->ndev->dev_addr[5]));
3194
3195 /* Program top 16 bits of the MAC address */
3196 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3197 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3198 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3199 ((qdev->ndev->dev_addr[0] << 8)
3200 | qdev->ndev->dev_addr[1]));
3201
3202 /* Enable Primary MAC */
3203 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3204 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3205 MAC_ADDR_INDIRECT_PTR_REG_PE));
3206
3207 /* Clear Primary and Secondary IP addresses */
3208 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3209 ((IP_ADDR_INDEX_REG_MASK << 16) |
3210 (qdev->mac_index << 2)));
3211 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3212
3213 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3214 ((IP_ADDR_INDEX_REG_MASK << 16) |
3215 ((qdev->mac_index << 2) + 1)));
3216 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3217
3218 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3219
3220 /* Indicate Configuration Complete */
3221 ql_write_page0_reg(qdev,
3222 &port_regs->portControl,
3223 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3224
3225 do {
3226 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3227 if (value & PORT_STATUS_IC)
3228 break;
3229 spin_unlock_irq(&qdev->hw_lock);
3230 msleep(500);
3231 spin_lock_irq(&qdev->hw_lock);
3232 } while (--delay);
3233
3234 if (delay == 0) {
3235 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3236 status = -1;
3237 goto out;
3238 }
3239
3240 /* Enable Ethernet Function */
3241 if (qdev->device_id == QL3032_DEVICE_ID) {
3242 value =
3243 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3244 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3245 QL3032_PORT_CONTROL_ET);
3246 ql_write_page0_reg(qdev, &port_regs->functionControl,
3247 ((value << 16) | value));
3248 } else {
3249 value =
3250 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3251 PORT_CONTROL_HH);
3252 ql_write_page0_reg(qdev, &port_regs->portControl,
3253 ((value << 16) | value));
3254 }
3255
3256
3257out:
3258 return status;
3259}
3260
3261/*
3262 * Caller holds hw_lock.
3263 */
3264static int ql_adapter_reset(struct ql3_adapter *qdev)
3265{
3266 struct ql3xxx_port_registers __iomem *port_regs =
3267 qdev->mem_map_registers;
3268 int status = 0;
3269 u16 value;
3270 int max_wait_time;
3271
3272 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3273 clear_bit(QL_RESET_DONE, &qdev->flags);
3274
3275 /*
3276 * Issue soft reset to chip.
3277 */
3278 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3279 ql_write_common_reg(qdev,
3280 &port_regs->CommonRegs.ispControlStatus,
3281 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3282
3283 /* Wait 3 seconds for reset to complete. */
3284 netdev_printk(KERN_DEBUG, qdev->ndev,
3285 "Wait 10 milliseconds for reset to complete\n");
3286
3287 /* Wait until the firmware tells us the Soft Reset is done */
3288 max_wait_time = 5;
3289 do {
3290 value =
3291 ql_read_common_reg(qdev,
3292 &port_regs->CommonRegs.ispControlStatus);
3293 if ((value & ISP_CONTROL_SR) == 0)
3294 break;
3295
3296 ssleep(1);
3297 } while ((--max_wait_time));
3298
3299 /*
3300 * Also, make sure that the Network Reset Interrupt bit has been
3301 * cleared after the soft reset has taken place.
3302 */
3303 value =
3304 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3305 if (value & ISP_CONTROL_RI) {
3306 netdev_printk(KERN_DEBUG, qdev->ndev,
3307 "clearing RI after reset\n");
3308 ql_write_common_reg(qdev,
3309 &port_regs->CommonRegs.
3310 ispControlStatus,
3311 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3312 }
3313
3314 if (max_wait_time == 0) {
3315 /* Issue Force Soft Reset */
3316 ql_write_common_reg(qdev,
3317 &port_regs->CommonRegs.
3318 ispControlStatus,
3319 ((ISP_CONTROL_FSR << 16) |
3320 ISP_CONTROL_FSR));
3321 /*
3322 * Wait until the firmware tells us the Force Soft Reset is
3323 * done
3324 */
3325 max_wait_time = 5;
3326 do {
3327 value = ql_read_common_reg(qdev,
3328 &port_regs->CommonRegs.
3329 ispControlStatus);
3330 if ((value & ISP_CONTROL_FSR) == 0)
3331 break;
3332 ssleep(1);
3333 } while ((--max_wait_time));
3334 }
3335 if (max_wait_time == 0)
3336 status = 1;
3337
3338 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3339 set_bit(QL_RESET_DONE, &qdev->flags);
3340 return status;
3341}
3342
3343static void ql_set_mac_info(struct ql3_adapter *qdev)
3344{
3345 struct ql3xxx_port_registers __iomem *port_regs =
3346 qdev->mem_map_registers;
3347 u32 value, port_status;
3348 u8 func_number;
3349
3350 /* Get the function number */
3351 value =
3352 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3353 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3354 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3355 switch (value & ISP_CONTROL_FN_MASK) {
3356 case ISP_CONTROL_FN0_NET:
3357 qdev->mac_index = 0;
3358 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3359 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3360 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3361 if (port_status & PORT_STATUS_SM0)
3362 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3363 else
3364 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3365 break;
3366
3367 case ISP_CONTROL_FN1_NET:
3368 qdev->mac_index = 1;
3369 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3370 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3371 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3372 if (port_status & PORT_STATUS_SM1)
3373 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3374 else
3375 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3376 break;
3377
3378 case ISP_CONTROL_FN0_SCSI:
3379 case ISP_CONTROL_FN1_SCSI:
3380 default:
3381 netdev_printk(KERN_DEBUG, qdev->ndev,
3382 "Invalid function number, ispControlStatus = 0x%x\n",
3383 value);
3384 break;
3385 }
3386 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3387}
3388
3389static void ql_display_dev_info(struct net_device *ndev)
3390{
3391 struct ql3_adapter *qdev = netdev_priv(ndev);
3392 struct pci_dev *pdev = qdev->pdev;
3393
3394 netdev_info(ndev,
3395 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3396 DRV_NAME, qdev->index, qdev->chip_rev_id,
3397 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3398 qdev->pci_slot);
3399 netdev_info(ndev, "%s Interface\n",
3400 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3401
3402 /*
3403 * Print PCI bus width/type.
3404 */
3405 netdev_info(ndev, "Bus interface is %s %s\n",
3406 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3407 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3408
3409 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3410 qdev->mem_map_registers);
3411 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3412
3413 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3414}
3415
3416static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3417{
3418 struct net_device *ndev = qdev->ndev;
3419 int retval = 0;
3420
3421 netif_stop_queue(ndev);
3422 netif_carrier_off(ndev);
3423
3424 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3425 clear_bit(QL_LINK_MASTER, &qdev->flags);
3426
3427 ql_disable_interrupts(qdev);
3428
3429 free_irq(qdev->pdev->irq, ndev);
3430
3431 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3432 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3433 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3434 pci_disable_msi(qdev->pdev);
3435 }
3436
3437 del_timer_sync(&qdev->adapter_timer);
3438
3439 napi_disable(&qdev->napi);
3440
3441 if (do_reset) {
3442 int soft_reset;
3443 unsigned long hw_flags;
3444
3445 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3446 if (ql_wait_for_drvr_lock(qdev)) {
3447 soft_reset = ql_adapter_reset(qdev);
3448 if (soft_reset) {
3449 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3450 qdev->index);
3451 }
3452 netdev_err(ndev,
3453 "Releasing driver lock via chip reset\n");
3454 } else {
3455 netdev_err(ndev,
3456 "Could not acquire driver lock to do reset!\n");
3457 retval = -1;
3458 }
3459 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3460 }
3461 ql_free_mem_resources(qdev);
3462 return retval;
3463}
3464
3465static int ql_adapter_up(struct ql3_adapter *qdev)
3466{
3467 struct net_device *ndev = qdev->ndev;
3468 int err;
3469 unsigned long irq_flags = IRQF_SHARED;
3470 unsigned long hw_flags;
3471
3472 if (ql_alloc_mem_resources(qdev)) {
3473 netdev_err(ndev, "Unable to allocate buffers\n");
3474 return -ENOMEM;
3475 }
3476
3477 if (qdev->msi) {
3478 if (pci_enable_msi(qdev->pdev)) {
3479 netdev_err(ndev,
3480 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3481 qdev->msi = 0;
3482 } else {
3483 netdev_info(ndev, "MSI Enabled...\n");
3484 set_bit(QL_MSI_ENABLED, &qdev->flags);
3485 irq_flags &= ~IRQF_SHARED;
3486 }
3487 }
3488
3489 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3490 irq_flags, ndev->name, ndev);
3491 if (err) {
3492 netdev_err(ndev,
3493 "Failed to reserve interrupt %d - already in use\n",
3494 qdev->pdev->irq);
3495 goto err_irq;
3496 }
3497
3498 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3499
3500 err = ql_wait_for_drvr_lock(qdev);
3501 if (err) {
3502 err = ql_adapter_initialize(qdev);
3503 if (err) {
3504 netdev_err(ndev, "Unable to initialize adapter\n");
3505 goto err_init;
3506 }
3507 netdev_err(ndev, "Releasing driver lock\n");
3508 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3509 } else {
3510 netdev_err(ndev, "Could not acquire driver lock\n");
3511 goto err_lock;
3512 }
3513
3514 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3515
3516 set_bit(QL_ADAPTER_UP, &qdev->flags);
3517
3518 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3519
3520 napi_enable(&qdev->napi);
3521 ql_enable_interrupts(qdev);
3522 return 0;
3523
3524err_init:
3525 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3526err_lock:
3527 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3528 free_irq(qdev->pdev->irq, ndev);
3529err_irq:
3530 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3531 netdev_info(ndev, "calling pci_disable_msi()\n");
3532 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3533 pci_disable_msi(qdev->pdev);
3534 }
3535 return err;
3536}
3537
3538static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3539{
3540 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3541 netdev_err(qdev->ndev,
3542 "Driver up/down cycle failed, closing device\n");
3543 rtnl_lock();
3544 dev_close(qdev->ndev);
3545 rtnl_unlock();
3546 return -1;
3547 }
3548 return 0;
3549}
3550
3551static int ql3xxx_close(struct net_device *ndev)
3552{
3553 struct ql3_adapter *qdev = netdev_priv(ndev);
3554
3555 /*
3556 * Wait for device to recover from a reset.
3557 * (Rarely happens, but possible.)
3558 */
3559 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3560 msleep(50);
3561
3562 ql_adapter_down(qdev, QL_DO_RESET);
3563 return 0;
3564}
3565
3566static int ql3xxx_open(struct net_device *ndev)
3567{
3568 struct ql3_adapter *qdev = netdev_priv(ndev);
3569 return ql_adapter_up(qdev);
3570}
3571
3572static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3573{
3574 struct ql3_adapter *qdev = netdev_priv(ndev);
3575 struct ql3xxx_port_registers __iomem *port_regs =
3576 qdev->mem_map_registers;
3577 struct sockaddr *addr = p;
3578 unsigned long hw_flags;
3579
3580 if (netif_running(ndev))
3581 return -EBUSY;
3582
3583 if (!is_valid_ether_addr(addr->sa_data))
3584 return -EADDRNOTAVAIL;
3585
3586 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3587
3588 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3589 /* Program lower 32 bits of the MAC address */
3590 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3591 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3592 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3593 ((ndev->dev_addr[2] << 24) | (ndev->
3594 dev_addr[3] << 16) |
3595 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3596
3597 /* Program top 16 bits of the MAC address */
3598 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3599 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3600 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3601 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3602 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3603
3604 return 0;
3605}
3606
3607static void ql3xxx_tx_timeout(struct net_device *ndev)
3608{
3609 struct ql3_adapter *qdev = netdev_priv(ndev);
3610
3611 netdev_err(ndev, "Resetting...\n");
3612 /*
3613 * Stop the queues, we've got a problem.
3614 */
3615 netif_stop_queue(ndev);
3616
3617 /*
3618 * Wake up the worker to process this event.
3619 */
3620 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3621}
3622
3623static void ql_reset_work(struct work_struct *work)
3624{
3625 struct ql3_adapter *qdev =
3626 container_of(work, struct ql3_adapter, reset_work.work);
3627 struct net_device *ndev = qdev->ndev;
3628 u32 value;
3629 struct ql_tx_buf_cb *tx_cb;
3630 int max_wait_time, i;
3631 struct ql3xxx_port_registers __iomem *port_regs =
3632 qdev->mem_map_registers;
3633 unsigned long hw_flags;
3634
3635 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
3636 clear_bit(QL_LINK_MASTER, &qdev->flags);
3637
3638 /*
3639 * Loop through the active list and return the skb.
3640 */
3641 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3642 int j;
3643 tx_cb = &qdev->tx_buf[i];
3644 if (tx_cb->skb) {
3645 netdev_printk(KERN_DEBUG, ndev,
3646 "Freeing lost SKB\n");
3647 pci_unmap_single(qdev->pdev,
3648 dma_unmap_addr(&tx_cb->map[0],
3649 mapaddr),
3650 dma_unmap_len(&tx_cb->map[0], maplen),
3651 PCI_DMA_TODEVICE);
3652 for (j = 1; j < tx_cb->seg_count; j++) {
3653 pci_unmap_page(qdev->pdev,
3654 dma_unmap_addr(&tx_cb->map[j],
3655 mapaddr),
3656 dma_unmap_len(&tx_cb->map[j],
3657 maplen),
3658 PCI_DMA_TODEVICE);
3659 }
3660 dev_kfree_skb(tx_cb->skb);
3661 tx_cb->skb = NULL;
3662 }
3663 }
3664
3665 netdev_err(ndev, "Clearing NRI after reset\n");
3666 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3667 ql_write_common_reg(qdev,
3668 &port_regs->CommonRegs.
3669 ispControlStatus,
3670 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3671 /*
3672 * Wait the for Soft Reset to Complete.
3673 */
3674 max_wait_time = 10;
3675 do {
3676 value = ql_read_common_reg(qdev,
3677 &port_regs->CommonRegs.
3678
3679 ispControlStatus);
3680 if ((value & ISP_CONTROL_SR) == 0) {
3681 netdev_printk(KERN_DEBUG, ndev,
3682 "reset completed\n");
3683 break;
3684 }
3685
3686 if (value & ISP_CONTROL_RI) {
3687 netdev_printk(KERN_DEBUG, ndev,
3688 "clearing NRI after reset\n");
3689 ql_write_common_reg(qdev,
3690 &port_regs->
3691 CommonRegs.
3692 ispControlStatus,
3693 ((ISP_CONTROL_RI <<
3694 16) | ISP_CONTROL_RI));
3695 }
3696
3697 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3698 ssleep(1);
3699 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3700 } while (--max_wait_time);
3701 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3702
3703 if (value & ISP_CONTROL_SR) {
3704
3705 /*
3706 * Set the reset flags and clear the board again.
3707 * Nothing else to do...
3708 */
3709 netdev_err(ndev,
3710 "Timed out waiting for reset to complete\n");
3711 netdev_err(ndev, "Do a reset\n");
3712 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3713 clear_bit(QL_RESET_START, &qdev->flags);
3714 ql_cycle_adapter(qdev, QL_DO_RESET);
3715 return;
3716 }
3717
3718 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3719 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3720 clear_bit(QL_RESET_START, &qdev->flags);
3721 ql_cycle_adapter(qdev, QL_NO_RESET);
3722 }
3723}
3724
3725static void ql_tx_timeout_work(struct work_struct *work)
3726{
3727 struct ql3_adapter *qdev =
3728 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3729
3730 ql_cycle_adapter(qdev, QL_DO_RESET);
3731}
3732
3733static void ql_get_board_info(struct ql3_adapter *qdev)
3734{
3735 struct ql3xxx_port_registers __iomem *port_regs =
3736 qdev->mem_map_registers;
3737 u32 value;
3738
3739 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3740
3741 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3742 if (value & PORT_STATUS_64)
3743 qdev->pci_width = 64;
3744 else
3745 qdev->pci_width = 32;
3746 if (value & PORT_STATUS_X)
3747 qdev->pci_x = 1;
3748 else
3749 qdev->pci_x = 0;
3750 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3751}
3752
3753static void ql3xxx_timer(struct timer_list *t)
3754{
3755 struct ql3_adapter *qdev = from_timer(qdev, t, adapter_timer);
3756 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3757}
3758
3759static const struct net_device_ops ql3xxx_netdev_ops = {
3760 .ndo_open = ql3xxx_open,
3761 .ndo_start_xmit = ql3xxx_send,
3762 .ndo_stop = ql3xxx_close,
3763 .ndo_validate_addr = eth_validate_addr,
3764 .ndo_set_mac_address = ql3xxx_set_mac_address,
3765 .ndo_tx_timeout = ql3xxx_tx_timeout,
3766};
3767
3768static int ql3xxx_probe(struct pci_dev *pdev,
3769 const struct pci_device_id *pci_entry)
3770{
3771 struct net_device *ndev = NULL;
3772 struct ql3_adapter *qdev = NULL;
3773 static int cards_found;
3774 int uninitialized_var(pci_using_dac), err;
3775
3776 err = pci_enable_device(pdev);
3777 if (err) {
3778 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3779 goto err_out;
3780 }
3781
3782 err = pci_request_regions(pdev, DRV_NAME);
3783 if (err) {
3784 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3785 goto err_out_disable_pdev;
3786 }
3787
3788 pci_set_master(pdev);
3789
3790 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3791 pci_using_dac = 1;
3792 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3793 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3794 pci_using_dac = 0;
3795 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3796 }
3797
3798 if (err) {
3799 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3800 goto err_out_free_regions;
3801 }
3802
3803 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3804 if (!ndev) {
3805 err = -ENOMEM;
3806 goto err_out_free_regions;
3807 }
3808
3809 SET_NETDEV_DEV(ndev, &pdev->dev);
3810
3811 pci_set_drvdata(pdev, ndev);
3812
3813 qdev = netdev_priv(ndev);
3814 qdev->index = cards_found;
3815 qdev->ndev = ndev;
3816 qdev->pdev = pdev;
3817 qdev->device_id = pci_entry->device;
3818 qdev->port_link_state = LS_DOWN;
3819 if (msi)
3820 qdev->msi = 1;
3821
3822 qdev->msg_enable = netif_msg_init(debug, default_msg);
3823
3824 if (pci_using_dac)
3825 ndev->features |= NETIF_F_HIGHDMA;
3826 if (qdev->device_id == QL3032_DEVICE_ID)
3827 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3828
3829 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3830 if (!qdev->mem_map_registers) {
3831 pr_err("%s: cannot map device registers\n", pci_name(pdev));
3832 err = -EIO;
3833 goto err_out_free_ndev;
3834 }
3835
3836 spin_lock_init(&qdev->adapter_lock);
3837 spin_lock_init(&qdev->hw_lock);
3838
3839 /* Set driver entry points */
3840 ndev->netdev_ops = &ql3xxx_netdev_ops;
3841 ndev->ethtool_ops = &ql3xxx_ethtool_ops;
3842 ndev->watchdog_timeo = 5 * HZ;
3843
3844 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
3845
3846 ndev->irq = pdev->irq;
3847
3848 /* make sure the EEPROM is good */
3849 if (ql_get_nvram_params(qdev)) {
3850 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3851 __func__, qdev->index);
3852 err = -EIO;
3853 goto err_out_iounmap;
3854 }
3855
3856 ql_set_mac_info(qdev);
3857
3858 /* Validate and set parameters */
3859 if (qdev->mac_index) {
3860 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3861 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3862 } else {
3863 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3864 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3865 }
3866
3867 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3868
3869 /* Record PCI bus information. */
3870 ql_get_board_info(qdev);
3871
3872 /*
3873 * Set the Maximum Memory Read Byte Count value. We do this to handle
3874 * jumbo frames.
3875 */
3876 if (qdev->pci_x)
3877 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3878
3879 err = register_netdev(ndev);
3880 if (err) {
3881 pr_err("%s: cannot register net device\n", pci_name(pdev));
3882 goto err_out_iounmap;
3883 }
3884
3885 /* we're going to reset, so assume we have no link for now */
3886
3887 netif_carrier_off(ndev);
3888 netif_stop_queue(ndev);
3889
3890 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3891 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3892 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3893 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3894
3895 timer_setup(&qdev->adapter_timer, ql3xxx_timer, 0);
3896 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3897
3898 if (!cards_found) {
3899 pr_alert("%s\n", DRV_STRING);
3900 pr_alert("Driver name: %s, Version: %s\n",
3901 DRV_NAME, DRV_VERSION);
3902 }
3903 ql_display_dev_info(ndev);
3904
3905 cards_found++;
3906 return 0;
3907
3908err_out_iounmap:
3909 iounmap(qdev->mem_map_registers);
3910err_out_free_ndev:
3911 free_netdev(ndev);
3912err_out_free_regions:
3913 pci_release_regions(pdev);
3914err_out_disable_pdev:
3915 pci_disable_device(pdev);
3916err_out:
3917 return err;
3918}
3919
3920static void ql3xxx_remove(struct pci_dev *pdev)
3921{
3922 struct net_device *ndev = pci_get_drvdata(pdev);
3923 struct ql3_adapter *qdev = netdev_priv(ndev);
3924
3925 unregister_netdev(ndev);
3926
3927 ql_disable_interrupts(qdev);
3928
3929 if (qdev->workqueue) {
3930 cancel_delayed_work(&qdev->reset_work);
3931 cancel_delayed_work(&qdev->tx_timeout_work);
3932 destroy_workqueue(qdev->workqueue);
3933 qdev->workqueue = NULL;
3934 }
3935
3936 iounmap(qdev->mem_map_registers);
3937 pci_release_regions(pdev);
3938 free_netdev(ndev);
3939}
3940
3941static struct pci_driver ql3xxx_driver = {
3942
3943 .name = DRV_NAME,
3944 .id_table = ql3xxx_pci_tbl,
3945 .probe = ql3xxx_probe,
3946 .remove = ql3xxx_remove,
3947};
3948
3949module_pci_driver(ql3xxx_driver);