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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "ixgbe_x540.h"
5#include "ixgbe_type.h"
6#include "ixgbe_common.h"
7#include "ixgbe_mbx.h"
8#include "ixgbe_phy.h"
9
10static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
11static int ixgbe_setup_fc_x550em(struct ixgbe_hw *);
12static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
13static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
14static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
15
16static int ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
17{
18 struct ixgbe_mac_info *mac = &hw->mac;
19 struct ixgbe_phy_info *phy = &hw->phy;
20 struct ixgbe_link_info *link = &hw->link;
21
22 /* Start with X540 invariants, since so simular */
23 ixgbe_get_invariants_X540(hw);
24
25 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
26 phy->ops.set_phy_power = NULL;
27
28 link->addr = IXGBE_CS4227;
29
30 return 0;
31}
32
33static int ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
34{
35 struct ixgbe_phy_info *phy = &hw->phy;
36
37 /* Start with X540 invariants, since so similar */
38 ixgbe_get_invariants_X540(hw);
39
40 phy->ops.set_phy_power = NULL;
41
42 return 0;
43}
44
45static int ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
46{
47 struct ixgbe_mac_info *mac = &hw->mac;
48 struct ixgbe_phy_info *phy = &hw->phy;
49
50 /* Start with X540 invariants, since so simular */
51 ixgbe_get_invariants_X540(hw);
52
53 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
54 phy->ops.set_phy_power = NULL;
55
56 return 0;
57}
58
59static int ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
60{
61 struct ixgbe_phy_info *phy = &hw->phy;
62
63 /* Start with X540 invariants, since so similar */
64 ixgbe_get_invariants_X540(hw);
65
66 phy->ops.set_phy_power = NULL;
67
68 return 0;
69}
70
71/** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
72 * @hw: pointer to hardware structure
73 **/
74static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
75{
76 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
77
78 if (hw->bus.lan_id) {
79 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
80 esdp |= IXGBE_ESDP_SDP1_DIR;
81 }
82 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
83 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
84 IXGBE_WRITE_FLUSH(hw);
85}
86
87/**
88 * ixgbe_read_cs4227 - Read CS4227 register
89 * @hw: pointer to hardware structure
90 * @reg: register number to write
91 * @value: pointer to receive value read
92 *
93 * Returns status code
94 */
95static int ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
96{
97 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
98}
99
100/**
101 * ixgbe_write_cs4227 - Write CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: value to write to register
105 *
106 * Returns status code
107 */
108static int ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
109{
110 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
111}
112
113/**
114 * ixgbe_read_pe - Read register from port expander
115 * @hw: pointer to hardware structure
116 * @reg: register number to read
117 * @value: pointer to receive read value
118 *
119 * Returns status code
120 */
121static int ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
122{
123 int status;
124
125 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
126 if (status)
127 hw_err(hw, "port expander access failed with %d\n", status);
128 return status;
129}
130
131/**
132 * ixgbe_write_pe - Write register to port expander
133 * @hw: pointer to hardware structure
134 * @reg: register number to write
135 * @value: value to write
136 *
137 * Returns status code
138 */
139static int ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
140{
141 int status;
142
143 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
144 value);
145 if (status)
146 hw_err(hw, "port expander access failed with %d\n", status);
147 return status;
148}
149
150/**
151 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
152 * @hw: pointer to hardware structure
153 *
154 * This function assumes that the caller has acquired the proper semaphore.
155 * Returns error code
156 */
157static int ixgbe_reset_cs4227(struct ixgbe_hw *hw)
158{
159 int status;
160 u32 retry;
161 u16 value;
162 u8 reg;
163
164 /* Trigger hard reset. */
165 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
166 if (status)
167 return status;
168 reg |= IXGBE_PE_BIT1;
169 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
170 if (status)
171 return status;
172
173 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
174 if (status)
175 return status;
176 reg &= ~IXGBE_PE_BIT1;
177 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
178 if (status)
179 return status;
180
181 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
182 if (status)
183 return status;
184 reg &= ~IXGBE_PE_BIT1;
185 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
186 if (status)
187 return status;
188
189 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
190
191 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
192 if (status)
193 return status;
194 reg |= IXGBE_PE_BIT1;
195 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
196 if (status)
197 return status;
198
199 /* Wait for the reset to complete. */
200 msleep(IXGBE_CS4227_RESET_DELAY);
201 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
202 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
203 &value);
204 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
205 break;
206 msleep(IXGBE_CS4227_CHECK_DELAY);
207 }
208 if (retry == IXGBE_CS4227_RETRIES) {
209 hw_err(hw, "CS4227 reset did not complete\n");
210 return -EIO;
211 }
212
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
214 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
215 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
216 return -EIO;
217 }
218
219 return 0;
220}
221
222/**
223 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
224 * @hw: pointer to hardware structure
225 */
226static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
227{
228 u32 swfw_mask = hw->phy.phy_semaphore_mask;
229 int status;
230 u16 value;
231 u8 retry;
232
233 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
234 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
235 if (status) {
236 hw_err(hw, "semaphore failed with %d\n", status);
237 msleep(IXGBE_CS4227_CHECK_DELAY);
238 continue;
239 }
240
241 /* Get status of reset flow. */
242 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
243 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
244 goto out;
245
246 if (status || value != IXGBE_CS4227_RESET_PENDING)
247 break;
248
249 /* Reset is pending. Wait and check again. */
250 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
251 msleep(IXGBE_CS4227_CHECK_DELAY);
252 }
253 /* If still pending, assume other instance failed. */
254 if (retry == IXGBE_CS4227_RETRIES) {
255 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
256 if (status) {
257 hw_err(hw, "semaphore failed with %d\n", status);
258 return;
259 }
260 }
261
262 /* Reset the CS4227. */
263 status = ixgbe_reset_cs4227(hw);
264 if (status) {
265 hw_err(hw, "CS4227 reset failed: %d", status);
266 goto out;
267 }
268
269 /* Reset takes so long, temporarily release semaphore in case the
270 * other driver instance is waiting for the reset indication.
271 */
272 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
273 IXGBE_CS4227_RESET_PENDING);
274 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
275 usleep_range(10000, 12000);
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status) {
278 hw_err(hw, "semaphore failed with %d", status);
279 return;
280 }
281
282 /* Record completion for next time. */
283 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
284 IXGBE_CS4227_RESET_COMPLETE);
285
286out:
287 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
288 msleep(hw->eeprom.semaphore_delay);
289}
290
291/** ixgbe_identify_phy_x550em - Get PHY type based on device id
292 * @hw: pointer to hardware structure
293 *
294 * Returns error code
295 */
296static int ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
297{
298 switch (hw->device_id) {
299 case IXGBE_DEV_ID_X550EM_A_SFP:
300 if (hw->bus.lan_id)
301 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
302 else
303 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
304 return ixgbe_identify_module_generic(hw);
305 case IXGBE_DEV_ID_X550EM_X_SFP:
306 /* set up for CS4227 usage */
307 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
308 ixgbe_setup_mux_ctl(hw);
309 ixgbe_check_cs4227(hw);
310 fallthrough;
311 case IXGBE_DEV_ID_X550EM_A_SFP_N:
312 return ixgbe_identify_module_generic(hw);
313 case IXGBE_DEV_ID_X550EM_X_KX4:
314 hw->phy.type = ixgbe_phy_x550em_kx4;
315 break;
316 case IXGBE_DEV_ID_X550EM_X_XFI:
317 hw->phy.type = ixgbe_phy_x550em_xfi;
318 break;
319 case IXGBE_DEV_ID_X550EM_X_KR:
320 case IXGBE_DEV_ID_X550EM_A_KR:
321 case IXGBE_DEV_ID_X550EM_A_KR_L:
322 hw->phy.type = ixgbe_phy_x550em_kr;
323 break;
324 case IXGBE_DEV_ID_X550EM_A_10G_T:
325 if (hw->bus.lan_id)
326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
327 else
328 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
329 fallthrough;
330 case IXGBE_DEV_ID_X550EM_X_10G_T:
331 return ixgbe_identify_phy_generic(hw);
332 case IXGBE_DEV_ID_X550EM_X_1G_T:
333 hw->phy.type = ixgbe_phy_ext_1g_t;
334 break;
335 case IXGBE_DEV_ID_X550EM_A_1G_T:
336 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
337 hw->phy.type = ixgbe_phy_fw;
338 hw->phy.ops.read_reg = NULL;
339 hw->phy.ops.write_reg = NULL;
340 if (hw->bus.lan_id)
341 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
342 else
343 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
344 break;
345 default:
346 break;
347 }
348 return 0;
349}
350
351static int ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
352 u32 device_type, u16 *phy_data)
353{
354 return -EOPNOTSUPP;
355}
356
357static int ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
358 u32 device_type, u16 phy_data)
359{
360 return -EOPNOTSUPP;
361}
362
363/**
364 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
365 * @hw: pointer to the hardware structure
366 * @addr: I2C bus address to read from
367 * @reg: I2C device register to read from
368 * @val: pointer to location to receive read value
369 *
370 * Returns an error code on error.
371 **/
372static int ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
373 u16 reg, u16 *val)
374{
375 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
376}
377
378/**
379 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
380 * @hw: pointer to the hardware structure
381 * @addr: I2C bus address to read from
382 * @reg: I2C device register to read from
383 * @val: pointer to location to receive read value
384 *
385 * Returns an error code on error.
386 **/
387static int
388ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
389 u16 reg, u16 *val)
390{
391 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
392}
393
394/**
395 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
396 * @hw: pointer to the hardware structure
397 * @addr: I2C bus address to write to
398 * @reg: I2C device register to write to
399 * @val: value to write
400 *
401 * Returns an error code on error.
402 **/
403static int ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
404 u8 addr, u16 reg, u16 val)
405{
406 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
407}
408
409/**
410 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
411 * @hw: pointer to the hardware structure
412 * @addr: I2C bus address to write to
413 * @reg: I2C device register to write to
414 * @val: value to write
415 *
416 * Returns an error code on error.
417 **/
418static int
419ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
420 u8 addr, u16 reg, u16 val)
421{
422 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
423}
424
425/**
426 * ixgbe_fw_phy_activity - Perform an activity on a PHY
427 * @hw: pointer to hardware structure
428 * @activity: activity to perform
429 * @data: Pointer to 4 32-bit words of data
430 */
431int ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
432 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
433{
434 union {
435 struct ixgbe_hic_phy_activity_req cmd;
436 struct ixgbe_hic_phy_activity_resp rsp;
437 } hic;
438 u16 retries = FW_PHY_ACT_RETRIES;
439 int rc;
440 u32 i;
441
442 do {
443 memset(&hic, 0, sizeof(hic));
444 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
445 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
446 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
447 hic.cmd.port_number = hw->bus.lan_id;
448 hic.cmd.activity_id = cpu_to_le16(activity);
449 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
450 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
451
452 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
453 IXGBE_HI_COMMAND_TIMEOUT,
454 true);
455 if (rc)
456 return rc;
457 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
458 FW_CEM_RESP_STATUS_SUCCESS) {
459 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
460 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
461 return 0;
462 }
463 usleep_range(20, 30);
464 --retries;
465 } while (retries > 0);
466
467 return -EIO;
468}
469
470static const struct {
471 u16 fw_speed;
472 ixgbe_link_speed phy_speed;
473} ixgbe_fw_map[] = {
474 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
475 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
476 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
477 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
478 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
479 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
480};
481
482/**
483 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
484 * @hw: pointer to hardware structure
485 *
486 * Returns error code
487 */
488static int ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
489{
490 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
491 u16 phy_speeds;
492 u16 phy_id_lo;
493 int rc;
494 u16 i;
495
496 if (hw->phy.id)
497 return 0;
498
499 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
500 if (rc)
501 return rc;
502
503 hw->phy.speeds_supported = 0;
504 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
505 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
506 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
507 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
508 }
509
510 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
511 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
512 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
513 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
514 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
515 return -EFAULT;
516
517 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
518 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
519 IXGBE_LINK_SPEED_1GB_FULL;
520 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
521 return 0;
522}
523
524/**
525 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
526 * @hw: pointer to hardware structure
527 *
528 * Returns error code
529 */
530static int ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
531{
532 if (hw->bus.lan_id)
533 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
534 else
535 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
536
537 hw->phy.type = ixgbe_phy_fw;
538 hw->phy.ops.read_reg = NULL;
539 hw->phy.ops.write_reg = NULL;
540 return ixgbe_get_phy_id_fw(hw);
541}
542
543/**
544 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
545 * @hw: pointer to hardware structure
546 *
547 * Returns error code
548 */
549static int ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
550{
551 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
552
553 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
554 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
555}
556
557/**
558 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
559 * @hw: pointer to hardware structure
560 */
561static int ixgbe_setup_fw_link(struct ixgbe_hw *hw)
562{
563 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
564 int rc;
565 u16 i;
566
567 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
568 return 0;
569
570 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
571 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
572 return -EINVAL;
573 }
574
575 switch (hw->fc.requested_mode) {
576 case ixgbe_fc_full:
577 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
578 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
579 break;
580 case ixgbe_fc_rx_pause:
581 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
582 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
583 break;
584 case ixgbe_fc_tx_pause:
585 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
586 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
587 break;
588 default:
589 break;
590 }
591
592 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
593 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
594 setup[0] |= ixgbe_fw_map[i].fw_speed;
595 }
596 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
597
598 if (hw->phy.eee_speeds_advertised)
599 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
600
601 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
602 if (rc)
603 return rc;
604
605 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
606 return -EIO;
607
608 return 0;
609}
610
611/**
612 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
613 * @hw: pointer to hardware structure
614 *
615 * Called at init time to set up flow control.
616 */
617static int ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
618{
619 if (hw->fc.requested_mode == ixgbe_fc_default)
620 hw->fc.requested_mode = ixgbe_fc_full;
621
622 return ixgbe_setup_fw_link(hw);
623}
624
625/** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
626 * @hw: pointer to hardware structure
627 *
628 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
629 * ixgbe_hw struct in order to set up EEPROM access.
630 **/
631static int ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
632{
633 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
634
635 if (eeprom->type == ixgbe_eeprom_uninitialized) {
636 u16 eeprom_size;
637 u32 eec;
638
639 eeprom->semaphore_delay = 10;
640 eeprom->type = ixgbe_flash;
641
642 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
643 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
644 eeprom->word_size = BIT(eeprom_size +
645 IXGBE_EEPROM_WORD_SIZE_SHIFT);
646
647 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
648 eeprom->type, eeprom->word_size);
649 }
650
651 return 0;
652}
653
654/**
655 * ixgbe_iosf_wait - Wait for IOSF command completion
656 * @hw: pointer to hardware structure
657 * @ctrl: pointer to location to receive final IOSF control value
658 *
659 * Return: failing status on timeout
660 *
661 * Note: ctrl can be NULL if the IOSF control register value is not needed
662 */
663static int ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
664{
665 u32 i, command;
666
667 /* Check every 10 usec to see if the address cycle completed.
668 * The SB IOSF BUSY bit will clear when the operation is
669 * complete.
670 */
671 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
672 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
673 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
674 break;
675 udelay(10);
676 }
677 if (ctrl)
678 *ctrl = command;
679 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
680 hw_dbg(hw, "IOSF wait timed out\n");
681 return -EIO;
682 }
683
684 return 0;
685}
686
687/** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
688 * IOSF device
689 * @hw: pointer to hardware structure
690 * @reg_addr: 32 bit PHY register to write
691 * @device_type: 3 bit device type
692 * @phy_data: Pointer to read data from the register
693 **/
694static int ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
695 u32 device_type, u32 *data)
696{
697 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
698 u32 command, error;
699 int ret;
700
701 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
702 if (ret)
703 return ret;
704
705 ret = ixgbe_iosf_wait(hw, NULL);
706 if (ret)
707 goto out;
708
709 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
710 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
711
712 /* Write IOSF control register */
713 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
714
715 ret = ixgbe_iosf_wait(hw, &command);
716
717 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
718 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
719 hw_dbg(hw, "Failed to read, error %x\n", error);
720 ret = -EIO;
721 goto out;
722 }
723
724 if (!ret)
725 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
726
727out:
728 hw->mac.ops.release_swfw_sync(hw, gssr);
729 return ret;
730}
731
732/**
733 * ixgbe_get_phy_token - Get the token for shared PHY access
734 * @hw: Pointer to hardware structure
735 */
736static int ixgbe_get_phy_token(struct ixgbe_hw *hw)
737{
738 struct ixgbe_hic_phy_token_req token_cmd;
739 int status;
740
741 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
742 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
743 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
744 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
745 token_cmd.port_number = hw->bus.lan_id;
746 token_cmd.command_type = FW_PHY_TOKEN_REQ;
747 token_cmd.pad = 0;
748 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
749 IXGBE_HI_COMMAND_TIMEOUT,
750 true);
751 if (status)
752 return status;
753 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
754 return 0;
755 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
756 return -EIO;
757
758 return -EAGAIN;
759}
760
761/**
762 * ixgbe_put_phy_token - Put the token for shared PHY access
763 * @hw: Pointer to hardware structure
764 */
765static int ixgbe_put_phy_token(struct ixgbe_hw *hw)
766{
767 struct ixgbe_hic_phy_token_req token_cmd;
768 int status;
769
770 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
771 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
772 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
773 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
774 token_cmd.port_number = hw->bus.lan_id;
775 token_cmd.command_type = FW_PHY_TOKEN_REL;
776 token_cmd.pad = 0;
777 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
778 IXGBE_HI_COMMAND_TIMEOUT,
779 true);
780 if (status)
781 return status;
782 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
783 return 0;
784 return -EIO;
785}
786
787/**
788 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
789 * @hw: pointer to hardware structure
790 * @reg_addr: 32 bit PHY register to write
791 * @device_type: 3 bit device type
792 * @data: Data to write to the register
793 **/
794static int ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
795 __always_unused u32 device_type,
796 u32 data)
797{
798 struct ixgbe_hic_internal_phy_req write_cmd;
799
800 memset(&write_cmd, 0, sizeof(write_cmd));
801 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
802 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
803 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
804 write_cmd.port_number = hw->bus.lan_id;
805 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
806 write_cmd.address = cpu_to_be16(reg_addr);
807 write_cmd.write_data = cpu_to_be32(data);
808
809 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
810 IXGBE_HI_COMMAND_TIMEOUT, false);
811}
812
813/**
814 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
815 * @hw: pointer to hardware structure
816 * @reg_addr: 32 bit PHY register to write
817 * @device_type: 3 bit device type
818 * @data: Pointer to read data from the register
819 **/
820static int ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
821 __always_unused u32 device_type,
822 u32 *data)
823{
824 union {
825 struct ixgbe_hic_internal_phy_req cmd;
826 struct ixgbe_hic_internal_phy_resp rsp;
827 } hic;
828 int status;
829
830 memset(&hic, 0, sizeof(hic));
831 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
832 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
833 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
834 hic.cmd.port_number = hw->bus.lan_id;
835 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
836 hic.cmd.address = cpu_to_be16(reg_addr);
837
838 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
839 IXGBE_HI_COMMAND_TIMEOUT, true);
840
841 /* Extract the register value from the response. */
842 *data = be32_to_cpu(hic.rsp.read_data);
843
844 return status;
845}
846
847/** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
848 * @hw: pointer to hardware structure
849 * @offset: offset of word in the EEPROM to read
850 * @words: number of words
851 * @data: word(s) read from the EEPROM
852 *
853 * Reads a 16 bit word(s) from the EEPROM using the hostif.
854 **/
855static int ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
856 u16 offset, u16 words, u16 *data)
857{
858 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
859 struct ixgbe_hic_read_shadow_ram buffer;
860 u32 current_word = 0;
861 u16 words_to_read;
862 int status;
863 u32 i;
864
865 /* Take semaphore for the entire operation. */
866 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
867 if (status) {
868 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
869 return status;
870 }
871
872 while (words) {
873 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
874 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
875 else
876 words_to_read = words;
877
878 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
879 buffer.hdr.req.buf_lenh = 0;
880 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
881 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
882
883 /* convert offset from words to bytes */
884 buffer.address = (__force u32)cpu_to_be32((offset +
885 current_word) * 2);
886 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
887 buffer.pad2 = 0;
888 buffer.pad3 = 0;
889
890 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
891 IXGBE_HI_COMMAND_TIMEOUT);
892 if (status) {
893 hw_dbg(hw, "Host interface command failed\n");
894 goto out;
895 }
896
897 for (i = 0; i < words_to_read; i++) {
898 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
899 2 * i;
900 u32 value = IXGBE_READ_REG(hw, reg);
901
902 data[current_word] = (u16)(value & 0xffff);
903 current_word++;
904 i++;
905 if (i < words_to_read) {
906 value >>= 16;
907 data[current_word] = (u16)(value & 0xffff);
908 current_word++;
909 }
910 }
911 words -= words_to_read;
912 }
913
914out:
915 hw->mac.ops.release_swfw_sync(hw, mask);
916 return status;
917}
918
919/** ixgbe_checksum_ptr_x550 - Checksum one pointer region
920 * @hw: pointer to hardware structure
921 * @ptr: pointer offset in eeprom
922 * @size: size of section pointed by ptr, if 0 first word will be used as size
923 * @csum: address of checksum to update
924 *
925 * Returns error status for any failure
926 **/
927static int ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
928 u16 size, u16 *csum, u16 *buffer,
929 u32 buffer_size)
930{
931 u16 length, bufsz, i, start;
932 u16 *local_buffer;
933 u16 buf[256];
934 int status;
935
936 bufsz = ARRAY_SIZE(buf);
937
938 /* Read a chunk at the pointer location */
939 if (!buffer) {
940 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
941 if (status) {
942 hw_dbg(hw, "Failed to read EEPROM image\n");
943 return status;
944 }
945 local_buffer = buf;
946 } else {
947 if (buffer_size < ptr)
948 return -EINVAL;
949 local_buffer = &buffer[ptr];
950 }
951
952 if (size) {
953 start = 0;
954 length = size;
955 } else {
956 start = 1;
957 length = local_buffer[0];
958
959 /* Skip pointer section if length is invalid. */
960 if (length == 0xFFFF || length == 0 ||
961 (ptr + length) >= hw->eeprom.word_size)
962 return 0;
963 }
964
965 if (buffer && ((u32)start + (u32)length > buffer_size))
966 return -EINVAL;
967
968 for (i = start; length; i++, length--) {
969 if (i == bufsz && !buffer) {
970 ptr += bufsz;
971 i = 0;
972 if (length < bufsz)
973 bufsz = length;
974
975 /* Read a chunk at the pointer location */
976 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
977 bufsz, buf);
978 if (status) {
979 hw_dbg(hw, "Failed to read EEPROM image\n");
980 return status;
981 }
982 }
983 *csum += local_buffer[i];
984 }
985 return 0;
986}
987
988/** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
989 * @hw: pointer to hardware structure
990 * @buffer: pointer to buffer containing calculated checksum
991 * @buffer_size: size of buffer
992 *
993 * Returns a negative error code on error, or the 16-bit checksum
994 **/
995static int ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
996 u32 buffer_size)
997{
998 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
999 u16 pointer, i, size;
1000 u16 *local_buffer;
1001 u16 checksum = 0;
1002 int status;
1003
1004 hw->eeprom.ops.init_params(hw);
1005
1006 if (!buffer) {
1007 /* Read pointer area */
1008 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1009 IXGBE_EEPROM_LAST_WORD + 1,
1010 eeprom_ptrs);
1011 if (status) {
1012 hw_dbg(hw, "Failed to read EEPROM image\n");
1013 return status;
1014 }
1015 local_buffer = eeprom_ptrs;
1016 } else {
1017 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1018 return -EINVAL;
1019 local_buffer = buffer;
1020 }
1021
1022 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1023 * checksum word itself
1024 */
1025 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1026 if (i != IXGBE_EEPROM_CHECKSUM)
1027 checksum += local_buffer[i];
1028
1029 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1030 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1031 */
1032 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1033 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1034 continue;
1035
1036 pointer = local_buffer[i];
1037
1038 /* Skip pointer section if the pointer is invalid. */
1039 if (pointer == 0xFFFF || pointer == 0 ||
1040 pointer >= hw->eeprom.word_size)
1041 continue;
1042
1043 switch (i) {
1044 case IXGBE_PCIE_GENERAL_PTR:
1045 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1046 break;
1047 case IXGBE_PCIE_CONFIG0_PTR:
1048 case IXGBE_PCIE_CONFIG1_PTR:
1049 size = IXGBE_PCIE_CONFIG_SIZE;
1050 break;
1051 default:
1052 size = 0;
1053 break;
1054 }
1055
1056 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1057 buffer, buffer_size);
1058 if (status)
1059 return status;
1060 }
1061
1062 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1063
1064 return (int)checksum;
1065}
1066
1067/** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1068 * @hw: pointer to hardware structure
1069 *
1070 * Returns a negative error code on error, or the 16-bit checksum
1071 **/
1072static int ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1073{
1074 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1075}
1076
1077/** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1078 * @hw: pointer to hardware structure
1079 * @offset: offset of word in the EEPROM to read
1080 * @data: word read from the EEPROM
1081 *
1082 * Reads a 16 bit word from the EEPROM using the hostif.
1083 **/
1084static int ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1085{
1086 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1087 struct ixgbe_hic_read_shadow_ram buffer;
1088 int status;
1089
1090 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1091 buffer.hdr.req.buf_lenh = 0;
1092 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1093 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1094
1095 /* convert offset from words to bytes */
1096 buffer.address = (__force u32)cpu_to_be32(offset * 2);
1097 /* one word */
1098 buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1099
1100 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1101 if (status)
1102 return status;
1103
1104 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1105 IXGBE_HI_COMMAND_TIMEOUT);
1106 if (!status) {
1107 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1108 FW_NVM_DATA_OFFSET);
1109 }
1110
1111 hw->mac.ops.release_swfw_sync(hw, mask);
1112 return status;
1113}
1114
1115/** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1116 * @hw: pointer to hardware structure
1117 * @checksum_val: calculated checksum
1118 *
1119 * Performs checksum calculation and validates the EEPROM checksum. If the
1120 * caller does not need checksum_val, the value can be NULL.
1121 **/
1122static int ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1123 u16 *checksum_val)
1124{
1125 u16 read_checksum = 0;
1126 u16 checksum;
1127 int status;
1128
1129 /* Read the first word from the EEPROM. If this times out or fails, do
1130 * not continue or we could be in for a very long wait while every
1131 * EEPROM read fails
1132 */
1133 status = hw->eeprom.ops.read(hw, 0, &checksum);
1134 if (status) {
1135 hw_dbg(hw, "EEPROM read failed\n");
1136 return status;
1137 }
1138
1139 status = hw->eeprom.ops.calc_checksum(hw);
1140 if (status < 0)
1141 return status;
1142
1143 checksum = (u16)(status & 0xffff);
1144
1145 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1146 &read_checksum);
1147 if (status)
1148 return status;
1149
1150 /* Verify read checksum from EEPROM is the same as
1151 * calculated checksum
1152 */
1153 if (read_checksum != checksum) {
1154 status = -EIO;
1155 hw_dbg(hw, "Invalid EEPROM checksum");
1156 }
1157
1158 /* If the user cares, return the calculated checksum */
1159 if (checksum_val)
1160 *checksum_val = checksum;
1161
1162 return status;
1163}
1164
1165/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1166 * @hw: pointer to hardware structure
1167 * @offset: offset of word in the EEPROM to write
1168 * @data: word write to the EEPROM
1169 *
1170 * Write a 16 bit word to the EEPROM using the hostif.
1171 **/
1172static int ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1173 u16 data)
1174{
1175 struct ixgbe_hic_write_shadow_ram buffer;
1176 int status;
1177
1178 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1179 buffer.hdr.req.buf_lenh = 0;
1180 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1181 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1182
1183 /* one word */
1184 buffer.length = cpu_to_be16(sizeof(u16));
1185 buffer.data = data;
1186 buffer.address = cpu_to_be32(offset * 2);
1187
1188 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1189 IXGBE_HI_COMMAND_TIMEOUT, false);
1190 return status;
1191}
1192
1193/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1194 * @hw: pointer to hardware structure
1195 * @offset: offset of word in the EEPROM to write
1196 * @data: word write to the EEPROM
1197 *
1198 * Write a 16 bit word to the EEPROM using the hostif.
1199 **/
1200static int ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1201{
1202 int status = 0;
1203
1204 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1205 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1206 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1207 } else {
1208 hw_dbg(hw, "write ee hostif failed to get semaphore");
1209 status = -EBUSY;
1210 }
1211
1212 return status;
1213}
1214
1215/** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1216 * @hw: pointer to hardware structure
1217 *
1218 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1219 **/
1220static int ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1221{
1222 union ixgbe_hic_hdr2 buffer;
1223 int status = 0;
1224
1225 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1226 buffer.req.buf_lenh = 0;
1227 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1228 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1229
1230 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1231 IXGBE_HI_COMMAND_TIMEOUT, false);
1232 return status;
1233}
1234
1235/**
1236 * ixgbe_get_bus_info_X550em - Set PCI bus info
1237 * @hw: pointer to hardware structure
1238 *
1239 * Sets bus link width and speed to unknown because X550em is
1240 * not a PCI device.
1241 **/
1242static int ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1243{
1244 hw->bus.type = ixgbe_bus_type_internal;
1245 hw->bus.width = ixgbe_bus_width_unknown;
1246 hw->bus.speed = ixgbe_bus_speed_unknown;
1247
1248 hw->mac.ops.set_lan_id(hw);
1249
1250 return 0;
1251}
1252
1253/**
1254 * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
1255 * @hw: pointer t hardware structure
1256 *
1257 * Returns true if in FW NVM recovery mode.
1258 */
1259static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1260{
1261 u32 fwsm;
1262
1263 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1264 return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1265}
1266
1267/** ixgbe_disable_rx_x550 - Disable RX unit
1268 *
1269 * Enables the Rx DMA unit for x550
1270 **/
1271static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1272{
1273 struct ixgbe_hic_disable_rxen fw_cmd;
1274 u32 rxctrl, pfdtxgswc;
1275 int status;
1276
1277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1278 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1280 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1281 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1282 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1283 hw->mac.set_lben = true;
1284 } else {
1285 hw->mac.set_lben = false;
1286 }
1287
1288 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1289 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1290 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291 fw_cmd.port_number = hw->bus.lan_id;
1292
1293 status = ixgbe_host_interface_command(hw, &fw_cmd,
1294 sizeof(struct ixgbe_hic_disable_rxen),
1295 IXGBE_HI_COMMAND_TIMEOUT, true);
1296
1297 /* If we fail - disable RX using register write */
1298 if (status) {
1299 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1300 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1301 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1303 }
1304 }
1305 }
1306}
1307
1308/** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1309 * @hw: pointer to hardware structure
1310 *
1311 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1312 * checksum and updates the EEPROM and instructs the hardware to update
1313 * the flash.
1314 **/
1315static int ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1316{
1317 u16 checksum = 0;
1318 int status;
1319
1320 /* Read the first word from the EEPROM. If this times out or fails, do
1321 * not continue or we could be in for a very long wait while every
1322 * EEPROM read fails
1323 */
1324 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1325 if (status) {
1326 hw_dbg(hw, "EEPROM read failed\n");
1327 return status;
1328 }
1329
1330 status = ixgbe_calc_eeprom_checksum_X550(hw);
1331 if (status < 0)
1332 return status;
1333
1334 checksum = (u16)(status & 0xffff);
1335
1336 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1337 checksum);
1338 if (status)
1339 return status;
1340
1341 status = ixgbe_update_flash_X550(hw);
1342
1343 return status;
1344}
1345
1346/** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1347 * @hw: pointer to hardware structure
1348 * @offset: offset of word in the EEPROM to write
1349 * @words: number of words
1350 * @data: word(s) write to the EEPROM
1351 *
1352 *
1353 * Write a 16 bit word(s) to the EEPROM using the hostif.
1354 **/
1355static int ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1356 u16 offset, u16 words,
1357 u16 *data)
1358{
1359 int status = 0;
1360 u32 i = 0;
1361
1362 /* Take semaphore for the entire operation. */
1363 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1364 if (status) {
1365 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1366 return status;
1367 }
1368
1369 for (i = 0; i < words; i++) {
1370 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1371 data[i]);
1372 if (status) {
1373 hw_dbg(hw, "Eeprom buffered write failed\n");
1374 break;
1375 }
1376 }
1377
1378 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1379
1380 return status;
1381}
1382
1383/** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1384 * IOSF device
1385 *
1386 * @hw: pointer to hardware structure
1387 * @reg_addr: 32 bit PHY register to write
1388 * @device_type: 3 bit device type
1389 * @data: Data to write to the register
1390 **/
1391static int ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1392 u32 device_type, u32 data)
1393{
1394 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1395 u32 command, error;
1396 int ret;
1397
1398 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1399 if (ret)
1400 return ret;
1401
1402 ret = ixgbe_iosf_wait(hw, NULL);
1403 if (ret)
1404 goto out;
1405
1406 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1407 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1408
1409 /* Write IOSF control register */
1410 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1411
1412 /* Write IOSF data register */
1413 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1414
1415 ret = ixgbe_iosf_wait(hw, &command);
1416
1417 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1418 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
1419 hw_dbg(hw, "Failed to write, error %x\n", error);
1420 return -EIO;
1421 }
1422
1423out:
1424 hw->mac.ops.release_swfw_sync(hw, gssr);
1425 return ret;
1426}
1427
1428/**
1429 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1430 * @hw: pointer to hardware structure
1431 *
1432 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1433 **/
1434static int ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1435{
1436 u32 reg_val;
1437 int status;
1438
1439 /* Disable training protocol FSM. */
1440 status = ixgbe_read_iosf_sb_reg_x550(hw,
1441 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1442 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1443 if (status)
1444 return status;
1445
1446 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1447 status = ixgbe_write_iosf_sb_reg_x550(hw,
1448 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1449 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1450 if (status)
1451 return status;
1452
1453 /* Disable Flex from training TXFFE. */
1454 status = ixgbe_read_iosf_sb_reg_x550(hw,
1455 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1456 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1457 if (status)
1458 return status;
1459
1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1463 status = ixgbe_write_iosf_sb_reg_x550(hw,
1464 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1465 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1466 if (status)
1467 return status;
1468
1469 status = ixgbe_read_iosf_sb_reg_x550(hw,
1470 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1471 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1472 if (status)
1473 return status;
1474
1475 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1478 status = ixgbe_write_iosf_sb_reg_x550(hw,
1479 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1480 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1481 if (status)
1482 return status;
1483
1484 /* Enable override for coefficients. */
1485 status = ixgbe_read_iosf_sb_reg_x550(hw,
1486 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1487 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1488 if (status)
1489 return status;
1490
1491 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1495 status = ixgbe_write_iosf_sb_reg_x550(hw,
1496 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1497 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1498 return status;
1499}
1500
1501/**
1502 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1503 * internal PHY
1504 * @hw: pointer to hardware structure
1505 **/
1506static int ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1507{
1508 u32 link_ctrl;
1509 int status;
1510
1511 /* Restart auto-negotiation. */
1512 status = hw->mac.ops.read_iosf_sb_reg(hw,
1513 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1514 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1515
1516 if (status) {
1517 hw_dbg(hw, "Auto-negotiation did not complete\n");
1518 return status;
1519 }
1520
1521 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1522 status = hw->mac.ops.write_iosf_sb_reg(hw,
1523 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1524 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1525
1526 if (hw->mac.type == ixgbe_mac_x550em_a) {
1527 u32 flx_mask_st20;
1528
1529 /* Indicate to FW that AN restart has been asserted */
1530 status = hw->mac.ops.read_iosf_sb_reg(hw,
1531 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1532 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1533
1534 if (status) {
1535 hw_dbg(hw, "Auto-negotiation did not complete\n");
1536 return status;
1537 }
1538
1539 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1540 status = hw->mac.ops.write_iosf_sb_reg(hw,
1541 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1542 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1543 }
1544
1545 return status;
1546}
1547
1548/** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1549 * @hw: pointer to hardware structure
1550 * @speed: the link speed to force
1551 *
1552 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1553 * internal and external PHY at a specific speed, without autonegotiation.
1554 **/
1555static int ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1556{
1557 struct ixgbe_mac_info *mac = &hw->mac;
1558 u32 reg_val;
1559 int status;
1560
1561 /* iXFI is only supported with X552 */
1562 if (mac->type != ixgbe_mac_X550EM_x)
1563 return -EIO;
1564
1565 /* Disable AN and force speed to 10G Serial. */
1566 status = ixgbe_read_iosf_sb_reg_x550(hw,
1567 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1568 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1569 if (status)
1570 return status;
1571
1572 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1573 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1574
1575 /* Select forced link speed for internal PHY. */
1576 switch (*speed) {
1577 case IXGBE_LINK_SPEED_10GB_FULL:
1578 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1579 break;
1580 case IXGBE_LINK_SPEED_1GB_FULL:
1581 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1582 break;
1583 default:
1584 /* Other link speeds are not supported by internal KR PHY. */
1585 return -EINVAL;
1586 }
1587
1588 status = ixgbe_write_iosf_sb_reg_x550(hw,
1589 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1590 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1591 if (status)
1592 return status;
1593
1594 /* Additional configuration needed for x550em_x */
1595 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1596 status = ixgbe_setup_ixfi_x550em_x(hw);
1597 if (status)
1598 return status;
1599 }
1600
1601 /* Toggle port SW reset by AN reset. */
1602 status = ixgbe_restart_an_internal_phy_x550em(hw);
1603
1604 return status;
1605}
1606
1607/**
1608 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1609 * @hw: pointer to hardware structure
1610 * @linear: true if SFP module is linear
1611 */
1612static int ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1613{
1614 switch (hw->phy.sfp_type) {
1615 case ixgbe_sfp_type_not_present:
1616 return -ENOENT;
1617 case ixgbe_sfp_type_da_cu_core0:
1618 case ixgbe_sfp_type_da_cu_core1:
1619 *linear = true;
1620 break;
1621 case ixgbe_sfp_type_srlr_core0:
1622 case ixgbe_sfp_type_srlr_core1:
1623 case ixgbe_sfp_type_da_act_lmt_core0:
1624 case ixgbe_sfp_type_da_act_lmt_core1:
1625 case ixgbe_sfp_type_1g_sx_core0:
1626 case ixgbe_sfp_type_1g_sx_core1:
1627 case ixgbe_sfp_type_1g_lx_core0:
1628 case ixgbe_sfp_type_1g_lx_core1:
1629 *linear = false;
1630 break;
1631 case ixgbe_sfp_type_unknown:
1632 case ixgbe_sfp_type_1g_cu_core0:
1633 case ixgbe_sfp_type_1g_cu_core1:
1634 default:
1635 return -EOPNOTSUPP;
1636 }
1637
1638 return 0;
1639}
1640
1641/**
1642 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1643 * @hw: pointer to hardware structure
1644 * @speed: the link speed to force
1645 * @autoneg_wait_to_complete: unused
1646 *
1647 * Configures the extern PHY and the integrated KR PHY for SFP support.
1648 */
1649static int
1650ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1651 ixgbe_link_speed speed,
1652 __always_unused bool autoneg_wait_to_complete)
1653{
1654 bool setup_linear = false;
1655 u16 reg_slice, reg_val;
1656 int status;
1657
1658 /* Check if SFP module is supported and linear */
1659 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1660
1661 /* If no SFP module present, then return success. Return success since
1662 * there is no reason to configure CS4227 and SFP not present error is
1663 * not accepted in the setup MAC link flow.
1664 */
1665 if (status == -ENOENT)
1666 return 0;
1667
1668 if (status)
1669 return status;
1670
1671 /* Configure internal PHY for KR/KX. */
1672 ixgbe_setup_kr_speed_x550em(hw, speed);
1673
1674 /* Configure CS4227 LINE side to proper mode. */
1675 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1676 if (setup_linear)
1677 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1678 else
1679 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1680
1681 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1682 reg_val);
1683
1684 return status;
1685}
1686
1687/**
1688 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1689 * @hw: pointer to hardware structure
1690 * @speed: the link speed to force
1691 *
1692 * Configures the integrated PHY for native SFI mode. Used to connect the
1693 * internal PHY directly to an SFP cage, without autonegotiation.
1694 **/
1695static int ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1696{
1697 struct ixgbe_mac_info *mac = &hw->mac;
1698 u32 reg_val;
1699 int status;
1700
1701 /* Disable all AN and force speed to 10G Serial. */
1702 status = mac->ops.read_iosf_sb_reg(hw,
1703 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1704 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1705 if (status)
1706 return status;
1707
1708 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1712
1713 /* Select forced link speed for internal PHY. */
1714 switch (*speed) {
1715 case IXGBE_LINK_SPEED_10GB_FULL:
1716 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1717 break;
1718 case IXGBE_LINK_SPEED_1GB_FULL:
1719 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1720 break;
1721 default:
1722 /* Other link speeds are not supported by internal PHY. */
1723 return -EINVAL;
1724 }
1725
1726 status = mac->ops.write_iosf_sb_reg(hw,
1727 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1728 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1729
1730 /* Toggle port SW reset by AN reset. */
1731 status = ixgbe_restart_an_internal_phy_x550em(hw);
1732
1733 return status;
1734}
1735
1736/**
1737 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1738 * @hw: pointer to hardware structure
1739 * @speed: link speed
1740 * @autoneg_wait_to_complete: unused
1741 *
1742 * Configure the integrated PHY for native SFP support.
1743 */
1744static int
1745ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1746 __always_unused bool autoneg_wait_to_complete)
1747{
1748 bool setup_linear = false;
1749 u32 reg_phy_int;
1750 int ret_val;
1751
1752 /* Check if SFP module is supported and linear */
1753 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1754
1755 /* If no SFP module present, then return success. Return success since
1756 * SFP not present error is not excepted in the setup MAC link flow.
1757 */
1758 if (ret_val == -ENOENT)
1759 return 0;
1760
1761 if (ret_val)
1762 return ret_val;
1763
1764 /* Configure internal PHY for native SFI based on module type */
1765 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1766 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1767 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1768 if (ret_val)
1769 return ret_val;
1770
1771 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1772 if (!setup_linear)
1773 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1774
1775 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1776 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1777 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1778 if (ret_val)
1779 return ret_val;
1780
1781 /* Setup SFI internal link. */
1782 return ixgbe_setup_sfi_x550a(hw, &speed);
1783}
1784
1785/**
1786 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1787 * @hw: pointer to hardware structure
1788 * @speed: link speed
1789 * @autoneg_wait_to_complete: unused
1790 *
1791 * Configure the integrated PHY for SFP support.
1792 */
1793static int
1794ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1795 __always_unused bool autoneg_wait_to_complete)
1796{
1797 u32 reg_slice, slice_offset;
1798 bool setup_linear = false;
1799 u16 reg_phy_ext;
1800 int ret_val;
1801
1802 /* Check if SFP module is supported and linear */
1803 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1804
1805 /* If no SFP module present, then return success. Return success since
1806 * SFP not present error is not excepted in the setup MAC link flow.
1807 */
1808 if (ret_val == -ENOENT)
1809 return 0;
1810
1811 if (ret_val)
1812 return ret_val;
1813
1814 /* Configure internal PHY for KR/KX. */
1815 ixgbe_setup_kr_speed_x550em(hw, speed);
1816
1817 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1818 return -EFAULT;
1819
1820 /* Get external PHY SKU id */
1821 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1822 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1823 if (ret_val)
1824 return ret_val;
1825
1826 /* When configuring quad port CS4223, the MAC instance is part
1827 * of the slice offset.
1828 */
1829 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1830 slice_offset = (hw->bus.lan_id +
1831 (hw->bus.instance_id << 1)) << 12;
1832 else
1833 slice_offset = hw->bus.lan_id << 12;
1834
1835 /* Configure CS4227/CS4223 LINE side to proper mode. */
1836 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1837
1838 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1839 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1840 if (ret_val)
1841 return ret_val;
1842
1843 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1844 (IXGBE_CS4227_EDC_MODE_SR << 1));
1845
1846 if (setup_linear)
1847 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1848 else
1849 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1850
1851 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1852 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1853 if (ret_val)
1854 return ret_val;
1855
1856 /* Flush previous write with a read */
1857 return hw->phy.ops.read_reg(hw, reg_slice,
1858 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1859}
1860
1861/**
1862 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1863 * @hw: pointer to hardware structure
1864 * @speed: new link speed
1865 * @autoneg_wait: true when waiting for completion is needed
1866 *
1867 * Setup internal/external PHY link speed based on link speed, then set
1868 * external PHY auto advertised link speed.
1869 *
1870 * Returns error status for any failure
1871 **/
1872static int ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1873 ixgbe_link_speed speed,
1874 bool autoneg_wait)
1875{
1876 ixgbe_link_speed force_speed;
1877 int status;
1878
1879 /* Setup internal/external PHY link speed to iXFI (10G), unless
1880 * only 1G is auto advertised then setup KX link.
1881 */
1882 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1883 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1884 else
1885 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1886
1887 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1888 */
1889 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1890 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1891 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1892
1893 if (status)
1894 return status;
1895 }
1896
1897 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1898}
1899
1900/** ixgbe_check_link_t_X550em - Determine link and speed status
1901 * @hw: pointer to hardware structure
1902 * @speed: pointer to link speed
1903 * @link_up: true when link is up
1904 * @link_up_wait_to_complete: bool used to wait for link up or not
1905 *
1906 * Check that both the MAC and X557 external PHY have link.
1907 **/
1908static int ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1909 ixgbe_link_speed *speed,
1910 bool *link_up,
1911 bool link_up_wait_to_complete)
1912{
1913 u32 status;
1914 u16 i, autoneg_status;
1915
1916 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1917 return -EIO;
1918
1919 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1920 link_up_wait_to_complete);
1921
1922 /* If check link fails or MAC link is not up, then return */
1923 if (status || !(*link_up))
1924 return status;
1925
1926 /* MAC link is up, so check external PHY link.
1927 * Link status is latching low, and can only be used to detect link
1928 * drop, and not the current status of the link without performing
1929 * back-to-back reads.
1930 */
1931 for (i = 0; i < 2; i++) {
1932 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1933 &autoneg_status);
1934
1935 if (status)
1936 return status;
1937 }
1938
1939 /* If external PHY link is not up, then indicate link not up */
1940 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1941 *link_up = false;
1942
1943 return 0;
1944}
1945
1946/**
1947 * ixgbe_setup_sgmii - Set up link for sgmii
1948 * @hw: pointer to hardware structure
1949 * @speed: unused
1950 * @autoneg_wait_to_complete: unused
1951 */
1952static int
1953ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1954 __always_unused bool autoneg_wait_to_complete)
1955{
1956 struct ixgbe_mac_info *mac = &hw->mac;
1957 u32 lval, sval, flx_val;
1958 int rc;
1959
1960 rc = mac->ops.read_iosf_sb_reg(hw,
1961 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1962 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1963 if (rc)
1964 return rc;
1965
1966 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1967 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1968 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1969 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1970 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1971 rc = mac->ops.write_iosf_sb_reg(hw,
1972 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1973 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1974 if (rc)
1975 return rc;
1976
1977 rc = mac->ops.read_iosf_sb_reg(hw,
1978 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1979 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1980 if (rc)
1981 return rc;
1982
1983 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1984 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1985 rc = mac->ops.write_iosf_sb_reg(hw,
1986 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1987 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1988 if (rc)
1989 return rc;
1990
1991 rc = mac->ops.read_iosf_sb_reg(hw,
1992 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1993 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1994 if (rc)
1995 return rc;
1996
1997 rc = mac->ops.read_iosf_sb_reg(hw,
1998 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1999 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2000 if (rc)
2001 return rc;
2002
2003 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2004 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2005 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2006 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2007 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2008
2009 rc = mac->ops.write_iosf_sb_reg(hw,
2010 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2011 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2012 if (rc)
2013 return rc;
2014
2015 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2016 return rc;
2017}
2018
2019/**
2020 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2021 * @hw: pointer to hardware structure
2022 * @speed: the link speed to force
2023 * @autoneg_wait: true when waiting for completion is needed
2024 */
2025static int ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2026 bool autoneg_wait)
2027{
2028 struct ixgbe_mac_info *mac = &hw->mac;
2029 u32 lval, sval, flx_val;
2030 int rc;
2031
2032 rc = mac->ops.read_iosf_sb_reg(hw,
2033 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2034 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2035 if (rc)
2036 return rc;
2037
2038 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2039 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2040 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2041 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2042 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2043 rc = mac->ops.write_iosf_sb_reg(hw,
2044 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2045 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2046 if (rc)
2047 return rc;
2048
2049 rc = mac->ops.read_iosf_sb_reg(hw,
2050 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2051 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2052 if (rc)
2053 return rc;
2054
2055 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2056 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2057 rc = mac->ops.write_iosf_sb_reg(hw,
2058 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2059 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2060 if (rc)
2061 return rc;
2062
2063 rc = mac->ops.write_iosf_sb_reg(hw,
2064 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2065 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2066 if (rc)
2067 return rc;
2068
2069 rc = mac->ops.read_iosf_sb_reg(hw,
2070 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2071 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2072 if (rc)
2073 return rc;
2074
2075 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2076 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2077 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2078 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2079 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2080
2081 rc = mac->ops.write_iosf_sb_reg(hw,
2082 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2083 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2084 if (rc)
2085 return rc;
2086
2087 ixgbe_restart_an_internal_phy_x550em(hw);
2088
2089 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2090}
2091
2092/**
2093 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2094 * @hw: pointer to hardware structure
2095 *
2096 * Enable flow control according to IEEE clause 37.
2097 */
2098static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2099{
2100 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2101 ixgbe_link_speed speed;
2102 int status = -EIO;
2103 bool link_up;
2104
2105 /* AN should have completed when the cable was plugged in.
2106 * Look for reasons to bail out. Bail out if:
2107 * - FC autoneg is disabled, or if
2108 * - link is not up.
2109 */
2110 if (hw->fc.disable_fc_autoneg)
2111 goto out;
2112
2113 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2114 if (!link_up)
2115 goto out;
2116
2117 /* Check if auto-negotiation has completed */
2118 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2119 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2120 status = -EIO;
2121 goto out;
2122 }
2123
2124 /* Negotiate the flow control */
2125 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2126 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2127 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2128 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2129 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2130
2131out:
2132 if (!status) {
2133 hw->fc.fc_was_autonegged = true;
2134 } else {
2135 hw->fc.fc_was_autonegged = false;
2136 hw->fc.current_mode = hw->fc.requested_mode;
2137 }
2138}
2139
2140/** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2141 * @hw: pointer to hardware structure
2142 **/
2143static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2144{
2145 struct ixgbe_mac_info *mac = &hw->mac;
2146
2147 switch (mac->ops.get_media_type(hw)) {
2148 case ixgbe_media_type_fiber:
2149 mac->ops.setup_fc = NULL;
2150 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2151 break;
2152 case ixgbe_media_type_copper:
2153 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2154 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2155 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2156 break;
2157 }
2158 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2159 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2160 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2161 mac->ops.check_link = ixgbe_check_mac_link_generic;
2162 break;
2163 case ixgbe_media_type_backplane:
2164 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2165 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2166 break;
2167 default:
2168 break;
2169 }
2170}
2171
2172/** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2173 * @hw: pointer to hardware structure
2174 **/
2175static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2176{
2177 struct ixgbe_mac_info *mac = &hw->mac;
2178
2179 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2180
2181 switch (mac->ops.get_media_type(hw)) {
2182 case ixgbe_media_type_fiber:
2183 /* CS4227 does not support autoneg, so disable the laser control
2184 * functions for SFP+ fiber
2185 */
2186 mac->ops.disable_tx_laser = NULL;
2187 mac->ops.enable_tx_laser = NULL;
2188 mac->ops.flap_tx_laser = NULL;
2189 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2190 switch (hw->device_id) {
2191 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2192 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2193 break;
2194 case IXGBE_DEV_ID_X550EM_A_SFP:
2195 mac->ops.setup_mac_link =
2196 ixgbe_setup_mac_link_sfp_x550a;
2197 break;
2198 default:
2199 mac->ops.setup_mac_link =
2200 ixgbe_setup_mac_link_sfp_x550em;
2201 break;
2202 }
2203 mac->ops.set_rate_select_speed =
2204 ixgbe_set_soft_rate_select_speed;
2205 break;
2206 case ixgbe_media_type_copper:
2207 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2208 break;
2209 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2210 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2211 mac->ops.check_link = ixgbe_check_link_t_X550em;
2212 break;
2213 case ixgbe_media_type_backplane:
2214 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2215 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2216 mac->ops.setup_link = ixgbe_setup_sgmii;
2217 break;
2218 default:
2219 break;
2220 }
2221
2222 /* Additional modification for X550em_a devices */
2223 if (hw->mac.type == ixgbe_mac_x550em_a)
2224 ixgbe_init_mac_link_ops_X550em_a(hw);
2225}
2226
2227/** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2228 * @hw: pointer to hardware structure
2229 */
2230static int ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2231{
2232 bool linear;
2233 int status;
2234
2235 /* Check if SFP module is supported */
2236 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2237 if (status)
2238 return status;
2239
2240 ixgbe_init_mac_link_ops_X550em(hw);
2241 hw->phy.ops.reset = NULL;
2242
2243 return 0;
2244}
2245
2246/** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2247 * @hw: pointer to hardware structure
2248 * @speed: pointer to link speed
2249 * @autoneg: true when autoneg or autotry is enabled
2250 **/
2251static int ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2252 ixgbe_link_speed *speed,
2253 bool *autoneg)
2254{
2255 if (hw->phy.type == ixgbe_phy_fw) {
2256 *autoneg = true;
2257 *speed = hw->phy.speeds_supported;
2258 return 0;
2259 }
2260
2261 /* SFP */
2262 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2263 /* CS4227 SFP must not enable auto-negotiation */
2264 *autoneg = false;
2265
2266 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2267 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2268 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2269 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2270 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2271 return 0;
2272 }
2273
2274 /* Link capabilities are based on SFP */
2275 if (hw->phy.multispeed_fiber)
2276 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2277 IXGBE_LINK_SPEED_1GB_FULL;
2278 else
2279 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2280 } else {
2281 switch (hw->phy.type) {
2282 case ixgbe_phy_x550em_kx4:
2283 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2284 IXGBE_LINK_SPEED_2_5GB_FULL |
2285 IXGBE_LINK_SPEED_10GB_FULL;
2286 break;
2287 case ixgbe_phy_x550em_xfi:
2288 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2289 IXGBE_LINK_SPEED_10GB_FULL;
2290 break;
2291 case ixgbe_phy_ext_1g_t:
2292 case ixgbe_phy_sgmii:
2293 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2294 break;
2295 case ixgbe_phy_x550em_kr:
2296 if (hw->mac.type == ixgbe_mac_x550em_a) {
2297 /* check different backplane modes */
2298 if (hw->phy.nw_mng_if_sel &
2299 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2300 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2301 break;
2302 } else if (hw->device_id ==
2303 IXGBE_DEV_ID_X550EM_A_KR_L) {
2304 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2305 break;
2306 }
2307 }
2308 fallthrough;
2309 default:
2310 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2311 IXGBE_LINK_SPEED_1GB_FULL;
2312 break;
2313 }
2314 *autoneg = true;
2315 }
2316 return 0;
2317}
2318
2319/**
2320 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2321 * @hw: pointer to hardware structure
2322 * @lsc: pointer to boolean flag which indicates whether external Base T
2323 * PHY interrupt is lsc
2324 * @is_overtemp: indicate whether an overtemp event encountered
2325 *
2326 * Determime if external Base T PHY interrupt cause is high temperature
2327 * failure alarm or link status change.
2328 **/
2329static int ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,
2330 bool *is_overtemp)
2331{
2332 u32 status;
2333 u16 reg;
2334
2335 *is_overtemp = false;
2336 *lsc = false;
2337
2338 /* Vendor alarm triggered */
2339 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2340 MDIO_MMD_VEND1,
2341 ®);
2342
2343 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2344 return status;
2345
2346 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2347 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2348 MDIO_MMD_VEND1,
2349 ®);
2350
2351 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2352 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2353 return status;
2354
2355 /* Global alarm triggered */
2356 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2357 MDIO_MMD_VEND1,
2358 ®);
2359
2360 if (status)
2361 return status;
2362
2363 /* If high temperature failure, then return over temp error and exit */
2364 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2365 /* power down the PHY in case the PHY FW didn't already */
2366 ixgbe_set_copper_phy_power(hw, false);
2367 *is_overtemp = true;
2368 return -EIO;
2369 }
2370 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2371 /* device fault alarm triggered */
2372 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2373 MDIO_MMD_VEND1,
2374 ®);
2375 if (status)
2376 return status;
2377
2378 /* if device fault was due to high temp alarm handle and exit */
2379 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2380 /* power down the PHY in case the PHY FW didn't */
2381 ixgbe_set_copper_phy_power(hw, false);
2382 *is_overtemp = true;
2383 return -EIO;
2384 }
2385 }
2386
2387 /* Vendor alarm 2 triggered */
2388 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2389 MDIO_MMD_AN, ®);
2390
2391 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2392 return status;
2393
2394 /* link connect/disconnect event occurred */
2395 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2396 MDIO_MMD_AN, ®);
2397
2398 if (status)
2399 return status;
2400
2401 /* Indicate LSC */
2402 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2403 *lsc = true;
2404
2405 return 0;
2406}
2407
2408/**
2409 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2410 * @hw: pointer to hardware structure
2411 *
2412 * Enable link status change and temperature failure alarm for the external
2413 * Base T PHY
2414 *
2415 * Returns PHY access status
2416 **/
2417static int ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2418{
2419 bool lsc, overtemp;
2420 u32 status;
2421 u16 reg;
2422
2423 /* Clear interrupt flags */
2424 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp);
2425
2426 /* Enable link status change alarm */
2427
2428 /* Enable the LASI interrupts on X552 devices to receive notifications
2429 * of the link configurations of the external PHY and correspondingly
2430 * support the configuration of the internal iXFI link, since iXFI does
2431 * not support auto-negotiation. This is not required for X553 devices
2432 * having KR support, which performs auto-negotiations and which is used
2433 * as the internal link to the external PHY. Hence adding a check here
2434 * to avoid enabling LASI interrupts for X553 devices.
2435 */
2436 if (hw->mac.type != ixgbe_mac_x550em_a) {
2437 status = hw->phy.ops.read_reg(hw,
2438 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2439 MDIO_MMD_AN, ®);
2440 if (status)
2441 return status;
2442
2443 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2444
2445 status = hw->phy.ops.write_reg(hw,
2446 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2447 MDIO_MMD_AN, reg);
2448 if (status)
2449 return status;
2450 }
2451
2452 /* Enable high temperature failure and global fault alarms */
2453 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2454 MDIO_MMD_VEND1,
2455 ®);
2456 if (status)
2457 return status;
2458
2459 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2460 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2461
2462 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2463 MDIO_MMD_VEND1,
2464 reg);
2465 if (status)
2466 return status;
2467
2468 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2469 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2470 MDIO_MMD_VEND1,
2471 ®);
2472 if (status)
2473 return status;
2474
2475 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2476 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2477
2478 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2479 MDIO_MMD_VEND1,
2480 reg);
2481 if (status)
2482 return status;
2483
2484 /* Enable chip-wide vendor alarm */
2485 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2486 MDIO_MMD_VEND1,
2487 ®);
2488 if (status)
2489 return status;
2490
2491 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2492
2493 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2494 MDIO_MMD_VEND1,
2495 reg);
2496
2497 return status;
2498}
2499
2500/**
2501 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2502 * @hw: pointer to hardware structure
2503 * @is_overtemp: indicate whether an overtemp event encountered
2504 *
2505 * Handle external Base T PHY interrupt. If high temperature
2506 * failure alarm then return error, else if link status change
2507 * then setup internal/external PHY link
2508 **/
2509static int ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,
2510 bool *is_overtemp)
2511{
2512 struct ixgbe_phy_info *phy = &hw->phy;
2513 bool lsc;
2514 u32 status;
2515
2516 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp);
2517 if (status)
2518 return status;
2519
2520 if (lsc && phy->ops.setup_internal_link)
2521 return phy->ops.setup_internal_link(hw);
2522
2523 return 0;
2524}
2525
2526/**
2527 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2528 * @hw: pointer to hardware structure
2529 * @speed: link speed
2530 *
2531 * Configures the integrated KR PHY.
2532 **/
2533static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2534 ixgbe_link_speed speed)
2535{
2536 u32 reg_val;
2537 int status;
2538
2539 status = hw->mac.ops.read_iosf_sb_reg(hw,
2540 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2541 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2542 if (status)
2543 return status;
2544
2545 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2546 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2547 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2548
2549 /* Advertise 10G support. */
2550 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2551 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2552
2553 /* Advertise 1G support. */
2554 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2556
2557 status = hw->mac.ops.write_iosf_sb_reg(hw,
2558 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2559 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2560
2561 if (hw->mac.type == ixgbe_mac_x550em_a) {
2562 /* Set lane mode to KR auto negotiation */
2563 status = hw->mac.ops.read_iosf_sb_reg(hw,
2564 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2565 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2566
2567 if (status)
2568 return status;
2569
2570 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2571 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2572 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2573 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2574 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2575
2576 status = hw->mac.ops.write_iosf_sb_reg(hw,
2577 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2578 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2579 }
2580
2581 return ixgbe_restart_an_internal_phy_x550em(hw);
2582}
2583
2584/**
2585 * ixgbe_setup_kr_x550em - Configure the KR PHY
2586 * @hw: pointer to hardware structure
2587 **/
2588static int ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2589{
2590 /* leave link alone for 2.5G */
2591 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2592 return 0;
2593
2594 if (ixgbe_check_reset_blocked(hw))
2595 return 0;
2596
2597 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2598}
2599
2600/** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2601 * @hw: address of hardware structure
2602 * @link_up: address of boolean to indicate link status
2603 *
2604 * Returns error code if unable to get link status.
2605 **/
2606static int ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2607{
2608 u32 ret;
2609 u16 autoneg_status;
2610
2611 *link_up = false;
2612
2613 /* read this twice back to back to indicate current status */
2614 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2615 &autoneg_status);
2616 if (ret)
2617 return ret;
2618
2619 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2620 &autoneg_status);
2621 if (ret)
2622 return ret;
2623
2624 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2625
2626 return 0;
2627}
2628
2629/** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2630 * @hw: point to hardware structure
2631 *
2632 * Configures the link between the integrated KR PHY and the external X557 PHY
2633 * The driver will call this function when it gets a link status change
2634 * interrupt from the X557 PHY. This function configures the link speed
2635 * between the PHYs to match the link speed of the BASE-T link.
2636 *
2637 * A return of a non-zero value indicates an error, and the base driver should
2638 * not report link up.
2639 **/
2640static int ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2641{
2642 ixgbe_link_speed force_speed;
2643 bool link_up;
2644 u32 status;
2645 u16 speed;
2646
2647 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2648 return -EIO;
2649
2650 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2651 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2652 speed = IXGBE_LINK_SPEED_10GB_FULL |
2653 IXGBE_LINK_SPEED_1GB_FULL;
2654 return ixgbe_setup_kr_speed_x550em(hw, speed);
2655 }
2656
2657 /* If link is not up, then there is no setup necessary so return */
2658 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2659 if (status)
2660 return status;
2661
2662 if (!link_up)
2663 return 0;
2664
2665 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2666 MDIO_MMD_AN,
2667 &speed);
2668 if (status)
2669 return status;
2670
2671 /* If link is not still up, then no setup is necessary so return */
2672 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2673 if (status)
2674 return status;
2675
2676 if (!link_up)
2677 return 0;
2678
2679 /* clear everything but the speed and duplex bits */
2680 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2681
2682 switch (speed) {
2683 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2684 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2685 break;
2686 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2687 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2688 break;
2689 default:
2690 /* Internal PHY does not support anything else */
2691 return -EINVAL;
2692 }
2693
2694 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2695}
2696
2697/** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2698 * @hw: pointer to hardware structure
2699 **/
2700static int ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2701{
2702 int status;
2703
2704 status = ixgbe_reset_phy_generic(hw);
2705
2706 if (status)
2707 return status;
2708
2709 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2710 return ixgbe_enable_lasi_ext_t_x550em(hw);
2711}
2712
2713/**
2714 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2715 * @hw: pointer to hardware structure
2716 * @led_idx: led number to turn on
2717 **/
2718static int ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2719{
2720 u16 phy_data;
2721
2722 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2723 return -EINVAL;
2724
2725 /* To turn on the LED, set mode to ON. */
2726 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2727 MDIO_MMD_VEND1, &phy_data);
2728 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2729 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2730 MDIO_MMD_VEND1, phy_data);
2731
2732 return 0;
2733}
2734
2735/**
2736 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2737 * @hw: pointer to hardware structure
2738 * @led_idx: led number to turn off
2739 **/
2740static int ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2741{
2742 u16 phy_data;
2743
2744 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2745 return -EINVAL;
2746
2747 /* To turn on the LED, set mode to ON. */
2748 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2749 MDIO_MMD_VEND1, &phy_data);
2750 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2751 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2752 MDIO_MMD_VEND1, phy_data);
2753
2754 return 0;
2755}
2756
2757/**
2758 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2759 * @hw: pointer to the HW structure
2760 * @maj: driver version major number
2761 * @min: driver version minor number
2762 * @build: driver version build number
2763 * @sub: driver version sub build number
2764 * @len: length of driver_ver string
2765 * @driver_ver: driver string
2766 *
2767 * Sends driver version number to firmware through the manageability
2768 * block. On success return 0
2769 * else returns -EBUSY when encountering an error acquiring
2770 * semaphore, -EIO when command fails or -ENIVAL when incorrect
2771 * params passed.
2772 **/
2773static int ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2774 u8 build, u8 sub, u16 len,
2775 const char *driver_ver)
2776{
2777 struct ixgbe_hic_drv_info2 fw_cmd;
2778 int ret_val;
2779 int i;
2780
2781 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2782 return -EINVAL;
2783
2784 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2785 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2786 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2787 fw_cmd.port_num = (u8)hw->bus.func;
2788 fw_cmd.ver_maj = maj;
2789 fw_cmd.ver_min = min;
2790 fw_cmd.ver_build = build;
2791 fw_cmd.ver_sub = sub;
2792 fw_cmd.hdr.checksum = 0;
2793 memcpy(fw_cmd.driver_string, driver_ver, len);
2794 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2795 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2796
2797 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2798 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2799 sizeof(fw_cmd),
2800 IXGBE_HI_COMMAND_TIMEOUT,
2801 true);
2802 if (ret_val)
2803 continue;
2804
2805 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2806 FW_CEM_RESP_STATUS_SUCCESS)
2807 return -EIO;
2808 return 0;
2809 }
2810
2811 return ret_val;
2812}
2813
2814/** ixgbe_get_lcd_x550em - Determine lowest common denominator
2815 * @hw: pointer to hardware structure
2816 * @lcd_speed: pointer to lowest common link speed
2817 *
2818 * Determine lowest common link speed with link partner.
2819 **/
2820static int ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2821 ixgbe_link_speed *lcd_speed)
2822{
2823 u16 word = hw->eeprom.ctrl_word_3;
2824 u16 an_lp_status;
2825 int status;
2826
2827 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2828
2829 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2830 MDIO_MMD_AN,
2831 &an_lp_status);
2832 if (status)
2833 return status;
2834
2835 /* If link partner advertised 1G, return 1G */
2836 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2837 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2838 return 0;
2839 }
2840
2841 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2842 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2843 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2844 return 0;
2845
2846 /* Link partner not capable of lower speeds, return 10G */
2847 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2848 return 0;
2849}
2850
2851/**
2852 * ixgbe_setup_fc_x550em - Set up flow control
2853 * @hw: pointer to hardware structure
2854 */
2855static int ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2856{
2857 bool pause, asm_dir;
2858 u32 reg_val;
2859 int rc = 0;
2860
2861 /* Validate the requested mode */
2862 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2863 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2864 return -EINVAL;
2865 }
2866
2867 /* 10gig parts do not have a word in the EEPROM to determine the
2868 * default flow control setting, so we explicitly set it to full.
2869 */
2870 if (hw->fc.requested_mode == ixgbe_fc_default)
2871 hw->fc.requested_mode = ixgbe_fc_full;
2872
2873 /* Determine PAUSE and ASM_DIR bits. */
2874 switch (hw->fc.requested_mode) {
2875 case ixgbe_fc_none:
2876 pause = false;
2877 asm_dir = false;
2878 break;
2879 case ixgbe_fc_tx_pause:
2880 pause = false;
2881 asm_dir = true;
2882 break;
2883 case ixgbe_fc_rx_pause:
2884 /* Rx Flow control is enabled and Tx Flow control is
2885 * disabled by software override. Since there really
2886 * isn't a way to advertise that we are capable of RX
2887 * Pause ONLY, we will advertise that we support both
2888 * symmetric and asymmetric Rx PAUSE, as such we fall
2889 * through to the fc_full statement. Later, we will
2890 * disable the adapter's ability to send PAUSE frames.
2891 */
2892 fallthrough;
2893 case ixgbe_fc_full:
2894 pause = true;
2895 asm_dir = true;
2896 break;
2897 default:
2898 hw_err(hw, "Flow control param set incorrectly\n");
2899 return -EIO;
2900 }
2901
2902 switch (hw->device_id) {
2903 case IXGBE_DEV_ID_X550EM_X_KR:
2904 case IXGBE_DEV_ID_X550EM_A_KR:
2905 case IXGBE_DEV_ID_X550EM_A_KR_L:
2906 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2907 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2908 IXGBE_SB_IOSF_TARGET_KR_PHY,
2909 ®_val);
2910 if (rc)
2911 return rc;
2912
2913 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2914 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2915 if (pause)
2916 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2917 if (asm_dir)
2918 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2919 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2920 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2921 IXGBE_SB_IOSF_TARGET_KR_PHY,
2922 reg_val);
2923
2924 /* This device does not fully support AN. */
2925 hw->fc.disable_fc_autoneg = true;
2926 break;
2927 case IXGBE_DEV_ID_X550EM_X_XFI:
2928 hw->fc.disable_fc_autoneg = true;
2929 break;
2930 default:
2931 break;
2932 }
2933 return rc;
2934}
2935
2936/**
2937 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2938 * @hw: pointer to hardware structure
2939 **/
2940static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2941{
2942 u32 link_s1, lp_an_page_low, an_cntl_1;
2943 ixgbe_link_speed speed;
2944 int status = -EIO;
2945 bool link_up;
2946
2947 /* AN should have completed when the cable was plugged in.
2948 * Look for reasons to bail out. Bail out if:
2949 * - FC autoneg is disabled, or if
2950 * - link is not up.
2951 */
2952 if (hw->fc.disable_fc_autoneg) {
2953 hw_err(hw, "Flow control autoneg is disabled");
2954 goto out;
2955 }
2956
2957 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2958 if (!link_up) {
2959 hw_err(hw, "The link is down");
2960 goto out;
2961 }
2962
2963 /* Check at auto-negotiation has completed */
2964 status = hw->mac.ops.read_iosf_sb_reg(hw,
2965 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2966 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2967
2968 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2969 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2970 status = -EIO;
2971 goto out;
2972 }
2973
2974 /* Read the 10g AN autoc and LP ability registers and resolve
2975 * local flow control settings accordingly
2976 */
2977 status = hw->mac.ops.read_iosf_sb_reg(hw,
2978 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2979 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2980
2981 if (status) {
2982 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2983 goto out;
2984 }
2985
2986 status = hw->mac.ops.read_iosf_sb_reg(hw,
2987 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2988 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2989
2990 if (status) {
2991 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2992 goto out;
2993 }
2994
2995 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2996 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2997 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2998 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2999 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3000
3001out:
3002 if (!status) {
3003 hw->fc.fc_was_autonegged = true;
3004 } else {
3005 hw->fc.fc_was_autonegged = false;
3006 hw->fc.current_mode = hw->fc.requested_mode;
3007 }
3008}
3009
3010/**
3011 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3012 * @hw: pointer to hardware structure
3013 **/
3014static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3015{
3016 hw->fc.fc_was_autonegged = false;
3017 hw->fc.current_mode = hw->fc.requested_mode;
3018}
3019
3020/** ixgbe_enter_lplu_x550em - Transition to low power states
3021 * @hw: pointer to hardware structure
3022 *
3023 * Configures Low Power Link Up on transition to low power states
3024 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3025 * the X557 PHY immediately prior to entering LPLU.
3026 **/
3027static int ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3028{
3029 u16 an_10g_cntl_reg, autoneg_reg, speed;
3030 ixgbe_link_speed lcd_speed;
3031 u32 save_autoneg;
3032 bool link_up;
3033 int status;
3034
3035 /* If blocked by MNG FW, then don't restart AN */
3036 if (ixgbe_check_reset_blocked(hw))
3037 return 0;
3038
3039 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3040 if (status)
3041 return status;
3042
3043 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3044 &hw->eeprom.ctrl_word_3);
3045 if (status)
3046 return status;
3047
3048 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3049 * manageability disabled, then force link down by entering
3050 * low power mode.
3051 */
3052 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3053 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3054 return ixgbe_set_copper_phy_power(hw, false);
3055
3056 /* Determine LCD */
3057 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3058 if (status)
3059 return status;
3060
3061 /* If no valid LCD link speed, then force link down and exit. */
3062 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3063 return ixgbe_set_copper_phy_power(hw, false);
3064
3065 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3066 MDIO_MMD_AN,
3067 &speed);
3068 if (status)
3069 return status;
3070
3071 /* If no link now, speed is invalid so take link down */
3072 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3073 if (status)
3074 return ixgbe_set_copper_phy_power(hw, false);
3075
3076 /* clear everything but the speed bits */
3077 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3078
3079 /* If current speed is already LCD, then exit. */
3080 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3081 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3082 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3083 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3084 return 0;
3085
3086 /* Clear AN completed indication */
3087 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3088 MDIO_MMD_AN,
3089 &autoneg_reg);
3090 if (status)
3091 return status;
3092
3093 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3094 MDIO_MMD_AN,
3095 &an_10g_cntl_reg);
3096 if (status)
3097 return status;
3098
3099 status = hw->phy.ops.read_reg(hw,
3100 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3101 MDIO_MMD_AN,
3102 &autoneg_reg);
3103 if (status)
3104 return status;
3105
3106 save_autoneg = hw->phy.autoneg_advertised;
3107
3108 /* Setup link at least common link speed */
3109 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3110
3111 /* restore autoneg from before setting lplu speed */
3112 hw->phy.autoneg_advertised = save_autoneg;
3113
3114 return status;
3115}
3116
3117/**
3118 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3119 * @hw: pointer to hardware structure
3120 */
3121static int ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3122{
3123 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3124 int rc;
3125
3126 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3127 return 0;
3128
3129 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3130 if (rc)
3131 return rc;
3132 memset(store, 0, sizeof(store));
3133
3134 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3135 if (rc)
3136 return rc;
3137
3138 return ixgbe_setup_fw_link(hw);
3139}
3140
3141/**
3142 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3143 * @hw: pointer to hardware structure
3144 *
3145 * Return true when an overtemp event detected, otherwise false.
3146 */
3147static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3148{
3149 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3150 int rc;
3151
3152 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3153 if (rc)
3154 return false;
3155
3156 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3157 ixgbe_shutdown_fw_phy(hw);
3158 return true;
3159 }
3160 return false;
3161}
3162
3163/**
3164 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3165 * @hw: pointer to hardware structure
3166 *
3167 * Read NW_MNG_IF_SEL register and save field values.
3168 */
3169static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3170{
3171 /* Save NW management interface connected on board. This is used
3172 * to determine internal PHY mode.
3173 */
3174 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3175
3176 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3177 * PHY address. This register field was has only been used for X552.
3178 */
3179 if (hw->mac.type == ixgbe_mac_x550em_a &&
3180 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3181 hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
3182 hw->phy.nw_mng_if_sel);
3183 }
3184}
3185
3186/** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3187 * @hw: pointer to hardware structure
3188 *
3189 * Initialize any function pointers that were not able to be
3190 * set during init_shared_code because the PHY/SFP type was
3191 * not known. Perform the SFP init if necessary.
3192 **/
3193static int ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3194{
3195 struct ixgbe_phy_info *phy = &hw->phy;
3196 int ret_val;
3197
3198 hw->mac.ops.set_lan_id(hw);
3199
3200 ixgbe_read_mng_if_sel_x550em(hw);
3201
3202 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3203 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3204 ixgbe_setup_mux_ctl(hw);
3205 }
3206
3207 /* Identify the PHY or SFP module */
3208 ret_val = phy->ops.identify(hw);
3209 if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)
3210 return ret_val;
3211
3212 /* Setup function pointers based on detected hardware */
3213 ixgbe_init_mac_link_ops_X550em(hw);
3214 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3215 phy->ops.reset = NULL;
3216
3217 /* Set functions pointers based on phy type */
3218 switch (hw->phy.type) {
3219 case ixgbe_phy_x550em_kx4:
3220 phy->ops.setup_link = NULL;
3221 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3222 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3223 break;
3224 case ixgbe_phy_x550em_kr:
3225 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3226 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3227 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3228 break;
3229 case ixgbe_phy_x550em_xfi:
3230 /* link is managed by HW */
3231 phy->ops.setup_link = NULL;
3232 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3233 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3234 break;
3235 case ixgbe_phy_x550em_ext_t:
3236 /* Save NW management interface connected on board. This is used
3237 * to determine internal PHY mode
3238 */
3239 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3240
3241 /* If internal link mode is XFI, then setup iXFI internal link,
3242 * else setup KR now.
3243 */
3244 phy->ops.setup_internal_link =
3245 ixgbe_setup_internal_phy_t_x550em;
3246
3247 /* setup SW LPLU only for first revision */
3248 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3249 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3250 IXGBE_FUSES0_REV_MASK))
3251 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3252
3253 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3254 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3255 break;
3256 case ixgbe_phy_sgmii:
3257 phy->ops.setup_link = NULL;
3258 break;
3259 case ixgbe_phy_fw:
3260 phy->ops.setup_link = ixgbe_setup_fw_link;
3261 phy->ops.reset = ixgbe_reset_phy_fw;
3262 break;
3263 case ixgbe_phy_ext_1g_t:
3264 phy->ops.setup_link = NULL;
3265 phy->ops.read_reg = NULL;
3266 phy->ops.write_reg = NULL;
3267 phy->ops.reset = NULL;
3268 break;
3269 default:
3270 break;
3271 }
3272
3273 return ret_val;
3274}
3275
3276/** ixgbe_get_media_type_X550em - Get media type
3277 * @hw: pointer to hardware structure
3278 *
3279 * Returns the media type (fiber, copper, backplane)
3280 *
3281 */
3282static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3283{
3284 enum ixgbe_media_type media_type;
3285
3286 /* Detect if there is a copper PHY attached. */
3287 switch (hw->device_id) {
3288 case IXGBE_DEV_ID_X550EM_A_SGMII:
3289 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3290 hw->phy.type = ixgbe_phy_sgmii;
3291 fallthrough;
3292 case IXGBE_DEV_ID_X550EM_X_KR:
3293 case IXGBE_DEV_ID_X550EM_X_KX4:
3294 case IXGBE_DEV_ID_X550EM_X_XFI:
3295 case IXGBE_DEV_ID_X550EM_A_KR:
3296 case IXGBE_DEV_ID_X550EM_A_KR_L:
3297 media_type = ixgbe_media_type_backplane;
3298 break;
3299 case IXGBE_DEV_ID_X550EM_X_SFP:
3300 case IXGBE_DEV_ID_X550EM_A_SFP:
3301 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3302 media_type = ixgbe_media_type_fiber;
3303 break;
3304 case IXGBE_DEV_ID_X550EM_X_1G_T:
3305 case IXGBE_DEV_ID_X550EM_X_10G_T:
3306 case IXGBE_DEV_ID_X550EM_A_10G_T:
3307 case IXGBE_DEV_ID_X550EM_A_1G_T:
3308 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3309 media_type = ixgbe_media_type_copper;
3310 break;
3311 default:
3312 media_type = ixgbe_media_type_unknown;
3313 break;
3314 }
3315 return media_type;
3316}
3317
3318/** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3319 ** @hw: pointer to hardware structure
3320 **/
3321static int ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3322{
3323 int status;
3324 u16 reg;
3325
3326 status = hw->phy.ops.read_reg(hw,
3327 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3328 MDIO_MMD_PMAPMD,
3329 ®);
3330 if (status)
3331 return status;
3332
3333 /* If PHY FW reset completed bit is set then this is the first
3334 * SW instance after a power on so the PHY FW must be un-stalled.
3335 */
3336 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3337 status = hw->phy.ops.read_reg(hw,
3338 IXGBE_MDIO_GLOBAL_RES_PR_10,
3339 MDIO_MMD_VEND1,
3340 ®);
3341 if (status)
3342 return status;
3343
3344 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3345
3346 status = hw->phy.ops.write_reg(hw,
3347 IXGBE_MDIO_GLOBAL_RES_PR_10,
3348 MDIO_MMD_VEND1,
3349 reg);
3350 if (status)
3351 return status;
3352 }
3353
3354 return status;
3355}
3356
3357/**
3358 * ixgbe_set_mdio_speed - Set MDIO clock speed
3359 * @hw: pointer to hardware structure
3360 */
3361static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3362{
3363 u32 hlreg0;
3364
3365 switch (hw->device_id) {
3366 case IXGBE_DEV_ID_X550EM_X_10G_T:
3367 case IXGBE_DEV_ID_X550EM_A_SGMII:
3368 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3369 case IXGBE_DEV_ID_X550EM_A_10G_T:
3370 case IXGBE_DEV_ID_X550EM_A_SFP:
3371 /* Config MDIO clock speed before the first MDIO PHY access */
3372 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3373 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3374 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3375 break;
3376 case IXGBE_DEV_ID_X550EM_A_1G_T:
3377 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3378 /* Select fast MDIO clock speed for these devices */
3379 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3380 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3381 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3382 break;
3383 default:
3384 break;
3385 }
3386}
3387
3388/** ixgbe_reset_hw_X550em - Perform hardware reset
3389 ** @hw: pointer to hardware structure
3390 **
3391 ** Resets the hardware by resetting the transmit and receive units, masks
3392 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3393 ** reset.
3394 **/
3395static int ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3396{
3397 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3398 ixgbe_link_speed link_speed;
3399 bool link_up = false;
3400 u32 ctrl = 0;
3401 int status;
3402 u32 i;
3403
3404 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3405 status = hw->mac.ops.stop_adapter(hw);
3406 if (status)
3407 return status;
3408
3409 /* flush pending Tx transactions */
3410 ixgbe_clear_tx_pending(hw);
3411
3412 /* set MDIO speed before talking to the PHY in case it's the 1st time */
3413 ixgbe_set_mdio_speed(hw);
3414
3415 /* PHY ops must be identified and initialized prior to reset */
3416 status = hw->phy.ops.init(hw);
3417 if (status == -EOPNOTSUPP || status == -EFAULT)
3418 return status;
3419
3420 /* start the external PHY */
3421 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3422 status = ixgbe_init_ext_t_x550em(hw);
3423 if (status)
3424 return status;
3425 }
3426
3427 /* Setup SFP module if there is one present. */
3428 if (hw->phy.sfp_setup_needed) {
3429 status = hw->mac.ops.setup_sfp(hw);
3430 hw->phy.sfp_setup_needed = false;
3431 }
3432
3433 if (status == -EOPNOTSUPP)
3434 return status;
3435
3436 /* Reset PHY */
3437 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3438 hw->phy.ops.reset(hw);
3439
3440mac_reset_top:
3441 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3442 * If link reset is used when link is up, it might reset the PHY when
3443 * mng is using it. If link is down or the flag to force full link
3444 * reset is set, then perform link reset.
3445 */
3446 ctrl = IXGBE_CTRL_LNK_RST;
3447
3448 if (!hw->force_full_reset) {
3449 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3450 if (link_up)
3451 ctrl = IXGBE_CTRL_RST;
3452 }
3453
3454 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3455 if (status) {
3456 hw_dbg(hw, "semaphore failed with %d", status);
3457 return -EBUSY;
3458 }
3459
3460 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3461 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3462 IXGBE_WRITE_FLUSH(hw);
3463 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3464 usleep_range(1000, 1200);
3465
3466 /* Poll for reset bit to self-clear meaning reset is complete */
3467 for (i = 0; i < 10; i++) {
3468 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3469 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3470 break;
3471 udelay(1);
3472 }
3473
3474 if (ctrl & IXGBE_CTRL_RST_MASK) {
3475 status = -EIO;
3476 hw_dbg(hw, "Reset polling failed to complete.\n");
3477 }
3478
3479 msleep(50);
3480
3481 /* Double resets are required for recovery from certain error
3482 * clear the multicast table. Also reset num_rar_entries to 128,
3483 * since we modify this value when programming the SAN MAC address.
3484 */
3485 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3486 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3487 goto mac_reset_top;
3488 }
3489
3490 /* Store the permanent mac address */
3491 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3492
3493 /* Store MAC address from RAR0, clear receive address registers, and
3494 * clear the multicast table. Also reset num_rar_entries to 128,
3495 * since we modify this value when programming the SAN MAC address.
3496 */
3497 hw->mac.num_rar_entries = 128;
3498 hw->mac.ops.init_rx_addrs(hw);
3499
3500 ixgbe_set_mdio_speed(hw);
3501
3502 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3503 ixgbe_setup_mux_ctl(hw);
3504
3505 return status;
3506}
3507
3508/** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3509 * anti-spoofing
3510 * @hw: pointer to hardware structure
3511 * @enable: enable or disable switch for Ethertype anti-spoofing
3512 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3513 **/
3514static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3515 bool enable, int vf)
3516{
3517 int vf_target_reg = vf >> 3;
3518 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3519 u32 pfvfspoof;
3520
3521 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3522 if (enable)
3523 pfvfspoof |= BIT(vf_target_shift);
3524 else
3525 pfvfspoof &= ~BIT(vf_target_shift);
3526
3527 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3528}
3529
3530/** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3531 * @hw: pointer to hardware structure
3532 * @enable: enable or disable source address pruning
3533 * @pool: Rx pool to set source address pruning for
3534 **/
3535static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3536 bool enable,
3537 unsigned int pool)
3538{
3539 u64 pfflp;
3540
3541 /* max rx pool is 63 */
3542 if (pool > 63)
3543 return;
3544
3545 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3546 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3547
3548 if (enable)
3549 pfflp |= (1ULL << pool);
3550 else
3551 pfflp &= ~(1ULL << pool);
3552
3553 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3554 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3555}
3556
3557/**
3558 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3559 * @hw: pointer to hardware structure
3560 *
3561 * Called at init time to set up flow control.
3562 **/
3563static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3564{
3565 u32 an_cntl = 0;
3566 int status = 0;
3567
3568 /* Validate the requested mode */
3569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3570 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3571 return -EINVAL;
3572 }
3573
3574 if (hw->fc.requested_mode == ixgbe_fc_default)
3575 hw->fc.requested_mode = ixgbe_fc_full;
3576
3577 /* Set up the 1G and 10G flow control advertisement registers so the
3578 * HW will be able to do FC autoneg once the cable is plugged in. If
3579 * we link at 10G, the 1G advertisement is harmless and vice versa.
3580 */
3581 status = hw->mac.ops.read_iosf_sb_reg(hw,
3582 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3583 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3584
3585 if (status) {
3586 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3587 return status;
3588 }
3589
3590 /* The possible values of fc.requested_mode are:
3591 * 0: Flow control is completely disabled
3592 * 1: Rx flow control is enabled (we can receive pause frames,
3593 * but not send pause frames).
3594 * 2: Tx flow control is enabled (we can send pause frames but
3595 * we do not support receiving pause frames).
3596 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3597 * other: Invalid.
3598 */
3599 switch (hw->fc.requested_mode) {
3600 case ixgbe_fc_none:
3601 /* Flow control completely disabled by software override. */
3602 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3603 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3604 break;
3605 case ixgbe_fc_tx_pause:
3606 /* Tx Flow control is enabled, and Rx Flow control is
3607 * disabled by software override.
3608 */
3609 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3610 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3611 break;
3612 case ixgbe_fc_rx_pause:
3613 /* Rx Flow control is enabled and Tx Flow control is
3614 * disabled by software override. Since there really
3615 * isn't a way to advertise that we are capable of RX
3616 * Pause ONLY, we will advertise that we support both
3617 * symmetric and asymmetric Rx PAUSE, as such we fall
3618 * through to the fc_full statement. Later, we will
3619 * disable the adapter's ability to send PAUSE frames.
3620 */
3621 case ixgbe_fc_full:
3622 /* Flow control (both Rx and Tx) is enabled by SW override. */
3623 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3624 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3625 break;
3626 default:
3627 hw_err(hw, "Flow control param set incorrectly\n");
3628 return -EIO;
3629 }
3630
3631 status = hw->mac.ops.write_iosf_sb_reg(hw,
3632 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3633 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3634
3635 /* Restart auto-negotiation. */
3636 status = ixgbe_restart_an_internal_phy_x550em(hw);
3637
3638 return status;
3639}
3640
3641/**
3642 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3643 * @hw: pointer to hardware structure
3644 * @state: set mux if 1, clear if 0
3645 */
3646static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3647{
3648 u32 esdp;
3649
3650 if (!hw->bus.lan_id)
3651 return;
3652 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3653 if (state)
3654 esdp |= IXGBE_ESDP_SDP1;
3655 else
3656 esdp &= ~IXGBE_ESDP_SDP1;
3657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3658 IXGBE_WRITE_FLUSH(hw);
3659}
3660
3661/**
3662 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3663 * @hw: pointer to hardware structure
3664 * @mask: Mask to specify which semaphore to acquire
3665 *
3666 * Acquires the SWFW semaphore and sets the I2C MUX
3667 */
3668static int ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3669{
3670 int status;
3671
3672 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3673 if (status)
3674 return status;
3675
3676 if (mask & IXGBE_GSSR_I2C_MASK)
3677 ixgbe_set_mux(hw, 1);
3678
3679 return 0;
3680}
3681
3682/**
3683 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3684 * @hw: pointer to hardware structure
3685 * @mask: Mask to specify which semaphore to release
3686 *
3687 * Releases the SWFW semaphore and sets the I2C MUX
3688 */
3689static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3690{
3691 if (mask & IXGBE_GSSR_I2C_MASK)
3692 ixgbe_set_mux(hw, 0);
3693
3694 ixgbe_release_swfw_sync_X540(hw, mask);
3695}
3696
3697/**
3698 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3699 * @hw: pointer to hardware structure
3700 * @mask: Mask to specify which semaphore to acquire
3701 *
3702 * Acquires the SWFW semaphore and get the shared PHY token as needed
3703 */
3704static int ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3705{
3706 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3707 int retries = FW_PHY_TOKEN_RETRIES;
3708 int status;
3709
3710 while (--retries) {
3711 status = 0;
3712 if (hmask)
3713 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3714 if (status)
3715 return status;
3716 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3717 return 0;
3718
3719 status = ixgbe_get_phy_token(hw);
3720 if (!status)
3721 return 0;
3722 if (hmask)
3723 ixgbe_release_swfw_sync_X540(hw, hmask);
3724 if (status != -EAGAIN)
3725 return status;
3726 msleep(FW_PHY_TOKEN_DELAY);
3727 }
3728
3729 return status;
3730}
3731
3732/**
3733 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3734 * @hw: pointer to hardware structure
3735 * @mask: Mask to specify which semaphore to release
3736 *
3737 * Release the SWFW semaphore and puts the shared PHY token as needed
3738 */
3739static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3740{
3741 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3742
3743 if (mask & IXGBE_GSSR_TOKEN_SM)
3744 ixgbe_put_phy_token(hw);
3745
3746 if (hmask)
3747 ixgbe_release_swfw_sync_X540(hw, hmask);
3748}
3749
3750/**
3751 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3752 * @hw: pointer to hardware structure
3753 * @reg_addr: 32 bit address of PHY register to read
3754 * @device_type: 5 bit device type
3755 * @phy_data: Pointer to read data from PHY register
3756 *
3757 * Reads a value from a specified PHY register using the SWFW lock and PHY
3758 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3759 * instances.
3760 */
3761static int ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3762 u32 device_type, u16 *phy_data)
3763{
3764 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3765 int status;
3766
3767 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3768 return -EBUSY;
3769
3770 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3771
3772 hw->mac.ops.release_swfw_sync(hw, mask);
3773
3774 return status;
3775}
3776
3777/**
3778 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3779 * @hw: pointer to hardware structure
3780 * @reg_addr: 32 bit PHY register to write
3781 * @device_type: 5 bit device type
3782 * @phy_data: Data to write to the PHY register
3783 *
3784 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3785 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3786 */
3787static int ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3788 u32 device_type, u16 phy_data)
3789{
3790 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3791 int status;
3792
3793 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3794 return -EBUSY;
3795
3796 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3797 hw->mac.ops.release_swfw_sync(hw, mask);
3798
3799 return status;
3800}
3801
3802#define X550_COMMON_MAC \
3803 .init_hw = &ixgbe_init_hw_generic, \
3804 .start_hw = &ixgbe_start_hw_X540, \
3805 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3806 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3807 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3808 .get_device_caps = &ixgbe_get_device_caps_generic, \
3809 .stop_adapter = &ixgbe_stop_adapter_generic, \
3810 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3811 .read_analog_reg8 = NULL, \
3812 .write_analog_reg8 = NULL, \
3813 .set_rxpba = &ixgbe_set_rxpba_generic, \
3814 .check_link = &ixgbe_check_mac_link_generic, \
3815 .blink_led_start = &ixgbe_blink_led_start_X540, \
3816 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3817 .set_rar = &ixgbe_set_rar_generic, \
3818 .clear_rar = &ixgbe_clear_rar_generic, \
3819 .set_vmdq = &ixgbe_set_vmdq_generic, \
3820 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3821 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3822 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3823 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3824 .enable_mc = &ixgbe_enable_mc_generic, \
3825 .disable_mc = &ixgbe_disable_mc_generic, \
3826 .clear_vfta = &ixgbe_clear_vfta_generic, \
3827 .set_vfta = &ixgbe_set_vfta_generic, \
3828 .fc_enable = &ixgbe_fc_enable_generic, \
3829 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3830 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3831 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3832 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3833 .set_source_address_pruning = \
3834 &ixgbe_set_source_address_pruning_X550, \
3835 .set_ethertype_anti_spoofing = \
3836 &ixgbe_set_ethertype_anti_spoofing_X550, \
3837 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3838 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3839 .get_thermal_sensor_data = NULL, \
3840 .init_thermal_sensor_thresh = NULL, \
3841 .fw_recovery_mode = &ixgbe_fw_recovery_mode_X550, \
3842 .enable_rx = &ixgbe_enable_rx_generic, \
3843 .disable_rx = &ixgbe_disable_rx_x550, \
3844
3845static const struct ixgbe_mac_operations mac_ops_X550 = {
3846 X550_COMMON_MAC
3847 .led_on = ixgbe_led_on_generic,
3848 .led_off = ixgbe_led_off_generic,
3849 .init_led_link_act = ixgbe_init_led_link_act_generic,
3850 .reset_hw = &ixgbe_reset_hw_X540,
3851 .get_media_type = &ixgbe_get_media_type_X540,
3852 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3853 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3854 .setup_link = &ixgbe_setup_mac_link_X540,
3855 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3856 .get_bus_info = &ixgbe_get_bus_info_generic,
3857 .setup_sfp = NULL,
3858 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3859 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3860 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3861 .prot_autoc_read = prot_autoc_read_generic,
3862 .prot_autoc_write = prot_autoc_write_generic,
3863 .setup_fc = ixgbe_setup_fc_generic,
3864 .fc_autoneg = ixgbe_fc_autoneg,
3865};
3866
3867static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3868 X550_COMMON_MAC
3869 .led_on = ixgbe_led_on_t_x550em,
3870 .led_off = ixgbe_led_off_t_x550em,
3871 .init_led_link_act = ixgbe_init_led_link_act_generic,
3872 .reset_hw = &ixgbe_reset_hw_X550em,
3873 .get_media_type = &ixgbe_get_media_type_X550em,
3874 .get_san_mac_addr = NULL,
3875 .get_wwn_prefix = NULL,
3876 .setup_link = &ixgbe_setup_mac_link_X540,
3877 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3878 .get_bus_info = &ixgbe_get_bus_info_X550em,
3879 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3880 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3881 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3882 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3883 .setup_fc = NULL, /* defined later */
3884 .fc_autoneg = ixgbe_fc_autoneg,
3885 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3886 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3887};
3888
3889static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3890 X550_COMMON_MAC
3891 .led_on = NULL,
3892 .led_off = NULL,
3893 .init_led_link_act = NULL,
3894 .reset_hw = &ixgbe_reset_hw_X550em,
3895 .get_media_type = &ixgbe_get_media_type_X550em,
3896 .get_san_mac_addr = NULL,
3897 .get_wwn_prefix = NULL,
3898 .setup_link = &ixgbe_setup_mac_link_X540,
3899 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3900 .get_bus_info = &ixgbe_get_bus_info_X550em,
3901 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3902 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3903 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3904 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3905 .setup_fc = NULL,
3906 .fc_autoneg = ixgbe_fc_autoneg,
3907 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3908 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3909};
3910
3911static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3912 X550_COMMON_MAC
3913 .led_on = ixgbe_led_on_t_x550em,
3914 .led_off = ixgbe_led_off_t_x550em,
3915 .init_led_link_act = ixgbe_init_led_link_act_generic,
3916 .reset_hw = ixgbe_reset_hw_X550em,
3917 .get_media_type = ixgbe_get_media_type_X550em,
3918 .get_san_mac_addr = NULL,
3919 .get_wwn_prefix = NULL,
3920 .setup_link = &ixgbe_setup_mac_link_X540,
3921 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3922 .get_bus_info = ixgbe_get_bus_info_X550em,
3923 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3924 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3925 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3926 .setup_fc = ixgbe_setup_fc_x550em,
3927 .fc_autoneg = ixgbe_fc_autoneg,
3928 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3929 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3930};
3931
3932static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3933 X550_COMMON_MAC
3934 .led_on = ixgbe_led_on_generic,
3935 .led_off = ixgbe_led_off_generic,
3936 .init_led_link_act = ixgbe_init_led_link_act_generic,
3937 .reset_hw = ixgbe_reset_hw_X550em,
3938 .get_media_type = ixgbe_get_media_type_X550em,
3939 .get_san_mac_addr = NULL,
3940 .get_wwn_prefix = NULL,
3941 .setup_link = NULL, /* defined later */
3942 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3943 .get_bus_info = ixgbe_get_bus_info_X550em,
3944 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3945 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3946 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3947 .setup_fc = ixgbe_setup_fc_x550em,
3948 .fc_autoneg = ixgbe_fc_autoneg,
3949 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3950 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3951};
3952
3953#define X550_COMMON_EEP \
3954 .read = &ixgbe_read_ee_hostif_X550, \
3955 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3956 .write = &ixgbe_write_ee_hostif_X550, \
3957 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3958 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3959 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3960 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3961
3962static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3963 X550_COMMON_EEP
3964 .init_params = &ixgbe_init_eeprom_params_X550,
3965};
3966
3967static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3968 X550_COMMON_EEP
3969 .init_params = &ixgbe_init_eeprom_params_X540,
3970};
3971
3972#define X550_COMMON_PHY \
3973 .identify_sfp = &ixgbe_identify_module_generic, \
3974 .reset = NULL, \
3975 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3976 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3977 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3978 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3979 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3980 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3981 .setup_link = &ixgbe_setup_phy_link_generic, \
3982 .set_phy_power = NULL,
3983
3984static const struct ixgbe_phy_operations phy_ops_X550 = {
3985 X550_COMMON_PHY
3986 .check_overtemp = &ixgbe_tn_check_overtemp,
3987 .init = NULL,
3988 .identify = &ixgbe_identify_phy_generic,
3989 .read_reg = &ixgbe_read_phy_reg_generic,
3990 .write_reg = &ixgbe_write_phy_reg_generic,
3991};
3992
3993static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3994 X550_COMMON_PHY
3995 .check_overtemp = &ixgbe_tn_check_overtemp,
3996 .init = &ixgbe_init_phy_ops_X550em,
3997 .identify = &ixgbe_identify_phy_x550em,
3998 .read_reg = &ixgbe_read_phy_reg_generic,
3999 .write_reg = &ixgbe_write_phy_reg_generic,
4000};
4001
4002static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
4003 X550_COMMON_PHY
4004 .check_overtemp = NULL,
4005 .init = ixgbe_init_phy_ops_X550em,
4006 .identify = ixgbe_identify_phy_x550em,
4007 .read_reg = NULL,
4008 .write_reg = NULL,
4009 .read_reg_mdi = NULL,
4010 .write_reg_mdi = NULL,
4011};
4012
4013static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4014 X550_COMMON_PHY
4015 .check_overtemp = &ixgbe_tn_check_overtemp,
4016 .init = &ixgbe_init_phy_ops_X550em,
4017 .identify = &ixgbe_identify_phy_x550em,
4018 .read_reg = &ixgbe_read_phy_reg_x550a,
4019 .write_reg = &ixgbe_write_phy_reg_x550a,
4020 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
4021 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
4022};
4023
4024static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4025 X550_COMMON_PHY
4026 .check_overtemp = ixgbe_check_overtemp_fw,
4027 .init = ixgbe_init_phy_ops_X550em,
4028 .identify = ixgbe_identify_phy_fw,
4029 .read_reg = NULL,
4030 .write_reg = NULL,
4031 .read_reg_mdi = NULL,
4032 .write_reg_mdi = NULL,
4033};
4034
4035static const struct ixgbe_link_operations link_ops_x550em_x = {
4036 .read_link = &ixgbe_read_i2c_combined_generic,
4037 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4038 .write_link = &ixgbe_write_i2c_combined_generic,
4039 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4040};
4041
4042static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4043 IXGBE_MVALS_INIT(X550)
4044};
4045
4046static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4047 IXGBE_MVALS_INIT(X550EM_x)
4048};
4049
4050static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4051 IXGBE_MVALS_INIT(X550EM_a)
4052};
4053
4054const struct ixgbe_info ixgbe_X550_info = {
4055 .mac = ixgbe_mac_X550,
4056 .get_invariants = &ixgbe_get_invariants_X540,
4057 .mac_ops = &mac_ops_X550,
4058 .eeprom_ops = &eeprom_ops_X550,
4059 .phy_ops = &phy_ops_X550,
4060 .mbx_ops = &mbx_ops_generic,
4061 .mvals = ixgbe_mvals_X550,
4062};
4063
4064const struct ixgbe_info ixgbe_X550EM_x_info = {
4065 .mac = ixgbe_mac_X550EM_x,
4066 .get_invariants = &ixgbe_get_invariants_X550_x,
4067 .mac_ops = &mac_ops_X550EM_x,
4068 .eeprom_ops = &eeprom_ops_X550EM_x,
4069 .phy_ops = &phy_ops_X550EM_x,
4070 .mbx_ops = &mbx_ops_generic,
4071 .mvals = ixgbe_mvals_X550EM_x,
4072 .link_ops = &link_ops_x550em_x,
4073};
4074
4075const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4076 .mac = ixgbe_mac_X550EM_x,
4077 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4078 .mac_ops = &mac_ops_X550EM_x_fw,
4079 .eeprom_ops = &eeprom_ops_X550EM_x,
4080 .phy_ops = &phy_ops_x550em_x_fw,
4081 .mbx_ops = &mbx_ops_generic,
4082 .mvals = ixgbe_mvals_X550EM_x,
4083};
4084
4085const struct ixgbe_info ixgbe_x550em_a_info = {
4086 .mac = ixgbe_mac_x550em_a,
4087 .get_invariants = &ixgbe_get_invariants_X550_a,
4088 .mac_ops = &mac_ops_x550em_a,
4089 .eeprom_ops = &eeprom_ops_X550EM_x,
4090 .phy_ops = &phy_ops_x550em_a,
4091 .mbx_ops = &mbx_ops_generic,
4092 .mvals = ixgbe_mvals_x550em_a,
4093};
4094
4095const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4096 .mac = ixgbe_mac_x550em_a,
4097 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4098 .mac_ops = &mac_ops_x550em_a_fw,
4099 .eeprom_ops = &eeprom_ops_X550EM_x,
4100 .phy_ops = &phy_ops_x550em_a_fw,
4101 .mbx_ops = &mbx_ops_generic,
4102 .mvals = ixgbe_mvals_x550em_a,
4103};
1/*******************************************************************************
2 *
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 1999 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * Linux NICS <linux.nics@intel.com>
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 *
23 ******************************************************************************/
24#include "ixgbe_x540.h"
25#include "ixgbe_type.h"
26#include "ixgbe_common.h"
27#include "ixgbe_phy.h"
28
29static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
30static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
31static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
32static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
33static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
34
35static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
36{
37 struct ixgbe_mac_info *mac = &hw->mac;
38 struct ixgbe_phy_info *phy = &hw->phy;
39 struct ixgbe_link_info *link = &hw->link;
40
41 /* Start with X540 invariants, since so simular */
42 ixgbe_get_invariants_X540(hw);
43
44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
45 phy->ops.set_phy_power = NULL;
46
47 link->addr = IXGBE_CS4227;
48
49 return 0;
50}
51
52static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
53{
54 struct ixgbe_phy_info *phy = &hw->phy;
55
56 /* Start with X540 invariants, since so similar */
57 ixgbe_get_invariants_X540(hw);
58
59 phy->ops.set_phy_power = NULL;
60
61 return 0;
62}
63
64static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
65{
66 struct ixgbe_mac_info *mac = &hw->mac;
67 struct ixgbe_phy_info *phy = &hw->phy;
68
69 /* Start with X540 invariants, since so simular */
70 ixgbe_get_invariants_X540(hw);
71
72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
73 phy->ops.set_phy_power = NULL;
74
75 return 0;
76}
77
78static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
79{
80 struct ixgbe_phy_info *phy = &hw->phy;
81
82 /* Start with X540 invariants, since so similar */
83 ixgbe_get_invariants_X540(hw);
84
85 phy->ops.set_phy_power = NULL;
86
87 return 0;
88}
89
90/** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
91 * @hw: pointer to hardware structure
92 **/
93static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
94{
95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
96
97 if (hw->bus.lan_id) {
98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
99 esdp |= IXGBE_ESDP_SDP1_DIR;
100 }
101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
103 IXGBE_WRITE_FLUSH(hw);
104}
105
106/**
107 * ixgbe_read_cs4227 - Read CS4227 register
108 * @hw: pointer to hardware structure
109 * @reg: register number to write
110 * @value: pointer to receive value read
111 *
112 * Returns status code
113 */
114static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
115{
116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
117}
118
119/**
120 * ixgbe_write_cs4227 - Write CS4227 register
121 * @hw: pointer to hardware structure
122 * @reg: register number to write
123 * @value: value to write to register
124 *
125 * Returns status code
126 */
127static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
128{
129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
130}
131
132/**
133 * ixgbe_read_pe - Read register from port expander
134 * @hw: pointer to hardware structure
135 * @reg: register number to read
136 * @value: pointer to receive read value
137 *
138 * Returns status code
139 */
140static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
141{
142 s32 status;
143
144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
145 if (status)
146 hw_err(hw, "port expander access failed with %d\n", status);
147 return status;
148}
149
150/**
151 * ixgbe_write_pe - Write register to port expander
152 * @hw: pointer to hardware structure
153 * @reg: register number to write
154 * @value: value to write
155 *
156 * Returns status code
157 */
158static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
159{
160 s32 status;
161
162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
163 value);
164 if (status)
165 hw_err(hw, "port expander access failed with %d\n", status);
166 return status;
167}
168
169/**
170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
171 * @hw: pointer to hardware structure
172 *
173 * This function assumes that the caller has acquired the proper semaphore.
174 * Returns error code
175 */
176static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
177{
178 s32 status;
179 u32 retry;
180 u16 value;
181 u8 reg;
182
183 /* Trigger hard reset. */
184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
185 if (status)
186 return status;
187 reg |= IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
189 if (status)
190 return status;
191
192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
193 if (status)
194 return status;
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
197 if (status)
198 return status;
199
200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
201 if (status)
202 return status;
203 reg &= ~IXGBE_PE_BIT1;
204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
205 if (status)
206 return status;
207
208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
209
210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
211 if (status)
212 return status;
213 reg |= IXGBE_PE_BIT1;
214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
215 if (status)
216 return status;
217
218 /* Wait for the reset to complete. */
219 msleep(IXGBE_CS4227_RESET_DELAY);
220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
222 &value);
223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
224 break;
225 msleep(IXGBE_CS4227_CHECK_DELAY);
226 }
227 if (retry == IXGBE_CS4227_RETRIES) {
228 hw_err(hw, "CS4227 reset did not complete\n");
229 return IXGBE_ERR_PHY;
230 }
231
232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
234 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
235 return IXGBE_ERR_PHY;
236 }
237
238 return 0;
239}
240
241/**
242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
243 * @hw: pointer to hardware structure
244 */
245static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246{
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 s32 status;
249 u16 value;
250 u8 retry;
251
252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
254 if (status) {
255 hw_err(hw, "semaphore failed with %d\n", status);
256 msleep(IXGBE_CS4227_CHECK_DELAY);
257 continue;
258 }
259
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
263 goto out;
264
265 if (status || value != IXGBE_CS4227_RESET_PENDING)
266 break;
267
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msleep(IXGBE_CS4227_CHECK_DELAY);
271 }
272 /* If still pending, assume other instance failed. */
273 if (retry == IXGBE_CS4227_RETRIES) {
274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
275 if (status) {
276 hw_err(hw, "semaphore failed with %d\n", status);
277 return;
278 }
279 }
280
281 /* Reset the CS4227. */
282 status = ixgbe_reset_cs4227(hw);
283 if (status) {
284 hw_err(hw, "CS4227 reset failed: %d", status);
285 goto out;
286 }
287
288 /* Reset takes so long, temporarily release semaphore in case the
289 * other driver instance is waiting for the reset indication.
290 */
291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
292 IXGBE_CS4227_RESET_PENDING);
293 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
294 usleep_range(10000, 12000);
295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
296 if (status) {
297 hw_err(hw, "semaphore failed with %d", status);
298 return;
299 }
300
301 /* Record completion for next time. */
302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
303 IXGBE_CS4227_RESET_COMPLETE);
304
305out:
306 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
307 msleep(hw->eeprom.semaphore_delay);
308}
309
310/** ixgbe_identify_phy_x550em - Get PHY type based on device id
311 * @hw: pointer to hardware structure
312 *
313 * Returns error code
314 */
315static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
316{
317 switch (hw->device_id) {
318 case IXGBE_DEV_ID_X550EM_A_SFP:
319 if (hw->bus.lan_id)
320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
321 else
322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
323 return ixgbe_identify_module_generic(hw);
324 case IXGBE_DEV_ID_X550EM_X_SFP:
325 /* set up for CS4227 usage */
326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
327 ixgbe_setup_mux_ctl(hw);
328 ixgbe_check_cs4227(hw);
329 /* Fallthrough */
330 case IXGBE_DEV_ID_X550EM_A_SFP_N:
331 return ixgbe_identify_module_generic(hw);
332 case IXGBE_DEV_ID_X550EM_X_KX4:
333 hw->phy.type = ixgbe_phy_x550em_kx4;
334 break;
335 case IXGBE_DEV_ID_X550EM_X_XFI:
336 hw->phy.type = ixgbe_phy_x550em_xfi;
337 break;
338 case IXGBE_DEV_ID_X550EM_X_KR:
339 case IXGBE_DEV_ID_X550EM_A_KR:
340 case IXGBE_DEV_ID_X550EM_A_KR_L:
341 hw->phy.type = ixgbe_phy_x550em_kr;
342 break;
343 case IXGBE_DEV_ID_X550EM_A_10G_T:
344 if (hw->bus.lan_id)
345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
346 else
347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
348 /* Fallthrough */
349 case IXGBE_DEV_ID_X550EM_X_10G_T:
350 return ixgbe_identify_phy_generic(hw);
351 case IXGBE_DEV_ID_X550EM_X_1G_T:
352 hw->phy.type = ixgbe_phy_ext_1g_t;
353 break;
354 case IXGBE_DEV_ID_X550EM_A_1G_T:
355 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
356 hw->phy.type = ixgbe_phy_fw;
357 hw->phy.ops.read_reg = NULL;
358 hw->phy.ops.write_reg = NULL;
359 if (hw->bus.lan_id)
360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
361 else
362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
363 break;
364 default:
365 break;
366 }
367 return 0;
368}
369
370static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
371 u32 device_type, u16 *phy_data)
372{
373 return IXGBE_NOT_IMPLEMENTED;
374}
375
376static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
377 u32 device_type, u16 phy_data)
378{
379 return IXGBE_NOT_IMPLEMENTED;
380}
381
382/**
383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
384 * @hw: pointer to the hardware structure
385 * @addr: I2C bus address to read from
386 * @reg: I2C device register to read from
387 * @val: pointer to location to receive read value
388 *
389 * Returns an error code on error.
390 **/
391static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
392 u16 reg, u16 *val)
393{
394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
395}
396
397/**
398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
399 * @hw: pointer to the hardware structure
400 * @addr: I2C bus address to read from
401 * @reg: I2C device register to read from
402 * @val: pointer to location to receive read value
403 *
404 * Returns an error code on error.
405 **/
406static s32
407ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
408 u16 reg, u16 *val)
409{
410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
411}
412
413/**
414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
415 * @hw: pointer to the hardware structure
416 * @addr: I2C bus address to write to
417 * @reg: I2C device register to write to
418 * @val: value to write
419 *
420 * Returns an error code on error.
421 **/
422static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
423 u8 addr, u16 reg, u16 val)
424{
425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
426}
427
428/**
429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
430 * @hw: pointer to the hardware structure
431 * @addr: I2C bus address to write to
432 * @reg: I2C device register to write to
433 * @val: value to write
434 *
435 * Returns an error code on error.
436 **/
437static s32
438ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
439 u8 addr, u16 reg, u16 val)
440{
441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
442}
443
444/**
445 * ixgbe_fw_phy_activity - Perform an activity on a PHY
446 * @hw: pointer to hardware structure
447 * @activity: activity to perform
448 * @data: Pointer to 4 32-bit words of data
449 */
450s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
451 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
452{
453 union {
454 struct ixgbe_hic_phy_activity_req cmd;
455 struct ixgbe_hic_phy_activity_resp rsp;
456 } hic;
457 u16 retries = FW_PHY_ACT_RETRIES;
458 s32 rc;
459 u32 i;
460
461 do {
462 memset(&hic, 0, sizeof(hic));
463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
466 hic.cmd.port_number = hw->bus.lan_id;
467 hic.cmd.activity_id = cpu_to_le16(activity);
468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
469 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
470
471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
472 IXGBE_HI_COMMAND_TIMEOUT,
473 true);
474 if (rc)
475 return rc;
476 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
477 FW_CEM_RESP_STATUS_SUCCESS) {
478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
480 return 0;
481 }
482 usleep_range(20, 30);
483 --retries;
484 } while (retries > 0);
485
486 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
487}
488
489static const struct {
490 u16 fw_speed;
491 ixgbe_link_speed phy_speed;
492} ixgbe_fw_map[] = {
493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
499};
500
501/**
502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
503 * @hw: pointer to hardware structure
504 *
505 * Returns error code
506 */
507static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
508{
509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
510 u16 phy_speeds;
511 u16 phy_id_lo;
512 s32 rc;
513 u16 i;
514
515 if (hw->phy.id)
516 return 0;
517
518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
519 if (rc)
520 return rc;
521
522 hw->phy.speeds_supported = 0;
523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
525 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
527 }
528
529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
534 return IXGBE_ERR_PHY_ADDR_INVALID;
535
536 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
538 IXGBE_LINK_SPEED_1GB_FULL;
539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
540 return 0;
541}
542
543/**
544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
545 * @hw: pointer to hardware structure
546 *
547 * Returns error code
548 */
549static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
550{
551 if (hw->bus.lan_id)
552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
553 else
554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
555
556 hw->phy.type = ixgbe_phy_fw;
557 hw->phy.ops.read_reg = NULL;
558 hw->phy.ops.write_reg = NULL;
559 return ixgbe_get_phy_id_fw(hw);
560}
561
562/**
563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
564 * @hw: pointer to hardware structure
565 *
566 * Returns error code
567 */
568static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
569{
570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
571
572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
574}
575
576/**
577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
578 * @hw: pointer to hardware structure
579 */
580static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
581{
582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
583 s32 rc;
584 u16 i;
585
586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
587 return 0;
588
589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
591 return IXGBE_ERR_INVALID_LINK_SETTINGS;
592 }
593
594 switch (hw->fc.requested_mode) {
595 case ixgbe_fc_full:
596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
598 break;
599 case ixgbe_fc_rx_pause:
600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
602 break;
603 case ixgbe_fc_tx_pause:
604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
606 break;
607 default:
608 break;
609 }
610
611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
613 setup[0] |= ixgbe_fw_map[i].fw_speed;
614 }
615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
616
617 if (hw->phy.eee_speeds_advertised)
618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
619
620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
621 if (rc)
622 return rc;
623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
624 return IXGBE_ERR_OVERTEMP;
625 return 0;
626}
627
628/**
629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
630 * @hw: pointer to hardware structure
631 *
632 * Called at init time to set up flow control.
633 */
634static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
635{
636 if (hw->fc.requested_mode == ixgbe_fc_default)
637 hw->fc.requested_mode = ixgbe_fc_full;
638
639 return ixgbe_setup_fw_link(hw);
640}
641
642/** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
643 * @hw: pointer to hardware structure
644 *
645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
646 * ixgbe_hw struct in order to set up EEPROM access.
647 **/
648static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
649{
650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
651 u32 eec;
652 u16 eeprom_size;
653
654 if (eeprom->type == ixgbe_eeprom_uninitialized) {
655 eeprom->semaphore_delay = 10;
656 eeprom->type = ixgbe_flash;
657
658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
660 IXGBE_EEC_SIZE_SHIFT);
661 eeprom->word_size = BIT(eeprom_size +
662 IXGBE_EEPROM_WORD_SIZE_SHIFT);
663
664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
665 eeprom->type, eeprom->word_size);
666 }
667
668 return 0;
669}
670
671/**
672 * ixgbe_iosf_wait - Wait for IOSF command completion
673 * @hw: pointer to hardware structure
674 * @ctrl: pointer to location to receive final IOSF control value
675 *
676 * Return: failing status on timeout
677 *
678 * Note: ctrl can be NULL if the IOSF control register value is not needed
679 */
680static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
681{
682 u32 i, command;
683
684 /* Check every 10 usec to see if the address cycle completed.
685 * The SB IOSF BUSY bit will clear when the operation is
686 * complete.
687 */
688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
691 break;
692 udelay(10);
693 }
694 if (ctrl)
695 *ctrl = command;
696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
697 hw_dbg(hw, "IOSF wait timed out\n");
698 return IXGBE_ERR_PHY;
699 }
700
701 return 0;
702}
703
704/** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
705 * IOSF device
706 * @hw: pointer to hardware structure
707 * @reg_addr: 32 bit PHY register to write
708 * @device_type: 3 bit device type
709 * @phy_data: Pointer to read data from the register
710 **/
711static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
712 u32 device_type, u32 *data)
713{
714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
715 u32 command, error;
716 s32 ret;
717
718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
719 if (ret)
720 return ret;
721
722 ret = ixgbe_iosf_wait(hw, NULL);
723 if (ret)
724 goto out;
725
726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
728
729 /* Write IOSF control register */
730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
731
732 ret = ixgbe_iosf_wait(hw, &command);
733
734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
737 hw_dbg(hw, "Failed to read, error %x\n", error);
738 return IXGBE_ERR_PHY;
739 }
740
741 if (!ret)
742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
743
744out:
745 hw->mac.ops.release_swfw_sync(hw, gssr);
746 return ret;
747}
748
749/**
750 * ixgbe_get_phy_token - Get the token for shared PHY access
751 * @hw: Pointer to hardware structure
752 */
753static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
754{
755 struct ixgbe_hic_phy_token_req token_cmd;
756 s32 status;
757
758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
762 token_cmd.port_number = hw->bus.lan_id;
763 token_cmd.command_type = FW_PHY_TOKEN_REQ;
764 token_cmd.pad = 0;
765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
766 IXGBE_HI_COMMAND_TIMEOUT,
767 true);
768 if (status)
769 return status;
770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
771 return 0;
772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
773 return IXGBE_ERR_FW_RESP_INVALID;
774
775 return IXGBE_ERR_TOKEN_RETRY;
776}
777
778/**
779 * ixgbe_put_phy_token - Put the token for shared PHY access
780 * @hw: Pointer to hardware structure
781 */
782static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
783{
784 struct ixgbe_hic_phy_token_req token_cmd;
785 s32 status;
786
787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
791 token_cmd.port_number = hw->bus.lan_id;
792 token_cmd.command_type = FW_PHY_TOKEN_REL;
793 token_cmd.pad = 0;
794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
795 IXGBE_HI_COMMAND_TIMEOUT,
796 true);
797 if (status)
798 return status;
799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
800 return 0;
801 return IXGBE_ERR_FW_RESP_INVALID;
802}
803
804/**
805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
806 * @hw: pointer to hardware structure
807 * @reg_addr: 32 bit PHY register to write
808 * @device_type: 3 bit device type
809 * @data: Data to write to the register
810 **/
811static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
812 __always_unused u32 device_type,
813 u32 data)
814{
815 struct ixgbe_hic_internal_phy_req write_cmd;
816
817 memset(&write_cmd, 0, sizeof(write_cmd));
818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
821 write_cmd.port_number = hw->bus.lan_id;
822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
823 write_cmd.address = cpu_to_be16(reg_addr);
824 write_cmd.write_data = cpu_to_be32(data);
825
826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
827 IXGBE_HI_COMMAND_TIMEOUT, false);
828}
829
830/**
831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
832 * @hw: pointer to hardware structure
833 * @reg_addr: 32 bit PHY register to write
834 * @device_type: 3 bit device type
835 * @data: Pointer to read data from the register
836 **/
837static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
838 __always_unused u32 device_type,
839 u32 *data)
840{
841 union {
842 struct ixgbe_hic_internal_phy_req cmd;
843 struct ixgbe_hic_internal_phy_resp rsp;
844 } hic;
845 s32 status;
846
847 memset(&hic, 0, sizeof(hic));
848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
851 hic.cmd.port_number = hw->bus.lan_id;
852 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
853 hic.cmd.address = cpu_to_be16(reg_addr);
854
855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
856 IXGBE_HI_COMMAND_TIMEOUT, true);
857
858 /* Extract the register value from the response. */
859 *data = be32_to_cpu(hic.rsp.read_data);
860
861 return status;
862}
863
864/** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
865 * @hw: pointer to hardware structure
866 * @offset: offset of word in the EEPROM to read
867 * @words: number of words
868 * @data: word(s) read from the EEPROM
869 *
870 * Reads a 16 bit word(s) from the EEPROM using the hostif.
871 **/
872static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
873 u16 offset, u16 words, u16 *data)
874{
875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
876 struct ixgbe_hic_read_shadow_ram buffer;
877 u32 current_word = 0;
878 u16 words_to_read;
879 s32 status;
880 u32 i;
881
882 /* Take semaphore for the entire operation. */
883 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
884 if (status) {
885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
886 return status;
887 }
888
889 while (words) {
890 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
892 else
893 words_to_read = words;
894
895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
896 buffer.hdr.req.buf_lenh = 0;
897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
899
900 /* convert offset from words to bytes */
901 buffer.address = cpu_to_be32((offset + current_word) * 2);
902 buffer.length = cpu_to_be16(words_to_read * 2);
903 buffer.pad2 = 0;
904 buffer.pad3 = 0;
905
906 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
907 IXGBE_HI_COMMAND_TIMEOUT);
908 if (status) {
909 hw_dbg(hw, "Host interface command failed\n");
910 goto out;
911 }
912
913 for (i = 0; i < words_to_read; i++) {
914 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
915 2 * i;
916 u32 value = IXGBE_READ_REG(hw, reg);
917
918 data[current_word] = (u16)(value & 0xffff);
919 current_word++;
920 i++;
921 if (i < words_to_read) {
922 value >>= 16;
923 data[current_word] = (u16)(value & 0xffff);
924 current_word++;
925 }
926 }
927 words -= words_to_read;
928 }
929
930out:
931 hw->mac.ops.release_swfw_sync(hw, mask);
932 return status;
933}
934
935/** ixgbe_checksum_ptr_x550 - Checksum one pointer region
936 * @hw: pointer to hardware structure
937 * @ptr: pointer offset in eeprom
938 * @size: size of section pointed by ptr, if 0 first word will be used as size
939 * @csum: address of checksum to update
940 *
941 * Returns error status for any failure
942 **/
943static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
944 u16 size, u16 *csum, u16 *buffer,
945 u32 buffer_size)
946{
947 u16 buf[256];
948 s32 status;
949 u16 length, bufsz, i, start;
950 u16 *local_buffer;
951
952 bufsz = ARRAY_SIZE(buf);
953
954 /* Read a chunk at the pointer location */
955 if (!buffer) {
956 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
957 if (status) {
958 hw_dbg(hw, "Failed to read EEPROM image\n");
959 return status;
960 }
961 local_buffer = buf;
962 } else {
963 if (buffer_size < ptr)
964 return IXGBE_ERR_PARAM;
965 local_buffer = &buffer[ptr];
966 }
967
968 if (size) {
969 start = 0;
970 length = size;
971 } else {
972 start = 1;
973 length = local_buffer[0];
974
975 /* Skip pointer section if length is invalid. */
976 if (length == 0xFFFF || length == 0 ||
977 (ptr + length) >= hw->eeprom.word_size)
978 return 0;
979 }
980
981 if (buffer && ((u32)start + (u32)length > buffer_size))
982 return IXGBE_ERR_PARAM;
983
984 for (i = start; length; i++, length--) {
985 if (i == bufsz && !buffer) {
986 ptr += bufsz;
987 i = 0;
988 if (length < bufsz)
989 bufsz = length;
990
991 /* Read a chunk at the pointer location */
992 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
993 bufsz, buf);
994 if (status) {
995 hw_dbg(hw, "Failed to read EEPROM image\n");
996 return status;
997 }
998 }
999 *csum += local_buffer[i];
1000 }
1001 return 0;
1002}
1003
1004/** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1005 * @hw: pointer to hardware structure
1006 * @buffer: pointer to buffer containing calculated checksum
1007 * @buffer_size: size of buffer
1008 *
1009 * Returns a negative error code on error, or the 16-bit checksum
1010 **/
1011static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
1012 u32 buffer_size)
1013{
1014 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1015 u16 *local_buffer;
1016 s32 status;
1017 u16 checksum = 0;
1018 u16 pointer, i, size;
1019
1020 hw->eeprom.ops.init_params(hw);
1021
1022 if (!buffer) {
1023 /* Read pointer area */
1024 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1025 IXGBE_EEPROM_LAST_WORD + 1,
1026 eeprom_ptrs);
1027 if (status) {
1028 hw_dbg(hw, "Failed to read EEPROM image\n");
1029 return status;
1030 }
1031 local_buffer = eeprom_ptrs;
1032 } else {
1033 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1034 return IXGBE_ERR_PARAM;
1035 local_buffer = buffer;
1036 }
1037
1038 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1039 * checksum word itself
1040 */
1041 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1042 if (i != IXGBE_EEPROM_CHECKSUM)
1043 checksum += local_buffer[i];
1044
1045 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1046 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1047 */
1048 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1049 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1050 continue;
1051
1052 pointer = local_buffer[i];
1053
1054 /* Skip pointer section if the pointer is invalid. */
1055 if (pointer == 0xFFFF || pointer == 0 ||
1056 pointer >= hw->eeprom.word_size)
1057 continue;
1058
1059 switch (i) {
1060 case IXGBE_PCIE_GENERAL_PTR:
1061 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1062 break;
1063 case IXGBE_PCIE_CONFIG0_PTR:
1064 case IXGBE_PCIE_CONFIG1_PTR:
1065 size = IXGBE_PCIE_CONFIG_SIZE;
1066 break;
1067 default:
1068 size = 0;
1069 break;
1070 }
1071
1072 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1073 buffer, buffer_size);
1074 if (status)
1075 return status;
1076 }
1077
1078 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1079
1080 return (s32)checksum;
1081}
1082
1083/** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1084 * @hw: pointer to hardware structure
1085 *
1086 * Returns a negative error code on error, or the 16-bit checksum
1087 **/
1088static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1089{
1090 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1091}
1092
1093/** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1094 * @hw: pointer to hardware structure
1095 * @offset: offset of word in the EEPROM to read
1096 * @data: word read from the EEPROM
1097 *
1098 * Reads a 16 bit word from the EEPROM using the hostif.
1099 **/
1100static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1101{
1102 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1103 struct ixgbe_hic_read_shadow_ram buffer;
1104 s32 status;
1105
1106 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1107 buffer.hdr.req.buf_lenh = 0;
1108 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1109 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1110
1111 /* convert offset from words to bytes */
1112 buffer.address = cpu_to_be32(offset * 2);
1113 /* one word */
1114 buffer.length = cpu_to_be16(sizeof(u16));
1115
1116 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1117 if (status)
1118 return status;
1119
1120 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1121 IXGBE_HI_COMMAND_TIMEOUT);
1122 if (!status) {
1123 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1124 FW_NVM_DATA_OFFSET);
1125 }
1126
1127 hw->mac.ops.release_swfw_sync(hw, mask);
1128 return status;
1129}
1130
1131/** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1132 * @hw: pointer to hardware structure
1133 * @checksum_val: calculated checksum
1134 *
1135 * Performs checksum calculation and validates the EEPROM checksum. If the
1136 * caller does not need checksum_val, the value can be NULL.
1137 **/
1138static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1139 u16 *checksum_val)
1140{
1141 s32 status;
1142 u16 checksum;
1143 u16 read_checksum = 0;
1144
1145 /* Read the first word from the EEPROM. If this times out or fails, do
1146 * not continue or we could be in for a very long wait while every
1147 * EEPROM read fails
1148 */
1149 status = hw->eeprom.ops.read(hw, 0, &checksum);
1150 if (status) {
1151 hw_dbg(hw, "EEPROM read failed\n");
1152 return status;
1153 }
1154
1155 status = hw->eeprom.ops.calc_checksum(hw);
1156 if (status < 0)
1157 return status;
1158
1159 checksum = (u16)(status & 0xffff);
1160
1161 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1162 &read_checksum);
1163 if (status)
1164 return status;
1165
1166 /* Verify read checksum from EEPROM is the same as
1167 * calculated checksum
1168 */
1169 if (read_checksum != checksum) {
1170 status = IXGBE_ERR_EEPROM_CHECKSUM;
1171 hw_dbg(hw, "Invalid EEPROM checksum");
1172 }
1173
1174 /* If the user cares, return the calculated checksum */
1175 if (checksum_val)
1176 *checksum_val = checksum;
1177
1178 return status;
1179}
1180
1181/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1182 * @hw: pointer to hardware structure
1183 * @offset: offset of word in the EEPROM to write
1184 * @data: word write to the EEPROM
1185 *
1186 * Write a 16 bit word to the EEPROM using the hostif.
1187 **/
1188static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1189 u16 data)
1190{
1191 s32 status;
1192 struct ixgbe_hic_write_shadow_ram buffer;
1193
1194 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1195 buffer.hdr.req.buf_lenh = 0;
1196 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1197 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1198
1199 /* one word */
1200 buffer.length = cpu_to_be16(sizeof(u16));
1201 buffer.data = data;
1202 buffer.address = cpu_to_be32(offset * 2);
1203
1204 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1205 IXGBE_HI_COMMAND_TIMEOUT, false);
1206 return status;
1207}
1208
1209/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1210 * @hw: pointer to hardware structure
1211 * @offset: offset of word in the EEPROM to write
1212 * @data: word write to the EEPROM
1213 *
1214 * Write a 16 bit word to the EEPROM using the hostif.
1215 **/
1216static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1217{
1218 s32 status = 0;
1219
1220 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1221 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1222 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1223 } else {
1224 hw_dbg(hw, "write ee hostif failed to get semaphore");
1225 status = IXGBE_ERR_SWFW_SYNC;
1226 }
1227
1228 return status;
1229}
1230
1231/** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1232 * @hw: pointer to hardware structure
1233 *
1234 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1235 **/
1236static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1237{
1238 s32 status = 0;
1239 union ixgbe_hic_hdr2 buffer;
1240
1241 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1242 buffer.req.buf_lenh = 0;
1243 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1244 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1245
1246 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1247 IXGBE_HI_COMMAND_TIMEOUT, false);
1248 return status;
1249}
1250
1251/**
1252 * ixgbe_get_bus_info_X550em - Set PCI bus info
1253 * @hw: pointer to hardware structure
1254 *
1255 * Sets bus link width and speed to unknown because X550em is
1256 * not a PCI device.
1257 **/
1258static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1259{
1260 hw->bus.type = ixgbe_bus_type_internal;
1261 hw->bus.width = ixgbe_bus_width_unknown;
1262 hw->bus.speed = ixgbe_bus_speed_unknown;
1263
1264 hw->mac.ops.set_lan_id(hw);
1265
1266 return 0;
1267}
1268
1269/** ixgbe_disable_rx_x550 - Disable RX unit
1270 *
1271 * Enables the Rx DMA unit for x550
1272 **/
1273static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1274{
1275 u32 rxctrl, pfdtxgswc;
1276 s32 status;
1277 struct ixgbe_hic_disable_rxen fw_cmd;
1278
1279 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1280 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1281 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1282 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1283 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1284 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1285 hw->mac.set_lben = true;
1286 } else {
1287 hw->mac.set_lben = false;
1288 }
1289
1290 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1291 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1292 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1293 fw_cmd.port_number = hw->bus.lan_id;
1294
1295 status = ixgbe_host_interface_command(hw, &fw_cmd,
1296 sizeof(struct ixgbe_hic_disable_rxen),
1297 IXGBE_HI_COMMAND_TIMEOUT, true);
1298
1299 /* If we fail - disable RX using register write */
1300 if (status) {
1301 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1302 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1303 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1304 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1305 }
1306 }
1307 }
1308}
1309
1310/** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1311 * @hw: pointer to hardware structure
1312 *
1313 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1314 * checksum and updates the EEPROM and instructs the hardware to update
1315 * the flash.
1316 **/
1317static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1318{
1319 s32 status;
1320 u16 checksum = 0;
1321
1322 /* Read the first word from the EEPROM. If this times out or fails, do
1323 * not continue or we could be in for a very long wait while every
1324 * EEPROM read fails
1325 */
1326 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1327 if (status) {
1328 hw_dbg(hw, "EEPROM read failed\n");
1329 return status;
1330 }
1331
1332 status = ixgbe_calc_eeprom_checksum_X550(hw);
1333 if (status < 0)
1334 return status;
1335
1336 checksum = (u16)(status & 0xffff);
1337
1338 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1339 checksum);
1340 if (status)
1341 return status;
1342
1343 status = ixgbe_update_flash_X550(hw);
1344
1345 return status;
1346}
1347
1348/** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1349 * @hw: pointer to hardware structure
1350 * @offset: offset of word in the EEPROM to write
1351 * @words: number of words
1352 * @data: word(s) write to the EEPROM
1353 *
1354 *
1355 * Write a 16 bit word(s) to the EEPROM using the hostif.
1356 **/
1357static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1358 u16 offset, u16 words,
1359 u16 *data)
1360{
1361 s32 status = 0;
1362 u32 i = 0;
1363
1364 /* Take semaphore for the entire operation. */
1365 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1366 if (status) {
1367 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1368 return status;
1369 }
1370
1371 for (i = 0; i < words; i++) {
1372 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1373 data[i]);
1374 if (status) {
1375 hw_dbg(hw, "Eeprom buffered write failed\n");
1376 break;
1377 }
1378 }
1379
1380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1381
1382 return status;
1383}
1384
1385/** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1386 * IOSF device
1387 *
1388 * @hw: pointer to hardware structure
1389 * @reg_addr: 32 bit PHY register to write
1390 * @device_type: 3 bit device type
1391 * @data: Data to write to the register
1392 **/
1393static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1394 u32 device_type, u32 data)
1395{
1396 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1397 u32 command, error;
1398 s32 ret;
1399
1400 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1401 if (ret)
1402 return ret;
1403
1404 ret = ixgbe_iosf_wait(hw, NULL);
1405 if (ret)
1406 goto out;
1407
1408 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1409 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1410
1411 /* Write IOSF control register */
1412 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1413
1414 /* Write IOSF data register */
1415 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1416
1417 ret = ixgbe_iosf_wait(hw, &command);
1418
1419 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1420 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1421 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1422 hw_dbg(hw, "Failed to write, error %x\n", error);
1423 return IXGBE_ERR_PHY;
1424 }
1425
1426out:
1427 hw->mac.ops.release_swfw_sync(hw, gssr);
1428 return ret;
1429}
1430
1431/**
1432 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1433 * @hw: pointer to hardware structure
1434 *
1435 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1436 **/
1437static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1438{
1439 s32 status;
1440 u32 reg_val;
1441
1442 /* Disable training protocol FSM. */
1443 status = ixgbe_read_iosf_sb_reg_x550(hw,
1444 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1445 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1446 if (status)
1447 return status;
1448
1449 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1450 status = ixgbe_write_iosf_sb_reg_x550(hw,
1451 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1452 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1453 if (status)
1454 return status;
1455
1456 /* Disable Flex from training TXFFE. */
1457 status = ixgbe_read_iosf_sb_reg_x550(hw,
1458 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1459 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1460 if (status)
1461 return status;
1462
1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1464 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1465 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1466 status = ixgbe_write_iosf_sb_reg_x550(hw,
1467 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1468 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1469 if (status)
1470 return status;
1471
1472 status = ixgbe_read_iosf_sb_reg_x550(hw,
1473 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1474 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1475 if (status)
1476 return status;
1477
1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1479 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1480 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1481 status = ixgbe_write_iosf_sb_reg_x550(hw,
1482 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1483 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1484 if (status)
1485 return status;
1486
1487 /* Enable override for coefficients. */
1488 status = ixgbe_read_iosf_sb_reg_x550(hw,
1489 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1490 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1491 if (status)
1492 return status;
1493
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1496 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1497 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1498 status = ixgbe_write_iosf_sb_reg_x550(hw,
1499 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1500 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1501 return status;
1502}
1503
1504/**
1505 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1506 * internal PHY
1507 * @hw: pointer to hardware structure
1508 **/
1509static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1510{
1511 s32 status;
1512 u32 link_ctrl;
1513
1514 /* Restart auto-negotiation. */
1515 status = hw->mac.ops.read_iosf_sb_reg(hw,
1516 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1517 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1518
1519 if (status) {
1520 hw_dbg(hw, "Auto-negotiation did not complete\n");
1521 return status;
1522 }
1523
1524 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1525 status = hw->mac.ops.write_iosf_sb_reg(hw,
1526 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1527 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1528
1529 if (hw->mac.type == ixgbe_mac_x550em_a) {
1530 u32 flx_mask_st20;
1531
1532 /* Indicate to FW that AN restart has been asserted */
1533 status = hw->mac.ops.read_iosf_sb_reg(hw,
1534 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1535 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1536
1537 if (status) {
1538 hw_dbg(hw, "Auto-negotiation did not complete\n");
1539 return status;
1540 }
1541
1542 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1543 status = hw->mac.ops.write_iosf_sb_reg(hw,
1544 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1545 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1546 }
1547
1548 return status;
1549}
1550
1551/** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1552 * @hw: pointer to hardware structure
1553 * @speed: the link speed to force
1554 *
1555 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1556 * internal and external PHY at a specific speed, without autonegotiation.
1557 **/
1558static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1559{
1560 struct ixgbe_mac_info *mac = &hw->mac;
1561 s32 status;
1562 u32 reg_val;
1563
1564 /* iXFI is only supported with X552 */
1565 if (mac->type != ixgbe_mac_X550EM_x)
1566 return IXGBE_ERR_LINK_SETUP;
1567
1568 /* Disable AN and force speed to 10G Serial. */
1569 status = ixgbe_read_iosf_sb_reg_x550(hw,
1570 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1571 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1572 if (status)
1573 return status;
1574
1575 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1576 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1577
1578 /* Select forced link speed for internal PHY. */
1579 switch (*speed) {
1580 case IXGBE_LINK_SPEED_10GB_FULL:
1581 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1582 break;
1583 case IXGBE_LINK_SPEED_1GB_FULL:
1584 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1585 break;
1586 default:
1587 /* Other link speeds are not supported by internal KR PHY. */
1588 return IXGBE_ERR_LINK_SETUP;
1589 }
1590
1591 status = ixgbe_write_iosf_sb_reg_x550(hw,
1592 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1593 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1594 if (status)
1595 return status;
1596
1597 /* Additional configuration needed for x550em_x */
1598 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1599 status = ixgbe_setup_ixfi_x550em_x(hw);
1600 if (status)
1601 return status;
1602 }
1603
1604 /* Toggle port SW reset by AN reset. */
1605 status = ixgbe_restart_an_internal_phy_x550em(hw);
1606
1607 return status;
1608}
1609
1610/**
1611 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1612 * @hw: pointer to hardware structure
1613 * @linear: true if SFP module is linear
1614 */
1615static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1616{
1617 switch (hw->phy.sfp_type) {
1618 case ixgbe_sfp_type_not_present:
1619 return IXGBE_ERR_SFP_NOT_PRESENT;
1620 case ixgbe_sfp_type_da_cu_core0:
1621 case ixgbe_sfp_type_da_cu_core1:
1622 *linear = true;
1623 break;
1624 case ixgbe_sfp_type_srlr_core0:
1625 case ixgbe_sfp_type_srlr_core1:
1626 case ixgbe_sfp_type_da_act_lmt_core0:
1627 case ixgbe_sfp_type_da_act_lmt_core1:
1628 case ixgbe_sfp_type_1g_sx_core0:
1629 case ixgbe_sfp_type_1g_sx_core1:
1630 case ixgbe_sfp_type_1g_lx_core0:
1631 case ixgbe_sfp_type_1g_lx_core1:
1632 *linear = false;
1633 break;
1634 case ixgbe_sfp_type_unknown:
1635 case ixgbe_sfp_type_1g_cu_core0:
1636 case ixgbe_sfp_type_1g_cu_core1:
1637 default:
1638 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1639 }
1640
1641 return 0;
1642}
1643
1644/**
1645 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1646 * @hw: pointer to hardware structure
1647 * @speed: the link speed to force
1648 * @autoneg_wait_to_complete: unused
1649 *
1650 * Configures the extern PHY and the integrated KR PHY for SFP support.
1651 */
1652static s32
1653ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1654 ixgbe_link_speed speed,
1655 __always_unused bool autoneg_wait_to_complete)
1656{
1657 s32 status;
1658 u16 reg_slice, reg_val;
1659 bool setup_linear = false;
1660
1661 /* Check if SFP module is supported and linear */
1662 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1663
1664 /* If no SFP module present, then return success. Return success since
1665 * there is no reason to configure CS4227 and SFP not present error is
1666 * not accepted in the setup MAC link flow.
1667 */
1668 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1669 return 0;
1670
1671 if (status)
1672 return status;
1673
1674 /* Configure internal PHY for KR/KX. */
1675 ixgbe_setup_kr_speed_x550em(hw, speed);
1676
1677 /* Configure CS4227 LINE side to proper mode. */
1678 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1679 if (setup_linear)
1680 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1681 else
1682 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1683
1684 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1685 reg_val);
1686
1687 return status;
1688}
1689
1690/**
1691 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1692 * @hw: pointer to hardware structure
1693 * @speed: the link speed to force
1694 *
1695 * Configures the integrated PHY for native SFI mode. Used to connect the
1696 * internal PHY directly to an SFP cage, without autonegotiation.
1697 **/
1698static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1699{
1700 struct ixgbe_mac_info *mac = &hw->mac;
1701 s32 status;
1702 u32 reg_val;
1703
1704 /* Disable all AN and force speed to 10G Serial. */
1705 status = mac->ops.read_iosf_sb_reg(hw,
1706 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1707 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1708 if (status)
1709 return status;
1710
1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1712 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1713 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1714 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1715
1716 /* Select forced link speed for internal PHY. */
1717 switch (*speed) {
1718 case IXGBE_LINK_SPEED_10GB_FULL:
1719 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1720 break;
1721 case IXGBE_LINK_SPEED_1GB_FULL:
1722 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1723 break;
1724 default:
1725 /* Other link speeds are not supported by internal PHY. */
1726 return IXGBE_ERR_LINK_SETUP;
1727 }
1728
1729 status = mac->ops.write_iosf_sb_reg(hw,
1730 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1731 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1732
1733 /* Toggle port SW reset by AN reset. */
1734 status = ixgbe_restart_an_internal_phy_x550em(hw);
1735
1736 return status;
1737}
1738
1739/**
1740 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1741 * @hw: pointer to hardware structure
1742 * @speed: link speed
1743 * @autoneg_wait_to_complete: unused
1744 *
1745 * Configure the the integrated PHY for native SFP support.
1746 */
1747static s32
1748ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1749 __always_unused bool autoneg_wait_to_complete)
1750{
1751 bool setup_linear = false;
1752 u32 reg_phy_int;
1753 s32 ret_val;
1754
1755 /* Check if SFP module is supported and linear */
1756 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1757
1758 /* If no SFP module present, then return success. Return success since
1759 * SFP not present error is not excepted in the setup MAC link flow.
1760 */
1761 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1762 return 0;
1763
1764 if (ret_val)
1765 return ret_val;
1766
1767 /* Configure internal PHY for native SFI based on module type */
1768 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1769 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1770 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1771 if (ret_val)
1772 return ret_val;
1773
1774 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1775 if (!setup_linear)
1776 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1777
1778 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1779 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1780 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1781 if (ret_val)
1782 return ret_val;
1783
1784 /* Setup SFI internal link. */
1785 return ixgbe_setup_sfi_x550a(hw, &speed);
1786}
1787
1788/**
1789 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1790 * @hw: pointer to hardware structure
1791 * @speed: link speed
1792 * @autoneg_wait_to_complete: unused
1793 *
1794 * Configure the the integrated PHY for SFP support.
1795 */
1796static s32
1797ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1798 __always_unused bool autoneg_wait_to_complete)
1799{
1800 u32 reg_slice, slice_offset;
1801 bool setup_linear = false;
1802 u16 reg_phy_ext;
1803 s32 ret_val;
1804
1805 /* Check if SFP module is supported and linear */
1806 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1807
1808 /* If no SFP module present, then return success. Return success since
1809 * SFP not present error is not excepted in the setup MAC link flow.
1810 */
1811 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1812 return 0;
1813
1814 if (ret_val)
1815 return ret_val;
1816
1817 /* Configure internal PHY for KR/KX. */
1818 ixgbe_setup_kr_speed_x550em(hw, speed);
1819
1820 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1821 return IXGBE_ERR_PHY_ADDR_INVALID;
1822
1823 /* Get external PHY SKU id */
1824 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1825 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1826 if (ret_val)
1827 return ret_val;
1828
1829 /* When configuring quad port CS4223, the MAC instance is part
1830 * of the slice offset.
1831 */
1832 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1833 slice_offset = (hw->bus.lan_id +
1834 (hw->bus.instance_id << 1)) << 12;
1835 else
1836 slice_offset = hw->bus.lan_id << 12;
1837
1838 /* Configure CS4227/CS4223 LINE side to proper mode. */
1839 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1840
1841 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1842 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1843 if (ret_val)
1844 return ret_val;
1845
1846 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1847 (IXGBE_CS4227_EDC_MODE_SR << 1));
1848
1849 if (setup_linear)
1850 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1851 else
1852 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1853
1854 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1855 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1856 if (ret_val)
1857 return ret_val;
1858
1859 /* Flush previous write with a read */
1860 return hw->phy.ops.read_reg(hw, reg_slice,
1861 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1862}
1863
1864/**
1865 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1866 * @hw: pointer to hardware structure
1867 * @speed: new link speed
1868 * @autoneg_wait: true when waiting for completion is needed
1869 *
1870 * Setup internal/external PHY link speed based on link speed, then set
1871 * external PHY auto advertised link speed.
1872 *
1873 * Returns error status for any failure
1874 **/
1875static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1876 ixgbe_link_speed speed,
1877 bool autoneg_wait)
1878{
1879 s32 status;
1880 ixgbe_link_speed force_speed;
1881
1882 /* Setup internal/external PHY link speed to iXFI (10G), unless
1883 * only 1G is auto advertised then setup KX link.
1884 */
1885 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1886 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1887 else
1888 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1889
1890 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1891 */
1892 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1893 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1894 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1895
1896 if (status)
1897 return status;
1898 }
1899
1900 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1901}
1902
1903/** ixgbe_check_link_t_X550em - Determine link and speed status
1904 * @hw: pointer to hardware structure
1905 * @speed: pointer to link speed
1906 * @link_up: true when link is up
1907 * @link_up_wait_to_complete: bool used to wait for link up or not
1908 *
1909 * Check that both the MAC and X557 external PHY have link.
1910 **/
1911static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1912 ixgbe_link_speed *speed,
1913 bool *link_up,
1914 bool link_up_wait_to_complete)
1915{
1916 u32 status;
1917 u16 i, autoneg_status;
1918
1919 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1920 return IXGBE_ERR_CONFIG;
1921
1922 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1923 link_up_wait_to_complete);
1924
1925 /* If check link fails or MAC link is not up, then return */
1926 if (status || !(*link_up))
1927 return status;
1928
1929 /* MAC link is up, so check external PHY link.
1930 * Link status is latching low, and can only be used to detect link
1931 * drop, and not the current status of the link without performing
1932 * back-to-back reads.
1933 */
1934 for (i = 0; i < 2; i++) {
1935 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1936 &autoneg_status);
1937
1938 if (status)
1939 return status;
1940 }
1941
1942 /* If external PHY link is not up, then indicate link not up */
1943 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1944 *link_up = false;
1945
1946 return 0;
1947}
1948
1949/**
1950 * ixgbe_setup_sgmii - Set up link for sgmii
1951 * @hw: pointer to hardware structure
1952 * @speed: unused
1953 * @autoneg_wait_to_complete: unused
1954 */
1955static s32
1956ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1957 __always_unused bool autoneg_wait_to_complete)
1958{
1959 struct ixgbe_mac_info *mac = &hw->mac;
1960 u32 lval, sval, flx_val;
1961 s32 rc;
1962
1963 rc = mac->ops.read_iosf_sb_reg(hw,
1964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1965 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1966 if (rc)
1967 return rc;
1968
1969 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1970 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1971 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1972 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1973 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1974 rc = mac->ops.write_iosf_sb_reg(hw,
1975 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1976 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1977 if (rc)
1978 return rc;
1979
1980 rc = mac->ops.read_iosf_sb_reg(hw,
1981 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1982 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1983 if (rc)
1984 return rc;
1985
1986 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1987 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1988 rc = mac->ops.write_iosf_sb_reg(hw,
1989 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1990 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1991 if (rc)
1992 return rc;
1993
1994 rc = mac->ops.read_iosf_sb_reg(hw,
1995 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1996 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1997 if (rc)
1998 return rc;
1999
2000 rc = mac->ops.read_iosf_sb_reg(hw,
2001 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2002 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2003 if (rc)
2004 return rc;
2005
2006 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2007 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2008 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2009 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2010 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2011
2012 rc = mac->ops.write_iosf_sb_reg(hw,
2013 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2014 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2015 if (rc)
2016 return rc;
2017
2018 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2019 return rc;
2020}
2021
2022/**
2023 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2024 * @hw: pointer to hardware structure
2025 * @speed: the link speed to force
2026 * @autoneg_wait: true when waiting for completion is needed
2027 */
2028static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2029 bool autoneg_wait)
2030{
2031 struct ixgbe_mac_info *mac = &hw->mac;
2032 u32 lval, sval, flx_val;
2033 s32 rc;
2034
2035 rc = mac->ops.read_iosf_sb_reg(hw,
2036 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2037 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2038 if (rc)
2039 return rc;
2040
2041 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2042 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2043 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2044 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2045 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2046 rc = mac->ops.write_iosf_sb_reg(hw,
2047 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2048 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2049 if (rc)
2050 return rc;
2051
2052 rc = mac->ops.read_iosf_sb_reg(hw,
2053 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2054 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2055 if (rc)
2056 return rc;
2057
2058 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2059 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2060 rc = mac->ops.write_iosf_sb_reg(hw,
2061 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2062 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2063 if (rc)
2064 return rc;
2065
2066 rc = mac->ops.write_iosf_sb_reg(hw,
2067 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2068 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2069 if (rc)
2070 return rc;
2071
2072 rc = mac->ops.read_iosf_sb_reg(hw,
2073 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2074 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2075 if (rc)
2076 return rc;
2077
2078 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2079 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2080 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2081 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2082 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2083
2084 rc = mac->ops.write_iosf_sb_reg(hw,
2085 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2086 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2087 if (rc)
2088 return rc;
2089
2090 ixgbe_restart_an_internal_phy_x550em(hw);
2091
2092 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2093}
2094
2095/**
2096 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2097 * @hw: pointer to hardware structure
2098 *
2099 * Enable flow control according to IEEE clause 37.
2100 */
2101static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2102{
2103 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2104 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2105 ixgbe_link_speed speed;
2106 bool link_up;
2107
2108 /* AN should have completed when the cable was plugged in.
2109 * Look for reasons to bail out. Bail out if:
2110 * - FC autoneg is disabled, or if
2111 * - link is not up.
2112 */
2113 if (hw->fc.disable_fc_autoneg)
2114 goto out;
2115
2116 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2117 if (!link_up)
2118 goto out;
2119
2120 /* Check if auto-negotiation has completed */
2121 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2122 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2123 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2124 goto out;
2125 }
2126
2127 /* Negotiate the flow control */
2128 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2129 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2130 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2131 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2132 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2133
2134out:
2135 if (!status) {
2136 hw->fc.fc_was_autonegged = true;
2137 } else {
2138 hw->fc.fc_was_autonegged = false;
2139 hw->fc.current_mode = hw->fc.requested_mode;
2140 }
2141}
2142
2143/** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2144 * @hw: pointer to hardware structure
2145 **/
2146static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2147{
2148 struct ixgbe_mac_info *mac = &hw->mac;
2149
2150 switch (mac->ops.get_media_type(hw)) {
2151 case ixgbe_media_type_fiber:
2152 mac->ops.setup_fc = NULL;
2153 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2154 break;
2155 case ixgbe_media_type_copper:
2156 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2157 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2158 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2159 break;
2160 }
2161 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2162 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2163 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2164 mac->ops.check_link = ixgbe_check_mac_link_generic;
2165 break;
2166 case ixgbe_media_type_backplane:
2167 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2168 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2169 break;
2170 default:
2171 break;
2172 }
2173}
2174
2175/** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2176 * @hw: pointer to hardware structure
2177 **/
2178static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2179{
2180 struct ixgbe_mac_info *mac = &hw->mac;
2181
2182 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2183
2184 switch (mac->ops.get_media_type(hw)) {
2185 case ixgbe_media_type_fiber:
2186 /* CS4227 does not support autoneg, so disable the laser control
2187 * functions for SFP+ fiber
2188 */
2189 mac->ops.disable_tx_laser = NULL;
2190 mac->ops.enable_tx_laser = NULL;
2191 mac->ops.flap_tx_laser = NULL;
2192 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2193 switch (hw->device_id) {
2194 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2195 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2196 break;
2197 case IXGBE_DEV_ID_X550EM_A_SFP:
2198 mac->ops.setup_mac_link =
2199 ixgbe_setup_mac_link_sfp_x550a;
2200 break;
2201 default:
2202 mac->ops.setup_mac_link =
2203 ixgbe_setup_mac_link_sfp_x550em;
2204 break;
2205 }
2206 mac->ops.set_rate_select_speed =
2207 ixgbe_set_soft_rate_select_speed;
2208 break;
2209 case ixgbe_media_type_copper:
2210 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2211 break;
2212 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2213 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2214 mac->ops.check_link = ixgbe_check_link_t_X550em;
2215 break;
2216 case ixgbe_media_type_backplane:
2217 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2218 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2219 mac->ops.setup_link = ixgbe_setup_sgmii;
2220 break;
2221 default:
2222 break;
2223 }
2224
2225 /* Additional modification for X550em_a devices */
2226 if (hw->mac.type == ixgbe_mac_x550em_a)
2227 ixgbe_init_mac_link_ops_X550em_a(hw);
2228}
2229
2230/** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2231 * @hw: pointer to hardware structure
2232 */
2233static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2234{
2235 s32 status;
2236 bool linear;
2237
2238 /* Check if SFP module is supported */
2239 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2240 if (status)
2241 return status;
2242
2243 ixgbe_init_mac_link_ops_X550em(hw);
2244 hw->phy.ops.reset = NULL;
2245
2246 return 0;
2247}
2248
2249/** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2250 * @hw: pointer to hardware structure
2251 * @speed: pointer to link speed
2252 * @autoneg: true when autoneg or autotry is enabled
2253 **/
2254static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2255 ixgbe_link_speed *speed,
2256 bool *autoneg)
2257{
2258 if (hw->phy.type == ixgbe_phy_fw) {
2259 *autoneg = true;
2260 *speed = hw->phy.speeds_supported;
2261 return 0;
2262 }
2263
2264 /* SFP */
2265 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2266 /* CS4227 SFP must not enable auto-negotiation */
2267 *autoneg = false;
2268
2269 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2270 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
2271 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2272 return 0;
2273 }
2274
2275 /* Link capabilities are based on SFP */
2276 if (hw->phy.multispeed_fiber)
2277 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2278 IXGBE_LINK_SPEED_1GB_FULL;
2279 else
2280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2281 } else {
2282 switch (hw->phy.type) {
2283 case ixgbe_phy_x550em_kx4:
2284 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2285 IXGBE_LINK_SPEED_2_5GB_FULL |
2286 IXGBE_LINK_SPEED_10GB_FULL;
2287 break;
2288 case ixgbe_phy_x550em_xfi:
2289 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2290 IXGBE_LINK_SPEED_10GB_FULL;
2291 break;
2292 case ixgbe_phy_ext_1g_t:
2293 case ixgbe_phy_sgmii:
2294 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2295 break;
2296 case ixgbe_phy_x550em_kr:
2297 if (hw->mac.type == ixgbe_mac_x550em_a) {
2298 /* check different backplane modes */
2299 if (hw->phy.nw_mng_if_sel &
2300 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2301 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2302 break;
2303 } else if (hw->device_id ==
2304 IXGBE_DEV_ID_X550EM_A_KR_L) {
2305 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2306 break;
2307 }
2308 }
2309 /* fall through */
2310 default:
2311 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2312 IXGBE_LINK_SPEED_1GB_FULL;
2313 break;
2314 }
2315 *autoneg = true;
2316 }
2317 return 0;
2318}
2319
2320/**
2321 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2322 * @hw: pointer to hardware structure
2323 * @lsc: pointer to boolean flag which indicates whether external Base T
2324 * PHY interrupt is lsc
2325 *
2326 * Determime if external Base T PHY interrupt cause is high temperature
2327 * failure alarm or link status change.
2328 *
2329 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2330 * failure alarm, else return PHY access status.
2331 **/
2332static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2333{
2334 u32 status;
2335 u16 reg;
2336
2337 *lsc = false;
2338
2339 /* Vendor alarm triggered */
2340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2341 MDIO_MMD_VEND1,
2342 ®);
2343
2344 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2345 return status;
2346
2347 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2348 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2349 MDIO_MMD_VEND1,
2350 ®);
2351
2352 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2353 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2354 return status;
2355
2356 /* Global alarm triggered */
2357 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2358 MDIO_MMD_VEND1,
2359 ®);
2360
2361 if (status)
2362 return status;
2363
2364 /* If high temperature failure, then return over temp error and exit */
2365 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2366 /* power down the PHY in case the PHY FW didn't already */
2367 ixgbe_set_copper_phy_power(hw, false);
2368 return IXGBE_ERR_OVERTEMP;
2369 }
2370 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2371 /* device fault alarm triggered */
2372 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2373 MDIO_MMD_VEND1,
2374 ®);
2375 if (status)
2376 return status;
2377
2378 /* if device fault was due to high temp alarm handle and exit */
2379 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2380 /* power down the PHY in case the PHY FW didn't */
2381 ixgbe_set_copper_phy_power(hw, false);
2382 return IXGBE_ERR_OVERTEMP;
2383 }
2384 }
2385
2386 /* Vendor alarm 2 triggered */
2387 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2388 MDIO_MMD_AN, ®);
2389
2390 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2391 return status;
2392
2393 /* link connect/disconnect event occurred */
2394 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2395 MDIO_MMD_AN, ®);
2396
2397 if (status)
2398 return status;
2399
2400 /* Indicate LSC */
2401 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2402 *lsc = true;
2403
2404 return 0;
2405}
2406
2407/**
2408 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2409 * @hw: pointer to hardware structure
2410 *
2411 * Enable link status change and temperature failure alarm for the external
2412 * Base T PHY
2413 *
2414 * Returns PHY access status
2415 **/
2416static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2417{
2418 u32 status;
2419 u16 reg;
2420 bool lsc;
2421
2422 /* Clear interrupt flags */
2423 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2424
2425 /* Enable link status change alarm */
2426
2427 /* Enable the LASI interrupts on X552 devices to receive notifications
2428 * of the link configurations of the external PHY and correspondingly
2429 * support the configuration of the internal iXFI link, since iXFI does
2430 * not support auto-negotiation. This is not required for X553 devices
2431 * having KR support, which performs auto-negotiations and which is used
2432 * as the internal link to the external PHY. Hence adding a check here
2433 * to avoid enabling LASI interrupts for X553 devices.
2434 */
2435 if (hw->mac.type != ixgbe_mac_x550em_a) {
2436 status = hw->phy.ops.read_reg(hw,
2437 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2438 MDIO_MMD_AN, ®);
2439 if (status)
2440 return status;
2441
2442 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2443
2444 status = hw->phy.ops.write_reg(hw,
2445 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2446 MDIO_MMD_AN, reg);
2447 if (status)
2448 return status;
2449 }
2450
2451 /* Enable high temperature failure and global fault alarms */
2452 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2453 MDIO_MMD_VEND1,
2454 ®);
2455 if (status)
2456 return status;
2457
2458 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2459 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2460
2461 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2462 MDIO_MMD_VEND1,
2463 reg);
2464 if (status)
2465 return status;
2466
2467 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2468 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2469 MDIO_MMD_VEND1,
2470 ®);
2471 if (status)
2472 return status;
2473
2474 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2475 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2476
2477 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2478 MDIO_MMD_VEND1,
2479 reg);
2480 if (status)
2481 return status;
2482
2483 /* Enable chip-wide vendor alarm */
2484 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2485 MDIO_MMD_VEND1,
2486 ®);
2487 if (status)
2488 return status;
2489
2490 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2491
2492 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2493 MDIO_MMD_VEND1,
2494 reg);
2495
2496 return status;
2497}
2498
2499/**
2500 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2501 * @hw: pointer to hardware structure
2502 *
2503 * Handle external Base T PHY interrupt. If high temperature
2504 * failure alarm then return error, else if link status change
2505 * then setup internal/external PHY link
2506 *
2507 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2508 * failure alarm, else return PHY access status.
2509 **/
2510static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2511{
2512 struct ixgbe_phy_info *phy = &hw->phy;
2513 bool lsc;
2514 u32 status;
2515
2516 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2517 if (status)
2518 return status;
2519
2520 if (lsc && phy->ops.setup_internal_link)
2521 return phy->ops.setup_internal_link(hw);
2522
2523 return 0;
2524}
2525
2526/**
2527 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2528 * @hw: pointer to hardware structure
2529 * @speed: link speed
2530 *
2531 * Configures the integrated KR PHY.
2532 **/
2533static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2534 ixgbe_link_speed speed)
2535{
2536 s32 status;
2537 u32 reg_val;
2538
2539 status = hw->mac.ops.read_iosf_sb_reg(hw,
2540 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2541 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2542 if (status)
2543 return status;
2544
2545 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2546 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2547 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2548
2549 /* Advertise 10G support. */
2550 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2551 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2552
2553 /* Advertise 1G support. */
2554 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2556
2557 status = hw->mac.ops.write_iosf_sb_reg(hw,
2558 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2559 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2560
2561 if (hw->mac.type == ixgbe_mac_x550em_a) {
2562 /* Set lane mode to KR auto negotiation */
2563 status = hw->mac.ops.read_iosf_sb_reg(hw,
2564 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2565 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2566
2567 if (status)
2568 return status;
2569
2570 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2571 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2572 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2573 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2574 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2575
2576 status = hw->mac.ops.write_iosf_sb_reg(hw,
2577 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2578 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2579 }
2580
2581 return ixgbe_restart_an_internal_phy_x550em(hw);
2582}
2583
2584/**
2585 * ixgbe_setup_kr_x550em - Configure the KR PHY
2586 * @hw: pointer to hardware structure
2587 **/
2588static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2589{
2590 /* leave link alone for 2.5G */
2591 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2592 return 0;
2593
2594 if (ixgbe_check_reset_blocked(hw))
2595 return 0;
2596
2597 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2598}
2599
2600/** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2601 * @hw: address of hardware structure
2602 * @link_up: address of boolean to indicate link status
2603 *
2604 * Returns error code if unable to get link status.
2605 **/
2606static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2607{
2608 u32 ret;
2609 u16 autoneg_status;
2610
2611 *link_up = false;
2612
2613 /* read this twice back to back to indicate current status */
2614 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2615 &autoneg_status);
2616 if (ret)
2617 return ret;
2618
2619 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2620 &autoneg_status);
2621 if (ret)
2622 return ret;
2623
2624 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2625
2626 return 0;
2627}
2628
2629/** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2630 * @hw: point to hardware structure
2631 *
2632 * Configures the link between the integrated KR PHY and the external X557 PHY
2633 * The driver will call this function when it gets a link status change
2634 * interrupt from the X557 PHY. This function configures the link speed
2635 * between the PHYs to match the link speed of the BASE-T link.
2636 *
2637 * A return of a non-zero value indicates an error, and the base driver should
2638 * not report link up.
2639 **/
2640static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2641{
2642 ixgbe_link_speed force_speed;
2643 bool link_up;
2644 u32 status;
2645 u16 speed;
2646
2647 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2648 return IXGBE_ERR_CONFIG;
2649
2650 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2651 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2652 speed = IXGBE_LINK_SPEED_10GB_FULL |
2653 IXGBE_LINK_SPEED_1GB_FULL;
2654 return ixgbe_setup_kr_speed_x550em(hw, speed);
2655 }
2656
2657 /* If link is not up, then there is no setup necessary so return */
2658 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2659 if (status)
2660 return status;
2661
2662 if (!link_up)
2663 return 0;
2664
2665 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2666 MDIO_MMD_AN,
2667 &speed);
2668 if (status)
2669 return status;
2670
2671 /* If link is not still up, then no setup is necessary so return */
2672 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2673 if (status)
2674 return status;
2675
2676 if (!link_up)
2677 return 0;
2678
2679 /* clear everything but the speed and duplex bits */
2680 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2681
2682 switch (speed) {
2683 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2684 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2685 break;
2686 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2687 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2688 break;
2689 default:
2690 /* Internal PHY does not support anything else */
2691 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2692 }
2693
2694 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2695}
2696
2697/** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2698 * @hw: pointer to hardware structure
2699 **/
2700static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2701{
2702 s32 status;
2703
2704 status = ixgbe_reset_phy_generic(hw);
2705
2706 if (status)
2707 return status;
2708
2709 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2710 return ixgbe_enable_lasi_ext_t_x550em(hw);
2711}
2712
2713/**
2714 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2715 * @hw: pointer to hardware structure
2716 * @led_idx: led number to turn on
2717 **/
2718static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2719{
2720 u16 phy_data;
2721
2722 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2723 return IXGBE_ERR_PARAM;
2724
2725 /* To turn on the LED, set mode to ON. */
2726 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2727 MDIO_MMD_VEND1, &phy_data);
2728 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2729 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2730 MDIO_MMD_VEND1, phy_data);
2731
2732 return 0;
2733}
2734
2735/**
2736 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2737 * @hw: pointer to hardware structure
2738 * @led_idx: led number to turn off
2739 **/
2740static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2741{
2742 u16 phy_data;
2743
2744 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2745 return IXGBE_ERR_PARAM;
2746
2747 /* To turn on the LED, set mode to ON. */
2748 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2749 MDIO_MMD_VEND1, &phy_data);
2750 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2751 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2752 MDIO_MMD_VEND1, phy_data);
2753
2754 return 0;
2755}
2756
2757/**
2758 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2759 * @hw: pointer to the HW structure
2760 * @maj: driver version major number
2761 * @min: driver version minor number
2762 * @build: driver version build number
2763 * @sub: driver version sub build number
2764 * @len: length of driver_ver string
2765 * @driver_ver: driver string
2766 *
2767 * Sends driver version number to firmware through the manageability
2768 * block. On success return 0
2769 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
2770 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
2771 **/
2772static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2773 u8 build, u8 sub, u16 len,
2774 const char *driver_ver)
2775{
2776 struct ixgbe_hic_drv_info2 fw_cmd;
2777 s32 ret_val;
2778 int i;
2779
2780 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2781 return IXGBE_ERR_INVALID_ARGUMENT;
2782
2783 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2784 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2785 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2786 fw_cmd.port_num = (u8)hw->bus.func;
2787 fw_cmd.ver_maj = maj;
2788 fw_cmd.ver_min = min;
2789 fw_cmd.ver_build = build;
2790 fw_cmd.ver_sub = sub;
2791 fw_cmd.hdr.checksum = 0;
2792 memcpy(fw_cmd.driver_string, driver_ver, len);
2793 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2794 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2795
2796 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2797 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2798 sizeof(fw_cmd),
2799 IXGBE_HI_COMMAND_TIMEOUT,
2800 true);
2801 if (ret_val)
2802 continue;
2803
2804 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2805 FW_CEM_RESP_STATUS_SUCCESS)
2806 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
2807 return 0;
2808 }
2809
2810 return ret_val;
2811}
2812
2813/** ixgbe_get_lcd_x550em - Determine lowest common denominator
2814 * @hw: pointer to hardware structure
2815 * @lcd_speed: pointer to lowest common link speed
2816 *
2817 * Determine lowest common link speed with link partner.
2818 **/
2819static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2820 ixgbe_link_speed *lcd_speed)
2821{
2822 u16 an_lp_status;
2823 s32 status;
2824 u16 word = hw->eeprom.ctrl_word_3;
2825
2826 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2827
2828 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2829 MDIO_MMD_AN,
2830 &an_lp_status);
2831 if (status)
2832 return status;
2833
2834 /* If link partner advertised 1G, return 1G */
2835 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2836 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2837 return status;
2838 }
2839
2840 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2841 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2842 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2843 return status;
2844
2845 /* Link partner not capable of lower speeds, return 10G */
2846 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2847 return status;
2848}
2849
2850/**
2851 * ixgbe_setup_fc_x550em - Set up flow control
2852 * @hw: pointer to hardware structure
2853 */
2854static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2855{
2856 bool pause, asm_dir;
2857 u32 reg_val;
2858 s32 rc = 0;
2859
2860 /* Validate the requested mode */
2861 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2862 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2863 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2864 }
2865
2866 /* 10gig parts do not have a word in the EEPROM to determine the
2867 * default flow control setting, so we explicitly set it to full.
2868 */
2869 if (hw->fc.requested_mode == ixgbe_fc_default)
2870 hw->fc.requested_mode = ixgbe_fc_full;
2871
2872 /* Determine PAUSE and ASM_DIR bits. */
2873 switch (hw->fc.requested_mode) {
2874 case ixgbe_fc_none:
2875 pause = false;
2876 asm_dir = false;
2877 break;
2878 case ixgbe_fc_tx_pause:
2879 pause = false;
2880 asm_dir = true;
2881 break;
2882 case ixgbe_fc_rx_pause:
2883 /* Rx Flow control is enabled and Tx Flow control is
2884 * disabled by software override. Since there really
2885 * isn't a way to advertise that we are capable of RX
2886 * Pause ONLY, we will advertise that we support both
2887 * symmetric and asymmetric Rx PAUSE, as such we fall
2888 * through to the fc_full statement. Later, we will
2889 * disable the adapter's ability to send PAUSE frames.
2890 */
2891 /* Fallthrough */
2892 case ixgbe_fc_full:
2893 pause = true;
2894 asm_dir = true;
2895 break;
2896 default:
2897 hw_err(hw, "Flow control param set incorrectly\n");
2898 return IXGBE_ERR_CONFIG;
2899 }
2900
2901 switch (hw->device_id) {
2902 case IXGBE_DEV_ID_X550EM_X_KR:
2903 case IXGBE_DEV_ID_X550EM_A_KR:
2904 case IXGBE_DEV_ID_X550EM_A_KR_L:
2905 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2906 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2907 IXGBE_SB_IOSF_TARGET_KR_PHY,
2908 ®_val);
2909 if (rc)
2910 return rc;
2911
2912 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2913 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2914 if (pause)
2915 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2916 if (asm_dir)
2917 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2918 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2919 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2920 IXGBE_SB_IOSF_TARGET_KR_PHY,
2921 reg_val);
2922
2923 /* This device does not fully support AN. */
2924 hw->fc.disable_fc_autoneg = true;
2925 break;
2926 case IXGBE_DEV_ID_X550EM_X_XFI:
2927 hw->fc.disable_fc_autoneg = true;
2928 break;
2929 default:
2930 break;
2931 }
2932 return rc;
2933}
2934
2935/**
2936 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2937 * @hw: pointer to hardware structure
2938 **/
2939static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2940{
2941 u32 link_s1, lp_an_page_low, an_cntl_1;
2942 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2943 ixgbe_link_speed speed;
2944 bool link_up;
2945
2946 /* AN should have completed when the cable was plugged in.
2947 * Look for reasons to bail out. Bail out if:
2948 * - FC autoneg is disabled, or if
2949 * - link is not up.
2950 */
2951 if (hw->fc.disable_fc_autoneg) {
2952 hw_err(hw, "Flow control autoneg is disabled");
2953 goto out;
2954 }
2955
2956 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2957 if (!link_up) {
2958 hw_err(hw, "The link is down");
2959 goto out;
2960 }
2961
2962 /* Check at auto-negotiation has completed */
2963 status = hw->mac.ops.read_iosf_sb_reg(hw,
2964 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2966
2967 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2968 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2969 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2970 goto out;
2971 }
2972
2973 /* Read the 10g AN autoc and LP ability registers and resolve
2974 * local flow control settings accordingly
2975 */
2976 status = hw->mac.ops.read_iosf_sb_reg(hw,
2977 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2978 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2979
2980 if (status) {
2981 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2982 goto out;
2983 }
2984
2985 status = hw->mac.ops.read_iosf_sb_reg(hw,
2986 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2987 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2988
2989 if (status) {
2990 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2991 goto out;
2992 }
2993
2994 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2995 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2996 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2997 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2998 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
2999
3000out:
3001 if (!status) {
3002 hw->fc.fc_was_autonegged = true;
3003 } else {
3004 hw->fc.fc_was_autonegged = false;
3005 hw->fc.current_mode = hw->fc.requested_mode;
3006 }
3007}
3008
3009/**
3010 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3011 * @hw: pointer to hardware structure
3012 **/
3013static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3014{
3015 hw->fc.fc_was_autonegged = false;
3016 hw->fc.current_mode = hw->fc.requested_mode;
3017}
3018
3019/** ixgbe_enter_lplu_x550em - Transition to low power states
3020 * @hw: pointer to hardware structure
3021 *
3022 * Configures Low Power Link Up on transition to low power states
3023 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3024 * the X557 PHY immediately prior to entering LPLU.
3025 **/
3026static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3027{
3028 u16 an_10g_cntl_reg, autoneg_reg, speed;
3029 s32 status;
3030 ixgbe_link_speed lcd_speed;
3031 u32 save_autoneg;
3032 bool link_up;
3033
3034 /* If blocked by MNG FW, then don't restart AN */
3035 if (ixgbe_check_reset_blocked(hw))
3036 return 0;
3037
3038 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3039 if (status)
3040 return status;
3041
3042 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3043 &hw->eeprom.ctrl_word_3);
3044 if (status)
3045 return status;
3046
3047 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3048 * manageability disabled, then force link down by entering
3049 * low power mode.
3050 */
3051 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3052 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3053 return ixgbe_set_copper_phy_power(hw, false);
3054
3055 /* Determine LCD */
3056 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3057 if (status)
3058 return status;
3059
3060 /* If no valid LCD link speed, then force link down and exit. */
3061 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3062 return ixgbe_set_copper_phy_power(hw, false);
3063
3064 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3065 MDIO_MMD_AN,
3066 &speed);
3067 if (status)
3068 return status;
3069
3070 /* If no link now, speed is invalid so take link down */
3071 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3072 if (status)
3073 return ixgbe_set_copper_phy_power(hw, false);
3074
3075 /* clear everything but the speed bits */
3076 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3077
3078 /* If current speed is already LCD, then exit. */
3079 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3080 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3081 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3082 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3083 return status;
3084
3085 /* Clear AN completed indication */
3086 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3087 MDIO_MMD_AN,
3088 &autoneg_reg);
3089 if (status)
3090 return status;
3091
3092 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3093 MDIO_MMD_AN,
3094 &an_10g_cntl_reg);
3095 if (status)
3096 return status;
3097
3098 status = hw->phy.ops.read_reg(hw,
3099 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3100 MDIO_MMD_AN,
3101 &autoneg_reg);
3102 if (status)
3103 return status;
3104
3105 save_autoneg = hw->phy.autoneg_advertised;
3106
3107 /* Setup link at least common link speed */
3108 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3109
3110 /* restore autoneg from before setting lplu speed */
3111 hw->phy.autoneg_advertised = save_autoneg;
3112
3113 return status;
3114}
3115
3116/**
3117 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3118 * @hw: pointer to hardware structure
3119 */
3120static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3121{
3122 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3123 s32 rc;
3124
3125 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3126 return 0;
3127
3128 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3129 if (rc)
3130 return rc;
3131 memset(store, 0, sizeof(store));
3132
3133 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3134 if (rc)
3135 return rc;
3136
3137 return ixgbe_setup_fw_link(hw);
3138}
3139
3140/**
3141 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3142 * @hw: pointer to hardware structure
3143 */
3144static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3145{
3146 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3147 s32 rc;
3148
3149 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3150 if (rc)
3151 return rc;
3152
3153 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3154 ixgbe_shutdown_fw_phy(hw);
3155 return IXGBE_ERR_OVERTEMP;
3156 }
3157 return 0;
3158}
3159
3160/**
3161 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3162 * @hw: pointer to hardware structure
3163 *
3164 * Read NW_MNG_IF_SEL register and save field values.
3165 */
3166static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3167{
3168 /* Save NW management interface connected on board. This is used
3169 * to determine internal PHY mode.
3170 */
3171 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3172
3173 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3174 * PHY address. This register field was has only been used for X552.
3175 */
3176 if (hw->mac.type == ixgbe_mac_x550em_a &&
3177 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3178 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
3179 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
3180 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
3181 }
3182}
3183
3184/** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3185 * @hw: pointer to hardware structure
3186 *
3187 * Initialize any function pointers that were not able to be
3188 * set during init_shared_code because the PHY/SFP type was
3189 * not known. Perform the SFP init if necessary.
3190 **/
3191static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3192{
3193 struct ixgbe_phy_info *phy = &hw->phy;
3194 s32 ret_val;
3195
3196 hw->mac.ops.set_lan_id(hw);
3197
3198 ixgbe_read_mng_if_sel_x550em(hw);
3199
3200 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3201 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3202 ixgbe_setup_mux_ctl(hw);
3203 }
3204
3205 /* Identify the PHY or SFP module */
3206 ret_val = phy->ops.identify(hw);
3207 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
3208 ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
3209 return ret_val;
3210
3211 /* Setup function pointers based on detected hardware */
3212 ixgbe_init_mac_link_ops_X550em(hw);
3213 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3214 phy->ops.reset = NULL;
3215
3216 /* Set functions pointers based on phy type */
3217 switch (hw->phy.type) {
3218 case ixgbe_phy_x550em_kx4:
3219 phy->ops.setup_link = NULL;
3220 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3221 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3222 break;
3223 case ixgbe_phy_x550em_kr:
3224 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3225 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3226 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3227 break;
3228 case ixgbe_phy_x550em_xfi:
3229 /* link is managed by HW */
3230 phy->ops.setup_link = NULL;
3231 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3232 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3233 break;
3234 case ixgbe_phy_x550em_ext_t:
3235 /* Save NW management interface connected on board. This is used
3236 * to determine internal PHY mode
3237 */
3238 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3239
3240 /* If internal link mode is XFI, then setup iXFI internal link,
3241 * else setup KR now.
3242 */
3243 phy->ops.setup_internal_link =
3244 ixgbe_setup_internal_phy_t_x550em;
3245
3246 /* setup SW LPLU only for first revision */
3247 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3248 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3249 IXGBE_FUSES0_REV_MASK))
3250 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3251
3252 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3253 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3254 break;
3255 case ixgbe_phy_sgmii:
3256 phy->ops.setup_link = NULL;
3257 break;
3258 case ixgbe_phy_fw:
3259 phy->ops.setup_link = ixgbe_setup_fw_link;
3260 phy->ops.reset = ixgbe_reset_phy_fw;
3261 break;
3262 case ixgbe_phy_ext_1g_t:
3263 phy->ops.setup_link = NULL;
3264 phy->ops.read_reg = NULL;
3265 phy->ops.write_reg = NULL;
3266 phy->ops.reset = NULL;
3267 break;
3268 default:
3269 break;
3270 }
3271
3272 return ret_val;
3273}
3274
3275/** ixgbe_get_media_type_X550em - Get media type
3276 * @hw: pointer to hardware structure
3277 *
3278 * Returns the media type (fiber, copper, backplane)
3279 *
3280 */
3281static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3282{
3283 enum ixgbe_media_type media_type;
3284
3285 /* Detect if there is a copper PHY attached. */
3286 switch (hw->device_id) {
3287 case IXGBE_DEV_ID_X550EM_A_SGMII:
3288 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3289 hw->phy.type = ixgbe_phy_sgmii;
3290 /* Fallthrough */
3291 case IXGBE_DEV_ID_X550EM_X_KR:
3292 case IXGBE_DEV_ID_X550EM_X_KX4:
3293 case IXGBE_DEV_ID_X550EM_X_XFI:
3294 case IXGBE_DEV_ID_X550EM_A_KR:
3295 case IXGBE_DEV_ID_X550EM_A_KR_L:
3296 media_type = ixgbe_media_type_backplane;
3297 break;
3298 case IXGBE_DEV_ID_X550EM_X_SFP:
3299 case IXGBE_DEV_ID_X550EM_A_SFP:
3300 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3301 media_type = ixgbe_media_type_fiber;
3302 break;
3303 case IXGBE_DEV_ID_X550EM_X_1G_T:
3304 case IXGBE_DEV_ID_X550EM_X_10G_T:
3305 case IXGBE_DEV_ID_X550EM_A_10G_T:
3306 case IXGBE_DEV_ID_X550EM_A_1G_T:
3307 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3308 media_type = ixgbe_media_type_copper;
3309 break;
3310 default:
3311 media_type = ixgbe_media_type_unknown;
3312 break;
3313 }
3314 return media_type;
3315}
3316
3317/** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3318 ** @hw: pointer to hardware structure
3319 **/
3320static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3321{
3322 s32 status;
3323 u16 reg;
3324
3325 status = hw->phy.ops.read_reg(hw,
3326 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3327 MDIO_MMD_PMAPMD,
3328 ®);
3329 if (status)
3330 return status;
3331
3332 /* If PHY FW reset completed bit is set then this is the first
3333 * SW instance after a power on so the PHY FW must be un-stalled.
3334 */
3335 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3336 status = hw->phy.ops.read_reg(hw,
3337 IXGBE_MDIO_GLOBAL_RES_PR_10,
3338 MDIO_MMD_VEND1,
3339 ®);
3340 if (status)
3341 return status;
3342
3343 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3344
3345 status = hw->phy.ops.write_reg(hw,
3346 IXGBE_MDIO_GLOBAL_RES_PR_10,
3347 MDIO_MMD_VEND1,
3348 reg);
3349 if (status)
3350 return status;
3351 }
3352
3353 return status;
3354}
3355
3356/**
3357 * ixgbe_set_mdio_speed - Set MDIO clock speed
3358 * @hw: pointer to hardware structure
3359 */
3360static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3361{
3362 u32 hlreg0;
3363
3364 switch (hw->device_id) {
3365 case IXGBE_DEV_ID_X550EM_X_10G_T:
3366 case IXGBE_DEV_ID_X550EM_A_SGMII:
3367 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3368 case IXGBE_DEV_ID_X550EM_A_10G_T:
3369 case IXGBE_DEV_ID_X550EM_A_SFP:
3370 /* Config MDIO clock speed before the first MDIO PHY access */
3371 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3372 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3373 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3374 break;
3375 case IXGBE_DEV_ID_X550EM_A_1G_T:
3376 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3377 /* Select fast MDIO clock speed for these devices */
3378 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3379 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3380 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3381 break;
3382 default:
3383 break;
3384 }
3385}
3386
3387/** ixgbe_reset_hw_X550em - Perform hardware reset
3388 ** @hw: pointer to hardware structure
3389 **
3390 ** Resets the hardware by resetting the transmit and receive units, masks
3391 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3392 ** reset.
3393 **/
3394static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3395{
3396 ixgbe_link_speed link_speed;
3397 s32 status;
3398 u32 ctrl = 0;
3399 u32 i;
3400 bool link_up = false;
3401 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3402
3403 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3404 status = hw->mac.ops.stop_adapter(hw);
3405 if (status)
3406 return status;
3407
3408 /* flush pending Tx transactions */
3409 ixgbe_clear_tx_pending(hw);
3410
3411 /* PHY ops must be identified and initialized prior to reset */
3412 status = hw->phy.ops.init(hw);
3413 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
3414 status == IXGBE_ERR_PHY_ADDR_INVALID)
3415 return status;
3416
3417 /* start the external PHY */
3418 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3419 status = ixgbe_init_ext_t_x550em(hw);
3420 if (status)
3421 return status;
3422 }
3423
3424 /* Setup SFP module if there is one present. */
3425 if (hw->phy.sfp_setup_needed) {
3426 status = hw->mac.ops.setup_sfp(hw);
3427 hw->phy.sfp_setup_needed = false;
3428 }
3429
3430 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
3431 return status;
3432
3433 /* Reset PHY */
3434 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3435 hw->phy.ops.reset(hw);
3436
3437mac_reset_top:
3438 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3439 * If link reset is used when link is up, it might reset the PHY when
3440 * mng is using it. If link is down or the flag to force full link
3441 * reset is set, then perform link reset.
3442 */
3443 ctrl = IXGBE_CTRL_LNK_RST;
3444
3445 if (!hw->force_full_reset) {
3446 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3447 if (link_up)
3448 ctrl = IXGBE_CTRL_RST;
3449 }
3450
3451 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3452 if (status) {
3453 hw_dbg(hw, "semaphore failed with %d", status);
3454 return IXGBE_ERR_SWFW_SYNC;
3455 }
3456
3457 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3458 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3459 IXGBE_WRITE_FLUSH(hw);
3460 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3461 usleep_range(1000, 1200);
3462
3463 /* Poll for reset bit to self-clear meaning reset is complete */
3464 for (i = 0; i < 10; i++) {
3465 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3466 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3467 break;
3468 udelay(1);
3469 }
3470
3471 if (ctrl & IXGBE_CTRL_RST_MASK) {
3472 status = IXGBE_ERR_RESET_FAILED;
3473 hw_dbg(hw, "Reset polling failed to complete.\n");
3474 }
3475
3476 msleep(50);
3477
3478 /* Double resets are required for recovery from certain error
3479 * clear the multicast table. Also reset num_rar_entries to 128,
3480 * since we modify this value when programming the SAN MAC address.
3481 */
3482 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3483 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3484 goto mac_reset_top;
3485 }
3486
3487 /* Store the permanent mac address */
3488 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3489
3490 /* Store MAC address from RAR0, clear receive address registers, and
3491 * clear the multicast table. Also reset num_rar_entries to 128,
3492 * since we modify this value when programming the SAN MAC address.
3493 */
3494 hw->mac.num_rar_entries = 128;
3495 hw->mac.ops.init_rx_addrs(hw);
3496
3497 ixgbe_set_mdio_speed(hw);
3498
3499 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3500 ixgbe_setup_mux_ctl(hw);
3501
3502 return status;
3503}
3504
3505/** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3506 * anti-spoofing
3507 * @hw: pointer to hardware structure
3508 * @enable: enable or disable switch for Ethertype anti-spoofing
3509 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3510 **/
3511static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3512 bool enable, int vf)
3513{
3514 int vf_target_reg = vf >> 3;
3515 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3516 u32 pfvfspoof;
3517
3518 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3519 if (enable)
3520 pfvfspoof |= BIT(vf_target_shift);
3521 else
3522 pfvfspoof &= ~BIT(vf_target_shift);
3523
3524 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3525}
3526
3527/** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3528 * @hw: pointer to hardware structure
3529 * @enable: enable or disable source address pruning
3530 * @pool: Rx pool to set source address pruning for
3531 **/
3532static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3533 bool enable,
3534 unsigned int pool)
3535{
3536 u64 pfflp;
3537
3538 /* max rx pool is 63 */
3539 if (pool > 63)
3540 return;
3541
3542 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3543 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3544
3545 if (enable)
3546 pfflp |= (1ULL << pool);
3547 else
3548 pfflp &= ~(1ULL << pool);
3549
3550 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3551 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3552}
3553
3554/**
3555 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3556 * @hw: pointer to hardware structure
3557 *
3558 * Called at init time to set up flow control.
3559 **/
3560static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3561{
3562 s32 status = 0;
3563 u32 an_cntl = 0;
3564
3565 /* Validate the requested mode */
3566 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3567 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3568 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3569 }
3570
3571 if (hw->fc.requested_mode == ixgbe_fc_default)
3572 hw->fc.requested_mode = ixgbe_fc_full;
3573
3574 /* Set up the 1G and 10G flow control advertisement registers so the
3575 * HW will be able to do FC autoneg once the cable is plugged in. If
3576 * we link at 10G, the 1G advertisement is harmless and vice versa.
3577 */
3578 status = hw->mac.ops.read_iosf_sb_reg(hw,
3579 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3580 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3581
3582 if (status) {
3583 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3584 return status;
3585 }
3586
3587 /* The possible values of fc.requested_mode are:
3588 * 0: Flow control is completely disabled
3589 * 1: Rx flow control is enabled (we can receive pause frames,
3590 * but not send pause frames).
3591 * 2: Tx flow control is enabled (we can send pause frames but
3592 * we do not support receiving pause frames).
3593 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3594 * other: Invalid.
3595 */
3596 switch (hw->fc.requested_mode) {
3597 case ixgbe_fc_none:
3598 /* Flow control completely disabled by software override. */
3599 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3600 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3601 break;
3602 case ixgbe_fc_tx_pause:
3603 /* Tx Flow control is enabled, and Rx Flow control is
3604 * disabled by software override.
3605 */
3606 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3607 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3608 break;
3609 case ixgbe_fc_rx_pause:
3610 /* Rx Flow control is enabled and Tx Flow control is
3611 * disabled by software override. Since there really
3612 * isn't a way to advertise that we are capable of RX
3613 * Pause ONLY, we will advertise that we support both
3614 * symmetric and asymmetric Rx PAUSE, as such we fall
3615 * through to the fc_full statement. Later, we will
3616 * disable the adapter's ability to send PAUSE frames.
3617 */
3618 case ixgbe_fc_full:
3619 /* Flow control (both Rx and Tx) is enabled by SW override. */
3620 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3621 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3622 break;
3623 default:
3624 hw_err(hw, "Flow control param set incorrectly\n");
3625 return IXGBE_ERR_CONFIG;
3626 }
3627
3628 status = hw->mac.ops.write_iosf_sb_reg(hw,
3629 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3630 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3631
3632 /* Restart auto-negotiation. */
3633 status = ixgbe_restart_an_internal_phy_x550em(hw);
3634
3635 return status;
3636}
3637
3638/**
3639 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3640 * @hw: pointer to hardware structure
3641 * @state: set mux if 1, clear if 0
3642 */
3643static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3644{
3645 u32 esdp;
3646
3647 if (!hw->bus.lan_id)
3648 return;
3649 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3650 if (state)
3651 esdp |= IXGBE_ESDP_SDP1;
3652 else
3653 esdp &= ~IXGBE_ESDP_SDP1;
3654 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3655 IXGBE_WRITE_FLUSH(hw);
3656}
3657
3658/**
3659 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3660 * @hw: pointer to hardware structure
3661 * @mask: Mask to specify which semaphore to acquire
3662 *
3663 * Acquires the SWFW semaphore and sets the I2C MUX
3664 */
3665static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3666{
3667 s32 status;
3668
3669 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3670 if (status)
3671 return status;
3672
3673 if (mask & IXGBE_GSSR_I2C_MASK)
3674 ixgbe_set_mux(hw, 1);
3675
3676 return 0;
3677}
3678
3679/**
3680 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3681 * @hw: pointer to hardware structure
3682 * @mask: Mask to specify which semaphore to release
3683 *
3684 * Releases the SWFW semaphore and sets the I2C MUX
3685 */
3686static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3687{
3688 if (mask & IXGBE_GSSR_I2C_MASK)
3689 ixgbe_set_mux(hw, 0);
3690
3691 ixgbe_release_swfw_sync_X540(hw, mask);
3692}
3693
3694/**
3695 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3696 * @hw: pointer to hardware structure
3697 * @mask: Mask to specify which semaphore to acquire
3698 *
3699 * Acquires the SWFW semaphore and get the shared PHY token as needed
3700 */
3701static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3702{
3703 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3704 int retries = FW_PHY_TOKEN_RETRIES;
3705 s32 status;
3706
3707 while (--retries) {
3708 status = 0;
3709 if (hmask)
3710 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3711 if (status)
3712 return status;
3713 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3714 return 0;
3715
3716 status = ixgbe_get_phy_token(hw);
3717 if (!status)
3718 return 0;
3719 if (hmask)
3720 ixgbe_release_swfw_sync_X540(hw, hmask);
3721 if (status != IXGBE_ERR_TOKEN_RETRY)
3722 return status;
3723 msleep(FW_PHY_TOKEN_DELAY);
3724 }
3725
3726 return status;
3727}
3728
3729/**
3730 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3731 * @hw: pointer to hardware structure
3732 * @mask: Mask to specify which semaphore to release
3733 *
3734 * Release the SWFW semaphore and puts the shared PHY token as needed
3735 */
3736static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3737{
3738 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3739
3740 if (mask & IXGBE_GSSR_TOKEN_SM)
3741 ixgbe_put_phy_token(hw);
3742
3743 if (hmask)
3744 ixgbe_release_swfw_sync_X540(hw, hmask);
3745}
3746
3747/**
3748 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3749 * @hw: pointer to hardware structure
3750 * @reg_addr: 32 bit address of PHY register to read
3751 * @device_type: 5 bit device type
3752 * @phy_data: Pointer to read data from PHY register
3753 *
3754 * Reads a value from a specified PHY register using the SWFW lock and PHY
3755 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3756 * instances.
3757 */
3758static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3759 u32 device_type, u16 *phy_data)
3760{
3761 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3762 s32 status;
3763
3764 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3765 return IXGBE_ERR_SWFW_SYNC;
3766
3767 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3768
3769 hw->mac.ops.release_swfw_sync(hw, mask);
3770
3771 return status;
3772}
3773
3774/**
3775 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3776 * @hw: pointer to hardware structure
3777 * @reg_addr: 32 bit PHY register to write
3778 * @device_type: 5 bit device type
3779 * @phy_data: Data to write to the PHY register
3780 *
3781 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3782 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3783 */
3784static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3785 u32 device_type, u16 phy_data)
3786{
3787 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3788 s32 status;
3789
3790 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3791 return IXGBE_ERR_SWFW_SYNC;
3792
3793 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3794 hw->mac.ops.release_swfw_sync(hw, mask);
3795
3796 return status;
3797}
3798
3799#define X550_COMMON_MAC \
3800 .init_hw = &ixgbe_init_hw_generic, \
3801 .start_hw = &ixgbe_start_hw_X540, \
3802 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3803 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3804 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3805 .get_device_caps = &ixgbe_get_device_caps_generic, \
3806 .stop_adapter = &ixgbe_stop_adapter_generic, \
3807 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3808 .read_analog_reg8 = NULL, \
3809 .write_analog_reg8 = NULL, \
3810 .set_rxpba = &ixgbe_set_rxpba_generic, \
3811 .check_link = &ixgbe_check_mac_link_generic, \
3812 .blink_led_start = &ixgbe_blink_led_start_X540, \
3813 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3814 .set_rar = &ixgbe_set_rar_generic, \
3815 .clear_rar = &ixgbe_clear_rar_generic, \
3816 .set_vmdq = &ixgbe_set_vmdq_generic, \
3817 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3818 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3819 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3820 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3821 .enable_mc = &ixgbe_enable_mc_generic, \
3822 .disable_mc = &ixgbe_disable_mc_generic, \
3823 .clear_vfta = &ixgbe_clear_vfta_generic, \
3824 .set_vfta = &ixgbe_set_vfta_generic, \
3825 .fc_enable = &ixgbe_fc_enable_generic, \
3826 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3827 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3828 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3829 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3830 .set_source_address_pruning = \
3831 &ixgbe_set_source_address_pruning_X550, \
3832 .set_ethertype_anti_spoofing = \
3833 &ixgbe_set_ethertype_anti_spoofing_X550, \
3834 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3835 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3836 .get_thermal_sensor_data = NULL, \
3837 .init_thermal_sensor_thresh = NULL, \
3838 .enable_rx = &ixgbe_enable_rx_generic, \
3839 .disable_rx = &ixgbe_disable_rx_x550, \
3840
3841static const struct ixgbe_mac_operations mac_ops_X550 = {
3842 X550_COMMON_MAC
3843 .led_on = ixgbe_led_on_generic,
3844 .led_off = ixgbe_led_off_generic,
3845 .init_led_link_act = ixgbe_init_led_link_act_generic,
3846 .reset_hw = &ixgbe_reset_hw_X540,
3847 .get_media_type = &ixgbe_get_media_type_X540,
3848 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3849 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3850 .setup_link = &ixgbe_setup_mac_link_X540,
3851 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3852 .get_bus_info = &ixgbe_get_bus_info_generic,
3853 .setup_sfp = NULL,
3854 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3855 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3856 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3857 .prot_autoc_read = prot_autoc_read_generic,
3858 .prot_autoc_write = prot_autoc_write_generic,
3859 .setup_fc = ixgbe_setup_fc_generic,
3860 .fc_autoneg = ixgbe_fc_autoneg,
3861};
3862
3863static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3864 X550_COMMON_MAC
3865 .led_on = ixgbe_led_on_t_x550em,
3866 .led_off = ixgbe_led_off_t_x550em,
3867 .init_led_link_act = ixgbe_init_led_link_act_generic,
3868 .reset_hw = &ixgbe_reset_hw_X550em,
3869 .get_media_type = &ixgbe_get_media_type_X550em,
3870 .get_san_mac_addr = NULL,
3871 .get_wwn_prefix = NULL,
3872 .setup_link = &ixgbe_setup_mac_link_X540,
3873 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3874 .get_bus_info = &ixgbe_get_bus_info_X550em,
3875 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3876 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3877 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3878 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3879 .setup_fc = NULL, /* defined later */
3880 .fc_autoneg = ixgbe_fc_autoneg,
3881 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3882 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3883};
3884
3885static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3886 X550_COMMON_MAC
3887 .led_on = NULL,
3888 .led_off = NULL,
3889 .init_led_link_act = NULL,
3890 .reset_hw = &ixgbe_reset_hw_X550em,
3891 .get_media_type = &ixgbe_get_media_type_X550em,
3892 .get_san_mac_addr = NULL,
3893 .get_wwn_prefix = NULL,
3894 .setup_link = &ixgbe_setup_mac_link_X540,
3895 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3896 .get_bus_info = &ixgbe_get_bus_info_X550em,
3897 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3898 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3899 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3900 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3901 .setup_fc = NULL,
3902 .fc_autoneg = ixgbe_fc_autoneg,
3903 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3904 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3905};
3906
3907static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3908 X550_COMMON_MAC
3909 .led_on = ixgbe_led_on_t_x550em,
3910 .led_off = ixgbe_led_off_t_x550em,
3911 .init_led_link_act = ixgbe_init_led_link_act_generic,
3912 .reset_hw = ixgbe_reset_hw_X550em,
3913 .get_media_type = ixgbe_get_media_type_X550em,
3914 .get_san_mac_addr = NULL,
3915 .get_wwn_prefix = NULL,
3916 .setup_link = &ixgbe_setup_mac_link_X540,
3917 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3918 .get_bus_info = ixgbe_get_bus_info_X550em,
3919 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3920 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3921 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3922 .setup_fc = ixgbe_setup_fc_x550em,
3923 .fc_autoneg = ixgbe_fc_autoneg,
3924 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3925 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3926};
3927
3928static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3929 X550_COMMON_MAC
3930 .led_on = ixgbe_led_on_generic,
3931 .led_off = ixgbe_led_off_generic,
3932 .init_led_link_act = ixgbe_init_led_link_act_generic,
3933 .reset_hw = ixgbe_reset_hw_X550em,
3934 .get_media_type = ixgbe_get_media_type_X550em,
3935 .get_san_mac_addr = NULL,
3936 .get_wwn_prefix = NULL,
3937 .setup_link = NULL, /* defined later */
3938 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3939 .get_bus_info = ixgbe_get_bus_info_X550em,
3940 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3941 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3942 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3943 .setup_fc = ixgbe_setup_fc_x550em,
3944 .fc_autoneg = ixgbe_fc_autoneg,
3945 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3946 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3947};
3948
3949#define X550_COMMON_EEP \
3950 .read = &ixgbe_read_ee_hostif_X550, \
3951 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3952 .write = &ixgbe_write_ee_hostif_X550, \
3953 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3954 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3955 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3956 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3957
3958static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3959 X550_COMMON_EEP
3960 .init_params = &ixgbe_init_eeprom_params_X550,
3961};
3962
3963static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3964 X550_COMMON_EEP
3965 .init_params = &ixgbe_init_eeprom_params_X540,
3966};
3967
3968#define X550_COMMON_PHY \
3969 .identify_sfp = &ixgbe_identify_module_generic, \
3970 .reset = NULL, \
3971 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3972 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3973 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3974 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3975 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3976 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3977 .setup_link = &ixgbe_setup_phy_link_generic, \
3978 .set_phy_power = NULL,
3979
3980static const struct ixgbe_phy_operations phy_ops_X550 = {
3981 X550_COMMON_PHY
3982 .check_overtemp = &ixgbe_tn_check_overtemp,
3983 .init = NULL,
3984 .identify = &ixgbe_identify_phy_generic,
3985 .read_reg = &ixgbe_read_phy_reg_generic,
3986 .write_reg = &ixgbe_write_phy_reg_generic,
3987};
3988
3989static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3990 X550_COMMON_PHY
3991 .check_overtemp = &ixgbe_tn_check_overtemp,
3992 .init = &ixgbe_init_phy_ops_X550em,
3993 .identify = &ixgbe_identify_phy_x550em,
3994 .read_reg = &ixgbe_read_phy_reg_generic,
3995 .write_reg = &ixgbe_write_phy_reg_generic,
3996};
3997
3998static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
3999 X550_COMMON_PHY
4000 .check_overtemp = NULL,
4001 .init = ixgbe_init_phy_ops_X550em,
4002 .identify = ixgbe_identify_phy_x550em,
4003 .read_reg = NULL,
4004 .write_reg = NULL,
4005 .read_reg_mdi = NULL,
4006 .write_reg_mdi = NULL,
4007};
4008
4009static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4010 X550_COMMON_PHY
4011 .check_overtemp = &ixgbe_tn_check_overtemp,
4012 .init = &ixgbe_init_phy_ops_X550em,
4013 .identify = &ixgbe_identify_phy_x550em,
4014 .read_reg = &ixgbe_read_phy_reg_x550a,
4015 .write_reg = &ixgbe_write_phy_reg_x550a,
4016 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
4017 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
4018};
4019
4020static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4021 X550_COMMON_PHY
4022 .check_overtemp = ixgbe_check_overtemp_fw,
4023 .init = ixgbe_init_phy_ops_X550em,
4024 .identify = ixgbe_identify_phy_fw,
4025 .read_reg = NULL,
4026 .write_reg = NULL,
4027 .read_reg_mdi = NULL,
4028 .write_reg_mdi = NULL,
4029};
4030
4031static const struct ixgbe_link_operations link_ops_x550em_x = {
4032 .read_link = &ixgbe_read_i2c_combined_generic,
4033 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4034 .write_link = &ixgbe_write_i2c_combined_generic,
4035 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4036};
4037
4038static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4039 IXGBE_MVALS_INIT(X550)
4040};
4041
4042static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4043 IXGBE_MVALS_INIT(X550EM_x)
4044};
4045
4046static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4047 IXGBE_MVALS_INIT(X550EM_a)
4048};
4049
4050const struct ixgbe_info ixgbe_X550_info = {
4051 .mac = ixgbe_mac_X550,
4052 .get_invariants = &ixgbe_get_invariants_X540,
4053 .mac_ops = &mac_ops_X550,
4054 .eeprom_ops = &eeprom_ops_X550,
4055 .phy_ops = &phy_ops_X550,
4056 .mbx_ops = &mbx_ops_generic,
4057 .mvals = ixgbe_mvals_X550,
4058};
4059
4060const struct ixgbe_info ixgbe_X550EM_x_info = {
4061 .mac = ixgbe_mac_X550EM_x,
4062 .get_invariants = &ixgbe_get_invariants_X550_x,
4063 .mac_ops = &mac_ops_X550EM_x,
4064 .eeprom_ops = &eeprom_ops_X550EM_x,
4065 .phy_ops = &phy_ops_X550EM_x,
4066 .mbx_ops = &mbx_ops_generic,
4067 .mvals = ixgbe_mvals_X550EM_x,
4068 .link_ops = &link_ops_x550em_x,
4069};
4070
4071const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4072 .mac = ixgbe_mac_X550EM_x,
4073 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4074 .mac_ops = &mac_ops_X550EM_x_fw,
4075 .eeprom_ops = &eeprom_ops_X550EM_x,
4076 .phy_ops = &phy_ops_x550em_x_fw,
4077 .mbx_ops = &mbx_ops_generic,
4078 .mvals = ixgbe_mvals_X550EM_x,
4079};
4080
4081const struct ixgbe_info ixgbe_x550em_a_info = {
4082 .mac = ixgbe_mac_x550em_a,
4083 .get_invariants = &ixgbe_get_invariants_X550_a,
4084 .mac_ops = &mac_ops_x550em_a,
4085 .eeprom_ops = &eeprom_ops_X550EM_x,
4086 .phy_ops = &phy_ops_x550em_a,
4087 .mbx_ops = &mbx_ops_generic,
4088 .mvals = ixgbe_mvals_x550em_a,
4089};
4090
4091const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4092 .mac = ixgbe_mac_x550em_a,
4093 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4094 .mac_ops = &mac_ops_x550em_a_fw,
4095 .eeprom_ops = &eeprom_ops_X550EM_x,
4096 .phy_ops = &phy_ops_x550em_a_fw,
4097 .mbx_ops = &mbx_ops_generic,
4098 .mvals = ixgbe_mvals_x550em_a,
4099};