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1/* SPDX-License-Identifier: GPL-2.0 */
2/*******************************************************************************
3
4 Intel PRO/10GbE Linux driver
5 Copyright(c) 1999 - 2008 Intel Corporation.
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30#ifndef _IXGB_HW_H_
31#define _IXGB_HW_H_
32
33#include <linux/mdio.h>
34
35#include "ixgb_osdep.h"
36
37/* Enums */
38typedef enum {
39 ixgb_mac_unknown = 0,
40 ixgb_82597,
41 ixgb_num_macs
42} ixgb_mac_type;
43
44/* Types of physical layer modules */
45typedef enum {
46 ixgb_phy_type_unknown = 0,
47 ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */
48 ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */
49 ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */
50 ixgb_phy_type_txn17401, /* 1310nm, SM fiber, XENPAK transceiver */
51 ixgb_phy_type_bcm /* SUN specific board */
52} ixgb_phy_type;
53
54/* XPAK transceiver vendors, for the SR adapters */
55typedef enum {
56 ixgb_xpak_vendor_intel,
57 ixgb_xpak_vendor_infineon
58} ixgb_xpak_vendor;
59
60/* Media Types */
61typedef enum {
62 ixgb_media_type_unknown = 0,
63 ixgb_media_type_fiber = 1,
64 ixgb_media_type_copper = 2,
65 ixgb_num_media_types
66} ixgb_media_type;
67
68/* Flow Control Settings */
69typedef enum {
70 ixgb_fc_none = 0,
71 ixgb_fc_rx_pause = 1,
72 ixgb_fc_tx_pause = 2,
73 ixgb_fc_full = 3,
74 ixgb_fc_default = 0xFF
75} ixgb_fc_type;
76
77/* PCI bus types */
78typedef enum {
79 ixgb_bus_type_unknown = 0,
80 ixgb_bus_type_pci,
81 ixgb_bus_type_pcix
82} ixgb_bus_type;
83
84/* PCI bus speeds */
85typedef enum {
86 ixgb_bus_speed_unknown = 0,
87 ixgb_bus_speed_33,
88 ixgb_bus_speed_66,
89 ixgb_bus_speed_100,
90 ixgb_bus_speed_133,
91 ixgb_bus_speed_reserved
92} ixgb_bus_speed;
93
94/* PCI bus widths */
95typedef enum {
96 ixgb_bus_width_unknown = 0,
97 ixgb_bus_width_32,
98 ixgb_bus_width_64
99} ixgb_bus_width;
100
101#define IXGB_EEPROM_SIZE 64 /* Size in words */
102
103#define SPEED_10000 10000
104#define FULL_DUPLEX 2
105
106#define MIN_NUMBER_OF_DESCRIPTORS 8
107#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */
108
109#define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */
110#define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */
111#define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */
112
113#define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */
114 /* NOTE: this is MICROSECONDS */
115#define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */
116
117/* General Registers */
118#define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */
119#define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */
120#define IXGB_STATUS 0x00010 /* Device Status Register - RO */
121#define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */
122#define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */
123
124/* Interrupt */
125#define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */
126#define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */
127#define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */
128#define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */
129
130/* Receive */
131#define IXGB_RCTL 0x00100 /* RX Control - RW */
132#define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */
133#define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */
134#define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */
135#define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */
136#define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */
137#define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */
138#define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */
139#define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */
140#define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */
141#define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */
142#define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */
143#define IXGB_RA 0x00180 /* Receive Address Array Base - RW */
144#define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */
145#define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */
146#define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */
147#define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */
148#define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
149
150/* Transmit */
151#define IXGB_TCTL 0x00600 /* TX Control - RW */
152#define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */
153#define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */
154#define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */
155#define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */
156#define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */
157#define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */
158#define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */
159#define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */
160#define IXGB_PAP 0x00640 /* Pause and Pace - RW */
161#define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
162
163/* Physical */
164#define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */
165#define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */
166#define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */
167#define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */
168#define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */
169#define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */
170#define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */
171#define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */
172#define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */
173#define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */
174#define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */
175#define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */
176#define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */
177
178/* Wake-up */
179#define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */
180#define IXGB_WUS 0x00810 /* Wake Up Status - RO */
181#define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */
182#define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */
183#define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */
184
185/* Statistics */
186#define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */
187#define IXGB_TPRH 0x02004 /* Total Packets Received (High) */
188#define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */
189#define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */
190#define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */
191#define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */
192#define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */
193#define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */
194#define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */
195#define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */
196#define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */
197#define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */
198#define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */
199#define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */
200#define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */
201#define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */
202#define IXGB_TORL 0x02040 /* Total Octets Received (Low) */
203#define IXGB_TORH 0x02044 /* Total Octets Received (High) */
204#define IXGB_RNBC 0x02048 /* Receive No Buffers Count */
205#define IXGB_RUC 0x02050 /* Receive Undersize Count */
206#define IXGB_ROC 0x02058 /* Receive Oversize Count */
207#define IXGB_RLEC 0x02060 /* Receive Length Error Count */
208#define IXGB_CRCERRS 0x02068 /* CRC Error Count */
209#define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */
210#define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */
211#define IXGB_MPC 0x02080 /* Missed Packets Count */
212#define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */
213#define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */
214#define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */
215#define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */
216#define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */
217#define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */
218#define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */
219#define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */
220#define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */
221#define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */
222#define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */
223#define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */
224#define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */
225#define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */
226#define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */
227#define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */
228#define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */
229#define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */
230#define IXGB_DC 0x02148 /* Defer Count */
231#define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */
232#define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */
233#define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */
234#define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */
235#define IXGB_RFC 0x02188 /* Remote Fault Count */
236#define IXGB_LFC 0x02190 /* Local Fault Count */
237#define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */
238#define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */
239#define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */
240#define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */
241#define IXGB_XONRXC 0x021B8 /* XON Received Count */
242#define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */
243#define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */
244#define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */
245#define IXGB_RJC 0x021D8 /* Receive Jabber Count */
246
247/* CTRL0 Bit Masks */
248#define IXGB_CTRL0_LRST 0x00000008
249#define IXGB_CTRL0_JFE 0x00000010
250#define IXGB_CTRL0_XLE 0x00000020
251#define IXGB_CTRL0_MDCS 0x00000040
252#define IXGB_CTRL0_CMDC 0x00000080
253#define IXGB_CTRL0_SDP0 0x00040000
254#define IXGB_CTRL0_SDP1 0x00080000
255#define IXGB_CTRL0_SDP2 0x00100000
256#define IXGB_CTRL0_SDP3 0x00200000
257#define IXGB_CTRL0_SDP0_DIR 0x00400000
258#define IXGB_CTRL0_SDP1_DIR 0x00800000
259#define IXGB_CTRL0_SDP2_DIR 0x01000000
260#define IXGB_CTRL0_SDP3_DIR 0x02000000
261#define IXGB_CTRL0_RST 0x04000000
262#define IXGB_CTRL0_RPE 0x08000000
263#define IXGB_CTRL0_TPE 0x10000000
264#define IXGB_CTRL0_VME 0x40000000
265
266/* CTRL1 Bit Masks */
267#define IXGB_CTRL1_GPI0_EN 0x00000001
268#define IXGB_CTRL1_GPI1_EN 0x00000002
269#define IXGB_CTRL1_GPI2_EN 0x00000004
270#define IXGB_CTRL1_GPI3_EN 0x00000008
271#define IXGB_CTRL1_SDP4 0x00000010
272#define IXGB_CTRL1_SDP5 0x00000020
273#define IXGB_CTRL1_SDP6 0x00000040
274#define IXGB_CTRL1_SDP7 0x00000080
275#define IXGB_CTRL1_SDP4_DIR 0x00000100
276#define IXGB_CTRL1_SDP5_DIR 0x00000200
277#define IXGB_CTRL1_SDP6_DIR 0x00000400
278#define IXGB_CTRL1_SDP7_DIR 0x00000800
279#define IXGB_CTRL1_EE_RST 0x00002000
280#define IXGB_CTRL1_RO_DIS 0x00020000
281#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
282#define IXGB_CTRL1_PCIXHM_1_2 0x00000000
283#define IXGB_CTRL1_PCIXHM_5_8 0x00400000
284#define IXGB_CTRL1_PCIXHM_3_4 0x00800000
285#define IXGB_CTRL1_PCIXHM_7_8 0x00C00000
286
287/* STATUS Bit Masks */
288#define IXGB_STATUS_LU 0x00000002
289#define IXGB_STATUS_AIP 0x00000004
290#define IXGB_STATUS_TXOFF 0x00000010
291#define IXGB_STATUS_XAUIME 0x00000020
292#define IXGB_STATUS_RES 0x00000040
293#define IXGB_STATUS_RIS 0x00000080
294#define IXGB_STATUS_RIE 0x00000100
295#define IXGB_STATUS_RLF 0x00000200
296#define IXGB_STATUS_RRF 0x00000400
297#define IXGB_STATUS_PCI_SPD 0x00000800
298#define IXGB_STATUS_BUS64 0x00001000
299#define IXGB_STATUS_PCIX_MODE 0x00002000
300#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
301#define IXGB_STATUS_PCIX_SPD_66 0x00000000
302#define IXGB_STATUS_PCIX_SPD_100 0x00004000
303#define IXGB_STATUS_PCIX_SPD_133 0x00008000
304#define IXGB_STATUS_REV_ID_MASK 0x000F0000
305#define IXGB_STATUS_REV_ID_SHIFT 16
306
307/* EECD Bit Masks */
308#define IXGB_EECD_SK 0x00000001
309#define IXGB_EECD_CS 0x00000002
310#define IXGB_EECD_DI 0x00000004
311#define IXGB_EECD_DO 0x00000008
312#define IXGB_EECD_FWE_MASK 0x00000030
313#define IXGB_EECD_FWE_DIS 0x00000010
314#define IXGB_EECD_FWE_EN 0x00000020
315
316/* MFS */
317#define IXGB_MFS_SHIFT 16
318
319/* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
320#define IXGB_INT_TXDW 0x00000001
321#define IXGB_INT_TXQE 0x00000002
322#define IXGB_INT_LSC 0x00000004
323#define IXGB_INT_RXSEQ 0x00000008
324#define IXGB_INT_RXDMT0 0x00000010
325#define IXGB_INT_RXO 0x00000040
326#define IXGB_INT_RXT0 0x00000080
327#define IXGB_INT_AUTOSCAN 0x00000200
328#define IXGB_INT_GPI0 0x00000800
329#define IXGB_INT_GPI1 0x00001000
330#define IXGB_INT_GPI2 0x00002000
331#define IXGB_INT_GPI3 0x00004000
332
333/* RCTL Bit Masks */
334#define IXGB_RCTL_RXEN 0x00000002
335#define IXGB_RCTL_SBP 0x00000004
336#define IXGB_RCTL_UPE 0x00000008
337#define IXGB_RCTL_MPE 0x00000010
338#define IXGB_RCTL_RDMTS_MASK 0x00000300
339#define IXGB_RCTL_RDMTS_1_2 0x00000000
340#define IXGB_RCTL_RDMTS_1_4 0x00000100
341#define IXGB_RCTL_RDMTS_1_8 0x00000200
342#define IXGB_RCTL_MO_MASK 0x00003000
343#define IXGB_RCTL_MO_47_36 0x00000000
344#define IXGB_RCTL_MO_46_35 0x00001000
345#define IXGB_RCTL_MO_45_34 0x00002000
346#define IXGB_RCTL_MO_43_32 0x00003000
347#define IXGB_RCTL_MO_SHIFT 12
348#define IXGB_RCTL_BAM 0x00008000
349#define IXGB_RCTL_BSIZE_MASK 0x00030000
350#define IXGB_RCTL_BSIZE_2048 0x00000000
351#define IXGB_RCTL_BSIZE_4096 0x00010000
352#define IXGB_RCTL_BSIZE_8192 0x00020000
353#define IXGB_RCTL_BSIZE_16384 0x00030000
354#define IXGB_RCTL_VFE 0x00040000
355#define IXGB_RCTL_CFIEN 0x00080000
356#define IXGB_RCTL_CFI 0x00100000
357#define IXGB_RCTL_RPDA_MASK 0x00600000
358#define IXGB_RCTL_RPDA_MC_MAC 0x00000000
359#define IXGB_RCTL_MC_ONLY 0x00400000
360#define IXGB_RCTL_CFF 0x00800000
361#define IXGB_RCTL_SECRC 0x04000000
362#define IXGB_RDT_FPDB 0x80000000
363
364#define IXGB_RCTL_IDLE_RX_UNIT 0
365
366/* FCRTL Bit Masks */
367#define IXGB_FCRTL_XONE 0x80000000
368
369/* RXDCTL Bit Masks */
370#define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF
371#define IXGB_RXDCTL_PTHRESH_SHIFT 0
372#define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00
373#define IXGB_RXDCTL_HTHRESH_SHIFT 9
374#define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000
375#define IXGB_RXDCTL_WTHRESH_SHIFT 18
376
377/* RAIDC Bit Masks */
378#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
379#define IXGB_RAIDC_DELAY_MASK 0x000FF800
380#define IXGB_RAIDC_DELAY_SHIFT 11
381#define IXGB_RAIDC_POLL_MASK 0x1FF00000
382#define IXGB_RAIDC_POLL_SHIFT 20
383#define IXGB_RAIDC_RXT_GATE 0x40000000
384#define IXGB_RAIDC_EN 0x80000000
385
386#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220
387#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244
388#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122
389#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61
390
391/* RXCSUM Bit Masks */
392#define IXGB_RXCSUM_IPOFL 0x00000100
393#define IXGB_RXCSUM_TUOFL 0x00000200
394
395/* RAH Bit Masks */
396#define IXGB_RAH_ASEL_MASK 0x00030000
397#define IXGB_RAH_ASEL_DEST 0x00000000
398#define IXGB_RAH_ASEL_SRC 0x00010000
399#define IXGB_RAH_AV 0x80000000
400
401/* TCTL Bit Masks */
402#define IXGB_TCTL_TCE 0x00000001
403#define IXGB_TCTL_TXEN 0x00000002
404#define IXGB_TCTL_TPDE 0x00000004
405
406#define IXGB_TCTL_IDLE_TX_UNIT 0
407
408/* TXDCTL Bit Masks */
409#define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F
410#define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00
411#define IXGB_TXDCTL_HTHRESH_SHIFT 8
412#define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000
413#define IXGB_TXDCTL_WTHRESH_SHIFT 16
414
415/* TSPMT Bit Masks */
416#define IXGB_TSPMT_TSMT_MASK 0x0000FFFF
417#define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000
418#define IXGB_TSPMT_TSPBP_SHIFT 16
419
420/* PAP Bit Masks */
421#define IXGB_PAP_TXPC_MASK 0x0000FFFF
422#define IXGB_PAP_TXPV_MASK 0x000F0000
423#define IXGB_PAP_TXPV_10G 0x00000000
424#define IXGB_PAP_TXPV_1G 0x00010000
425#define IXGB_PAP_TXPV_2G 0x00020000
426#define IXGB_PAP_TXPV_3G 0x00030000
427#define IXGB_PAP_TXPV_4G 0x00040000
428#define IXGB_PAP_TXPV_5G 0x00050000
429#define IXGB_PAP_TXPV_6G 0x00060000
430#define IXGB_PAP_TXPV_7G 0x00070000
431#define IXGB_PAP_TXPV_8G 0x00080000
432#define IXGB_PAP_TXPV_9G 0x00090000
433#define IXGB_PAP_TXPV_WAN 0x000F0000
434
435/* PCSC1 Bit Masks */
436#define IXGB_PCSC1_LOOPBACK 0x00004000
437
438/* PCSC2 Bit Masks */
439#define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003
440#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
441
442/* PCSS1 Bit Masks */
443#define IXGB_PCSS1_LOCAL_FAULT 0x00000080
444#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
445
446/* PCSS2 Bit Masks */
447#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
448#define IXGB_PCSS2_DEV_PRES 0x00004000
449#define IXGB_PCSS2_TX_LF 0x00000800
450#define IXGB_PCSS2_RX_LF 0x00000400
451#define IXGB_PCSS2_10GBW 0x00000004
452#define IXGB_PCSS2_10GBX 0x00000002
453#define IXGB_PCSS2_10GBR 0x00000001
454
455/* XPCSS Bit Masks */
456#define IXGB_XPCSS_ALIGN_STATUS 0x00001000
457#define IXGB_XPCSS_PATTERN_TEST 0x00000800
458#define IXGB_XPCSS_LANE_3_SYNC 0x00000008
459#define IXGB_XPCSS_LANE_2_SYNC 0x00000004
460#define IXGB_XPCSS_LANE_1_SYNC 0x00000002
461#define IXGB_XPCSS_LANE_0_SYNC 0x00000001
462
463/* XPCSTC Bit Masks */
464#define IXGB_XPCSTC_BERT_TRIG 0x00200000
465#define IXGB_XPCSTC_BERT_SST 0x00100000
466#define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000
467#define IXGB_XPCSTC_BERT_PSZ_SHIFT 17
468#define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003
469#define IXGB_XPCSTC_BERT_PSZ_68 0x00000001
470#define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000
471
472/* MSCA bit Masks */
473/* New Protocol Address */
474#define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF
475#define IXGB_MSCA_NP_ADDR_SHIFT 0
476/* Either Device Type or Register Address,depending on ST_CODE */
477#define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000
478#define IXGB_MSCA_DEV_TYPE_SHIFT 16
479#define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000
480#define IXGB_MSCA_PHY_ADDR_SHIFT 21
481#define IXGB_MSCA_OP_CODE_MASK 0x0C000000
482/* OP_CODE == 00, Address cycle, New Protocol */
483/* OP_CODE == 01, Write operation */
484/* OP_CODE == 10, Read operation */
485/* OP_CODE == 11, Read, auto increment, New Protocol */
486#define IXGB_MSCA_ADDR_CYCLE 0x00000000
487#define IXGB_MSCA_WRITE 0x04000000
488#define IXGB_MSCA_READ 0x08000000
489#define IXGB_MSCA_READ_AUTOINC 0x0C000000
490#define IXGB_MSCA_OP_CODE_SHIFT 26
491#define IXGB_MSCA_ST_CODE_MASK 0x30000000
492/* ST_CODE == 00, New Protocol */
493/* ST_CODE == 01, Old Protocol */
494#define IXGB_MSCA_NEW_PROTOCOL 0x00000000
495#define IXGB_MSCA_OLD_PROTOCOL 0x10000000
496#define IXGB_MSCA_ST_CODE_SHIFT 28
497/* Initiate command, self-clearing when command completes */
498#define IXGB_MSCA_MDI_COMMAND 0x40000000
499/*MDI In Progress Enable. */
500#define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000
501
502/* MSRWD bit masks */
503#define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF
504#define IXGB_MSRWD_WRITE_DATA_SHIFT 0
505#define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000
506#define IXGB_MSRWD_READ_DATA_SHIFT 16
507
508/* Definitions for the optics devices on the MDIO bus. */
509#define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */
510
511#define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */
512
513/* Vendor-specific MDIO registers */
514#define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */
515#define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */
516
517#define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80
518#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00
519#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */
520
521/* Layout of a single receive descriptor. The controller assumes that this
522 * structure is packed into 16 bytes, which is a safe assumption with most
523 * compilers. However, some compilers may insert padding between the fields,
524 * in which case the structure must be packed in some compiler-specific
525 * manner. */
526struct ixgb_rx_desc {
527 __le64 buff_addr;
528 __le16 length;
529 __le16 reserved;
530 u8 status;
531 u8 errors;
532 __le16 special;
533};
534
535#define IXGB_RX_DESC_STATUS_DD 0x01
536#define IXGB_RX_DESC_STATUS_EOP 0x02
537#define IXGB_RX_DESC_STATUS_IXSM 0x04
538#define IXGB_RX_DESC_STATUS_VP 0x08
539#define IXGB_RX_DESC_STATUS_TCPCS 0x20
540#define IXGB_RX_DESC_STATUS_IPCS 0x40
541#define IXGB_RX_DESC_STATUS_PIF 0x80
542
543#define IXGB_RX_DESC_ERRORS_CE 0x01
544#define IXGB_RX_DESC_ERRORS_SE 0x02
545#define IXGB_RX_DESC_ERRORS_P 0x08
546#define IXGB_RX_DESC_ERRORS_TCPE 0x20
547#define IXGB_RX_DESC_ERRORS_IPE 0x40
548#define IXGB_RX_DESC_ERRORS_RXE 0x80
549
550#define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
551#define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
552#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
553
554/* Layout of a single transmit descriptor. The controller assumes that this
555 * structure is packed into 16 bytes, which is a safe assumption with most
556 * compilers. However, some compilers may insert padding between the fields,
557 * in which case the structure must be packed in some compiler-specific
558 * manner. */
559struct ixgb_tx_desc {
560 __le64 buff_addr;
561 __le32 cmd_type_len;
562 u8 status;
563 u8 popts;
564 __le16 vlan;
565};
566
567#define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF
568#define IXGB_TX_DESC_TYPE_MASK 0x00F00000
569#define IXGB_TX_DESC_TYPE_SHIFT 20
570#define IXGB_TX_DESC_CMD_MASK 0xFF000000
571#define IXGB_TX_DESC_CMD_SHIFT 24
572#define IXGB_TX_DESC_CMD_EOP 0x01000000
573#define IXGB_TX_DESC_CMD_TSE 0x04000000
574#define IXGB_TX_DESC_CMD_RS 0x08000000
575#define IXGB_TX_DESC_CMD_VLE 0x40000000
576#define IXGB_TX_DESC_CMD_IDE 0x80000000
577
578#define IXGB_TX_DESC_TYPE 0x00100000
579
580#define IXGB_TX_DESC_STATUS_DD 0x01
581
582#define IXGB_TX_DESC_POPTS_IXSM 0x01
583#define IXGB_TX_DESC_POPTS_TXSM 0x02
584#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */
585
586struct ixgb_context_desc {
587 u8 ipcss;
588 u8 ipcso;
589 __le16 ipcse;
590 u8 tucss;
591 u8 tucso;
592 __le16 tucse;
593 __le32 cmd_type_len;
594 u8 status;
595 u8 hdr_len;
596 __le16 mss;
597};
598
599#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
600#define IXGB_CONTEXT_DESC_CMD_IP 0x02000000
601#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
602#define IXGB_CONTEXT_DESC_CMD_RS 0x08000000
603#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
604
605#define IXGB_CONTEXT_DESC_TYPE 0x00000000
606
607#define IXGB_CONTEXT_DESC_STATUS_DD 0x01
608
609/* Filters */
610#define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
611#define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
612#define IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */
613
614#define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0
615#define ENET_HEADER_SIZE 14
616#define ENET_FCS_LENGTH 4
617#define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128
618#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60
619#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514
620#define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00
621
622/* Phy Addresses */
623#define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */
624#define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */
625#define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */
626
627/* This structure takes a 64k flash and maps it for identification commands */
628struct ixgb_flash_buffer {
629 u8 manufacturer_id;
630 u8 device_id;
631 u8 filler1[0x2AA8];
632 u8 cmd2;
633 u8 filler2[0x2AAA];
634 u8 cmd1;
635 u8 filler3[0xAAAA];
636};
637
638/* Flow control parameters */
639struct ixgb_fc {
640 u32 high_water; /* Flow Control High-water */
641 u32 low_water; /* Flow Control Low-water */
642 u16 pause_time; /* Flow Control Pause timer */
643 bool send_xon; /* Flow control send XON */
644 ixgb_fc_type type; /* Type of flow control */
645};
646
647/* The historical defaults for the flow control values are given below. */
648#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
649#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
650#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
651
652/* Phy definitions */
653#define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF
654#define IXGB_MAX_PHY_ADDRESS 31
655#define IXGB_MAX_PHY_DEV_TYPE 31
656
657/* Bus parameters */
658struct ixgb_bus {
659 ixgb_bus_speed speed;
660 ixgb_bus_width width;
661 ixgb_bus_type type;
662};
663
664struct ixgb_hw {
665 u8 __iomem *hw_addr;/* Base Address of the hardware */
666 void *back; /* Pointer to OS-dependent struct */
667 struct ixgb_fc fc; /* Flow control parameters */
668 struct ixgb_bus bus; /* Bus parameters */
669 u32 phy_id; /* Phy Identifier */
670 u32 phy_addr; /* XGMII address of Phy */
671 ixgb_mac_type mac_type; /* Identifier for MAC controller */
672 ixgb_phy_type phy_type; /* Transceiver/phy identifier */
673 u32 max_frame_size; /* Maximum frame size supported */
674 u32 mc_filter_type; /* Multicast filter hash type */
675 u32 num_mc_addrs; /* Number of current Multicast addrs */
676 u8 curr_mac_addr[ETH_ALEN]; /* Individual address currently programmed in MAC */
677 u32 num_tx_desc; /* Number of Transmit descriptors */
678 u32 num_rx_desc; /* Number of Receive descriptors */
679 u32 rx_buffer_size; /* Size of Receive buffer */
680 bool link_up; /* true if link is valid */
681 bool adapter_stopped; /* State of adapter */
682 u16 device_id; /* device id from PCI configuration space */
683 u16 vendor_id; /* vendor id from PCI configuration space */
684 u8 revision_id; /* revision id from PCI configuration space */
685 u16 subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */
686 u16 subsystem_id; /* subsystem id from PCI configuration space */
687 u32 bar0; /* Base Address registers */
688 u32 bar1;
689 u32 bar2;
690 u32 bar3;
691 u16 pci_cmd_word; /* PCI command register id from PCI configuration space */
692 __le16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */
693 unsigned long io_base; /* Our I/O mapped location */
694 u32 lastLFC;
695 u32 lastRFC;
696};
697
698/* Statistics reported by the hardware */
699struct ixgb_hw_stats {
700 u64 tprl;
701 u64 tprh;
702 u64 gprcl;
703 u64 gprch;
704 u64 bprcl;
705 u64 bprch;
706 u64 mprcl;
707 u64 mprch;
708 u64 uprcl;
709 u64 uprch;
710 u64 vprcl;
711 u64 vprch;
712 u64 jprcl;
713 u64 jprch;
714 u64 gorcl;
715 u64 gorch;
716 u64 torl;
717 u64 torh;
718 u64 rnbc;
719 u64 ruc;
720 u64 roc;
721 u64 rlec;
722 u64 crcerrs;
723 u64 icbc;
724 u64 ecbc;
725 u64 mpc;
726 u64 tptl;
727 u64 tpth;
728 u64 gptcl;
729 u64 gptch;
730 u64 bptcl;
731 u64 bptch;
732 u64 mptcl;
733 u64 mptch;
734 u64 uptcl;
735 u64 uptch;
736 u64 vptcl;
737 u64 vptch;
738 u64 jptcl;
739 u64 jptch;
740 u64 gotcl;
741 u64 gotch;
742 u64 totl;
743 u64 toth;
744 u64 dc;
745 u64 plt64c;
746 u64 tsctc;
747 u64 tsctfc;
748 u64 ibic;
749 u64 rfc;
750 u64 lfc;
751 u64 pfrc;
752 u64 pftc;
753 u64 mcfrc;
754 u64 mcftc;
755 u64 xonrxc;
756 u64 xontxc;
757 u64 xoffrxc;
758 u64 xofftxc;
759 u64 rjc;
760};
761
762/* Function Prototypes */
763bool ixgb_adapter_stop(struct ixgb_hw *hw);
764bool ixgb_init_hw(struct ixgb_hw *hw);
765bool ixgb_adapter_start(struct ixgb_hw *hw);
766void ixgb_check_for_link(struct ixgb_hw *hw);
767bool ixgb_check_for_bad_link(struct ixgb_hw *hw);
768
769void ixgb_rar_set(struct ixgb_hw *hw, u8 *addr, u32 index);
770
771/* Filters (multicast, vlan, receive) */
772void ixgb_mc_addr_list_update(struct ixgb_hw *hw, u8 *mc_addr_list,
773 u32 mc_addr_count, u32 pad);
774
775/* Vfta functions */
776void ixgb_write_vfta(struct ixgb_hw *hw, u32 offset, u32 value);
777
778/* Access functions to eeprom data */
779void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, u8 *mac_addr);
780u32 ixgb_get_ee_pba_number(struct ixgb_hw *hw);
781u16 ixgb_get_ee_device_id(struct ixgb_hw *hw);
782bool ixgb_get_eeprom_data(struct ixgb_hw *hw);
783__le16 ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index);
784
785/* Everything else */
786void ixgb_led_on(struct ixgb_hw *hw);
787void ixgb_led_off(struct ixgb_hw *hw);
788void ixgb_write_pci_cfg(struct ixgb_hw *hw,
789 u32 reg,
790 u16 * value);
791
792
793#endif /* _IXGB_HW_H_ */