1/* SPDX-License-Identifier: GPL-2.0 */
  2/*******************************************************************************
  3 *
  4 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
  5 * Copyright(c) 2013 - 2014 Intel Corporation.
  6 *
  7 * This program is free software; you can redistribute it and/or modify it
  8 * under the terms and conditions of the GNU General Public License,
  9 * version 2, as published by the Free Software Foundation.
 10 *
 11 * This program is distributed in the hope it will be useful, but WITHOUT
 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14 * more details.
 15 *
 16 * You should have received a copy of the GNU General Public License along
 17 * with this program.  If not, see <http://www.gnu.org/licenses/>.
 18 *
 19 * The full GNU General Public License is included in this distribution in
 20 * the file called "COPYING".
 21 *
 22 * Contact Information:
 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 25 *
 26 ******************************************************************************/
 27
 28#ifndef _I40E_REGISTER_H_
 29#define _I40E_REGISTER_H_
 30
 31#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
 32#define I40E_VFMSIX_PBA1_MAX_INDEX 19
 33#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
 34#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
 35#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 36#define I40E_VFMSIX_TADD1_MAX_INDEX 639
 37#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
 38#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
 39#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2
 40#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
 41#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 42#define I40E_VFMSIX_TMSG1_MAX_INDEX 639
 43#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
 44#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
 45#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 46#define I40E_VFMSIX_TUADD1_MAX_INDEX 639
 47#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
 48#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
 49#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 50#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
 51#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
 52#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
 53#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
 54#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
 55#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
 56#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
 57#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
 58#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
 59#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
 60#define I40E_VF_ARQH1_ARQH_SHIFT 0
 61#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
 62#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
 63#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0
 64#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
 65#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
 66#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
 67#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
 68#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
 69#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
 70#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
 71#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
 72#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
 73#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
 74#define I40E_VF_ARQT1_ARQT_SHIFT 0
 75#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
 76#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
 77#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
 78#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
 79#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
 80#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
 81#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
 82#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
 83#define I40E_VF_ATQH1_ATQH_SHIFT 0
 84#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
 85#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
 86#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
 87#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
 88#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
 89#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
 90#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
 91#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
 92#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
 93#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
 94#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
 95#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
 96#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
 97#define I40E_VF_ATQT1_ATQT_SHIFT 0
 98#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
 99#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
100#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
101#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
102#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
103#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
104#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
105#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
106#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
107#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
108#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
109#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
110#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
111#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
112#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
113#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
114#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
115#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
116#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
117#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
118#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
119#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
120#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15
121#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0
122#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
123#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
124#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
125#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
126#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
127#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
128#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
129#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
130#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
131#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
132#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
133#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
134#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
135#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
136#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
137#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
138#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
139#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
140#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
141#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
142#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31
143#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
144#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */
145#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0
146#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)
147#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1
148#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)
149#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2
150#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)
151#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3
152#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)
153#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4
154#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)
155#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
156#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
157#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30
158#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)
159#define I40E_VFINT_ICR01_SWINT_SHIFT 31
160#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)
161#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
162#define I40E_VFINT_ITR01_MAX_INDEX 2
163#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
164#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
165#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
166#define I40E_VFINT_ITRN1_MAX_INDEX 2
167#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
168#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
169#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
170#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
171#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
172#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
173#define I40E_QRX_TAIL1_MAX_INDEX 15
174#define I40E_QRX_TAIL1_TAIL_SHIFT 0
175#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
176#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
177#define I40E_QTX_TAIL1_MAX_INDEX 15
178#define I40E_QTX_TAIL1_TAIL_SHIFT 0
179#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
180#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */
181#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
182#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
183#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
184#define I40E_VFMSIX_TADD_MAX_INDEX 16
185#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
186#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
187#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
188#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
189#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
190#define I40E_VFMSIX_TMSG_MAX_INDEX 16
191#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
192#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
193#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
194#define I40E_VFMSIX_TUADD_MAX_INDEX 16
195#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
196#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
197#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
198#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
199#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
200#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
201#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */
202#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
203#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
204#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
205#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
206#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8
207#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
208#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */
209#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
210#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
211#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
212#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
213#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
214#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
215#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
216#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
217#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
218#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
219#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
220#define I40E_VFQF_HENA_MAX_INDEX 1
221#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
222#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
223#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
224#define I40E_VFQF_HKEY_MAX_INDEX 12
225#define I40E_VFQF_HKEY_KEY_0_SHIFT 0
226#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
227#define I40E_VFQF_HKEY_KEY_1_SHIFT 8
228#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)
229#define I40E_VFQF_HKEY_KEY_2_SHIFT 16
230#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
231#define I40E_VFQF_HKEY_KEY_3_SHIFT 24
232#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
233#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
234#define I40E_VFQF_HLUT_MAX_INDEX 15
235#define I40E_VFQF_HLUT_LUT0_SHIFT 0
236#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
237#define I40E_VFQF_HLUT_LUT1_SHIFT 8
238#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)
239#define I40E_VFQF_HLUT_LUT2_SHIFT 16
240#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
241#define I40E_VFQF_HLUT_LUT3_SHIFT 24
242#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
243#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
244#define I40E_VFQF_HREGION_MAX_INDEX 7
245#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
246#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
247#define I40E_VFQF_HREGION_REGION_0_SHIFT 1
248#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)
249#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
250#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
251#define I40E_VFQF_HREGION_REGION_1_SHIFT 5
252#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)
253#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
254#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
255#define I40E_VFQF_HREGION_REGION_2_SHIFT 9
256#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)
257#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
258#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
259#define I40E_VFQF_HREGION_REGION_3_SHIFT 13
260#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)
261#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
262#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
263#define I40E_VFQF_HREGION_REGION_4_SHIFT 17
264#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)
265#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
266#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
267#define I40E_VFQF_HREGION_REGION_5_SHIFT 21
268#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)
269#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
270#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
271#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
272#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
273#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
274#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
275#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
276#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
277#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30
278#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
279#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
280#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
281#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
282#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
283#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
284#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
285#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
286#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
287#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
288#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
289#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
290#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
291#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
292#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
293#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
294#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
295#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
296#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
297#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
298#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
299#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
300#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
301#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)
302#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
303#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
304#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)
305#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
306#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
307#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
308#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
309#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
310#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
311#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
312#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
313#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
314#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
315#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
316#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
317#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
318#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */
319#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
320#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
321#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
322#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
323#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */
324#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
325#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
326#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */
327#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
328#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
329#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */
330#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
331#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
332#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
333#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
334#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
335#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
336#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
337#endif /* _I40E_REGISTER_H_ */