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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88E6xxx Switch Global (1) Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11#include <linux/bitfield.h>
12
13#include "chip.h"
14#include "global1.h"
15
16int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17{
18 int addr = chip->info->global1_addr;
19
20 return mv88e6xxx_read(chip, addr, reg, val);
21}
22
23int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24{
25 int addr = chip->info->global1_addr;
26
27 return mv88e6xxx_write(chip, addr, reg, val);
28}
29
30int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 bit, int val)
32{
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 bit, val);
35}
36
37int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 u16 mask, u16 val)
39{
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 mask, val);
42}
43
44/* Offset 0x00: Switch Global Status Register */
45
46static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47{
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 MV88E6185_G1_STS_PPU_STATE_MASK,
50 MV88E6185_G1_STS_PPU_STATE_DISABLED);
51}
52
53static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54{
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 MV88E6185_G1_STS_PPU_STATE_MASK,
57 MV88E6185_G1_STS_PPU_STATE_POLLING);
58}
59
60static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61{
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65}
66
67static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68{
69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 * have finished their initialization and are ready to accept frames.
74 */
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76}
77
78static int mv88e6250_g1_eeprom_reload(struct mv88e6xxx_chip *chip)
79{
80 /* MV88E6185_G1_CTL1_RELOAD_EEPROM is also valid for 88E6250 */
81 int bit = __bf_shf(MV88E6185_G1_CTL1_RELOAD_EEPROM);
82 u16 val;
83 int err;
84
85 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
86 if (err)
87 return err;
88
89 val |= MV88E6185_G1_CTL1_RELOAD_EEPROM;
90
91 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
92 if (err)
93 return err;
94
95 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_CTL1, bit, 0);
96}
97
98/* Returns 0 when done, -EBUSY when waiting, other negative codes on error */
99static int mv88e6xxx_g1_is_eeprom_done(struct mv88e6xxx_chip *chip)
100{
101 u16 val;
102 int err;
103
104 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
105 if (err < 0) {
106 dev_err(chip->dev, "Error reading status");
107 return err;
108 }
109
110 /* If the switch is still resetting, it may not
111 * respond on the bus, and so MDIO read returns
112 * 0xffff. Differentiate between that, and waiting for
113 * the EEPROM to be done by bit 0 being set.
114 */
115 if (val == 0xffff || !(val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE)))
116 return -EBUSY;
117
118 return 0;
119}
120
121/* As the EEInt (EEPROM done) flag clears on read if the status register, this
122 * function must be called directly after a hard reset or EEPROM ReLoad request,
123 * or the done condition may have been missed
124 */
125int mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
126{
127 const unsigned long timeout = jiffies + 1 * HZ;
128 int ret;
129
130 /* Wait up to 1 second for the switch to finish reading the
131 * EEPROM.
132 */
133 while (time_before(jiffies, timeout)) {
134 ret = mv88e6xxx_g1_is_eeprom_done(chip);
135 if (ret != -EBUSY)
136 return ret;
137 }
138
139 dev_err(chip->dev, "Timeout waiting for EEPROM done");
140 return -ETIMEDOUT;
141}
142
143int mv88e6250_g1_wait_eeprom_done_prereset(struct mv88e6xxx_chip *chip)
144{
145 int ret;
146
147 ret = mv88e6xxx_g1_is_eeprom_done(chip);
148 if (ret != -EBUSY)
149 return ret;
150
151 /* Pre-reset, we don't know the state of the switch - when
152 * mv88e6xxx_g1_is_eeprom_done() returns -EBUSY, that may be because
153 * the switch is actually busy reading the EEPROM, or because
154 * MV88E6XXX_G1_STS_IRQ_EEPROM_DONE has been cleared by an unrelated
155 * status register read already.
156 *
157 * To account for the latter case, trigger another EEPROM reload for
158 * another chance at seeing the done flag.
159 */
160 ret = mv88e6250_g1_eeprom_reload(chip);
161 if (ret)
162 return ret;
163
164 return mv88e6xxx_g1_wait_eeprom_done(chip);
165}
166
167/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
168 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
169 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
170 */
171int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
172{
173 u16 reg;
174 int err;
175
176 reg = (addr[0] << 8) | addr[1];
177 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
178 if (err)
179 return err;
180
181 reg = (addr[2] << 8) | addr[3];
182 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
183 if (err)
184 return err;
185
186 reg = (addr[4] << 8) | addr[5];
187 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
188 if (err)
189 return err;
190
191 return 0;
192}
193
194/* Offset 0x04: Switch Global Control Register */
195
196int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
197{
198 u16 val;
199 int err;
200
201 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
202 * the PPU, including re-doing PHY detection and initialization
203 */
204 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
205 if (err)
206 return err;
207
208 val |= MV88E6XXX_G1_CTL1_SW_RESET;
209 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
210
211 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
212 if (err)
213 return err;
214
215 err = mv88e6xxx_g1_wait_init_ready(chip);
216 if (err)
217 return err;
218
219 return mv88e6185_g1_wait_ppu_polling(chip);
220}
221
222int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
223{
224 u16 val;
225 int err;
226
227 /* Set the SWReset bit 15 */
228 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
229 if (err)
230 return err;
231
232 val |= MV88E6XXX_G1_CTL1_SW_RESET;
233
234 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
235 if (err)
236 return err;
237
238 return mv88e6xxx_g1_wait_init_ready(chip);
239}
240
241int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
242{
243 int err;
244
245 err = mv88e6250_g1_reset(chip);
246 if (err)
247 return err;
248
249 return mv88e6352_g1_wait_ppu_polling(chip);
250}
251
252int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
253{
254 u16 val;
255 int err;
256
257 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
258 if (err)
259 return err;
260
261 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
262
263 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
264 if (err)
265 return err;
266
267 return mv88e6185_g1_wait_ppu_polling(chip);
268}
269
270int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
271{
272 u16 val;
273 int err;
274
275 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
276 if (err)
277 return err;
278
279 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
280
281 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
282 if (err)
283 return err;
284
285 return mv88e6185_g1_wait_ppu_disabled(chip);
286}
287
288int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
289{
290 u16 val;
291 int err;
292
293 mtu += ETH_HLEN + ETH_FCS_LEN;
294
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
296 if (err)
297 return err;
298
299 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
300
301 if (mtu > 1518)
302 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
303
304 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
305}
306
307/* Offset 0x10: IP-PRI Mapping Register 0
308 * Offset 0x11: IP-PRI Mapping Register 1
309 * Offset 0x12: IP-PRI Mapping Register 2
310 * Offset 0x13: IP-PRI Mapping Register 3
311 * Offset 0x14: IP-PRI Mapping Register 4
312 * Offset 0x15: IP-PRI Mapping Register 5
313 * Offset 0x16: IP-PRI Mapping Register 6
314 * Offset 0x17: IP-PRI Mapping Register 7
315 */
316
317int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
318{
319 int err;
320
321 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
322 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
323 if (err)
324 return err;
325
326 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
327 if (err)
328 return err;
329
330 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
331 if (err)
332 return err;
333
334 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
335 if (err)
336 return err;
337
338 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
339 if (err)
340 return err;
341
342 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
343 if (err)
344 return err;
345
346 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
347 if (err)
348 return err;
349
350 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
351 if (err)
352 return err;
353
354 return 0;
355}
356
357/* Offset 0x18: IEEE-PRI Register */
358
359int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
360{
361 /* Reset the IEEE Tag priorities to defaults */
362 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
363}
364
365int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
366{
367 /* Reset the IEEE Tag priorities to defaults */
368 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
369}
370
371/* Offset 0x1a: Monitor Control */
372/* Offset 0x1a: Monitor & MGMT Control on some devices */
373
374int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
375 enum mv88e6xxx_egress_direction direction,
376 int port)
377{
378 u16 reg;
379 int err;
380
381 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
382 if (err)
383 return err;
384
385 switch (direction) {
386 case MV88E6XXX_EGRESS_DIR_INGRESS:
387 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
388 reg |= port <<
389 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
390 break;
391 case MV88E6XXX_EGRESS_DIR_EGRESS:
392 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
393 reg |= port <<
394 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
395 break;
396 default:
397 return -EINVAL;
398 }
399
400 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
401}
402
403/* Older generations also call this the ARP destination. It has been
404 * generalized in more modern devices such that more than ARP can
405 * egress it
406 */
407int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
408{
409 u16 reg;
410 int err;
411
412 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
413 if (err)
414 return err;
415
416 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
417 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
418
419 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
420}
421
422static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
423 u16 pointer, u8 data)
424{
425 u16 reg;
426
427 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
428
429 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
430}
431
432int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
433 enum mv88e6xxx_egress_direction direction,
434 int port)
435{
436 u16 ptr;
437
438 switch (direction) {
439 case MV88E6XXX_EGRESS_DIR_INGRESS:
440 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
441 break;
442 case MV88E6XXX_EGRESS_DIR_EGRESS:
443 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
444 break;
445 default:
446 return -EINVAL;
447 }
448
449 return mv88e6390_g1_monitor_write(chip, ptr, port);
450}
451
452int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
453{
454 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
455
456 /* Use the default high priority for management frames sent to
457 * the CPU.
458 */
459 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
460
461 return mv88e6390_g1_monitor_write(chip, ptr, port);
462}
463
464int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port)
465{
466 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST;
467
468 /* Use the default high priority for PTP frames sent to
469 * the CPU.
470 */
471 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
472
473 return mv88e6390_g1_monitor_write(chip, ptr, port);
474}
475
476int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
477{
478 u16 ptr;
479 int err;
480
481 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
482 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
483 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
484 if (err)
485 return err;
486
487 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
488 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
489 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
490 if (err)
491 return err;
492
493 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
494 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
495 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
496 if (err)
497 return err;
498
499 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
500 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
501 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
502 if (err)
503 return err;
504
505 return 0;
506}
507
508/* Offset 0x1c: Global Control 2 */
509
510static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
511 u16 val)
512{
513 u16 reg;
514 int err;
515
516 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
517 if (err)
518 return err;
519
520 reg &= ~mask;
521 reg |= val & mask;
522
523 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
524}
525
526int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
527{
528 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
529
530 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
531}
532
533int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
534{
535 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
536 MV88E6085_G1_CTL2_RM_ENABLE, 0);
537}
538
539int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
540{
541 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
542 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
543}
544
545int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
546{
547 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
548 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
549}
550
551int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
552{
553 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
554 MV88E6390_G1_CTL2_HIST_MODE_RX);
555}
556
557int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
558{
559 return mv88e6xxx_g1_ctl2_mask(chip,
560 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
561 index);
562}
563
564/* Offset 0x1d: Statistics Operation 2 */
565
566static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
567{
568 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
569
570 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
571}
572
573int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
574{
575 u16 val;
576 int err;
577
578 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
579 if (err)
580 return err;
581
582 val |= MV88E6XXX_G1_STATS_OP_HIST_RX;
583
584 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
585
586 return err;
587}
588
589int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
590{
591 int err;
592
593 /* Snapshot the hardware statistics counters for this port. */
594 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
595 MV88E6XXX_G1_STATS_OP_BUSY |
596 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
597 MV88E6XXX_G1_STATS_OP_HIST_RX | port);
598 if (err)
599 return err;
600
601 /* Wait for the snapshotting to complete. */
602 return mv88e6xxx_g1_stats_wait(chip);
603}
604
605int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
606{
607 port = (port + 1) << 5;
608
609 return mv88e6xxx_g1_stats_snapshot(chip, port);
610}
611
612int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
613{
614 int err;
615
616 port = (port + 1) << 5;
617
618 /* Snapshot the hardware statistics counters for this port. */
619 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
620 MV88E6XXX_G1_STATS_OP_BUSY |
621 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
622 if (err)
623 return err;
624
625 /* Wait for the snapshotting to complete. */
626 return mv88e6xxx_g1_stats_wait(chip);
627}
628
629void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
630{
631 u32 value;
632 u16 reg;
633 int err;
634
635 *val = 0;
636
637 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
638 MV88E6XXX_G1_STATS_OP_BUSY |
639 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
640 if (err)
641 return;
642
643 err = mv88e6xxx_g1_stats_wait(chip);
644 if (err)
645 return;
646
647 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
648 if (err)
649 return;
650
651 value = reg << 16;
652
653 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
654 if (err)
655 return;
656
657 *val = value | reg;
658}
659
660int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
661{
662 int err;
663 u16 val;
664
665 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
666 if (err)
667 return err;
668
669 /* Keep the histogram mode bits */
670 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
671 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
672
673 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
674 if (err)
675 return err;
676
677 /* Wait for the flush to complete. */
678 return mv88e6xxx_g1_stats_wait(chip);
679}
1/*
2 * Marvell 88E6xxx Switch Global (1) Registers support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/bitfield.h>
16
17#include "chip.h"
18#include "global1.h"
19
20int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
21{
22 int addr = chip->info->global1_addr;
23
24 return mv88e6xxx_read(chip, addr, reg, val);
25}
26
27int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
28{
29 int addr = chip->info->global1_addr;
30
31 return mv88e6xxx_write(chip, addr, reg, val);
32}
33
34int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
35{
36 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
37}
38
39/* Offset 0x00: Switch Global Status Register */
40
41static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
42{
43 u16 state;
44 int i, err;
45
46 for (i = 0; i < 16; i++) {
47 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
48 if (err)
49 return err;
50
51 /* Check the value of the PPUState bits 15:14 */
52 state &= MV88E6185_G1_STS_PPU_STATE_MASK;
53 if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
54 return 0;
55
56 usleep_range(1000, 2000);
57 }
58
59 return -ETIMEDOUT;
60}
61
62static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
63{
64 u16 state;
65 int i, err;
66
67 for (i = 0; i < 16; ++i) {
68 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
69 if (err)
70 return err;
71
72 /* Check the value of the PPUState bits 15:14 */
73 state &= MV88E6185_G1_STS_PPU_STATE_MASK;
74 if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
75 return 0;
76
77 usleep_range(1000, 2000);
78 }
79
80 return -ETIMEDOUT;
81}
82
83static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
84{
85 u16 state;
86 int i, err;
87
88 for (i = 0; i < 16; ++i) {
89 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
90 if (err)
91 return err;
92
93 /* Check the value of the PPUState (or InitState) bit 15 */
94 if (state & MV88E6352_G1_STS_PPU_STATE)
95 return 0;
96
97 usleep_range(1000, 2000);
98 }
99
100 return -ETIMEDOUT;
101}
102
103static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
104{
105 const unsigned long timeout = jiffies + 1 * HZ;
106 u16 val;
107 int err;
108
109 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
110 * is set to a one when all units inside the device (ATU, VTU, etc.)
111 * have finished their initialization and are ready to accept frames.
112 */
113 while (time_before(jiffies, timeout)) {
114 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
115 if (err)
116 return err;
117
118 if (val & MV88E6XXX_G1_STS_INIT_READY)
119 break;
120
121 usleep_range(1000, 2000);
122 }
123
124 if (time_after(jiffies, timeout))
125 return -ETIMEDOUT;
126
127 return 0;
128}
129
130/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
131 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
132 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
133 */
134int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
135{
136 u16 reg;
137 int err;
138
139 reg = (addr[0] << 8) | addr[1];
140 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
141 if (err)
142 return err;
143
144 reg = (addr[2] << 8) | addr[3];
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
146 if (err)
147 return err;
148
149 reg = (addr[4] << 8) | addr[5];
150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
151 if (err)
152 return err;
153
154 return 0;
155}
156
157/* Offset 0x04: Switch Global Control Register */
158
159int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
160{
161 u16 val;
162 int err;
163
164 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
165 * the PPU, including re-doing PHY detection and initialization
166 */
167 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
168 if (err)
169 return err;
170
171 val |= MV88E6XXX_G1_CTL1_SW_RESET;
172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
173
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
175 if (err)
176 return err;
177
178 err = mv88e6xxx_g1_wait_init_ready(chip);
179 if (err)
180 return err;
181
182 return mv88e6185_g1_wait_ppu_polling(chip);
183}
184
185int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
186{
187 u16 val;
188 int err;
189
190 /* Set the SWReset bit 15 */
191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
192 if (err)
193 return err;
194
195 val |= MV88E6XXX_G1_CTL1_SW_RESET;
196
197 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
198 if (err)
199 return err;
200
201 err = mv88e6xxx_g1_wait_init_ready(chip);
202 if (err)
203 return err;
204
205 return mv88e6352_g1_wait_ppu_polling(chip);
206}
207
208int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
209{
210 u16 val;
211 int err;
212
213 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
214 if (err)
215 return err;
216
217 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
218
219 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
220 if (err)
221 return err;
222
223 return mv88e6185_g1_wait_ppu_polling(chip);
224}
225
226int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
227{
228 u16 val;
229 int err;
230
231 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
232 if (err)
233 return err;
234
235 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
236
237 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
238 if (err)
239 return err;
240
241 return mv88e6185_g1_wait_ppu_disabled(chip);
242}
243
244/* Offset 0x1a: Monitor Control */
245/* Offset 0x1a: Monitor & MGMT Control on some devices */
246
247int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
248{
249 u16 reg;
250 int err;
251
252 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
253 if (err)
254 return err;
255
256 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
257 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
258
259 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
260 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
261
262 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
263}
264
265/* Older generations also call this the ARP destination. It has been
266 * generalized in more modern devices such that more than ARP can
267 * egress it
268 */
269int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
270{
271 u16 reg;
272 int err;
273
274 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
275 if (err)
276 return err;
277
278 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
279 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
280
281 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
282}
283
284static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
285 u16 pointer, u8 data)
286{
287 u16 reg;
288
289 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
290
291 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
292}
293
294int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
295{
296 u16 ptr;
297 int err;
298
299 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
300 err = mv88e6390_g1_monitor_write(chip, ptr, port);
301 if (err)
302 return err;
303
304 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
305 err = mv88e6390_g1_monitor_write(chip, ptr, port);
306 if (err)
307 return err;
308
309 return 0;
310}
311
312int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
313{
314 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
315
316 return mv88e6390_g1_monitor_write(chip, ptr, port);
317}
318
319int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
320{
321 u16 ptr;
322 int err;
323
324 /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
325 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
326 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
327 if (err)
328 return err;
329
330 /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
331 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
332 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
333 if (err)
334 return err;
335
336 /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
337 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
338 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
339 if (err)
340 return err;
341
342 /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
343 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
344 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
345 if (err)
346 return err;
347
348 return 0;
349}
350
351/* Offset 0x1c: Global Control 2 */
352
353int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
354{
355 u16 val;
356 int err;
357
358 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &val);
359 if (err)
360 return err;
361
362 val |= MV88E6XXX_G1_CTL2_HIST_RX_TX;
363
364 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, val);
365
366 return err;
367}
368
369/* Offset 0x1d: Statistics Operation 2 */
370
371int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
372{
373 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
374 MV88E6XXX_G1_STATS_OP_BUSY);
375}
376
377int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
378{
379 u16 val;
380 int err;
381
382 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
383 if (err)
384 return err;
385
386 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
387
388 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
389
390 return err;
391}
392
393int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
394{
395 int err;
396
397 /* Snapshot the hardware statistics counters for this port. */
398 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
399 MV88E6XXX_G1_STATS_OP_BUSY |
400 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
401 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
402 if (err)
403 return err;
404
405 /* Wait for the snapshotting to complete. */
406 return mv88e6xxx_g1_stats_wait(chip);
407}
408
409int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
410{
411 port = (port + 1) << 5;
412
413 return mv88e6xxx_g1_stats_snapshot(chip, port);
414}
415
416int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
417{
418 int err;
419
420 port = (port + 1) << 5;
421
422 /* Snapshot the hardware statistics counters for this port. */
423 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
424 MV88E6XXX_G1_STATS_OP_BUSY |
425 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
426 if (err)
427 return err;
428
429 /* Wait for the snapshotting to complete. */
430 return mv88e6xxx_g1_stats_wait(chip);
431}
432
433void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
434{
435 u32 value;
436 u16 reg;
437 int err;
438
439 *val = 0;
440
441 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
442 MV88E6XXX_G1_STATS_OP_BUSY |
443 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
444 if (err)
445 return;
446
447 err = mv88e6xxx_g1_stats_wait(chip);
448 if (err)
449 return;
450
451 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
452 if (err)
453 return;
454
455 value = reg << 16;
456
457 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
458 if (err)
459 return;
460
461 *val = value | reg;
462}
463
464int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
465{
466 int err;
467 u16 val;
468
469 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
470 if (err)
471 return err;
472
473 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
474
475 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
476 if (err)
477 return err;
478
479 /* Wait for the flush to complete. */
480 return mv88e6xxx_g1_stats_wait(chip);
481}