Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
6 */
7
8#include <linux/delay.h>
9#include <linux/dsa/ksz_common.h>
10#include <linux/export.h>
11#include <linux/gpio/consumer.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
18#include <linux/if_vlan.h>
19#include <linux/if_hsr.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_mdio.h>
24#include <linux/of_net.h>
25#include <linux/micrel_phy.h>
26#include <net/dsa.h>
27#include <net/ieee8021q.h>
28#include <net/pkt_cls.h>
29#include <net/switchdev.h>
30
31#include "ksz_common.h"
32#include "ksz_dcb.h"
33#include "ksz_ptp.h"
34#include "ksz8.h"
35#include "ksz9477.h"
36#include "lan937x.h"
37
38#define MIB_COUNTER_NUM 0x20
39
40struct ksz_stats_raw {
41 u64 rx_hi;
42 u64 rx_undersize;
43 u64 rx_fragments;
44 u64 rx_oversize;
45 u64 rx_jabbers;
46 u64 rx_symbol_err;
47 u64 rx_crc_err;
48 u64 rx_align_err;
49 u64 rx_mac_ctrl;
50 u64 rx_pause;
51 u64 rx_bcast;
52 u64 rx_mcast;
53 u64 rx_ucast;
54 u64 rx_64_or_less;
55 u64 rx_65_127;
56 u64 rx_128_255;
57 u64 rx_256_511;
58 u64 rx_512_1023;
59 u64 rx_1024_1522;
60 u64 rx_1523_2000;
61 u64 rx_2001;
62 u64 tx_hi;
63 u64 tx_late_col;
64 u64 tx_pause;
65 u64 tx_bcast;
66 u64 tx_mcast;
67 u64 tx_ucast;
68 u64 tx_deferred;
69 u64 tx_total_col;
70 u64 tx_exc_col;
71 u64 tx_single_col;
72 u64 tx_mult_col;
73 u64 rx_total;
74 u64 tx_total;
75 u64 rx_discards;
76 u64 tx_discards;
77};
78
79struct ksz88xx_stats_raw {
80 u64 rx;
81 u64 rx_hi;
82 u64 rx_undersize;
83 u64 rx_fragments;
84 u64 rx_oversize;
85 u64 rx_jabbers;
86 u64 rx_symbol_err;
87 u64 rx_crc_err;
88 u64 rx_align_err;
89 u64 rx_mac_ctrl;
90 u64 rx_pause;
91 u64 rx_bcast;
92 u64 rx_mcast;
93 u64 rx_ucast;
94 u64 rx_64_or_less;
95 u64 rx_65_127;
96 u64 rx_128_255;
97 u64 rx_256_511;
98 u64 rx_512_1023;
99 u64 rx_1024_1522;
100 u64 tx;
101 u64 tx_hi;
102 u64 tx_late_col;
103 u64 tx_pause;
104 u64 tx_bcast;
105 u64 tx_mcast;
106 u64 tx_ucast;
107 u64 tx_deferred;
108 u64 tx_total_col;
109 u64 tx_exc_col;
110 u64 tx_single_col;
111 u64 tx_mult_col;
112 u64 rx_discards;
113 u64 tx_discards;
114};
115
116static const struct ksz_mib_names ksz88xx_mib_names[] = {
117 { 0x00, "rx" },
118 { 0x01, "rx_hi" },
119 { 0x02, "rx_undersize" },
120 { 0x03, "rx_fragments" },
121 { 0x04, "rx_oversize" },
122 { 0x05, "rx_jabbers" },
123 { 0x06, "rx_symbol_err" },
124 { 0x07, "rx_crc_err" },
125 { 0x08, "rx_align_err" },
126 { 0x09, "rx_mac_ctrl" },
127 { 0x0a, "rx_pause" },
128 { 0x0b, "rx_bcast" },
129 { 0x0c, "rx_mcast" },
130 { 0x0d, "rx_ucast" },
131 { 0x0e, "rx_64_or_less" },
132 { 0x0f, "rx_65_127" },
133 { 0x10, "rx_128_255" },
134 { 0x11, "rx_256_511" },
135 { 0x12, "rx_512_1023" },
136 { 0x13, "rx_1024_1522" },
137 { 0x14, "tx" },
138 { 0x15, "tx_hi" },
139 { 0x16, "tx_late_col" },
140 { 0x17, "tx_pause" },
141 { 0x18, "tx_bcast" },
142 { 0x19, "tx_mcast" },
143 { 0x1a, "tx_ucast" },
144 { 0x1b, "tx_deferred" },
145 { 0x1c, "tx_total_col" },
146 { 0x1d, "tx_exc_col" },
147 { 0x1e, "tx_single_col" },
148 { 0x1f, "tx_mult_col" },
149 { 0x100, "rx_discards" },
150 { 0x101, "tx_discards" },
151};
152
153static const struct ksz_mib_names ksz9477_mib_names[] = {
154 { 0x00, "rx_hi" },
155 { 0x01, "rx_undersize" },
156 { 0x02, "rx_fragments" },
157 { 0x03, "rx_oversize" },
158 { 0x04, "rx_jabbers" },
159 { 0x05, "rx_symbol_err" },
160 { 0x06, "rx_crc_err" },
161 { 0x07, "rx_align_err" },
162 { 0x08, "rx_mac_ctrl" },
163 { 0x09, "rx_pause" },
164 { 0x0A, "rx_bcast" },
165 { 0x0B, "rx_mcast" },
166 { 0x0C, "rx_ucast" },
167 { 0x0D, "rx_64_or_less" },
168 { 0x0E, "rx_65_127" },
169 { 0x0F, "rx_128_255" },
170 { 0x10, "rx_256_511" },
171 { 0x11, "rx_512_1023" },
172 { 0x12, "rx_1024_1522" },
173 { 0x13, "rx_1523_2000" },
174 { 0x14, "rx_2001" },
175 { 0x15, "tx_hi" },
176 { 0x16, "tx_late_col" },
177 { 0x17, "tx_pause" },
178 { 0x18, "tx_bcast" },
179 { 0x19, "tx_mcast" },
180 { 0x1A, "tx_ucast" },
181 { 0x1B, "tx_deferred" },
182 { 0x1C, "tx_total_col" },
183 { 0x1D, "tx_exc_col" },
184 { 0x1E, "tx_single_col" },
185 { 0x1F, "tx_mult_col" },
186 { 0x80, "rx_total" },
187 { 0x81, "tx_total" },
188 { 0x82, "rx_discards" },
189 { 0x83, "tx_discards" },
190};
191
192struct ksz_driver_strength_prop {
193 const char *name;
194 int offset;
195 int value;
196};
197
198enum ksz_driver_strength_type {
199 KSZ_DRIVER_STRENGTH_HI,
200 KSZ_DRIVER_STRENGTH_LO,
201 KSZ_DRIVER_STRENGTH_IO,
202};
203
204/**
205 * struct ksz_drive_strength - drive strength mapping
206 * @reg_val: register value
207 * @microamp: microamp value
208 */
209struct ksz_drive_strength {
210 u32 reg_val;
211 u32 microamp;
212};
213
214/* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
215 *
216 * This values are not documented in KSZ9477 variants but confirmed by
217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
219 *
220 * Documentation in KSZ8795CLX provides more information with some
221 * recommendations:
222 * - for high speed signals
223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
224 * 2.5V or 3.3V VDDIO.
225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
226 * using 1.8V VDDIO.
227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
228 * or 3.3V VDDIO.
229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
230 * 5. In same interface, the heavy loading should use higher one of the
231 * drive current strength.
232 * - for low speed signals
233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
236 * 4. If it is heavy loading, can use higher drive current strength.
237 */
238static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
239 { SW_DRIVE_STRENGTH_2MA, 2000 },
240 { SW_DRIVE_STRENGTH_4MA, 4000 },
241 { SW_DRIVE_STRENGTH_8MA, 8000 },
242 { SW_DRIVE_STRENGTH_12MA, 12000 },
243 { SW_DRIVE_STRENGTH_16MA, 16000 },
244 { SW_DRIVE_STRENGTH_20MA, 20000 },
245 { SW_DRIVE_STRENGTH_24MA, 24000 },
246 { SW_DRIVE_STRENGTH_28MA, 28000 },
247};
248
249/* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
250 * variants.
251 * This values are documented in KSZ8873 and KSZ8863 datasheets.
252 */
253static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
254 { 0, 8000 },
255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
256};
257
258static void ksz88x3_phylink_mac_config(struct phylink_config *config,
259 unsigned int mode,
260 const struct phylink_link_state *state);
261static void ksz_phylink_mac_config(struct phylink_config *config,
262 unsigned int mode,
263 const struct phylink_link_state *state);
264static void ksz_phylink_mac_link_down(struct phylink_config *config,
265 unsigned int mode,
266 phy_interface_t interface);
267
268static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
269 .mac_config = ksz88x3_phylink_mac_config,
270 .mac_link_down = ksz_phylink_mac_link_down,
271 .mac_link_up = ksz8_phylink_mac_link_up,
272};
273
274static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
275 .mac_config = ksz_phylink_mac_config,
276 .mac_link_down = ksz_phylink_mac_link_down,
277 .mac_link_up = ksz8_phylink_mac_link_up,
278};
279
280static const struct ksz_dev_ops ksz88xx_dev_ops = {
281 .setup = ksz8_setup,
282 .get_port_addr = ksz8_get_port_addr,
283 .cfg_port_member = ksz8_cfg_port_member,
284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
285 .port_setup = ksz8_port_setup,
286 .r_phy = ksz8_r_phy,
287 .w_phy = ksz8_w_phy,
288 .r_mib_cnt = ksz8_r_mib_cnt,
289 .r_mib_pkt = ksz8_r_mib_pkt,
290 .r_mib_stat64 = ksz88xx_r_mib_stats64,
291 .freeze_mib = ksz8_freeze_mib,
292 .port_init_cnt = ksz8_port_init_cnt,
293 .fdb_dump = ksz8_fdb_dump,
294 .fdb_add = ksz8_fdb_add,
295 .fdb_del = ksz8_fdb_del,
296 .mdb_add = ksz8_mdb_add,
297 .mdb_del = ksz8_mdb_del,
298 .vlan_filtering = ksz8_port_vlan_filtering,
299 .vlan_add = ksz8_port_vlan_add,
300 .vlan_del = ksz8_port_vlan_del,
301 .mirror_add = ksz8_port_mirror_add,
302 .mirror_del = ksz8_port_mirror_del,
303 .get_caps = ksz8_get_caps,
304 .config_cpu_port = ksz8_config_cpu_port,
305 .enable_stp_addr = ksz8_enable_stp_addr,
306 .reset = ksz8_reset_switch,
307 .init = ksz8_switch_init,
308 .exit = ksz8_switch_exit,
309 .change_mtu = ksz8_change_mtu,
310 .pme_write8 = ksz8_pme_write8,
311 .pme_pread8 = ksz8_pme_pread8,
312 .pme_pwrite8 = ksz8_pme_pwrite8,
313};
314
315static const struct ksz_dev_ops ksz87xx_dev_ops = {
316 .setup = ksz8_setup,
317 .get_port_addr = ksz8_get_port_addr,
318 .cfg_port_member = ksz8_cfg_port_member,
319 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
320 .port_setup = ksz8_port_setup,
321 .r_phy = ksz8_r_phy,
322 .w_phy = ksz8_w_phy,
323 .r_mib_cnt = ksz8_r_mib_cnt,
324 .r_mib_pkt = ksz8_r_mib_pkt,
325 .r_mib_stat64 = ksz_r_mib_stats64,
326 .freeze_mib = ksz8_freeze_mib,
327 .port_init_cnt = ksz8_port_init_cnt,
328 .fdb_dump = ksz8_fdb_dump,
329 .fdb_add = ksz8_fdb_add,
330 .fdb_del = ksz8_fdb_del,
331 .mdb_add = ksz8_mdb_add,
332 .mdb_del = ksz8_mdb_del,
333 .vlan_filtering = ksz8_port_vlan_filtering,
334 .vlan_add = ksz8_port_vlan_add,
335 .vlan_del = ksz8_port_vlan_del,
336 .mirror_add = ksz8_port_mirror_add,
337 .mirror_del = ksz8_port_mirror_del,
338 .get_caps = ksz8_get_caps,
339 .config_cpu_port = ksz8_config_cpu_port,
340 .enable_stp_addr = ksz8_enable_stp_addr,
341 .reset = ksz8_reset_switch,
342 .init = ksz8_switch_init,
343 .exit = ksz8_switch_exit,
344 .change_mtu = ksz8_change_mtu,
345 .pme_write8 = ksz8_pme_write8,
346 .pme_pread8 = ksz8_pme_pread8,
347 .pme_pwrite8 = ksz8_pme_pwrite8,
348};
349
350static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
351 struct phy_device *phydev,
352 unsigned int mode,
353 phy_interface_t interface,
354 int speed, int duplex, bool tx_pause,
355 bool rx_pause);
356
357static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
358 .mac_config = ksz_phylink_mac_config,
359 .mac_link_down = ksz_phylink_mac_link_down,
360 .mac_link_up = ksz9477_phylink_mac_link_up,
361};
362
363static const struct ksz_dev_ops ksz9477_dev_ops = {
364 .setup = ksz9477_setup,
365 .get_port_addr = ksz9477_get_port_addr,
366 .cfg_port_member = ksz9477_cfg_port_member,
367 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
368 .port_setup = ksz9477_port_setup,
369 .set_ageing_time = ksz9477_set_ageing_time,
370 .r_phy = ksz9477_r_phy,
371 .w_phy = ksz9477_w_phy,
372 .r_mib_cnt = ksz9477_r_mib_cnt,
373 .r_mib_pkt = ksz9477_r_mib_pkt,
374 .r_mib_stat64 = ksz_r_mib_stats64,
375 .freeze_mib = ksz9477_freeze_mib,
376 .port_init_cnt = ksz9477_port_init_cnt,
377 .vlan_filtering = ksz9477_port_vlan_filtering,
378 .vlan_add = ksz9477_port_vlan_add,
379 .vlan_del = ksz9477_port_vlan_del,
380 .mirror_add = ksz9477_port_mirror_add,
381 .mirror_del = ksz9477_port_mirror_del,
382 .get_caps = ksz9477_get_caps,
383 .fdb_dump = ksz9477_fdb_dump,
384 .fdb_add = ksz9477_fdb_add,
385 .fdb_del = ksz9477_fdb_del,
386 .mdb_add = ksz9477_mdb_add,
387 .mdb_del = ksz9477_mdb_del,
388 .change_mtu = ksz9477_change_mtu,
389 .pme_write8 = ksz_write8,
390 .pme_pread8 = ksz_pread8,
391 .pme_pwrite8 = ksz_pwrite8,
392 .config_cpu_port = ksz9477_config_cpu_port,
393 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
394 .enable_stp_addr = ksz9477_enable_stp_addr,
395 .reset = ksz9477_reset_switch,
396 .init = ksz9477_switch_init,
397 .exit = ksz9477_switch_exit,
398};
399
400static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
401 .mac_config = ksz_phylink_mac_config,
402 .mac_link_down = ksz_phylink_mac_link_down,
403 .mac_link_up = ksz9477_phylink_mac_link_up,
404};
405
406static const struct ksz_dev_ops lan937x_dev_ops = {
407 .setup = lan937x_setup,
408 .teardown = lan937x_teardown,
409 .get_port_addr = ksz9477_get_port_addr,
410 .cfg_port_member = ksz9477_cfg_port_member,
411 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
412 .port_setup = lan937x_port_setup,
413 .set_ageing_time = lan937x_set_ageing_time,
414 .mdio_bus_preinit = lan937x_mdio_bus_preinit,
415 .create_phy_addr_map = lan937x_create_phy_addr_map,
416 .r_phy = lan937x_r_phy,
417 .w_phy = lan937x_w_phy,
418 .r_mib_cnt = ksz9477_r_mib_cnt,
419 .r_mib_pkt = ksz9477_r_mib_pkt,
420 .r_mib_stat64 = ksz_r_mib_stats64,
421 .freeze_mib = ksz9477_freeze_mib,
422 .port_init_cnt = ksz9477_port_init_cnt,
423 .vlan_filtering = ksz9477_port_vlan_filtering,
424 .vlan_add = ksz9477_port_vlan_add,
425 .vlan_del = ksz9477_port_vlan_del,
426 .mirror_add = ksz9477_port_mirror_add,
427 .mirror_del = ksz9477_port_mirror_del,
428 .get_caps = lan937x_phylink_get_caps,
429 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
430 .fdb_dump = ksz9477_fdb_dump,
431 .fdb_add = ksz9477_fdb_add,
432 .fdb_del = ksz9477_fdb_del,
433 .mdb_add = ksz9477_mdb_add,
434 .mdb_del = ksz9477_mdb_del,
435 .change_mtu = lan937x_change_mtu,
436 .config_cpu_port = lan937x_config_cpu_port,
437 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
438 .enable_stp_addr = ksz9477_enable_stp_addr,
439 .reset = lan937x_reset_switch,
440 .init = lan937x_switch_init,
441 .exit = lan937x_switch_exit,
442};
443
444static const u16 ksz8795_regs[] = {
445 [REG_SW_MAC_ADDR] = 0x68,
446 [REG_IND_CTRL_0] = 0x6E,
447 [REG_IND_DATA_8] = 0x70,
448 [REG_IND_DATA_CHECK] = 0x72,
449 [REG_IND_DATA_HI] = 0x71,
450 [REG_IND_DATA_LO] = 0x75,
451 [REG_IND_MIB_CHECK] = 0x74,
452 [REG_IND_BYTE] = 0xA0,
453 [P_FORCE_CTRL] = 0x0C,
454 [P_LINK_STATUS] = 0x0E,
455 [P_LOCAL_CTRL] = 0x07,
456 [P_NEG_RESTART_CTRL] = 0x0D,
457 [P_REMOTE_STATUS] = 0x08,
458 [P_SPEED_STATUS] = 0x09,
459 [S_TAIL_TAG_CTRL] = 0x0C,
460 [P_STP_CTRL] = 0x02,
461 [S_START_CTRL] = 0x01,
462 [S_BROADCAST_CTRL] = 0x06,
463 [S_MULTICAST_CTRL] = 0x04,
464 [P_XMII_CTRL_0] = 0x06,
465 [P_XMII_CTRL_1] = 0x06,
466 [REG_SW_PME_CTRL] = 0x8003,
467 [REG_PORT_PME_STATUS] = 0x8003,
468 [REG_PORT_PME_CTRL] = 0x8007,
469};
470
471static const u32 ksz8795_masks[] = {
472 [PORT_802_1P_REMAPPING] = BIT(7),
473 [SW_TAIL_TAG_ENABLE] = BIT(1),
474 [MIB_COUNTER_OVERFLOW] = BIT(6),
475 [MIB_COUNTER_VALID] = BIT(5),
476 [VLAN_TABLE_FID] = GENMASK(6, 0),
477 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
478 [VLAN_TABLE_VALID] = BIT(12),
479 [STATIC_MAC_TABLE_VALID] = BIT(21),
480 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
481 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
482 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
483 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
484 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
485 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
486 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
487 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
488 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
489 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
490 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
491 [P_MII_TX_FLOW_CTRL] = BIT(5),
492 [P_MII_RX_FLOW_CTRL] = BIT(5),
493};
494
495static const u8 ksz8795_xmii_ctrl0[] = {
496 [P_MII_100MBIT] = 0,
497 [P_MII_10MBIT] = 1,
498 [P_MII_FULL_DUPLEX] = 0,
499 [P_MII_HALF_DUPLEX] = 1,
500};
501
502static const u8 ksz8795_xmii_ctrl1[] = {
503 [P_RGMII_SEL] = 3,
504 [P_GMII_SEL] = 2,
505 [P_RMII_SEL] = 1,
506 [P_MII_SEL] = 0,
507 [P_GMII_1GBIT] = 1,
508 [P_GMII_NOT_1GBIT] = 0,
509};
510
511static const u8 ksz8795_shifts[] = {
512 [VLAN_TABLE_MEMBERSHIP_S] = 7,
513 [VLAN_TABLE] = 16,
514 [STATIC_MAC_FWD_PORTS] = 16,
515 [STATIC_MAC_FID] = 24,
516 [DYNAMIC_MAC_ENTRIES_H] = 3,
517 [DYNAMIC_MAC_ENTRIES] = 29,
518 [DYNAMIC_MAC_FID] = 16,
519 [DYNAMIC_MAC_TIMESTAMP] = 27,
520 [DYNAMIC_MAC_SRC_PORT] = 24,
521};
522
523static const u16 ksz8863_regs[] = {
524 [REG_SW_MAC_ADDR] = 0x70,
525 [REG_IND_CTRL_0] = 0x79,
526 [REG_IND_DATA_8] = 0x7B,
527 [REG_IND_DATA_CHECK] = 0x7B,
528 [REG_IND_DATA_HI] = 0x7C,
529 [REG_IND_DATA_LO] = 0x80,
530 [REG_IND_MIB_CHECK] = 0x80,
531 [P_FORCE_CTRL] = 0x0C,
532 [P_LINK_STATUS] = 0x0E,
533 [P_LOCAL_CTRL] = 0x0C,
534 [P_NEG_RESTART_CTRL] = 0x0D,
535 [P_REMOTE_STATUS] = 0x0E,
536 [P_SPEED_STATUS] = 0x0F,
537 [S_TAIL_TAG_CTRL] = 0x03,
538 [P_STP_CTRL] = 0x02,
539 [S_START_CTRL] = 0x01,
540 [S_BROADCAST_CTRL] = 0x06,
541 [S_MULTICAST_CTRL] = 0x04,
542};
543
544static const u32 ksz8863_masks[] = {
545 [PORT_802_1P_REMAPPING] = BIT(3),
546 [SW_TAIL_TAG_ENABLE] = BIT(6),
547 [MIB_COUNTER_OVERFLOW] = BIT(7),
548 [MIB_COUNTER_VALID] = BIT(6),
549 [VLAN_TABLE_FID] = GENMASK(15, 12),
550 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
551 [VLAN_TABLE_VALID] = BIT(19),
552 [STATIC_MAC_TABLE_VALID] = BIT(19),
553 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
554 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
555 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
556 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
557 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
558 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
559 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
560 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
561 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
562 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
563 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
564};
565
566static u8 ksz8863_shifts[] = {
567 [VLAN_TABLE_MEMBERSHIP_S] = 16,
568 [STATIC_MAC_FWD_PORTS] = 16,
569 [STATIC_MAC_FID] = 22,
570 [DYNAMIC_MAC_ENTRIES_H] = 8,
571 [DYNAMIC_MAC_ENTRIES] = 24,
572 [DYNAMIC_MAC_FID] = 16,
573 [DYNAMIC_MAC_TIMESTAMP] = 22,
574 [DYNAMIC_MAC_SRC_PORT] = 20,
575};
576
577static const u16 ksz8895_regs[] = {
578 [REG_SW_MAC_ADDR] = 0x68,
579 [REG_IND_CTRL_0] = 0x6E,
580 [REG_IND_DATA_8] = 0x70,
581 [REG_IND_DATA_CHECK] = 0x72,
582 [REG_IND_DATA_HI] = 0x71,
583 [REG_IND_DATA_LO] = 0x75,
584 [REG_IND_MIB_CHECK] = 0x75,
585 [P_FORCE_CTRL] = 0x0C,
586 [P_LINK_STATUS] = 0x0E,
587 [P_LOCAL_CTRL] = 0x0C,
588 [P_NEG_RESTART_CTRL] = 0x0D,
589 [P_REMOTE_STATUS] = 0x0E,
590 [P_SPEED_STATUS] = 0x09,
591 [S_TAIL_TAG_CTRL] = 0x0C,
592 [P_STP_CTRL] = 0x02,
593 [S_START_CTRL] = 0x01,
594 [S_BROADCAST_CTRL] = 0x06,
595 [S_MULTICAST_CTRL] = 0x04,
596};
597
598static const u32 ksz8895_masks[] = {
599 [PORT_802_1P_REMAPPING] = BIT(7),
600 [SW_TAIL_TAG_ENABLE] = BIT(1),
601 [MIB_COUNTER_OVERFLOW] = BIT(7),
602 [MIB_COUNTER_VALID] = BIT(6),
603 [VLAN_TABLE_FID] = GENMASK(6, 0),
604 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
605 [VLAN_TABLE_VALID] = BIT(12),
606 [STATIC_MAC_TABLE_VALID] = BIT(21),
607 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
608 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
609 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
610 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
611 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
612 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
613 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
614 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
615 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
616 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
617 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
618};
619
620static const u8 ksz8895_shifts[] = {
621 [VLAN_TABLE_MEMBERSHIP_S] = 7,
622 [VLAN_TABLE] = 13,
623 [STATIC_MAC_FWD_PORTS] = 16,
624 [STATIC_MAC_FID] = 24,
625 [DYNAMIC_MAC_ENTRIES_H] = 3,
626 [DYNAMIC_MAC_ENTRIES] = 29,
627 [DYNAMIC_MAC_FID] = 16,
628 [DYNAMIC_MAC_TIMESTAMP] = 27,
629 [DYNAMIC_MAC_SRC_PORT] = 24,
630};
631
632static const u16 ksz9477_regs[] = {
633 [REG_SW_MAC_ADDR] = 0x0302,
634 [P_STP_CTRL] = 0x0B04,
635 [S_START_CTRL] = 0x0300,
636 [S_BROADCAST_CTRL] = 0x0332,
637 [S_MULTICAST_CTRL] = 0x0331,
638 [P_XMII_CTRL_0] = 0x0300,
639 [P_XMII_CTRL_1] = 0x0301,
640 [REG_SW_PME_CTRL] = 0x0006,
641 [REG_PORT_PME_STATUS] = 0x0013,
642 [REG_PORT_PME_CTRL] = 0x0017,
643};
644
645static const u32 ksz9477_masks[] = {
646 [ALU_STAT_WRITE] = 0,
647 [ALU_STAT_READ] = 1,
648 [P_MII_TX_FLOW_CTRL] = BIT(5),
649 [P_MII_RX_FLOW_CTRL] = BIT(3),
650};
651
652static const u8 ksz9477_shifts[] = {
653 [ALU_STAT_INDEX] = 16,
654};
655
656static const u8 ksz9477_xmii_ctrl0[] = {
657 [P_MII_100MBIT] = 1,
658 [P_MII_10MBIT] = 0,
659 [P_MII_FULL_DUPLEX] = 1,
660 [P_MII_HALF_DUPLEX] = 0,
661};
662
663static const u8 ksz9477_xmii_ctrl1[] = {
664 [P_RGMII_SEL] = 0,
665 [P_RMII_SEL] = 1,
666 [P_GMII_SEL] = 2,
667 [P_MII_SEL] = 3,
668 [P_GMII_1GBIT] = 0,
669 [P_GMII_NOT_1GBIT] = 1,
670};
671
672static const u32 lan937x_masks[] = {
673 [ALU_STAT_WRITE] = 1,
674 [ALU_STAT_READ] = 2,
675 [P_MII_TX_FLOW_CTRL] = BIT(5),
676 [P_MII_RX_FLOW_CTRL] = BIT(3),
677};
678
679static const u8 lan937x_shifts[] = {
680 [ALU_STAT_INDEX] = 8,
681};
682
683static const struct regmap_range ksz8563_valid_regs[] = {
684 regmap_reg_range(0x0000, 0x0003),
685 regmap_reg_range(0x0006, 0x0006),
686 regmap_reg_range(0x000f, 0x001f),
687 regmap_reg_range(0x0100, 0x0100),
688 regmap_reg_range(0x0104, 0x0107),
689 regmap_reg_range(0x010d, 0x010d),
690 regmap_reg_range(0x0110, 0x0113),
691 regmap_reg_range(0x0120, 0x012b),
692 regmap_reg_range(0x0201, 0x0201),
693 regmap_reg_range(0x0210, 0x0213),
694 regmap_reg_range(0x0300, 0x0300),
695 regmap_reg_range(0x0302, 0x031b),
696 regmap_reg_range(0x0320, 0x032b),
697 regmap_reg_range(0x0330, 0x0336),
698 regmap_reg_range(0x0338, 0x033e),
699 regmap_reg_range(0x0340, 0x035f),
700 regmap_reg_range(0x0370, 0x0370),
701 regmap_reg_range(0x0378, 0x0378),
702 regmap_reg_range(0x037c, 0x037d),
703 regmap_reg_range(0x0390, 0x0393),
704 regmap_reg_range(0x0400, 0x040e),
705 regmap_reg_range(0x0410, 0x042f),
706 regmap_reg_range(0x0500, 0x0519),
707 regmap_reg_range(0x0520, 0x054b),
708 regmap_reg_range(0x0550, 0x05b3),
709
710 /* port 1 */
711 regmap_reg_range(0x1000, 0x1001),
712 regmap_reg_range(0x1004, 0x100b),
713 regmap_reg_range(0x1013, 0x1013),
714 regmap_reg_range(0x1017, 0x1017),
715 regmap_reg_range(0x101b, 0x101b),
716 regmap_reg_range(0x101f, 0x1021),
717 regmap_reg_range(0x1030, 0x1030),
718 regmap_reg_range(0x1100, 0x1111),
719 regmap_reg_range(0x111a, 0x111d),
720 regmap_reg_range(0x1122, 0x1127),
721 regmap_reg_range(0x112a, 0x112b),
722 regmap_reg_range(0x1136, 0x1139),
723 regmap_reg_range(0x113e, 0x113f),
724 regmap_reg_range(0x1400, 0x1401),
725 regmap_reg_range(0x1403, 0x1403),
726 regmap_reg_range(0x1410, 0x1417),
727 regmap_reg_range(0x1420, 0x1423),
728 regmap_reg_range(0x1500, 0x1507),
729 regmap_reg_range(0x1600, 0x1612),
730 regmap_reg_range(0x1800, 0x180f),
731 regmap_reg_range(0x1900, 0x1907),
732 regmap_reg_range(0x1914, 0x191b),
733 regmap_reg_range(0x1a00, 0x1a03),
734 regmap_reg_range(0x1a04, 0x1a08),
735 regmap_reg_range(0x1b00, 0x1b01),
736 regmap_reg_range(0x1b04, 0x1b04),
737 regmap_reg_range(0x1c00, 0x1c05),
738 regmap_reg_range(0x1c08, 0x1c1b),
739
740 /* port 2 */
741 regmap_reg_range(0x2000, 0x2001),
742 regmap_reg_range(0x2004, 0x200b),
743 regmap_reg_range(0x2013, 0x2013),
744 regmap_reg_range(0x2017, 0x2017),
745 regmap_reg_range(0x201b, 0x201b),
746 regmap_reg_range(0x201f, 0x2021),
747 regmap_reg_range(0x2030, 0x2030),
748 regmap_reg_range(0x2100, 0x2111),
749 regmap_reg_range(0x211a, 0x211d),
750 regmap_reg_range(0x2122, 0x2127),
751 regmap_reg_range(0x212a, 0x212b),
752 regmap_reg_range(0x2136, 0x2139),
753 regmap_reg_range(0x213e, 0x213f),
754 regmap_reg_range(0x2400, 0x2401),
755 regmap_reg_range(0x2403, 0x2403),
756 regmap_reg_range(0x2410, 0x2417),
757 regmap_reg_range(0x2420, 0x2423),
758 regmap_reg_range(0x2500, 0x2507),
759 regmap_reg_range(0x2600, 0x2612),
760 regmap_reg_range(0x2800, 0x280f),
761 regmap_reg_range(0x2900, 0x2907),
762 regmap_reg_range(0x2914, 0x291b),
763 regmap_reg_range(0x2a00, 0x2a03),
764 regmap_reg_range(0x2a04, 0x2a08),
765 regmap_reg_range(0x2b00, 0x2b01),
766 regmap_reg_range(0x2b04, 0x2b04),
767 regmap_reg_range(0x2c00, 0x2c05),
768 regmap_reg_range(0x2c08, 0x2c1b),
769
770 /* port 3 */
771 regmap_reg_range(0x3000, 0x3001),
772 regmap_reg_range(0x3004, 0x300b),
773 regmap_reg_range(0x3013, 0x3013),
774 regmap_reg_range(0x3017, 0x3017),
775 regmap_reg_range(0x301b, 0x301b),
776 regmap_reg_range(0x301f, 0x3021),
777 regmap_reg_range(0x3030, 0x3030),
778 regmap_reg_range(0x3300, 0x3301),
779 regmap_reg_range(0x3303, 0x3303),
780 regmap_reg_range(0x3400, 0x3401),
781 regmap_reg_range(0x3403, 0x3403),
782 regmap_reg_range(0x3410, 0x3417),
783 regmap_reg_range(0x3420, 0x3423),
784 regmap_reg_range(0x3500, 0x3507),
785 regmap_reg_range(0x3600, 0x3612),
786 regmap_reg_range(0x3800, 0x380f),
787 regmap_reg_range(0x3900, 0x3907),
788 regmap_reg_range(0x3914, 0x391b),
789 regmap_reg_range(0x3a00, 0x3a03),
790 regmap_reg_range(0x3a04, 0x3a08),
791 regmap_reg_range(0x3b00, 0x3b01),
792 regmap_reg_range(0x3b04, 0x3b04),
793 regmap_reg_range(0x3c00, 0x3c05),
794 regmap_reg_range(0x3c08, 0x3c1b),
795};
796
797static const struct regmap_access_table ksz8563_register_set = {
798 .yes_ranges = ksz8563_valid_regs,
799 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
800};
801
802static const struct regmap_range ksz9477_valid_regs[] = {
803 regmap_reg_range(0x0000, 0x0003),
804 regmap_reg_range(0x0006, 0x0006),
805 regmap_reg_range(0x0010, 0x001f),
806 regmap_reg_range(0x0100, 0x0100),
807 regmap_reg_range(0x0103, 0x0107),
808 regmap_reg_range(0x010d, 0x010d),
809 regmap_reg_range(0x0110, 0x0113),
810 regmap_reg_range(0x0120, 0x012b),
811 regmap_reg_range(0x0201, 0x0201),
812 regmap_reg_range(0x0210, 0x0213),
813 regmap_reg_range(0x0300, 0x0300),
814 regmap_reg_range(0x0302, 0x031b),
815 regmap_reg_range(0x0320, 0x032b),
816 regmap_reg_range(0x0330, 0x0336),
817 regmap_reg_range(0x0338, 0x033b),
818 regmap_reg_range(0x033e, 0x033e),
819 regmap_reg_range(0x0340, 0x035f),
820 regmap_reg_range(0x0370, 0x0370),
821 regmap_reg_range(0x0378, 0x0378),
822 regmap_reg_range(0x037c, 0x037d),
823 regmap_reg_range(0x0390, 0x0393),
824 regmap_reg_range(0x0400, 0x040e),
825 regmap_reg_range(0x0410, 0x042f),
826 regmap_reg_range(0x0444, 0x044b),
827 regmap_reg_range(0x0450, 0x046f),
828 regmap_reg_range(0x0500, 0x0519),
829 regmap_reg_range(0x0520, 0x054b),
830 regmap_reg_range(0x0550, 0x05b3),
831 regmap_reg_range(0x0604, 0x060b),
832 regmap_reg_range(0x0610, 0x0612),
833 regmap_reg_range(0x0614, 0x062c),
834 regmap_reg_range(0x0640, 0x0645),
835 regmap_reg_range(0x0648, 0x064d),
836
837 /* port 1 */
838 regmap_reg_range(0x1000, 0x1001),
839 regmap_reg_range(0x1013, 0x1013),
840 regmap_reg_range(0x1017, 0x1017),
841 regmap_reg_range(0x101b, 0x101b),
842 regmap_reg_range(0x101f, 0x1020),
843 regmap_reg_range(0x1030, 0x1030),
844 regmap_reg_range(0x1100, 0x1115),
845 regmap_reg_range(0x111a, 0x111f),
846 regmap_reg_range(0x1120, 0x112b),
847 regmap_reg_range(0x1134, 0x113b),
848 regmap_reg_range(0x113c, 0x113f),
849 regmap_reg_range(0x1400, 0x1401),
850 regmap_reg_range(0x1403, 0x1403),
851 regmap_reg_range(0x1410, 0x1417),
852 regmap_reg_range(0x1420, 0x1423),
853 regmap_reg_range(0x1500, 0x1507),
854 regmap_reg_range(0x1600, 0x1613),
855 regmap_reg_range(0x1800, 0x180f),
856 regmap_reg_range(0x1820, 0x1827),
857 regmap_reg_range(0x1830, 0x1837),
858 regmap_reg_range(0x1840, 0x184b),
859 regmap_reg_range(0x1900, 0x1907),
860 regmap_reg_range(0x1914, 0x191b),
861 regmap_reg_range(0x1920, 0x1920),
862 regmap_reg_range(0x1923, 0x1927),
863 regmap_reg_range(0x1a00, 0x1a03),
864 regmap_reg_range(0x1a04, 0x1a07),
865 regmap_reg_range(0x1b00, 0x1b01),
866 regmap_reg_range(0x1b04, 0x1b04),
867 regmap_reg_range(0x1c00, 0x1c05),
868 regmap_reg_range(0x1c08, 0x1c1b),
869
870 /* port 2 */
871 regmap_reg_range(0x2000, 0x2001),
872 regmap_reg_range(0x2013, 0x2013),
873 regmap_reg_range(0x2017, 0x2017),
874 regmap_reg_range(0x201b, 0x201b),
875 regmap_reg_range(0x201f, 0x2020),
876 regmap_reg_range(0x2030, 0x2030),
877 regmap_reg_range(0x2100, 0x2115),
878 regmap_reg_range(0x211a, 0x211f),
879 regmap_reg_range(0x2120, 0x212b),
880 regmap_reg_range(0x2134, 0x213b),
881 regmap_reg_range(0x213c, 0x213f),
882 regmap_reg_range(0x2400, 0x2401),
883 regmap_reg_range(0x2403, 0x2403),
884 regmap_reg_range(0x2410, 0x2417),
885 regmap_reg_range(0x2420, 0x2423),
886 regmap_reg_range(0x2500, 0x2507),
887 regmap_reg_range(0x2600, 0x2613),
888 regmap_reg_range(0x2800, 0x280f),
889 regmap_reg_range(0x2820, 0x2827),
890 regmap_reg_range(0x2830, 0x2837),
891 regmap_reg_range(0x2840, 0x284b),
892 regmap_reg_range(0x2900, 0x2907),
893 regmap_reg_range(0x2914, 0x291b),
894 regmap_reg_range(0x2920, 0x2920),
895 regmap_reg_range(0x2923, 0x2927),
896 regmap_reg_range(0x2a00, 0x2a03),
897 regmap_reg_range(0x2a04, 0x2a07),
898 regmap_reg_range(0x2b00, 0x2b01),
899 regmap_reg_range(0x2b04, 0x2b04),
900 regmap_reg_range(0x2c00, 0x2c05),
901 regmap_reg_range(0x2c08, 0x2c1b),
902
903 /* port 3 */
904 regmap_reg_range(0x3000, 0x3001),
905 regmap_reg_range(0x3013, 0x3013),
906 regmap_reg_range(0x3017, 0x3017),
907 regmap_reg_range(0x301b, 0x301b),
908 regmap_reg_range(0x301f, 0x3020),
909 regmap_reg_range(0x3030, 0x3030),
910 regmap_reg_range(0x3100, 0x3115),
911 regmap_reg_range(0x311a, 0x311f),
912 regmap_reg_range(0x3120, 0x312b),
913 regmap_reg_range(0x3134, 0x313b),
914 regmap_reg_range(0x313c, 0x313f),
915 regmap_reg_range(0x3400, 0x3401),
916 regmap_reg_range(0x3403, 0x3403),
917 regmap_reg_range(0x3410, 0x3417),
918 regmap_reg_range(0x3420, 0x3423),
919 regmap_reg_range(0x3500, 0x3507),
920 regmap_reg_range(0x3600, 0x3613),
921 regmap_reg_range(0x3800, 0x380f),
922 regmap_reg_range(0x3820, 0x3827),
923 regmap_reg_range(0x3830, 0x3837),
924 regmap_reg_range(0x3840, 0x384b),
925 regmap_reg_range(0x3900, 0x3907),
926 regmap_reg_range(0x3914, 0x391b),
927 regmap_reg_range(0x3920, 0x3920),
928 regmap_reg_range(0x3923, 0x3927),
929 regmap_reg_range(0x3a00, 0x3a03),
930 regmap_reg_range(0x3a04, 0x3a07),
931 regmap_reg_range(0x3b00, 0x3b01),
932 regmap_reg_range(0x3b04, 0x3b04),
933 regmap_reg_range(0x3c00, 0x3c05),
934 regmap_reg_range(0x3c08, 0x3c1b),
935
936 /* port 4 */
937 regmap_reg_range(0x4000, 0x4001),
938 regmap_reg_range(0x4013, 0x4013),
939 regmap_reg_range(0x4017, 0x4017),
940 regmap_reg_range(0x401b, 0x401b),
941 regmap_reg_range(0x401f, 0x4020),
942 regmap_reg_range(0x4030, 0x4030),
943 regmap_reg_range(0x4100, 0x4115),
944 regmap_reg_range(0x411a, 0x411f),
945 regmap_reg_range(0x4120, 0x412b),
946 regmap_reg_range(0x4134, 0x413b),
947 regmap_reg_range(0x413c, 0x413f),
948 regmap_reg_range(0x4400, 0x4401),
949 regmap_reg_range(0x4403, 0x4403),
950 regmap_reg_range(0x4410, 0x4417),
951 regmap_reg_range(0x4420, 0x4423),
952 regmap_reg_range(0x4500, 0x4507),
953 regmap_reg_range(0x4600, 0x4613),
954 regmap_reg_range(0x4800, 0x480f),
955 regmap_reg_range(0x4820, 0x4827),
956 regmap_reg_range(0x4830, 0x4837),
957 regmap_reg_range(0x4840, 0x484b),
958 regmap_reg_range(0x4900, 0x4907),
959 regmap_reg_range(0x4914, 0x491b),
960 regmap_reg_range(0x4920, 0x4920),
961 regmap_reg_range(0x4923, 0x4927),
962 regmap_reg_range(0x4a00, 0x4a03),
963 regmap_reg_range(0x4a04, 0x4a07),
964 regmap_reg_range(0x4b00, 0x4b01),
965 regmap_reg_range(0x4b04, 0x4b04),
966 regmap_reg_range(0x4c00, 0x4c05),
967 regmap_reg_range(0x4c08, 0x4c1b),
968
969 /* port 5 */
970 regmap_reg_range(0x5000, 0x5001),
971 regmap_reg_range(0x5013, 0x5013),
972 regmap_reg_range(0x5017, 0x5017),
973 regmap_reg_range(0x501b, 0x501b),
974 regmap_reg_range(0x501f, 0x5020),
975 regmap_reg_range(0x5030, 0x5030),
976 regmap_reg_range(0x5100, 0x5115),
977 regmap_reg_range(0x511a, 0x511f),
978 regmap_reg_range(0x5120, 0x512b),
979 regmap_reg_range(0x5134, 0x513b),
980 regmap_reg_range(0x513c, 0x513f),
981 regmap_reg_range(0x5400, 0x5401),
982 regmap_reg_range(0x5403, 0x5403),
983 regmap_reg_range(0x5410, 0x5417),
984 regmap_reg_range(0x5420, 0x5423),
985 regmap_reg_range(0x5500, 0x5507),
986 regmap_reg_range(0x5600, 0x5613),
987 regmap_reg_range(0x5800, 0x580f),
988 regmap_reg_range(0x5820, 0x5827),
989 regmap_reg_range(0x5830, 0x5837),
990 regmap_reg_range(0x5840, 0x584b),
991 regmap_reg_range(0x5900, 0x5907),
992 regmap_reg_range(0x5914, 0x591b),
993 regmap_reg_range(0x5920, 0x5920),
994 regmap_reg_range(0x5923, 0x5927),
995 regmap_reg_range(0x5a00, 0x5a03),
996 regmap_reg_range(0x5a04, 0x5a07),
997 regmap_reg_range(0x5b00, 0x5b01),
998 regmap_reg_range(0x5b04, 0x5b04),
999 regmap_reg_range(0x5c00, 0x5c05),
1000 regmap_reg_range(0x5c08, 0x5c1b),
1001
1002 /* port 6 */
1003 regmap_reg_range(0x6000, 0x6001),
1004 regmap_reg_range(0x6013, 0x6013),
1005 regmap_reg_range(0x6017, 0x6017),
1006 regmap_reg_range(0x601b, 0x601b),
1007 regmap_reg_range(0x601f, 0x6020),
1008 regmap_reg_range(0x6030, 0x6030),
1009 regmap_reg_range(0x6300, 0x6301),
1010 regmap_reg_range(0x6400, 0x6401),
1011 regmap_reg_range(0x6403, 0x6403),
1012 regmap_reg_range(0x6410, 0x6417),
1013 regmap_reg_range(0x6420, 0x6423),
1014 regmap_reg_range(0x6500, 0x6507),
1015 regmap_reg_range(0x6600, 0x6613),
1016 regmap_reg_range(0x6800, 0x680f),
1017 regmap_reg_range(0x6820, 0x6827),
1018 regmap_reg_range(0x6830, 0x6837),
1019 regmap_reg_range(0x6840, 0x684b),
1020 regmap_reg_range(0x6900, 0x6907),
1021 regmap_reg_range(0x6914, 0x691b),
1022 regmap_reg_range(0x6920, 0x6920),
1023 regmap_reg_range(0x6923, 0x6927),
1024 regmap_reg_range(0x6a00, 0x6a03),
1025 regmap_reg_range(0x6a04, 0x6a07),
1026 regmap_reg_range(0x6b00, 0x6b01),
1027 regmap_reg_range(0x6b04, 0x6b04),
1028 regmap_reg_range(0x6c00, 0x6c05),
1029 regmap_reg_range(0x6c08, 0x6c1b),
1030
1031 /* port 7 */
1032 regmap_reg_range(0x7000, 0x7001),
1033 regmap_reg_range(0x7013, 0x7013),
1034 regmap_reg_range(0x7017, 0x7017),
1035 regmap_reg_range(0x701b, 0x701b),
1036 regmap_reg_range(0x701f, 0x7020),
1037 regmap_reg_range(0x7030, 0x7030),
1038 regmap_reg_range(0x7200, 0x7203),
1039 regmap_reg_range(0x7206, 0x7207),
1040 regmap_reg_range(0x7300, 0x7301),
1041 regmap_reg_range(0x7400, 0x7401),
1042 regmap_reg_range(0x7403, 0x7403),
1043 regmap_reg_range(0x7410, 0x7417),
1044 regmap_reg_range(0x7420, 0x7423),
1045 regmap_reg_range(0x7500, 0x7507),
1046 regmap_reg_range(0x7600, 0x7613),
1047 regmap_reg_range(0x7800, 0x780f),
1048 regmap_reg_range(0x7820, 0x7827),
1049 regmap_reg_range(0x7830, 0x7837),
1050 regmap_reg_range(0x7840, 0x784b),
1051 regmap_reg_range(0x7900, 0x7907),
1052 regmap_reg_range(0x7914, 0x791b),
1053 regmap_reg_range(0x7920, 0x7920),
1054 regmap_reg_range(0x7923, 0x7927),
1055 regmap_reg_range(0x7a00, 0x7a03),
1056 regmap_reg_range(0x7a04, 0x7a07),
1057 regmap_reg_range(0x7b00, 0x7b01),
1058 regmap_reg_range(0x7b04, 0x7b04),
1059 regmap_reg_range(0x7c00, 0x7c05),
1060 regmap_reg_range(0x7c08, 0x7c1b),
1061};
1062
1063static const struct regmap_access_table ksz9477_register_set = {
1064 .yes_ranges = ksz9477_valid_regs,
1065 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
1066};
1067
1068static const struct regmap_range ksz9896_valid_regs[] = {
1069 regmap_reg_range(0x0000, 0x0003),
1070 regmap_reg_range(0x0006, 0x0006),
1071 regmap_reg_range(0x0010, 0x001f),
1072 regmap_reg_range(0x0100, 0x0100),
1073 regmap_reg_range(0x0103, 0x0107),
1074 regmap_reg_range(0x010d, 0x010d),
1075 regmap_reg_range(0x0110, 0x0113),
1076 regmap_reg_range(0x0120, 0x0127),
1077 regmap_reg_range(0x0201, 0x0201),
1078 regmap_reg_range(0x0210, 0x0213),
1079 regmap_reg_range(0x0300, 0x0300),
1080 regmap_reg_range(0x0302, 0x030b),
1081 regmap_reg_range(0x0310, 0x031b),
1082 regmap_reg_range(0x0320, 0x032b),
1083 regmap_reg_range(0x0330, 0x0336),
1084 regmap_reg_range(0x0338, 0x033b),
1085 regmap_reg_range(0x033e, 0x033e),
1086 regmap_reg_range(0x0340, 0x035f),
1087 regmap_reg_range(0x0370, 0x0370),
1088 regmap_reg_range(0x0378, 0x0378),
1089 regmap_reg_range(0x037c, 0x037d),
1090 regmap_reg_range(0x0390, 0x0393),
1091 regmap_reg_range(0x0400, 0x040e),
1092 regmap_reg_range(0x0410, 0x042f),
1093
1094 /* port 1 */
1095 regmap_reg_range(0x1000, 0x1001),
1096 regmap_reg_range(0x1013, 0x1013),
1097 regmap_reg_range(0x1017, 0x1017),
1098 regmap_reg_range(0x101b, 0x101b),
1099 regmap_reg_range(0x101f, 0x1020),
1100 regmap_reg_range(0x1030, 0x1030),
1101 regmap_reg_range(0x1100, 0x1115),
1102 regmap_reg_range(0x111a, 0x111f),
1103 regmap_reg_range(0x1120, 0x112b),
1104 regmap_reg_range(0x1134, 0x113b),
1105 regmap_reg_range(0x113c, 0x113f),
1106 regmap_reg_range(0x1400, 0x1401),
1107 regmap_reg_range(0x1403, 0x1403),
1108 regmap_reg_range(0x1410, 0x1417),
1109 regmap_reg_range(0x1420, 0x1423),
1110 regmap_reg_range(0x1500, 0x1507),
1111 regmap_reg_range(0x1600, 0x1612),
1112 regmap_reg_range(0x1800, 0x180f),
1113 regmap_reg_range(0x1820, 0x1827),
1114 regmap_reg_range(0x1830, 0x1837),
1115 regmap_reg_range(0x1840, 0x184b),
1116 regmap_reg_range(0x1900, 0x1907),
1117 regmap_reg_range(0x1914, 0x1915),
1118 regmap_reg_range(0x1a00, 0x1a03),
1119 regmap_reg_range(0x1a04, 0x1a07),
1120 regmap_reg_range(0x1b00, 0x1b01),
1121 regmap_reg_range(0x1b04, 0x1b04),
1122
1123 /* port 2 */
1124 regmap_reg_range(0x2000, 0x2001),
1125 regmap_reg_range(0x2013, 0x2013),
1126 regmap_reg_range(0x2017, 0x2017),
1127 regmap_reg_range(0x201b, 0x201b),
1128 regmap_reg_range(0x201f, 0x2020),
1129 regmap_reg_range(0x2030, 0x2030),
1130 regmap_reg_range(0x2100, 0x2115),
1131 regmap_reg_range(0x211a, 0x211f),
1132 regmap_reg_range(0x2120, 0x212b),
1133 regmap_reg_range(0x2134, 0x213b),
1134 regmap_reg_range(0x213c, 0x213f),
1135 regmap_reg_range(0x2400, 0x2401),
1136 regmap_reg_range(0x2403, 0x2403),
1137 regmap_reg_range(0x2410, 0x2417),
1138 regmap_reg_range(0x2420, 0x2423),
1139 regmap_reg_range(0x2500, 0x2507),
1140 regmap_reg_range(0x2600, 0x2612),
1141 regmap_reg_range(0x2800, 0x280f),
1142 regmap_reg_range(0x2820, 0x2827),
1143 regmap_reg_range(0x2830, 0x2837),
1144 regmap_reg_range(0x2840, 0x284b),
1145 regmap_reg_range(0x2900, 0x2907),
1146 regmap_reg_range(0x2914, 0x2915),
1147 regmap_reg_range(0x2a00, 0x2a03),
1148 regmap_reg_range(0x2a04, 0x2a07),
1149 regmap_reg_range(0x2b00, 0x2b01),
1150 regmap_reg_range(0x2b04, 0x2b04),
1151
1152 /* port 3 */
1153 regmap_reg_range(0x3000, 0x3001),
1154 regmap_reg_range(0x3013, 0x3013),
1155 regmap_reg_range(0x3017, 0x3017),
1156 regmap_reg_range(0x301b, 0x301b),
1157 regmap_reg_range(0x301f, 0x3020),
1158 regmap_reg_range(0x3030, 0x3030),
1159 regmap_reg_range(0x3100, 0x3115),
1160 regmap_reg_range(0x311a, 0x311f),
1161 regmap_reg_range(0x3120, 0x312b),
1162 regmap_reg_range(0x3134, 0x313b),
1163 regmap_reg_range(0x313c, 0x313f),
1164 regmap_reg_range(0x3400, 0x3401),
1165 regmap_reg_range(0x3403, 0x3403),
1166 regmap_reg_range(0x3410, 0x3417),
1167 regmap_reg_range(0x3420, 0x3423),
1168 regmap_reg_range(0x3500, 0x3507),
1169 regmap_reg_range(0x3600, 0x3612),
1170 regmap_reg_range(0x3800, 0x380f),
1171 regmap_reg_range(0x3820, 0x3827),
1172 regmap_reg_range(0x3830, 0x3837),
1173 regmap_reg_range(0x3840, 0x384b),
1174 regmap_reg_range(0x3900, 0x3907),
1175 regmap_reg_range(0x3914, 0x3915),
1176 regmap_reg_range(0x3a00, 0x3a03),
1177 regmap_reg_range(0x3a04, 0x3a07),
1178 regmap_reg_range(0x3b00, 0x3b01),
1179 regmap_reg_range(0x3b04, 0x3b04),
1180
1181 /* port 4 */
1182 regmap_reg_range(0x4000, 0x4001),
1183 regmap_reg_range(0x4013, 0x4013),
1184 regmap_reg_range(0x4017, 0x4017),
1185 regmap_reg_range(0x401b, 0x401b),
1186 regmap_reg_range(0x401f, 0x4020),
1187 regmap_reg_range(0x4030, 0x4030),
1188 regmap_reg_range(0x4100, 0x4115),
1189 regmap_reg_range(0x411a, 0x411f),
1190 regmap_reg_range(0x4120, 0x412b),
1191 regmap_reg_range(0x4134, 0x413b),
1192 regmap_reg_range(0x413c, 0x413f),
1193 regmap_reg_range(0x4400, 0x4401),
1194 regmap_reg_range(0x4403, 0x4403),
1195 regmap_reg_range(0x4410, 0x4417),
1196 regmap_reg_range(0x4420, 0x4423),
1197 regmap_reg_range(0x4500, 0x4507),
1198 regmap_reg_range(0x4600, 0x4612),
1199 regmap_reg_range(0x4800, 0x480f),
1200 regmap_reg_range(0x4820, 0x4827),
1201 regmap_reg_range(0x4830, 0x4837),
1202 regmap_reg_range(0x4840, 0x484b),
1203 regmap_reg_range(0x4900, 0x4907),
1204 regmap_reg_range(0x4914, 0x4915),
1205 regmap_reg_range(0x4a00, 0x4a03),
1206 regmap_reg_range(0x4a04, 0x4a07),
1207 regmap_reg_range(0x4b00, 0x4b01),
1208 regmap_reg_range(0x4b04, 0x4b04),
1209
1210 /* port 5 */
1211 regmap_reg_range(0x5000, 0x5001),
1212 regmap_reg_range(0x5013, 0x5013),
1213 regmap_reg_range(0x5017, 0x5017),
1214 regmap_reg_range(0x501b, 0x501b),
1215 regmap_reg_range(0x501f, 0x5020),
1216 regmap_reg_range(0x5030, 0x5030),
1217 regmap_reg_range(0x5100, 0x5115),
1218 regmap_reg_range(0x511a, 0x511f),
1219 regmap_reg_range(0x5120, 0x512b),
1220 regmap_reg_range(0x5134, 0x513b),
1221 regmap_reg_range(0x513c, 0x513f),
1222 regmap_reg_range(0x5400, 0x5401),
1223 regmap_reg_range(0x5403, 0x5403),
1224 regmap_reg_range(0x5410, 0x5417),
1225 regmap_reg_range(0x5420, 0x5423),
1226 regmap_reg_range(0x5500, 0x5507),
1227 regmap_reg_range(0x5600, 0x5612),
1228 regmap_reg_range(0x5800, 0x580f),
1229 regmap_reg_range(0x5820, 0x5827),
1230 regmap_reg_range(0x5830, 0x5837),
1231 regmap_reg_range(0x5840, 0x584b),
1232 regmap_reg_range(0x5900, 0x5907),
1233 regmap_reg_range(0x5914, 0x5915),
1234 regmap_reg_range(0x5a00, 0x5a03),
1235 regmap_reg_range(0x5a04, 0x5a07),
1236 regmap_reg_range(0x5b00, 0x5b01),
1237 regmap_reg_range(0x5b04, 0x5b04),
1238
1239 /* port 6 */
1240 regmap_reg_range(0x6000, 0x6001),
1241 regmap_reg_range(0x6013, 0x6013),
1242 regmap_reg_range(0x6017, 0x6017),
1243 regmap_reg_range(0x601b, 0x601b),
1244 regmap_reg_range(0x601f, 0x6020),
1245 regmap_reg_range(0x6030, 0x6030),
1246 regmap_reg_range(0x6100, 0x6115),
1247 regmap_reg_range(0x611a, 0x611f),
1248 regmap_reg_range(0x6120, 0x612b),
1249 regmap_reg_range(0x6134, 0x613b),
1250 regmap_reg_range(0x613c, 0x613f),
1251 regmap_reg_range(0x6300, 0x6301),
1252 regmap_reg_range(0x6400, 0x6401),
1253 regmap_reg_range(0x6403, 0x6403),
1254 regmap_reg_range(0x6410, 0x6417),
1255 regmap_reg_range(0x6420, 0x6423),
1256 regmap_reg_range(0x6500, 0x6507),
1257 regmap_reg_range(0x6600, 0x6612),
1258 regmap_reg_range(0x6800, 0x680f),
1259 regmap_reg_range(0x6820, 0x6827),
1260 regmap_reg_range(0x6830, 0x6837),
1261 regmap_reg_range(0x6840, 0x684b),
1262 regmap_reg_range(0x6900, 0x6907),
1263 regmap_reg_range(0x6914, 0x6915),
1264 regmap_reg_range(0x6a00, 0x6a03),
1265 regmap_reg_range(0x6a04, 0x6a07),
1266 regmap_reg_range(0x6b00, 0x6b01),
1267 regmap_reg_range(0x6b04, 0x6b04),
1268};
1269
1270static const struct regmap_access_table ksz9896_register_set = {
1271 .yes_ranges = ksz9896_valid_regs,
1272 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1273};
1274
1275static const struct regmap_range ksz8873_valid_regs[] = {
1276 regmap_reg_range(0x00, 0x01),
1277 /* global control register */
1278 regmap_reg_range(0x02, 0x0f),
1279
1280 /* port registers */
1281 regmap_reg_range(0x10, 0x1d),
1282 regmap_reg_range(0x1e, 0x1f),
1283 regmap_reg_range(0x20, 0x2d),
1284 regmap_reg_range(0x2e, 0x2f),
1285 regmap_reg_range(0x30, 0x39),
1286 regmap_reg_range(0x3f, 0x3f),
1287
1288 /* advanced control registers */
1289 regmap_reg_range(0x60, 0x6f),
1290 regmap_reg_range(0x70, 0x75),
1291 regmap_reg_range(0x76, 0x78),
1292 regmap_reg_range(0x79, 0x7a),
1293 regmap_reg_range(0x7b, 0x83),
1294 regmap_reg_range(0x8e, 0x99),
1295 regmap_reg_range(0x9a, 0xa5),
1296 regmap_reg_range(0xa6, 0xa6),
1297 regmap_reg_range(0xa7, 0xaa),
1298 regmap_reg_range(0xab, 0xae),
1299 regmap_reg_range(0xaf, 0xba),
1300 regmap_reg_range(0xbb, 0xbc),
1301 regmap_reg_range(0xbd, 0xbd),
1302 regmap_reg_range(0xc0, 0xc0),
1303 regmap_reg_range(0xc2, 0xc2),
1304 regmap_reg_range(0xc3, 0xc3),
1305 regmap_reg_range(0xc4, 0xc4),
1306 regmap_reg_range(0xc6, 0xc6),
1307};
1308
1309static const struct regmap_access_table ksz8873_register_set = {
1310 .yes_ranges = ksz8873_valid_regs,
1311 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1312};
1313
1314const struct ksz_chip_data ksz_switch_chips[] = {
1315 [KSZ8563] = {
1316 .chip_id = KSZ8563_CHIP_ID,
1317 .dev_name = "KSZ8563",
1318 .num_vlans = 4096,
1319 .num_alus = 4096,
1320 .num_statics = 16,
1321 .cpu_ports = 0x07, /* can be configured as cpu port */
1322 .port_cnt = 3, /* total port count */
1323 .port_nirqs = 3,
1324 .num_tx_queues = 4,
1325 .num_ipms = 8,
1326 .tc_cbs_supported = true,
1327 .ops = &ksz9477_dev_ops,
1328 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1329 .mib_names = ksz9477_mib_names,
1330 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1331 .reg_mib_cnt = MIB_COUNTER_NUM,
1332 .regs = ksz9477_regs,
1333 .masks = ksz9477_masks,
1334 .shifts = ksz9477_shifts,
1335 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1336 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1337 .supports_mii = {false, false, true},
1338 .supports_rmii = {false, false, true},
1339 .supports_rgmii = {false, false, true},
1340 .internal_phy = {true, true, false},
1341 .gbit_capable = {false, false, true},
1342 .wr_table = &ksz8563_register_set,
1343 .rd_table = &ksz8563_register_set,
1344 },
1345
1346 [KSZ8795] = {
1347 .chip_id = KSZ8795_CHIP_ID,
1348 .dev_name = "KSZ8795",
1349 .num_vlans = 4096,
1350 .num_alus = 0,
1351 .num_statics = 32,
1352 .cpu_ports = 0x10, /* can be configured as cpu port */
1353 .port_cnt = 5, /* total cpu and user ports */
1354 .num_tx_queues = 4,
1355 .num_ipms = 4,
1356 .ops = &ksz87xx_dev_ops,
1357 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1358 .ksz87xx_eee_link_erratum = true,
1359 .mib_names = ksz9477_mib_names,
1360 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1361 .reg_mib_cnt = MIB_COUNTER_NUM,
1362 .regs = ksz8795_regs,
1363 .masks = ksz8795_masks,
1364 .shifts = ksz8795_shifts,
1365 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1366 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1367 .supports_mii = {false, false, false, false, true},
1368 .supports_rmii = {false, false, false, false, true},
1369 .supports_rgmii = {false, false, false, false, true},
1370 .internal_phy = {true, true, true, true, false},
1371 },
1372
1373 [KSZ8794] = {
1374 /* WARNING
1375 * =======
1376 * KSZ8794 is similar to KSZ8795, except the port map
1377 * contains a gap between external and CPU ports, the
1378 * port map is NOT continuous. The per-port register
1379 * map is shifted accordingly too, i.e. registers at
1380 * offset 0x40 are NOT used on KSZ8794 and they ARE
1381 * used on KSZ8795 for external port 3.
1382 * external cpu
1383 * KSZ8794 0,1,2 4
1384 * KSZ8795 0,1,2,3 4
1385 * KSZ8765 0,1,2,3 4
1386 * port_cnt is configured as 5, even though it is 4
1387 */
1388 .chip_id = KSZ8794_CHIP_ID,
1389 .dev_name = "KSZ8794",
1390 .num_vlans = 4096,
1391 .num_alus = 0,
1392 .num_statics = 32,
1393 .cpu_ports = 0x10, /* can be configured as cpu port */
1394 .port_cnt = 5, /* total cpu and user ports */
1395 .num_tx_queues = 4,
1396 .num_ipms = 4,
1397 .ops = &ksz87xx_dev_ops,
1398 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1399 .ksz87xx_eee_link_erratum = true,
1400 .mib_names = ksz9477_mib_names,
1401 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1402 .reg_mib_cnt = MIB_COUNTER_NUM,
1403 .regs = ksz8795_regs,
1404 .masks = ksz8795_masks,
1405 .shifts = ksz8795_shifts,
1406 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1407 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1408 .supports_mii = {false, false, false, false, true},
1409 .supports_rmii = {false, false, false, false, true},
1410 .supports_rgmii = {false, false, false, false, true},
1411 .internal_phy = {true, true, true, false, false},
1412 },
1413
1414 [KSZ8765] = {
1415 .chip_id = KSZ8765_CHIP_ID,
1416 .dev_name = "KSZ8765",
1417 .num_vlans = 4096,
1418 .num_alus = 0,
1419 .num_statics = 32,
1420 .cpu_ports = 0x10, /* can be configured as cpu port */
1421 .port_cnt = 5, /* total cpu and user ports */
1422 .num_tx_queues = 4,
1423 .num_ipms = 4,
1424 .ops = &ksz87xx_dev_ops,
1425 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1426 .ksz87xx_eee_link_erratum = true,
1427 .mib_names = ksz9477_mib_names,
1428 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1429 .reg_mib_cnt = MIB_COUNTER_NUM,
1430 .regs = ksz8795_regs,
1431 .masks = ksz8795_masks,
1432 .shifts = ksz8795_shifts,
1433 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1434 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1435 .supports_mii = {false, false, false, false, true},
1436 .supports_rmii = {false, false, false, false, true},
1437 .supports_rgmii = {false, false, false, false, true},
1438 .internal_phy = {true, true, true, true, false},
1439 },
1440
1441 [KSZ88X3] = {
1442 .chip_id = KSZ88X3_CHIP_ID,
1443 .dev_name = "KSZ8863/KSZ8873",
1444 .num_vlans = 16,
1445 .num_alus = 0,
1446 .num_statics = 8,
1447 .cpu_ports = 0x4, /* can be configured as cpu port */
1448 .port_cnt = 3,
1449 .num_tx_queues = 4,
1450 .num_ipms = 4,
1451 .ops = &ksz88xx_dev_ops,
1452 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1453 .mib_names = ksz88xx_mib_names,
1454 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1455 .reg_mib_cnt = MIB_COUNTER_NUM,
1456 .regs = ksz8863_regs,
1457 .masks = ksz8863_masks,
1458 .shifts = ksz8863_shifts,
1459 .supports_mii = {false, false, true},
1460 .supports_rmii = {false, false, true},
1461 .internal_phy = {true, true, false},
1462 .wr_table = &ksz8873_register_set,
1463 .rd_table = &ksz8873_register_set,
1464 },
1465
1466 [KSZ8864] = {
1467 /* WARNING
1468 * =======
1469 * KSZ8864 is similar to KSZ8895, except the first port
1470 * does not exist.
1471 * external cpu
1472 * KSZ8864 1,2,3 4
1473 * KSZ8895 0,1,2,3 4
1474 * port_cnt is configured as 5, even though it is 4
1475 */
1476 .chip_id = KSZ8864_CHIP_ID,
1477 .dev_name = "KSZ8864",
1478 .num_vlans = 4096,
1479 .num_alus = 0,
1480 .num_statics = 32,
1481 .cpu_ports = 0x10, /* can be configured as cpu port */
1482 .port_cnt = 5, /* total cpu and user ports */
1483 .num_tx_queues = 4,
1484 .num_ipms = 4,
1485 .ops = &ksz88xx_dev_ops,
1486 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1487 .mib_names = ksz88xx_mib_names,
1488 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1489 .reg_mib_cnt = MIB_COUNTER_NUM,
1490 .regs = ksz8895_regs,
1491 .masks = ksz8895_masks,
1492 .shifts = ksz8895_shifts,
1493 .supports_mii = {false, false, false, false, true},
1494 .supports_rmii = {false, false, false, false, true},
1495 .internal_phy = {false, true, true, true, false},
1496 },
1497
1498 [KSZ8895] = {
1499 .chip_id = KSZ8895_CHIP_ID,
1500 .dev_name = "KSZ8895",
1501 .num_vlans = 4096,
1502 .num_alus = 0,
1503 .num_statics = 32,
1504 .cpu_ports = 0x10, /* can be configured as cpu port */
1505 .port_cnt = 5, /* total cpu and user ports */
1506 .num_tx_queues = 4,
1507 .num_ipms = 4,
1508 .ops = &ksz88xx_dev_ops,
1509 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1510 .mib_names = ksz88xx_mib_names,
1511 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1512 .reg_mib_cnt = MIB_COUNTER_NUM,
1513 .regs = ksz8895_regs,
1514 .masks = ksz8895_masks,
1515 .shifts = ksz8895_shifts,
1516 .supports_mii = {false, false, false, false, true},
1517 .supports_rmii = {false, false, false, false, true},
1518 .internal_phy = {true, true, true, true, false},
1519 },
1520
1521 [KSZ9477] = {
1522 .chip_id = KSZ9477_CHIP_ID,
1523 .dev_name = "KSZ9477",
1524 .num_vlans = 4096,
1525 .num_alus = 4096,
1526 .num_statics = 16,
1527 .cpu_ports = 0x7F, /* can be configured as cpu port */
1528 .port_cnt = 7, /* total physical port count */
1529 .port_nirqs = 4,
1530 .num_tx_queues = 4,
1531 .num_ipms = 8,
1532 .tc_cbs_supported = true,
1533 .ops = &ksz9477_dev_ops,
1534 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1535 .phy_errata_9477 = true,
1536 .mib_names = ksz9477_mib_names,
1537 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1538 .reg_mib_cnt = MIB_COUNTER_NUM,
1539 .regs = ksz9477_regs,
1540 .masks = ksz9477_masks,
1541 .shifts = ksz9477_shifts,
1542 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1543 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1544 .supports_mii = {false, false, false, false,
1545 false, true, false},
1546 .supports_rmii = {false, false, false, false,
1547 false, true, false},
1548 .supports_rgmii = {false, false, false, false,
1549 false, true, false},
1550 .internal_phy = {true, true, true, true,
1551 true, false, false},
1552 .gbit_capable = {true, true, true, true, true, true, true},
1553 .wr_table = &ksz9477_register_set,
1554 .rd_table = &ksz9477_register_set,
1555 },
1556
1557 [KSZ9896] = {
1558 .chip_id = KSZ9896_CHIP_ID,
1559 .dev_name = "KSZ9896",
1560 .num_vlans = 4096,
1561 .num_alus = 4096,
1562 .num_statics = 16,
1563 .cpu_ports = 0x3F, /* can be configured as cpu port */
1564 .port_cnt = 6, /* total physical port count */
1565 .port_nirqs = 2,
1566 .num_tx_queues = 4,
1567 .num_ipms = 8,
1568 .ops = &ksz9477_dev_ops,
1569 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1570 .phy_errata_9477 = true,
1571 .mib_names = ksz9477_mib_names,
1572 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1573 .reg_mib_cnt = MIB_COUNTER_NUM,
1574 .regs = ksz9477_regs,
1575 .masks = ksz9477_masks,
1576 .shifts = ksz9477_shifts,
1577 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1578 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1579 .supports_mii = {false, false, false, false,
1580 false, true},
1581 .supports_rmii = {false, false, false, false,
1582 false, true},
1583 .supports_rgmii = {false, false, false, false,
1584 false, true},
1585 .internal_phy = {true, true, true, true,
1586 true, false},
1587 .gbit_capable = {true, true, true, true, true, true},
1588 .wr_table = &ksz9896_register_set,
1589 .rd_table = &ksz9896_register_set,
1590 },
1591
1592 [KSZ9897] = {
1593 .chip_id = KSZ9897_CHIP_ID,
1594 .dev_name = "KSZ9897",
1595 .num_vlans = 4096,
1596 .num_alus = 4096,
1597 .num_statics = 16,
1598 .cpu_ports = 0x7F, /* can be configured as cpu port */
1599 .port_cnt = 7, /* total physical port count */
1600 .port_nirqs = 2,
1601 .num_tx_queues = 4,
1602 .num_ipms = 8,
1603 .ops = &ksz9477_dev_ops,
1604 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1605 .phy_errata_9477 = true,
1606 .mib_names = ksz9477_mib_names,
1607 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1608 .reg_mib_cnt = MIB_COUNTER_NUM,
1609 .regs = ksz9477_regs,
1610 .masks = ksz9477_masks,
1611 .shifts = ksz9477_shifts,
1612 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1613 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1614 .supports_mii = {false, false, false, false,
1615 false, true, true},
1616 .supports_rmii = {false, false, false, false,
1617 false, true, true},
1618 .supports_rgmii = {false, false, false, false,
1619 false, true, true},
1620 .internal_phy = {true, true, true, true,
1621 true, false, false},
1622 .gbit_capable = {true, true, true, true, true, true, true},
1623 },
1624
1625 [KSZ9893] = {
1626 .chip_id = KSZ9893_CHIP_ID,
1627 .dev_name = "KSZ9893",
1628 .num_vlans = 4096,
1629 .num_alus = 4096,
1630 .num_statics = 16,
1631 .cpu_ports = 0x07, /* can be configured as cpu port */
1632 .port_cnt = 3, /* total port count */
1633 .port_nirqs = 2,
1634 .num_tx_queues = 4,
1635 .num_ipms = 8,
1636 .ops = &ksz9477_dev_ops,
1637 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1638 .mib_names = ksz9477_mib_names,
1639 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1640 .reg_mib_cnt = MIB_COUNTER_NUM,
1641 .regs = ksz9477_regs,
1642 .masks = ksz9477_masks,
1643 .shifts = ksz9477_shifts,
1644 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1645 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1646 .supports_mii = {false, false, true},
1647 .supports_rmii = {false, false, true},
1648 .supports_rgmii = {false, false, true},
1649 .internal_phy = {true, true, false},
1650 .gbit_capable = {true, true, true},
1651 },
1652
1653 [KSZ9563] = {
1654 .chip_id = KSZ9563_CHIP_ID,
1655 .dev_name = "KSZ9563",
1656 .num_vlans = 4096,
1657 .num_alus = 4096,
1658 .num_statics = 16,
1659 .cpu_ports = 0x07, /* can be configured as cpu port */
1660 .port_cnt = 3, /* total port count */
1661 .port_nirqs = 3,
1662 .num_tx_queues = 4,
1663 .num_ipms = 8,
1664 .tc_cbs_supported = true,
1665 .ops = &ksz9477_dev_ops,
1666 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1667 .mib_names = ksz9477_mib_names,
1668 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1669 .reg_mib_cnt = MIB_COUNTER_NUM,
1670 .regs = ksz9477_regs,
1671 .masks = ksz9477_masks,
1672 .shifts = ksz9477_shifts,
1673 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1674 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1675 .supports_mii = {false, false, true},
1676 .supports_rmii = {false, false, true},
1677 .supports_rgmii = {false, false, true},
1678 .internal_phy = {true, true, false},
1679 .gbit_capable = {true, true, true},
1680 },
1681
1682 [KSZ8567] = {
1683 .chip_id = KSZ8567_CHIP_ID,
1684 .dev_name = "KSZ8567",
1685 .num_vlans = 4096,
1686 .num_alus = 4096,
1687 .num_statics = 16,
1688 .cpu_ports = 0x7F, /* can be configured as cpu port */
1689 .port_cnt = 7, /* total port count */
1690 .port_nirqs = 3,
1691 .num_tx_queues = 4,
1692 .num_ipms = 8,
1693 .tc_cbs_supported = true,
1694 .ops = &ksz9477_dev_ops,
1695 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1696 .phy_errata_9477 = true,
1697 .mib_names = ksz9477_mib_names,
1698 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1699 .reg_mib_cnt = MIB_COUNTER_NUM,
1700 .regs = ksz9477_regs,
1701 .masks = ksz9477_masks,
1702 .shifts = ksz9477_shifts,
1703 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1704 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1705 .supports_mii = {false, false, false, false,
1706 false, true, true},
1707 .supports_rmii = {false, false, false, false,
1708 false, true, true},
1709 .supports_rgmii = {false, false, false, false,
1710 false, true, true},
1711 .internal_phy = {true, true, true, true,
1712 true, false, false},
1713 .gbit_capable = {false, false, false, false, false,
1714 true, true},
1715 },
1716
1717 [KSZ9567] = {
1718 .chip_id = KSZ9567_CHIP_ID,
1719 .dev_name = "KSZ9567",
1720 .num_vlans = 4096,
1721 .num_alus = 4096,
1722 .num_statics = 16,
1723 .cpu_ports = 0x7F, /* can be configured as cpu port */
1724 .port_cnt = 7, /* total physical port count */
1725 .port_nirqs = 3,
1726 .num_tx_queues = 4,
1727 .num_ipms = 8,
1728 .tc_cbs_supported = true,
1729 .ops = &ksz9477_dev_ops,
1730 .mib_names = ksz9477_mib_names,
1731 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1732 .reg_mib_cnt = MIB_COUNTER_NUM,
1733 .regs = ksz9477_regs,
1734 .masks = ksz9477_masks,
1735 .shifts = ksz9477_shifts,
1736 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1737 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1738 .supports_mii = {false, false, false, false,
1739 false, true, true},
1740 .supports_rmii = {false, false, false, false,
1741 false, true, true},
1742 .supports_rgmii = {false, false, false, false,
1743 false, true, true},
1744 .internal_phy = {true, true, true, true,
1745 true, false, false},
1746 .gbit_capable = {true, true, true, true, true, true, true},
1747 },
1748
1749 [LAN9370] = {
1750 .chip_id = LAN9370_CHIP_ID,
1751 .dev_name = "LAN9370",
1752 .num_vlans = 4096,
1753 .num_alus = 1024,
1754 .num_statics = 256,
1755 .cpu_ports = 0x10, /* can be configured as cpu port */
1756 .port_cnt = 5, /* total physical port count */
1757 .port_nirqs = 6,
1758 .num_tx_queues = 8,
1759 .num_ipms = 8,
1760 .tc_cbs_supported = true,
1761 .phy_side_mdio_supported = true,
1762 .ops = &lan937x_dev_ops,
1763 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1764 .mib_names = ksz9477_mib_names,
1765 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1766 .reg_mib_cnt = MIB_COUNTER_NUM,
1767 .regs = ksz9477_regs,
1768 .masks = lan937x_masks,
1769 .shifts = lan937x_shifts,
1770 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1771 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1772 .supports_mii = {false, false, false, false, true},
1773 .supports_rmii = {false, false, false, false, true},
1774 .supports_rgmii = {false, false, false, false, true},
1775 .internal_phy = {true, true, true, true, false},
1776 },
1777
1778 [LAN9371] = {
1779 .chip_id = LAN9371_CHIP_ID,
1780 .dev_name = "LAN9371",
1781 .num_vlans = 4096,
1782 .num_alus = 1024,
1783 .num_statics = 256,
1784 .cpu_ports = 0x30, /* can be configured as cpu port */
1785 .port_cnt = 6, /* total physical port count */
1786 .port_nirqs = 6,
1787 .num_tx_queues = 8,
1788 .num_ipms = 8,
1789 .tc_cbs_supported = true,
1790 .phy_side_mdio_supported = true,
1791 .ops = &lan937x_dev_ops,
1792 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1793 .mib_names = ksz9477_mib_names,
1794 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1795 .reg_mib_cnt = MIB_COUNTER_NUM,
1796 .regs = ksz9477_regs,
1797 .masks = lan937x_masks,
1798 .shifts = lan937x_shifts,
1799 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1800 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1801 .supports_mii = {false, false, false, false, true, true},
1802 .supports_rmii = {false, false, false, false, true, true},
1803 .supports_rgmii = {false, false, false, false, true, true},
1804 .internal_phy = {true, true, true, true, false, false},
1805 },
1806
1807 [LAN9372] = {
1808 .chip_id = LAN9372_CHIP_ID,
1809 .dev_name = "LAN9372",
1810 .num_vlans = 4096,
1811 .num_alus = 1024,
1812 .num_statics = 256,
1813 .cpu_ports = 0x30, /* can be configured as cpu port */
1814 .port_cnt = 8, /* total physical port count */
1815 .port_nirqs = 6,
1816 .num_tx_queues = 8,
1817 .num_ipms = 8,
1818 .tc_cbs_supported = true,
1819 .phy_side_mdio_supported = true,
1820 .ops = &lan937x_dev_ops,
1821 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1822 .mib_names = ksz9477_mib_names,
1823 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1824 .reg_mib_cnt = MIB_COUNTER_NUM,
1825 .regs = ksz9477_regs,
1826 .masks = lan937x_masks,
1827 .shifts = lan937x_shifts,
1828 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1829 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1830 .supports_mii = {false, false, false, false,
1831 true, true, false, false},
1832 .supports_rmii = {false, false, false, false,
1833 true, true, false, false},
1834 .supports_rgmii = {false, false, false, false,
1835 true, true, false, false},
1836 .internal_phy = {true, true, true, true,
1837 false, false, true, true},
1838 },
1839
1840 [LAN9373] = {
1841 .chip_id = LAN9373_CHIP_ID,
1842 .dev_name = "LAN9373",
1843 .num_vlans = 4096,
1844 .num_alus = 1024,
1845 .num_statics = 256,
1846 .cpu_ports = 0x38, /* can be configured as cpu port */
1847 .port_cnt = 5, /* total physical port count */
1848 .port_nirqs = 6,
1849 .num_tx_queues = 8,
1850 .num_ipms = 8,
1851 .tc_cbs_supported = true,
1852 .phy_side_mdio_supported = true,
1853 .ops = &lan937x_dev_ops,
1854 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1855 .mib_names = ksz9477_mib_names,
1856 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1857 .reg_mib_cnt = MIB_COUNTER_NUM,
1858 .regs = ksz9477_regs,
1859 .masks = lan937x_masks,
1860 .shifts = lan937x_shifts,
1861 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1862 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1863 .supports_mii = {false, false, false, false,
1864 true, true, false, false},
1865 .supports_rmii = {false, false, false, false,
1866 true, true, false, false},
1867 .supports_rgmii = {false, false, false, false,
1868 true, true, false, false},
1869 .internal_phy = {true, true, true, false,
1870 false, false, true, true},
1871 },
1872
1873 [LAN9374] = {
1874 .chip_id = LAN9374_CHIP_ID,
1875 .dev_name = "LAN9374",
1876 .num_vlans = 4096,
1877 .num_alus = 1024,
1878 .num_statics = 256,
1879 .cpu_ports = 0x30, /* can be configured as cpu port */
1880 .port_cnt = 8, /* total physical port count */
1881 .port_nirqs = 6,
1882 .num_tx_queues = 8,
1883 .num_ipms = 8,
1884 .tc_cbs_supported = true,
1885 .phy_side_mdio_supported = true,
1886 .ops = &lan937x_dev_ops,
1887 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1888 .mib_names = ksz9477_mib_names,
1889 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1890 .reg_mib_cnt = MIB_COUNTER_NUM,
1891 .regs = ksz9477_regs,
1892 .masks = lan937x_masks,
1893 .shifts = lan937x_shifts,
1894 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1895 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1896 .supports_mii = {false, false, false, false,
1897 true, true, false, false},
1898 .supports_rmii = {false, false, false, false,
1899 true, true, false, false},
1900 .supports_rgmii = {false, false, false, false,
1901 true, true, false, false},
1902 .internal_phy = {true, true, true, true,
1903 false, false, true, true},
1904 },
1905
1906 [LAN9646] = {
1907 .chip_id = LAN9646_CHIP_ID,
1908 .dev_name = "LAN9646",
1909 .num_vlans = 4096,
1910 .num_alus = 4096,
1911 .num_statics = 16,
1912 .cpu_ports = 0x7F, /* can be configured as cpu port */
1913 .port_cnt = 7, /* total physical port count */
1914 .port_nirqs = 4,
1915 .num_tx_queues = 4,
1916 .num_ipms = 8,
1917 .ops = &ksz9477_dev_ops,
1918 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1919 .phy_errata_9477 = true,
1920 .mib_names = ksz9477_mib_names,
1921 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1922 .reg_mib_cnt = MIB_COUNTER_NUM,
1923 .regs = ksz9477_regs,
1924 .masks = ksz9477_masks,
1925 .shifts = ksz9477_shifts,
1926 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1927 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1928 .supports_mii = {false, false, false, false,
1929 false, true, true},
1930 .supports_rmii = {false, false, false, false,
1931 false, true, true},
1932 .supports_rgmii = {false, false, false, false,
1933 false, true, true},
1934 .internal_phy = {true, true, true, true,
1935 true, false, false},
1936 .gbit_capable = {true, true, true, true, true, true, true},
1937 .wr_table = &ksz9477_register_set,
1938 .rd_table = &ksz9477_register_set,
1939 },
1940};
1941EXPORT_SYMBOL_GPL(ksz_switch_chips);
1942
1943static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1944{
1945 int i;
1946
1947 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1948 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1949
1950 if (chip->chip_id == prod_num)
1951 return chip;
1952 }
1953
1954 return NULL;
1955}
1956
1957static int ksz_check_device_id(struct ksz_device *dev)
1958{
1959 const struct ksz_chip_data *expected_chip_data;
1960 u32 expected_chip_id;
1961
1962 if (dev->pdata) {
1963 expected_chip_id = dev->pdata->chip_id;
1964 expected_chip_data = ksz_lookup_info(expected_chip_id);
1965 if (WARN_ON(!expected_chip_data))
1966 return -ENODEV;
1967 } else {
1968 expected_chip_data = of_device_get_match_data(dev->dev);
1969 expected_chip_id = expected_chip_data->chip_id;
1970 }
1971
1972 if (expected_chip_id != dev->chip_id) {
1973 dev_err(dev->dev,
1974 "Device tree specifies chip %s but found %s, please fix it!\n",
1975 expected_chip_data->dev_name, dev->info->dev_name);
1976 return -ENODEV;
1977 }
1978
1979 return 0;
1980}
1981
1982static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1983 struct phylink_config *config)
1984{
1985 struct ksz_device *dev = ds->priv;
1986
1987 if (dev->info->supports_mii[port])
1988 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1989
1990 if (dev->info->supports_rmii[port])
1991 __set_bit(PHY_INTERFACE_MODE_RMII,
1992 config->supported_interfaces);
1993
1994 if (dev->info->supports_rgmii[port])
1995 phy_interface_set_rgmii(config->supported_interfaces);
1996
1997 if (dev->info->internal_phy[port]) {
1998 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1999 config->supported_interfaces);
2000 /* Compatibility for phylib's default interface type when the
2001 * phy-mode property is absent
2002 */
2003 __set_bit(PHY_INTERFACE_MODE_GMII,
2004 config->supported_interfaces);
2005 }
2006
2007 if (dev->dev_ops->get_caps)
2008 dev->dev_ops->get_caps(dev, port, config);
2009}
2010
2011void ksz_r_mib_stats64(struct ksz_device *dev, int port)
2012{
2013 struct ethtool_pause_stats *pstats;
2014 struct rtnl_link_stats64 *stats;
2015 struct ksz_stats_raw *raw;
2016 struct ksz_port_mib *mib;
2017 int ret;
2018
2019 mib = &dev->ports[port].mib;
2020 stats = &mib->stats64;
2021 pstats = &mib->pause_stats;
2022 raw = (struct ksz_stats_raw *)mib->counters;
2023
2024 spin_lock(&mib->stats64_lock);
2025
2026 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2027 raw->rx_pause;
2028 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2029 raw->tx_pause;
2030
2031 /* HW counters are counting bytes + FCS which is not acceptable
2032 * for rtnl_link_stats64 interface
2033 */
2034 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
2035 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
2036
2037 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2038 raw->rx_oversize;
2039
2040 stats->rx_crc_errors = raw->rx_crc_err;
2041 stats->rx_frame_errors = raw->rx_align_err;
2042 stats->rx_dropped = raw->rx_discards;
2043 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2044 stats->rx_frame_errors + stats->rx_dropped;
2045
2046 stats->tx_window_errors = raw->tx_late_col;
2047 stats->tx_fifo_errors = raw->tx_discards;
2048 stats->tx_aborted_errors = raw->tx_exc_col;
2049 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2050 stats->tx_aborted_errors;
2051
2052 stats->multicast = raw->rx_mcast;
2053 stats->collisions = raw->tx_total_col;
2054
2055 pstats->tx_pause_frames = raw->tx_pause;
2056 pstats->rx_pause_frames = raw->rx_pause;
2057
2058 spin_unlock(&mib->stats64_lock);
2059
2060 if (dev->info->phy_errata_9477) {
2061 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col);
2062 if (ret)
2063 dev_err(dev->dev, "Failed to monitor transmission halt\n");
2064 }
2065}
2066
2067void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2068{
2069 struct ethtool_pause_stats *pstats;
2070 struct rtnl_link_stats64 *stats;
2071 struct ksz88xx_stats_raw *raw;
2072 struct ksz_port_mib *mib;
2073
2074 mib = &dev->ports[port].mib;
2075 stats = &mib->stats64;
2076 pstats = &mib->pause_stats;
2077 raw = (struct ksz88xx_stats_raw *)mib->counters;
2078
2079 spin_lock(&mib->stats64_lock);
2080
2081 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2082 raw->rx_pause;
2083 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2084 raw->tx_pause;
2085
2086 /* HW counters are counting bytes + FCS which is not acceptable
2087 * for rtnl_link_stats64 interface
2088 */
2089 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2090 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2091
2092 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2093 raw->rx_oversize;
2094
2095 stats->rx_crc_errors = raw->rx_crc_err;
2096 stats->rx_frame_errors = raw->rx_align_err;
2097 stats->rx_dropped = raw->rx_discards;
2098 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2099 stats->rx_frame_errors + stats->rx_dropped;
2100
2101 stats->tx_window_errors = raw->tx_late_col;
2102 stats->tx_fifo_errors = raw->tx_discards;
2103 stats->tx_aborted_errors = raw->tx_exc_col;
2104 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2105 stats->tx_aborted_errors;
2106
2107 stats->multicast = raw->rx_mcast;
2108 stats->collisions = raw->tx_total_col;
2109
2110 pstats->tx_pause_frames = raw->tx_pause;
2111 pstats->rx_pause_frames = raw->rx_pause;
2112
2113 spin_unlock(&mib->stats64_lock);
2114}
2115
2116static void ksz_get_stats64(struct dsa_switch *ds, int port,
2117 struct rtnl_link_stats64 *s)
2118{
2119 struct ksz_device *dev = ds->priv;
2120 struct ksz_port_mib *mib;
2121
2122 mib = &dev->ports[port].mib;
2123
2124 spin_lock(&mib->stats64_lock);
2125 memcpy(s, &mib->stats64, sizeof(*s));
2126 spin_unlock(&mib->stats64_lock);
2127}
2128
2129static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
2130 struct ethtool_pause_stats *pause_stats)
2131{
2132 struct ksz_device *dev = ds->priv;
2133 struct ksz_port_mib *mib;
2134
2135 mib = &dev->ports[port].mib;
2136
2137 spin_lock(&mib->stats64_lock);
2138 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
2139 spin_unlock(&mib->stats64_lock);
2140}
2141
2142static void ksz_get_strings(struct dsa_switch *ds, int port,
2143 u32 stringset, uint8_t *buf)
2144{
2145 struct ksz_device *dev = ds->priv;
2146 int i;
2147
2148 if (stringset != ETH_SS_STATS)
2149 return;
2150
2151 for (i = 0; i < dev->info->mib_cnt; i++)
2152 ethtool_puts(&buf, dev->info->mib_names[i].string);
2153}
2154
2155/**
2156 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
2157 * isolation settings.
2158 * @dev: A pointer to the struct ksz_device representing the device.
2159 * @port: The port number to adjust.
2160 *
2161 * This function dynamically adjusts the port membership configuration for a
2162 * specified port and other device ports, based on Spanning Tree Protocol (STP)
2163 * states and port isolation settings. Each port, including the CPU port, has a
2164 * membership register, represented as a bitfield, where each bit corresponds
2165 * to a port number. A set bit indicates permission to forward frames to that
2166 * port. This function iterates over all ports, updating the membership register
2167 * to reflect current forwarding permissions:
2168 *
2169 * 1. Forwards frames only to ports that are part of the same bridge group and
2170 * in the BR_STATE_FORWARDING state.
2171 * 2. Takes into account the isolation status of ports; ports in the
2172 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2173 * frames to each other, even if they are in the same bridge group.
2174 * 3. Ensures that the CPU port is included in the membership based on its
2175 * upstream port configuration, allowing for management and control traffic
2176 * to flow as required.
2177 */
2178static void ksz_update_port_member(struct ksz_device *dev, int port)
2179{
2180 struct ksz_port *p = &dev->ports[port];
2181 struct dsa_switch *ds = dev->ds;
2182 u8 port_member = 0, cpu_port;
2183 const struct dsa_port *dp;
2184 int i, j;
2185
2186 if (!dsa_is_user_port(ds, port))
2187 return;
2188
2189 dp = dsa_to_port(ds, port);
2190 cpu_port = BIT(dsa_upstream_port(ds, port));
2191
2192 for (i = 0; i < ds->num_ports; i++) {
2193 const struct dsa_port *other_dp = dsa_to_port(ds, i);
2194 struct ksz_port *other_p = &dev->ports[i];
2195 u8 val = 0;
2196
2197 if (!dsa_is_user_port(ds, i))
2198 continue;
2199 if (port == i)
2200 continue;
2201 if (!dsa_port_bridge_same(dp, other_dp))
2202 continue;
2203 if (other_p->stp_state != BR_STATE_FORWARDING)
2204 continue;
2205
2206 /* At this point we know that "port" and "other" port [i] are in
2207 * the same bridge group and that "other" port [i] is in
2208 * forwarding stp state. If "port" is also in forwarding stp
2209 * state, we can allow forwarding from port [port] to port [i].
2210 * Except if both ports are isolated.
2211 */
2212 if (p->stp_state == BR_STATE_FORWARDING &&
2213 !(p->isolated && other_p->isolated)) {
2214 val |= BIT(port);
2215 port_member |= BIT(i);
2216 }
2217
2218 /* Retain port [i]'s relationship to other ports than [port] */
2219 for (j = 0; j < ds->num_ports; j++) {
2220 const struct dsa_port *third_dp;
2221 struct ksz_port *third_p;
2222
2223 if (j == i)
2224 continue;
2225 if (j == port)
2226 continue;
2227 if (!dsa_is_user_port(ds, j))
2228 continue;
2229 third_p = &dev->ports[j];
2230 if (third_p->stp_state != BR_STATE_FORWARDING)
2231 continue;
2232
2233 third_dp = dsa_to_port(ds, j);
2234
2235 /* Now we updating relation of the "other" port [i] to
2236 * the "third" port [j]. We already know that "other"
2237 * port [i] is in forwarding stp state and that "third"
2238 * port [j] is in forwarding stp state too.
2239 * We need to check if "other" port [i] and "third" port
2240 * [j] are in the same bridge group and not isolated
2241 * before allowing forwarding from port [i] to port [j].
2242 */
2243 if (dsa_port_bridge_same(other_dp, third_dp) &&
2244 !(other_p->isolated && third_p->isolated))
2245 val |= BIT(j);
2246 }
2247
2248 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2249 }
2250
2251 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2252}
2253
2254static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2255{
2256 struct ksz_device *dev = bus->priv;
2257 u16 val;
2258 int ret;
2259
2260 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2261 if (ret < 0)
2262 return ret;
2263
2264 return val;
2265}
2266
2267static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2268 u16 val)
2269{
2270 struct ksz_device *dev = bus->priv;
2271
2272 return dev->dev_ops->w_phy(dev, addr, regnum, val);
2273}
2274
2275/**
2276 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2277 * @bus: MDIO bus structure.
2278 * @addr: PHY address on the parent MDIO bus.
2279 * @regnum: Register number to read.
2280 *
2281 * This function provides a direct read operation on the parent MDIO bus for
2282 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2283 * to retrieve data from the PHY registers at the specified address and register
2284 * number.
2285 *
2286 * Return: Value of the PHY register, or a negative error code on failure.
2287 */
2288static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2289{
2290 struct ksz_device *dev = bus->priv;
2291
2292 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum);
2293}
2294
2295/**
2296 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2297 * @bus: MDIO bus structure.
2298 * @addr: PHY address on the parent MDIO bus.
2299 * @regnum: Register number to write to.
2300 * @val: Value to write to the PHY register.
2301 *
2302 * This function provides a direct write operation on the parent MDIO bus for
2303 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2304 * to modify the PHY register values at the specified address.
2305 *
2306 * Return: 0 on success, or a negative error code on failure.
2307 */
2308static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum,
2309 u16 val)
2310{
2311 struct ksz_device *dev = bus->priv;
2312
2313 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val);
2314}
2315
2316/**
2317 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2318 * @dev: Pointer to device structure.
2319 * @addr: PHY address to map to a port.
2320 *
2321 * This function finds the corresponding switch port for a given PHY address by
2322 * iterating over all user ports on the device. It checks if a port's PHY
2323 * address in `phy_addr_map` matches the specified address and if the port
2324 * contains an internal PHY. If a match is found, the index of the port is
2325 * returned.
2326 *
2327 * Return: Port index on success, or -EINVAL if no matching port is found.
2328 */
2329static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2330{
2331 struct dsa_switch *ds = dev->ds;
2332 struct dsa_port *dp;
2333
2334 dsa_switch_for_each_user_port(dp, ds) {
2335 if (dev->info->internal_phy[dp->index] &&
2336 dev->phy_addr_map[dp->index] == addr)
2337 return dp->index;
2338 }
2339
2340 return -EINVAL;
2341}
2342
2343/**
2344 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2345 * @dev: Pointer to the KSZ device structure.
2346 *
2347 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2348 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2349 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2350 *
2351 * Return: 0 on success, or a negative error code on failure.
2352 */
2353static int ksz_irq_phy_setup(struct ksz_device *dev)
2354{
2355 struct dsa_switch *ds = dev->ds;
2356 int phy, port;
2357 int irq;
2358 int ret;
2359
2360 for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2361 if (BIT(phy) & ds->phys_mii_mask) {
2362 port = ksz_phy_addr_to_port(dev, phy);
2363 if (port < 0) {
2364 ret = port;
2365 goto out;
2366 }
2367
2368 irq = irq_find_mapping(dev->ports[port].pirq.domain,
2369 PORT_SRC_PHY_INT);
2370 if (irq < 0) {
2371 ret = irq;
2372 goto out;
2373 }
2374 ds->user_mii_bus->irq[phy] = irq;
2375 }
2376 }
2377 return 0;
2378out:
2379 while (phy--)
2380 if (BIT(phy) & ds->phys_mii_mask)
2381 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2382
2383 return ret;
2384}
2385
2386/**
2387 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2388 * @dev: Pointer to the KSZ device structure.
2389 *
2390 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2391 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2392 */
2393static void ksz_irq_phy_free(struct ksz_device *dev)
2394{
2395 struct dsa_switch *ds = dev->ds;
2396 int phy;
2397
2398 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2399 if (BIT(phy) & ds->phys_mii_mask)
2400 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2401}
2402
2403/**
2404 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2405 * @dev: pointer to the KSZ device structure
2406 * @bus: pointer to the MII bus structure
2407 * @mdio_np: pointer to the MDIO node in the device tree
2408 *
2409 * This function parses and validates PHY configurations for each user port
2410 * defined in the device tree for a KSZ switch device. It verifies that the
2411 * `phy-handle` properties are correctly set and that the internal PHYs match
2412 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2413 * all validations pass. Logs error messages for any mismatches or missing data.
2414 *
2415 * Return: 0 on success, or a negative error code on failure.
2416 */
2417static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2418 struct device_node *mdio_np)
2419{
2420 struct device_node *phy_node, *phy_parent_node;
2421 bool phys_are_valid = true;
2422 struct dsa_port *dp;
2423 u32 phy_addr;
2424 int ret;
2425
2426 dsa_switch_for_each_user_port(dp, dev->ds) {
2427 if (!dev->info->internal_phy[dp->index])
2428 continue;
2429
2430 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0);
2431 if (!phy_node) {
2432 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2433 dp->index);
2434 phys_are_valid = false;
2435 continue;
2436 }
2437
2438 phy_parent_node = of_get_parent(phy_node);
2439 if (!phy_parent_node) {
2440 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2441 dp->index);
2442 phys_are_valid = false;
2443 } else if (phy_parent_node != mdio_np) {
2444 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2445 dp->index, mdio_np, phy_parent_node);
2446 phys_are_valid = false;
2447 } else {
2448 ret = of_property_read_u32(phy_node, "reg", &phy_addr);
2449 if (ret < 0) {
2450 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2451 dp->index, ret);
2452 phys_are_valid = false;
2453 } else if (phy_addr != dev->phy_addr_map[dp->index]) {
2454 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2455 dp->index, dev->phy_addr_map[dp->index],
2456 phy_addr);
2457 phys_are_valid = false;
2458 } else {
2459 bus->phy_mask |= BIT(phy_addr);
2460 }
2461 }
2462
2463 of_node_put(phy_node);
2464 of_node_put(phy_parent_node);
2465 }
2466
2467 if (!phys_are_valid)
2468 return -EINVAL;
2469
2470 return 0;
2471}
2472
2473/**
2474 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2475 * @dev: Pointer to the KSZ device structure.
2476 *
2477 * This function sets up and registers an MDIO bus for the KSZ switch device,
2478 * allowing access to its internal PHYs. If the device supports side MDIO,
2479 * the function will configure the external MDIO controller specified by the
2480 * "mdio-parent-bus" device tree property to directly manage internal PHYs.
2481 * Otherwise, SPI or I2C access is set up for PHY access.
2482 *
2483 * Return: 0 on success, or a negative error code on failure.
2484 */
2485static int ksz_mdio_register(struct ksz_device *dev)
2486{
2487 struct device_node *parent_bus_node;
2488 struct mii_bus *parent_bus = NULL;
2489 struct dsa_switch *ds = dev->ds;
2490 struct device_node *mdio_np;
2491 struct mii_bus *bus;
2492 int ret, i;
2493
2494 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2495 if (!mdio_np)
2496 return 0;
2497
2498 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0);
2499 if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2500 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2501 ret = -EINVAL;
2502
2503 goto put_mdio_node;
2504 } else if (parent_bus_node) {
2505 parent_bus = of_mdio_find_bus(parent_bus_node);
2506 if (!parent_bus) {
2507 ret = -EPROBE_DEFER;
2508
2509 goto put_mdio_node;
2510 }
2511
2512 dev->parent_mdio_bus = parent_bus;
2513 }
2514
2515 bus = devm_mdiobus_alloc(ds->dev);
2516 if (!bus) {
2517 ret = -ENOMEM;
2518 goto put_mdio_node;
2519 }
2520
2521 if (dev->dev_ops->mdio_bus_preinit) {
2522 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus);
2523 if (ret)
2524 goto put_mdio_node;
2525 }
2526
2527 if (dev->dev_ops->create_phy_addr_map) {
2528 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus);
2529 if (ret)
2530 goto put_mdio_node;
2531 } else {
2532 for (i = 0; i < dev->info->port_cnt; i++)
2533 dev->phy_addr_map[i] = i;
2534 }
2535
2536 bus->priv = dev;
2537 if (parent_bus) {
2538 bus->read = ksz_parent_mdio_read;
2539 bus->write = ksz_parent_mdio_write;
2540 bus->name = "KSZ side MDIO";
2541 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d",
2542 ds->index);
2543 } else {
2544 bus->read = ksz_sw_mdio_read;
2545 bus->write = ksz_sw_mdio_write;
2546 bus->name = "ksz user smi";
2547 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2548 }
2549
2550 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2551 if (ret)
2552 goto put_mdio_node;
2553
2554 ds->phys_mii_mask = bus->phy_mask;
2555 bus->parent = ds->dev;
2556
2557 ds->user_mii_bus = bus;
2558
2559 if (dev->irq > 0) {
2560 ret = ksz_irq_phy_setup(dev);
2561 if (ret)
2562 goto put_mdio_node;
2563 }
2564
2565 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2566 if (ret) {
2567 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2568 bus->id);
2569 if (dev->irq > 0)
2570 ksz_irq_phy_free(dev);
2571 }
2572
2573put_mdio_node:
2574 of_node_put(mdio_np);
2575 of_node_put(parent_bus_node);
2576
2577 return ret;
2578}
2579
2580static void ksz_irq_mask(struct irq_data *d)
2581{
2582 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2583
2584 kirq->masked |= BIT(d->hwirq);
2585}
2586
2587static void ksz_irq_unmask(struct irq_data *d)
2588{
2589 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2590
2591 kirq->masked &= ~BIT(d->hwirq);
2592}
2593
2594static void ksz_irq_bus_lock(struct irq_data *d)
2595{
2596 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2597
2598 mutex_lock(&kirq->dev->lock_irq);
2599}
2600
2601static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2602{
2603 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2604 struct ksz_device *dev = kirq->dev;
2605 int ret;
2606
2607 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
2608 if (ret)
2609 dev_err(dev->dev, "failed to change IRQ mask\n");
2610
2611 mutex_unlock(&dev->lock_irq);
2612}
2613
2614static const struct irq_chip ksz_irq_chip = {
2615 .name = "ksz-irq",
2616 .irq_mask = ksz_irq_mask,
2617 .irq_unmask = ksz_irq_unmask,
2618 .irq_bus_lock = ksz_irq_bus_lock,
2619 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2620};
2621
2622static int ksz_irq_domain_map(struct irq_domain *d,
2623 unsigned int irq, irq_hw_number_t hwirq)
2624{
2625 irq_set_chip_data(irq, d->host_data);
2626 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2627 irq_set_noprobe(irq);
2628
2629 return 0;
2630}
2631
2632static const struct irq_domain_ops ksz_irq_domain_ops = {
2633 .map = ksz_irq_domain_map,
2634 .xlate = irq_domain_xlate_twocell,
2635};
2636
2637static void ksz_irq_free(struct ksz_irq *kirq)
2638{
2639 int irq, virq;
2640
2641 free_irq(kirq->irq_num, kirq);
2642
2643 for (irq = 0; irq < kirq->nirqs; irq++) {
2644 virq = irq_find_mapping(kirq->domain, irq);
2645 irq_dispose_mapping(virq);
2646 }
2647
2648 irq_domain_remove(kirq->domain);
2649}
2650
2651static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2652{
2653 struct ksz_irq *kirq = dev_id;
2654 unsigned int nhandled = 0;
2655 struct ksz_device *dev;
2656 unsigned int sub_irq;
2657 u8 data;
2658 int ret;
2659 u8 n;
2660
2661 dev = kirq->dev;
2662
2663 /* Read interrupt status register */
2664 ret = ksz_read8(dev, kirq->reg_status, &data);
2665 if (ret)
2666 goto out;
2667
2668 for (n = 0; n < kirq->nirqs; ++n) {
2669 if (data & BIT(n)) {
2670 sub_irq = irq_find_mapping(kirq->domain, n);
2671 handle_nested_irq(sub_irq);
2672 ++nhandled;
2673 }
2674 }
2675out:
2676 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2677}
2678
2679static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2680{
2681 int ret, n;
2682
2683 kirq->dev = dev;
2684 kirq->masked = ~0;
2685
2686 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2687 &ksz_irq_domain_ops, kirq);
2688 if (!kirq->domain)
2689 return -ENOMEM;
2690
2691 for (n = 0; n < kirq->nirqs; n++)
2692 irq_create_mapping(kirq->domain, n);
2693
2694 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2695 IRQF_ONESHOT, kirq->name, kirq);
2696 if (ret)
2697 goto out;
2698
2699 return 0;
2700
2701out:
2702 ksz_irq_free(kirq);
2703
2704 return ret;
2705}
2706
2707static int ksz_girq_setup(struct ksz_device *dev)
2708{
2709 struct ksz_irq *girq = &dev->girq;
2710
2711 girq->nirqs = dev->info->port_cnt;
2712 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2713 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2714 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2715
2716 girq->irq_num = dev->irq;
2717
2718 return ksz_irq_common_setup(dev, girq);
2719}
2720
2721static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2722{
2723 struct ksz_irq *pirq = &dev->ports[p].pirq;
2724
2725 pirq->nirqs = dev->info->port_nirqs;
2726 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2727 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2728 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2729
2730 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2731 if (pirq->irq_num < 0)
2732 return pirq->irq_num;
2733
2734 return ksz_irq_common_setup(dev, pirq);
2735}
2736
2737static int ksz_parse_drive_strength(struct ksz_device *dev);
2738
2739static int ksz_setup(struct dsa_switch *ds)
2740{
2741 struct ksz_device *dev = ds->priv;
2742 struct dsa_port *dp;
2743 struct ksz_port *p;
2744 const u16 *regs;
2745 int ret;
2746
2747 regs = dev->info->regs;
2748
2749 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2750 dev->info->num_vlans, GFP_KERNEL);
2751 if (!dev->vlan_cache)
2752 return -ENOMEM;
2753
2754 ret = dev->dev_ops->reset(dev);
2755 if (ret) {
2756 dev_err(ds->dev, "failed to reset switch\n");
2757 return ret;
2758 }
2759
2760 ret = ksz_parse_drive_strength(dev);
2761 if (ret)
2762 return ret;
2763
2764 /* set broadcast storm protection 10% rate */
2765 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2766 BROADCAST_STORM_RATE,
2767 (BROADCAST_STORM_VALUE *
2768 BROADCAST_STORM_PROT_RATE) / 100);
2769
2770 dev->dev_ops->config_cpu_port(ds);
2771
2772 dev->dev_ops->enable_stp_addr(dev);
2773
2774 ds->num_tx_queues = dev->info->num_tx_queues;
2775
2776 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2777 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2778
2779 ksz_init_mib_timer(dev);
2780
2781 ds->configure_vlan_while_not_filtering = false;
2782 ds->dscp_prio_mapping_is_global = true;
2783
2784 if (dev->dev_ops->setup) {
2785 ret = dev->dev_ops->setup(ds);
2786 if (ret)
2787 return ret;
2788 }
2789
2790 /* Start with learning disabled on standalone user ports, and enabled
2791 * on the CPU port. In lack of other finer mechanisms, learning on the
2792 * CPU port will avoid flooding bridge local addresses on the network
2793 * in some cases.
2794 */
2795 p = &dev->ports[dev->cpu_port];
2796 p->learning = true;
2797
2798 if (dev->irq > 0) {
2799 ret = ksz_girq_setup(dev);
2800 if (ret)
2801 return ret;
2802
2803 dsa_switch_for_each_user_port(dp, dev->ds) {
2804 ret = ksz_pirq_setup(dev, dp->index);
2805 if (ret)
2806 goto out_girq;
2807
2808 ret = ksz_ptp_irq_setup(ds, dp->index);
2809 if (ret)
2810 goto out_pirq;
2811 }
2812 }
2813
2814 ret = ksz_ptp_clock_register(ds);
2815 if (ret) {
2816 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2817 goto out_ptpirq;
2818 }
2819
2820 ret = ksz_mdio_register(dev);
2821 if (ret < 0) {
2822 dev_err(dev->dev, "failed to register the mdio");
2823 goto out_ptp_clock_unregister;
2824 }
2825
2826 ret = ksz_dcb_init(dev);
2827 if (ret)
2828 goto out_ptp_clock_unregister;
2829
2830 /* start switch */
2831 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2832 SW_START, SW_START);
2833
2834 return 0;
2835
2836out_ptp_clock_unregister:
2837 ksz_ptp_clock_unregister(ds);
2838out_ptpirq:
2839 if (dev->irq > 0)
2840 dsa_switch_for_each_user_port(dp, dev->ds)
2841 ksz_ptp_irq_free(ds, dp->index);
2842out_pirq:
2843 if (dev->irq > 0)
2844 dsa_switch_for_each_user_port(dp, dev->ds)
2845 ksz_irq_free(&dev->ports[dp->index].pirq);
2846out_girq:
2847 if (dev->irq > 0)
2848 ksz_irq_free(&dev->girq);
2849
2850 return ret;
2851}
2852
2853static void ksz_teardown(struct dsa_switch *ds)
2854{
2855 struct ksz_device *dev = ds->priv;
2856 struct dsa_port *dp;
2857
2858 ksz_ptp_clock_unregister(ds);
2859
2860 if (dev->irq > 0) {
2861 dsa_switch_for_each_user_port(dp, dev->ds) {
2862 ksz_ptp_irq_free(ds, dp->index);
2863
2864 ksz_irq_free(&dev->ports[dp->index].pirq);
2865 }
2866
2867 ksz_irq_free(&dev->girq);
2868 }
2869
2870 if (dev->dev_ops->teardown)
2871 dev->dev_ops->teardown(ds);
2872}
2873
2874static void port_r_cnt(struct ksz_device *dev, int port)
2875{
2876 struct ksz_port_mib *mib = &dev->ports[port].mib;
2877 u64 *dropped;
2878
2879 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2880 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2881 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2882 &mib->counters[mib->cnt_ptr]);
2883 ++mib->cnt_ptr;
2884 }
2885
2886 /* last one in storage */
2887 dropped = &mib->counters[dev->info->mib_cnt];
2888
2889 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2890 while (mib->cnt_ptr < dev->info->mib_cnt) {
2891 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2892 dropped, &mib->counters[mib->cnt_ptr]);
2893 ++mib->cnt_ptr;
2894 }
2895 mib->cnt_ptr = 0;
2896}
2897
2898static void ksz_mib_read_work(struct work_struct *work)
2899{
2900 struct ksz_device *dev = container_of(work, struct ksz_device,
2901 mib_read.work);
2902 struct ksz_port_mib *mib;
2903 struct ksz_port *p;
2904 int i;
2905
2906 for (i = 0; i < dev->info->port_cnt; i++) {
2907 if (dsa_is_unused_port(dev->ds, i))
2908 continue;
2909
2910 p = &dev->ports[i];
2911 mib = &p->mib;
2912 mutex_lock(&mib->cnt_mutex);
2913
2914 /* Only read MIB counters when the port is told to do.
2915 * If not, read only dropped counters when link is not up.
2916 */
2917 if (!p->read) {
2918 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2919
2920 if (!netif_carrier_ok(dp->user))
2921 mib->cnt_ptr = dev->info->reg_mib_cnt;
2922 }
2923 port_r_cnt(dev, i);
2924 p->read = false;
2925
2926 if (dev->dev_ops->r_mib_stat64)
2927 dev->dev_ops->r_mib_stat64(dev, i);
2928
2929 mutex_unlock(&mib->cnt_mutex);
2930 }
2931
2932 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2933}
2934
2935void ksz_init_mib_timer(struct ksz_device *dev)
2936{
2937 int i;
2938
2939 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2940
2941 for (i = 0; i < dev->info->port_cnt; i++) {
2942 struct ksz_port_mib *mib = &dev->ports[i].mib;
2943
2944 dev->dev_ops->port_init_cnt(dev, i);
2945
2946 mib->cnt_ptr = 0;
2947 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2948 }
2949}
2950
2951static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2952{
2953 struct ksz_device *dev = ds->priv;
2954 u16 val = 0xffff;
2955 int ret;
2956
2957 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2958 if (ret)
2959 return ret;
2960
2961 return val;
2962}
2963
2964static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2965{
2966 struct ksz_device *dev = ds->priv;
2967 int ret;
2968
2969 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2970 if (ret)
2971 return ret;
2972
2973 return 0;
2974}
2975
2976static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2977{
2978 struct ksz_device *dev = ds->priv;
2979
2980 switch (dev->chip_id) {
2981 case KSZ88X3_CHIP_ID:
2982 /* Silicon Errata Sheet (DS80000830A):
2983 * Port 1 does not work with LinkMD Cable-Testing.
2984 * Port 1 does not respond to received PAUSE control frames.
2985 */
2986 if (!port)
2987 return MICREL_KSZ8_P1_ERRATA;
2988 break;
2989 case KSZ8567_CHIP_ID:
2990 /* KSZ8567R Errata DS80000752C Module 4 */
2991 case KSZ8765_CHIP_ID:
2992 case KSZ8794_CHIP_ID:
2993 case KSZ8795_CHIP_ID:
2994 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */
2995 case KSZ9477_CHIP_ID:
2996 /* KSZ9477S Errata DS80000754A Module 4 */
2997 case KSZ9567_CHIP_ID:
2998 /* KSZ9567S Errata DS80000756A Module 4 */
2999 case KSZ9896_CHIP_ID:
3000 /* KSZ9896C Errata DS80000757A Module 3 */
3001 case KSZ9897_CHIP_ID:
3002 case LAN9646_CHIP_ID:
3003 /* KSZ9897R Errata DS80000758C Module 4 */
3004 /* Energy Efficient Ethernet (EEE) feature select must be manually disabled
3005 * The EEE feature is enabled by default, but it is not fully
3006 * operational. It must be manually disabled through register
3007 * controls. If not disabled, the PHY ports can auto-negotiate
3008 * to enable EEE, and this feature can cause link drops when
3009 * linked to another device supporting EEE.
3010 *
3011 * The same item appears in the errata for all switches above.
3012 */
3013 return MICREL_NO_EEE;
3014 }
3015
3016 return 0;
3017}
3018
3019static void ksz_phylink_mac_link_down(struct phylink_config *config,
3020 unsigned int mode,
3021 phy_interface_t interface)
3022{
3023 struct dsa_port *dp = dsa_phylink_to_port(config);
3024 struct ksz_device *dev = dp->ds->priv;
3025
3026 /* Read all MIB counters when the link is going down. */
3027 dev->ports[dp->index].read = true;
3028 /* timer started */
3029 if (dev->mib_read_interval)
3030 schedule_delayed_work(&dev->mib_read, 0);
3031}
3032
3033static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
3034{
3035 struct ksz_device *dev = ds->priv;
3036
3037 if (sset != ETH_SS_STATS)
3038 return 0;
3039
3040 return dev->info->mib_cnt;
3041}
3042
3043static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
3044 uint64_t *buf)
3045{
3046 const struct dsa_port *dp = dsa_to_port(ds, port);
3047 struct ksz_device *dev = ds->priv;
3048 struct ksz_port_mib *mib;
3049
3050 mib = &dev->ports[port].mib;
3051 mutex_lock(&mib->cnt_mutex);
3052
3053 /* Only read dropped counters if no link. */
3054 if (!netif_carrier_ok(dp->user))
3055 mib->cnt_ptr = dev->info->reg_mib_cnt;
3056 port_r_cnt(dev, port);
3057 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
3058 mutex_unlock(&mib->cnt_mutex);
3059}
3060
3061static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
3062 struct dsa_bridge bridge,
3063 bool *tx_fwd_offload,
3064 struct netlink_ext_ack *extack)
3065{
3066 /* port_stp_state_set() will be called after to put the port in
3067 * appropriate state so there is no need to do anything.
3068 */
3069
3070 return 0;
3071}
3072
3073static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
3074 struct dsa_bridge bridge)
3075{
3076 /* port_stp_state_set() will be called after to put the port in
3077 * forwarding state so there is no need to do anything.
3078 */
3079}
3080
3081static void ksz_port_fast_age(struct dsa_switch *ds, int port)
3082{
3083 struct ksz_device *dev = ds->priv;
3084
3085 dev->dev_ops->flush_dyn_mac_table(dev, port);
3086}
3087
3088static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
3089{
3090 struct ksz_device *dev = ds->priv;
3091
3092 if (!dev->dev_ops->set_ageing_time)
3093 return -EOPNOTSUPP;
3094
3095 return dev->dev_ops->set_ageing_time(dev, msecs);
3096}
3097
3098static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
3099 const unsigned char *addr, u16 vid,
3100 struct dsa_db db)
3101{
3102 struct ksz_device *dev = ds->priv;
3103
3104 if (!dev->dev_ops->fdb_add)
3105 return -EOPNOTSUPP;
3106
3107 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
3108}
3109
3110static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
3111 const unsigned char *addr,
3112 u16 vid, struct dsa_db db)
3113{
3114 struct ksz_device *dev = ds->priv;
3115
3116 if (!dev->dev_ops->fdb_del)
3117 return -EOPNOTSUPP;
3118
3119 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
3120}
3121
3122static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
3123 dsa_fdb_dump_cb_t *cb, void *data)
3124{
3125 struct ksz_device *dev = ds->priv;
3126
3127 if (!dev->dev_ops->fdb_dump)
3128 return -EOPNOTSUPP;
3129
3130 return dev->dev_ops->fdb_dump(dev, port, cb, data);
3131}
3132
3133static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
3134 const struct switchdev_obj_port_mdb *mdb,
3135 struct dsa_db db)
3136{
3137 struct ksz_device *dev = ds->priv;
3138
3139 if (!dev->dev_ops->mdb_add)
3140 return -EOPNOTSUPP;
3141
3142 return dev->dev_ops->mdb_add(dev, port, mdb, db);
3143}
3144
3145static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
3146 const struct switchdev_obj_port_mdb *mdb,
3147 struct dsa_db db)
3148{
3149 struct ksz_device *dev = ds->priv;
3150
3151 if (!dev->dev_ops->mdb_del)
3152 return -EOPNOTSUPP;
3153
3154 return dev->dev_ops->mdb_del(dev, port, mdb, db);
3155}
3156
3157static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
3158 int port)
3159{
3160 u32 queue_map = 0;
3161 int ipm;
3162
3163 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
3164 int queue;
3165
3166 /* Traffic Type (TT) is corresponding to the Internal Priority
3167 * Map (IPM) in the switch. Traffic Class (TC) is
3168 * corresponding to the queue in the switch.
3169 */
3170 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues);
3171 if (queue < 0)
3172 return queue;
3173
3174 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
3175 }
3176
3177 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3178}
3179
3180static int ksz_port_setup(struct dsa_switch *ds, int port)
3181{
3182 struct ksz_device *dev = ds->priv;
3183 int ret;
3184
3185 if (!dsa_is_user_port(ds, port))
3186 return 0;
3187
3188 /* setup user port */
3189 dev->dev_ops->port_setup(dev, port, false);
3190
3191 if (!is_ksz8(dev)) {
3192 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
3193 if (ret)
3194 return ret;
3195 }
3196
3197 /* port_stp_state_set() will be called after to enable the port so
3198 * there is no need to do anything.
3199 */
3200
3201 return ksz_dcb_init_port(dev, port);
3202}
3203
3204void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
3205{
3206 struct ksz_device *dev = ds->priv;
3207 struct ksz_port *p;
3208 const u16 *regs;
3209 u8 data;
3210
3211 regs = dev->info->regs;
3212
3213 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
3214 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3215
3216 p = &dev->ports[port];
3217
3218 switch (state) {
3219 case BR_STATE_DISABLED:
3220 data |= PORT_LEARN_DISABLE;
3221 break;
3222 case BR_STATE_LISTENING:
3223 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3224 break;
3225 case BR_STATE_LEARNING:
3226 data |= PORT_RX_ENABLE;
3227 if (!p->learning)
3228 data |= PORT_LEARN_DISABLE;
3229 break;
3230 case BR_STATE_FORWARDING:
3231 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
3232 if (!p->learning)
3233 data |= PORT_LEARN_DISABLE;
3234 break;
3235 case BR_STATE_BLOCKING:
3236 data |= PORT_LEARN_DISABLE;
3237 break;
3238 default:
3239 dev_err(ds->dev, "invalid STP state: %d\n", state);
3240 return;
3241 }
3242
3243 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
3244
3245 p->stp_state = state;
3246
3247 ksz_update_port_member(dev, port);
3248}
3249
3250static void ksz_port_teardown(struct dsa_switch *ds, int port)
3251{
3252 struct ksz_device *dev = ds->priv;
3253
3254 switch (dev->chip_id) {
3255 case KSZ8563_CHIP_ID:
3256 case KSZ8567_CHIP_ID:
3257 case KSZ9477_CHIP_ID:
3258 case KSZ9563_CHIP_ID:
3259 case KSZ9567_CHIP_ID:
3260 case KSZ9893_CHIP_ID:
3261 case KSZ9896_CHIP_ID:
3262 case KSZ9897_CHIP_ID:
3263 case LAN9646_CHIP_ID:
3264 if (dsa_is_user_port(ds, port))
3265 ksz9477_port_acl_free(dev, port);
3266 }
3267}
3268
3269static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3270 struct switchdev_brport_flags flags,
3271 struct netlink_ext_ack *extack)
3272{
3273 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
3274 return -EINVAL;
3275
3276 return 0;
3277}
3278
3279static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
3280 struct switchdev_brport_flags flags,
3281 struct netlink_ext_ack *extack)
3282{
3283 struct ksz_device *dev = ds->priv;
3284 struct ksz_port *p = &dev->ports[port];
3285
3286 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
3287 if (flags.mask & BR_LEARNING)
3288 p->learning = !!(flags.val & BR_LEARNING);
3289
3290 if (flags.mask & BR_ISOLATED)
3291 p->isolated = !!(flags.val & BR_ISOLATED);
3292
3293 /* Make the change take effect immediately */
3294 ksz_port_stp_state_set(ds, port, p->stp_state);
3295 }
3296
3297 return 0;
3298}
3299
3300static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
3301 int port,
3302 enum dsa_tag_protocol mp)
3303{
3304 struct ksz_device *dev = ds->priv;
3305 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
3306
3307 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
3308 proto = DSA_TAG_PROTO_KSZ8795;
3309
3310 if (dev->chip_id == KSZ88X3_CHIP_ID ||
3311 dev->chip_id == KSZ8563_CHIP_ID ||
3312 dev->chip_id == KSZ9893_CHIP_ID ||
3313 dev->chip_id == KSZ9563_CHIP_ID)
3314 proto = DSA_TAG_PROTO_KSZ9893;
3315
3316 if (dev->chip_id == KSZ8567_CHIP_ID ||
3317 dev->chip_id == KSZ9477_CHIP_ID ||
3318 dev->chip_id == KSZ9896_CHIP_ID ||
3319 dev->chip_id == KSZ9897_CHIP_ID ||
3320 dev->chip_id == KSZ9567_CHIP_ID ||
3321 dev->chip_id == LAN9646_CHIP_ID)
3322 proto = DSA_TAG_PROTO_KSZ9477;
3323
3324 if (is_lan937x(dev))
3325 proto = DSA_TAG_PROTO_LAN937X;
3326
3327 return proto;
3328}
3329
3330static int ksz_connect_tag_protocol(struct dsa_switch *ds,
3331 enum dsa_tag_protocol proto)
3332{
3333 struct ksz_tagger_data *tagger_data;
3334
3335 switch (proto) {
3336 case DSA_TAG_PROTO_KSZ8795:
3337 return 0;
3338 case DSA_TAG_PROTO_KSZ9893:
3339 case DSA_TAG_PROTO_KSZ9477:
3340 case DSA_TAG_PROTO_LAN937X:
3341 tagger_data = ksz_tagger_data(ds);
3342 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3343 return 0;
3344 default:
3345 return -EPROTONOSUPPORT;
3346 }
3347}
3348
3349static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
3350 bool flag, struct netlink_ext_ack *extack)
3351{
3352 struct ksz_device *dev = ds->priv;
3353
3354 if (!dev->dev_ops->vlan_filtering)
3355 return -EOPNOTSUPP;
3356
3357 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
3358}
3359
3360static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
3361 const struct switchdev_obj_port_vlan *vlan,
3362 struct netlink_ext_ack *extack)
3363{
3364 struct ksz_device *dev = ds->priv;
3365
3366 if (!dev->dev_ops->vlan_add)
3367 return -EOPNOTSUPP;
3368
3369 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
3370}
3371
3372static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
3373 const struct switchdev_obj_port_vlan *vlan)
3374{
3375 struct ksz_device *dev = ds->priv;
3376
3377 if (!dev->dev_ops->vlan_del)
3378 return -EOPNOTSUPP;
3379
3380 return dev->dev_ops->vlan_del(dev, port, vlan);
3381}
3382
3383static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
3384 struct dsa_mall_mirror_tc_entry *mirror,
3385 bool ingress, struct netlink_ext_ack *extack)
3386{
3387 struct ksz_device *dev = ds->priv;
3388
3389 if (!dev->dev_ops->mirror_add)
3390 return -EOPNOTSUPP;
3391
3392 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
3393}
3394
3395static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
3396 struct dsa_mall_mirror_tc_entry *mirror)
3397{
3398 struct ksz_device *dev = ds->priv;
3399
3400 if (dev->dev_ops->mirror_del)
3401 dev->dev_ops->mirror_del(dev, port, mirror);
3402}
3403
3404static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
3405{
3406 struct ksz_device *dev = ds->priv;
3407
3408 if (!dev->dev_ops->change_mtu)
3409 return -EOPNOTSUPP;
3410
3411 return dev->dev_ops->change_mtu(dev, port, mtu);
3412}
3413
3414static int ksz_max_mtu(struct dsa_switch *ds, int port)
3415{
3416 struct ksz_device *dev = ds->priv;
3417
3418 switch (dev->chip_id) {
3419 case KSZ8795_CHIP_ID:
3420 case KSZ8794_CHIP_ID:
3421 case KSZ8765_CHIP_ID:
3422 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3423 case KSZ88X3_CHIP_ID:
3424 case KSZ8864_CHIP_ID:
3425 case KSZ8895_CHIP_ID:
3426 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3427 case KSZ8563_CHIP_ID:
3428 case KSZ8567_CHIP_ID:
3429 case KSZ9477_CHIP_ID:
3430 case KSZ9563_CHIP_ID:
3431 case KSZ9567_CHIP_ID:
3432 case KSZ9893_CHIP_ID:
3433 case KSZ9896_CHIP_ID:
3434 case KSZ9897_CHIP_ID:
3435 case LAN9370_CHIP_ID:
3436 case LAN9371_CHIP_ID:
3437 case LAN9372_CHIP_ID:
3438 case LAN9373_CHIP_ID:
3439 case LAN9374_CHIP_ID:
3440 case LAN9646_CHIP_ID:
3441 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3442 }
3443
3444 return -EOPNOTSUPP;
3445}
3446
3447static int ksz_validate_eee(struct dsa_switch *ds, int port)
3448{
3449 struct ksz_device *dev = ds->priv;
3450
3451 if (!dev->info->internal_phy[port])
3452 return -EOPNOTSUPP;
3453
3454 switch (dev->chip_id) {
3455 case KSZ8563_CHIP_ID:
3456 case KSZ8567_CHIP_ID:
3457 case KSZ9477_CHIP_ID:
3458 case KSZ9563_CHIP_ID:
3459 case KSZ9567_CHIP_ID:
3460 case KSZ9893_CHIP_ID:
3461 case KSZ9896_CHIP_ID:
3462 case KSZ9897_CHIP_ID:
3463 case LAN9646_CHIP_ID:
3464 return 0;
3465 }
3466
3467 return -EOPNOTSUPP;
3468}
3469
3470static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
3471 struct ethtool_keee *e)
3472{
3473 int ret;
3474
3475 ret = ksz_validate_eee(ds, port);
3476 if (ret)
3477 return ret;
3478
3479 /* There is no documented control of Tx LPI configuration. */
3480 e->tx_lpi_enabled = true;
3481
3482 /* There is no documented control of Tx LPI timer. According to tests
3483 * Tx LPI timer seems to be set by default to minimal value.
3484 */
3485 e->tx_lpi_timer = 0;
3486
3487 return 0;
3488}
3489
3490static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3491 struct ethtool_keee *e)
3492{
3493 struct ksz_device *dev = ds->priv;
3494 int ret;
3495
3496 ret = ksz_validate_eee(ds, port);
3497 if (ret)
3498 return ret;
3499
3500 if (!e->tx_lpi_enabled) {
3501 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3502 return -EINVAL;
3503 }
3504
3505 if (e->tx_lpi_timer) {
3506 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3507 return -EINVAL;
3508 }
3509
3510 return 0;
3511}
3512
3513static void ksz_set_xmii(struct ksz_device *dev, int port,
3514 phy_interface_t interface)
3515{
3516 const u8 *bitval = dev->info->xmii_ctrl1;
3517 struct ksz_port *p = &dev->ports[port];
3518 const u16 *regs = dev->info->regs;
3519 u8 data8;
3520
3521 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3522
3523 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3524 P_RGMII_ID_EG_ENABLE);
3525
3526 switch (interface) {
3527 case PHY_INTERFACE_MODE_MII:
3528 data8 |= bitval[P_MII_SEL];
3529 break;
3530 case PHY_INTERFACE_MODE_RMII:
3531 data8 |= bitval[P_RMII_SEL];
3532 break;
3533 case PHY_INTERFACE_MODE_GMII:
3534 data8 |= bitval[P_GMII_SEL];
3535 break;
3536 case PHY_INTERFACE_MODE_RGMII:
3537 case PHY_INTERFACE_MODE_RGMII_ID:
3538 case PHY_INTERFACE_MODE_RGMII_TXID:
3539 case PHY_INTERFACE_MODE_RGMII_RXID:
3540 data8 |= bitval[P_RGMII_SEL];
3541 /* On KSZ9893, disable RGMII in-band status support */
3542 if (dev->chip_id == KSZ9893_CHIP_ID ||
3543 dev->chip_id == KSZ8563_CHIP_ID ||
3544 dev->chip_id == KSZ9563_CHIP_ID ||
3545 is_lan937x(dev))
3546 data8 &= ~P_MII_MAC_MODE;
3547 break;
3548 default:
3549 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3550 phy_modes(interface), port);
3551 return;
3552 }
3553
3554 if (p->rgmii_tx_val)
3555 data8 |= P_RGMII_ID_EG_ENABLE;
3556
3557 if (p->rgmii_rx_val)
3558 data8 |= P_RGMII_ID_IG_ENABLE;
3559
3560 /* Write the updated value */
3561 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3562}
3563
3564phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3565{
3566 const u8 *bitval = dev->info->xmii_ctrl1;
3567 const u16 *regs = dev->info->regs;
3568 phy_interface_t interface;
3569 u8 data8;
3570 u8 val;
3571
3572 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3573
3574 val = FIELD_GET(P_MII_SEL_M, data8);
3575
3576 if (val == bitval[P_MII_SEL]) {
3577 if (gbit)
3578 interface = PHY_INTERFACE_MODE_GMII;
3579 else
3580 interface = PHY_INTERFACE_MODE_MII;
3581 } else if (val == bitval[P_RMII_SEL]) {
3582 interface = PHY_INTERFACE_MODE_RMII;
3583 } else {
3584 interface = PHY_INTERFACE_MODE_RGMII;
3585 if (data8 & P_RGMII_ID_EG_ENABLE)
3586 interface = PHY_INTERFACE_MODE_RGMII_TXID;
3587 if (data8 & P_RGMII_ID_IG_ENABLE) {
3588 interface = PHY_INTERFACE_MODE_RGMII_RXID;
3589 if (data8 & P_RGMII_ID_EG_ENABLE)
3590 interface = PHY_INTERFACE_MODE_RGMII_ID;
3591 }
3592 }
3593
3594 return interface;
3595}
3596
3597static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3598 unsigned int mode,
3599 const struct phylink_link_state *state)
3600{
3601 struct dsa_port *dp = dsa_phylink_to_port(config);
3602 struct ksz_device *dev = dp->ds->priv;
3603
3604 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3605}
3606
3607static void ksz_phylink_mac_config(struct phylink_config *config,
3608 unsigned int mode,
3609 const struct phylink_link_state *state)
3610{
3611 struct dsa_port *dp = dsa_phylink_to_port(config);
3612 struct ksz_device *dev = dp->ds->priv;
3613 int port = dp->index;
3614
3615 /* Internal PHYs */
3616 if (dev->info->internal_phy[port])
3617 return;
3618
3619 if (phylink_autoneg_inband(mode)) {
3620 dev_err(dev->dev, "In-band AN not supported!\n");
3621 return;
3622 }
3623
3624 ksz_set_xmii(dev, port, state->interface);
3625
3626 if (dev->dev_ops->setup_rgmii_delay)
3627 dev->dev_ops->setup_rgmii_delay(dev, port);
3628}
3629
3630bool ksz_get_gbit(struct ksz_device *dev, int port)
3631{
3632 const u8 *bitval = dev->info->xmii_ctrl1;
3633 const u16 *regs = dev->info->regs;
3634 bool gbit = false;
3635 u8 data8;
3636 bool val;
3637
3638 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3639
3640 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3641
3642 if (val == bitval[P_GMII_1GBIT])
3643 gbit = true;
3644
3645 return gbit;
3646}
3647
3648static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3649{
3650 const u8 *bitval = dev->info->xmii_ctrl1;
3651 const u16 *regs = dev->info->regs;
3652 u8 data8;
3653
3654 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3655
3656 data8 &= ~P_GMII_1GBIT_M;
3657
3658 if (gbit)
3659 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3660 else
3661 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3662
3663 /* Write the updated value */
3664 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3665}
3666
3667static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3668{
3669 const u8 *bitval = dev->info->xmii_ctrl0;
3670 const u16 *regs = dev->info->regs;
3671 u8 data8;
3672
3673 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3674
3675 data8 &= ~P_MII_100MBIT_M;
3676
3677 if (speed == SPEED_100)
3678 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3679 else
3680 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3681
3682 /* Write the updated value */
3683 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3684}
3685
3686static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3687{
3688 if (speed == SPEED_1000)
3689 ksz_set_gbit(dev, port, true);
3690 else
3691 ksz_set_gbit(dev, port, false);
3692
3693 if (speed == SPEED_100 || speed == SPEED_10)
3694 ksz_set_100_10mbit(dev, port, speed);
3695}
3696
3697static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3698 bool tx_pause, bool rx_pause)
3699{
3700 const u8 *bitval = dev->info->xmii_ctrl0;
3701 const u32 *masks = dev->info->masks;
3702 const u16 *regs = dev->info->regs;
3703 u8 mask;
3704 u8 val;
3705
3706 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3707 masks[P_MII_RX_FLOW_CTRL];
3708
3709 if (duplex == DUPLEX_FULL)
3710 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3711 else
3712 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3713
3714 if (tx_pause)
3715 val |= masks[P_MII_TX_FLOW_CTRL];
3716
3717 if (rx_pause)
3718 val |= masks[P_MII_RX_FLOW_CTRL];
3719
3720 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3721}
3722
3723static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3724 struct phy_device *phydev,
3725 unsigned int mode,
3726 phy_interface_t interface,
3727 int speed, int duplex, bool tx_pause,
3728 bool rx_pause)
3729{
3730 struct dsa_port *dp = dsa_phylink_to_port(config);
3731 struct ksz_device *dev = dp->ds->priv;
3732 int port = dp->index;
3733 struct ksz_port *p;
3734
3735 p = &dev->ports[port];
3736
3737 /* Internal PHYs */
3738 if (dev->info->internal_phy[port])
3739 return;
3740
3741 p->phydev.speed = speed;
3742
3743 ksz_port_set_xmii_speed(dev, port, speed);
3744
3745 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3746}
3747
3748static int ksz_switch_detect(struct ksz_device *dev)
3749{
3750 u8 id1, id2, id4;
3751 u16 id16;
3752 u32 id32;
3753 int ret;
3754
3755 /* read chip id */
3756 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3757 if (ret)
3758 return ret;
3759
3760 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3761 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3762
3763 switch (id1) {
3764 case KSZ87_FAMILY_ID:
3765 if (id2 == KSZ87_CHIP_ID_95) {
3766 u8 val;
3767
3768 dev->chip_id = KSZ8795_CHIP_ID;
3769
3770 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3771 if (val & KSZ8_PORT_FIBER_MODE)
3772 dev->chip_id = KSZ8765_CHIP_ID;
3773 } else if (id2 == KSZ87_CHIP_ID_94) {
3774 dev->chip_id = KSZ8794_CHIP_ID;
3775 } else {
3776 return -ENODEV;
3777 }
3778 break;
3779 case KSZ88_FAMILY_ID:
3780 if (id2 == KSZ88_CHIP_ID_63)
3781 dev->chip_id = KSZ88X3_CHIP_ID;
3782 else
3783 return -ENODEV;
3784 break;
3785 case KSZ8895_FAMILY_ID:
3786 if (id2 == KSZ8895_CHIP_ID_95 ||
3787 id2 == KSZ8895_CHIP_ID_95R)
3788 dev->chip_id = KSZ8895_CHIP_ID;
3789 else
3790 return -ENODEV;
3791 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4);
3792 if (ret)
3793 return ret;
3794 if (id4 & SW_KSZ8864)
3795 dev->chip_id = KSZ8864_CHIP_ID;
3796 break;
3797 default:
3798 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3799 if (ret)
3800 return ret;
3801
3802 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3803 id32 &= ~0xFF;
3804
3805 switch (id32) {
3806 case KSZ9477_CHIP_ID:
3807 case KSZ9896_CHIP_ID:
3808 case KSZ9897_CHIP_ID:
3809 case KSZ9567_CHIP_ID:
3810 case KSZ8567_CHIP_ID:
3811 case LAN9370_CHIP_ID:
3812 case LAN9371_CHIP_ID:
3813 case LAN9372_CHIP_ID:
3814 case LAN9373_CHIP_ID:
3815 case LAN9374_CHIP_ID:
3816
3817 /* LAN9646 does not have its own chip id. */
3818 if (dev->chip_id != LAN9646_CHIP_ID)
3819 dev->chip_id = id32;
3820 break;
3821 case KSZ9893_CHIP_ID:
3822 ret = ksz_read8(dev, REG_CHIP_ID4,
3823 &id4);
3824 if (ret)
3825 return ret;
3826
3827 if (id4 == SKU_ID_KSZ8563)
3828 dev->chip_id = KSZ8563_CHIP_ID;
3829 else if (id4 == SKU_ID_KSZ9563)
3830 dev->chip_id = KSZ9563_CHIP_ID;
3831 else
3832 dev->chip_id = KSZ9893_CHIP_ID;
3833
3834 break;
3835 default:
3836 dev_err(dev->dev,
3837 "unsupported switch detected %x)\n", id32);
3838 return -ENODEV;
3839 }
3840 }
3841 return 0;
3842}
3843
3844static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3845 struct flow_cls_offload *cls, bool ingress)
3846{
3847 struct ksz_device *dev = ds->priv;
3848
3849 switch (dev->chip_id) {
3850 case KSZ8563_CHIP_ID:
3851 case KSZ8567_CHIP_ID:
3852 case KSZ9477_CHIP_ID:
3853 case KSZ9563_CHIP_ID:
3854 case KSZ9567_CHIP_ID:
3855 case KSZ9893_CHIP_ID:
3856 case KSZ9896_CHIP_ID:
3857 case KSZ9897_CHIP_ID:
3858 case LAN9646_CHIP_ID:
3859 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3860 }
3861
3862 return -EOPNOTSUPP;
3863}
3864
3865static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3866 struct flow_cls_offload *cls, bool ingress)
3867{
3868 struct ksz_device *dev = ds->priv;
3869
3870 switch (dev->chip_id) {
3871 case KSZ8563_CHIP_ID:
3872 case KSZ8567_CHIP_ID:
3873 case KSZ9477_CHIP_ID:
3874 case KSZ9563_CHIP_ID:
3875 case KSZ9567_CHIP_ID:
3876 case KSZ9893_CHIP_ID:
3877 case KSZ9896_CHIP_ID:
3878 case KSZ9897_CHIP_ID:
3879 case LAN9646_CHIP_ID:
3880 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3881 }
3882
3883 return -EOPNOTSUPP;
3884}
3885
3886/* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3887 * is converted to Hex-decimal using the successive multiplication method. On
3888 * every step, integer part is taken and decimal part is carry forwarded.
3889 */
3890static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3891{
3892 u32 cinc = 0;
3893 u32 txrate;
3894 u32 rate;
3895 u8 temp;
3896 u8 i;
3897
3898 txrate = idle_slope - send_slope;
3899
3900 if (!txrate)
3901 return -EINVAL;
3902
3903 rate = idle_slope;
3904
3905 /* 24 bit register */
3906 for (i = 0; i < 6; i++) {
3907 rate = rate * 16;
3908
3909 temp = rate / txrate;
3910
3911 rate %= txrate;
3912
3913 cinc = ((cinc << 4) | temp);
3914 }
3915
3916 *bw = cinc;
3917
3918 return 0;
3919}
3920
3921static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3922 u8 shaper)
3923{
3924 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3925 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3926 FIELD_PREP(MTI_SHAPING_M, shaper));
3927}
3928
3929static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3930 struct tc_cbs_qopt_offload *qopt)
3931{
3932 struct ksz_device *dev = ds->priv;
3933 int ret;
3934 u32 bw;
3935
3936 if (!dev->info->tc_cbs_supported)
3937 return -EOPNOTSUPP;
3938
3939 if (qopt->queue > dev->info->num_tx_queues)
3940 return -EINVAL;
3941
3942 /* Queue Selection */
3943 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3944 if (ret)
3945 return ret;
3946
3947 if (!qopt->enable)
3948 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3949 MTI_SHAPING_OFF);
3950
3951 /* High Credit */
3952 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3953 qopt->hicredit);
3954 if (ret)
3955 return ret;
3956
3957 /* Low Credit */
3958 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3959 qopt->locredit);
3960 if (ret)
3961 return ret;
3962
3963 /* Credit Increment Register */
3964 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3965 if (ret)
3966 return ret;
3967
3968 if (dev->dev_ops->tc_cbs_set_cinc) {
3969 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3970 if (ret)
3971 return ret;
3972 }
3973
3974 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3975 MTI_SHAPING_SRP);
3976}
3977
3978static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3979{
3980 int queue, ret;
3981
3982 /* Configuration will not take effect until the last Port Queue X
3983 * Egress Limit Control Register is written.
3984 */
3985 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3986 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3987 KSZ9477_OUT_RATE_NO_LIMIT);
3988 if (ret)
3989 return ret;
3990 }
3991
3992 return 0;
3993}
3994
3995static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3996 int band)
3997{
3998 /* Compared to queues, bands prioritize packets differently. In strict
3999 * priority mode, the lowest priority is assigned to Queue 0 while the
4000 * highest priority is given to Band 0.
4001 */
4002 return p->bands - 1 - band;
4003}
4004
4005static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
4006{
4007 int ret;
4008
4009 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4010 if (ret)
4011 return ret;
4012
4013 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4014 MTI_SHAPING_OFF);
4015}
4016
4017static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
4018 int weight)
4019{
4020 int ret;
4021
4022 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4023 if (ret)
4024 return ret;
4025
4026 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4027 MTI_SHAPING_OFF);
4028 if (ret)
4029 return ret;
4030
4031 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
4032}
4033
4034static int ksz_tc_ets_add(struct ksz_device *dev, int port,
4035 struct tc_ets_qopt_offload_replace_params *p)
4036{
4037 int ret, band, tc_prio;
4038 u32 queue_map = 0;
4039
4040 /* In order to ensure proper prioritization, it is necessary to set the
4041 * rate limit for the related queue to zero. Otherwise strict priority
4042 * or WRR mode will not work. This is a hardware limitation.
4043 */
4044 ret = ksz_disable_egress_rate_limit(dev, port);
4045 if (ret)
4046 return ret;
4047
4048 /* Configure queue scheduling mode for all bands. Currently only strict
4049 * prio mode is supported.
4050 */
4051 for (band = 0; band < p->bands; band++) {
4052 int queue = ksz_ets_band_to_queue(p, band);
4053
4054 ret = ksz_queue_set_strict(dev, port, queue);
4055 if (ret)
4056 return ret;
4057 }
4058
4059 /* Configure the mapping between traffic classes and queues. Note:
4060 * priomap variable support 16 traffic classes, but the chip can handle
4061 * only 8 classes.
4062 */
4063 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
4064 int queue;
4065
4066 if (tc_prio >= dev->info->num_ipms)
4067 break;
4068
4069 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
4070 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
4071 }
4072
4073 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
4074}
4075
4076static int ksz_tc_ets_del(struct ksz_device *dev, int port)
4077{
4078 int ret, queue;
4079
4080 /* To restore the default chip configuration, set all queues to use the
4081 * WRR scheduler with a weight of 1.
4082 */
4083 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4084 ret = ksz_queue_set_wrr(dev, port, queue,
4085 KSZ9477_DEFAULT_WRR_WEIGHT);
4086 if (ret)
4087 return ret;
4088 }
4089
4090 /* Revert the queue mapping for TC-priority to its default setting on
4091 * the chip.
4092 */
4093 return ksz9477_set_default_prio_queue_mapping(dev, port);
4094}
4095
4096static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
4097 struct tc_ets_qopt_offload_replace_params *p)
4098{
4099 int band;
4100
4101 /* Since it is not feasible to share one port among multiple qdisc,
4102 * the user must configure all available queues appropriately.
4103 */
4104 if (p->bands != dev->info->num_tx_queues) {
4105 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
4106 dev->info->num_tx_queues);
4107 return -EOPNOTSUPP;
4108 }
4109
4110 for (band = 0; band < p->bands; ++band) {
4111 /* The KSZ switches utilize a weighted round robin configuration
4112 * where a certain number of packets can be transmitted from a
4113 * queue before the next queue is serviced. For more information
4114 * on this, refer to section 5.2.8.4 of the KSZ8565R
4115 * documentation on the Port Transmit Queue Control 1 Register.
4116 * However, the current ETS Qdisc implementation (as of February
4117 * 2023) assigns a weight to each queue based on the number of
4118 * bytes or extrapolated bandwidth in percentages. Since this
4119 * differs from the KSZ switches' method and we don't want to
4120 * fake support by converting bytes to packets, it is better to
4121 * return an error instead.
4122 */
4123 if (p->quanta[band]) {
4124 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
4125 return -EOPNOTSUPP;
4126 }
4127 }
4128
4129 return 0;
4130}
4131
4132static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
4133 struct tc_ets_qopt_offload *qopt)
4134{
4135 struct ksz_device *dev = ds->priv;
4136 int ret;
4137
4138 if (is_ksz8(dev))
4139 return -EOPNOTSUPP;
4140
4141 if (qopt->parent != TC_H_ROOT) {
4142 dev_err(dev->dev, "Parent should be \"root\"\n");
4143 return -EOPNOTSUPP;
4144 }
4145
4146 switch (qopt->command) {
4147 case TC_ETS_REPLACE:
4148 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
4149 if (ret)
4150 return ret;
4151
4152 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
4153 case TC_ETS_DESTROY:
4154 return ksz_tc_ets_del(dev, port);
4155 case TC_ETS_STATS:
4156 case TC_ETS_GRAFT:
4157 return -EOPNOTSUPP;
4158 }
4159
4160 return -EOPNOTSUPP;
4161}
4162
4163static int ksz_setup_tc(struct dsa_switch *ds, int port,
4164 enum tc_setup_type type, void *type_data)
4165{
4166 switch (type) {
4167 case TC_SETUP_QDISC_CBS:
4168 return ksz_setup_tc_cbs(ds, port, type_data);
4169 case TC_SETUP_QDISC_ETS:
4170 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
4171 default:
4172 return -EOPNOTSUPP;
4173 }
4174}
4175
4176/**
4177 * ksz_handle_wake_reason - Handle wake reason on a specified port.
4178 * @dev: The device structure.
4179 * @port: The port number.
4180 *
4181 * This function reads the PME (Power Management Event) status register of a
4182 * specified port to determine the wake reason. If there is no wake event, it
4183 * returns early. Otherwise, it logs the wake reason which could be due to a
4184 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
4185 * is then cleared to acknowledge the handling of the wake event.
4186 *
4187 * Return: 0 on success, or an error code on failure.
4188 */
4189int ksz_handle_wake_reason(struct ksz_device *dev, int port)
4190{
4191 const struct ksz_dev_ops *ops = dev->dev_ops;
4192 const u16 *regs = dev->info->regs;
4193 u8 pme_status;
4194 int ret;
4195
4196 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
4197 &pme_status);
4198 if (ret)
4199 return ret;
4200
4201 if (!pme_status)
4202 return 0;
4203
4204 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
4205 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
4206 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
4207 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
4208
4209 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
4210 pme_status);
4211}
4212
4213/**
4214 * ksz_get_wol - Get Wake-on-LAN settings for a specified port.
4215 * @ds: The dsa_switch structure.
4216 * @port: The port number.
4217 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4218 *
4219 * This function checks the device PME wakeup_source flag and chip_id.
4220 * If enabled and supported, it sets the supported and active WoL
4221 * flags.
4222 */
4223static void ksz_get_wol(struct dsa_switch *ds, int port,
4224 struct ethtool_wolinfo *wol)
4225{
4226 struct ksz_device *dev = ds->priv;
4227 const u16 *regs = dev->info->regs;
4228 u8 pme_ctrl;
4229 int ret;
4230
4231 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4232 return;
4233
4234 if (!dev->wakeup_source)
4235 return;
4236
4237 wol->supported = WAKE_PHY;
4238
4239 /* Check if the current MAC address on this port can be set
4240 * as global for WAKE_MAGIC support. The result may vary
4241 * dynamically based on other ports configurations.
4242 */
4243 if (ksz_is_port_mac_global_usable(dev->ds, port))
4244 wol->supported |= WAKE_MAGIC;
4245
4246 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4247 &pme_ctrl);
4248 if (ret)
4249 return;
4250
4251 if (pme_ctrl & PME_WOL_MAGICPKT)
4252 wol->wolopts |= WAKE_MAGIC;
4253 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
4254 wol->wolopts |= WAKE_PHY;
4255}
4256
4257/**
4258 * ksz_set_wol - Set Wake-on-LAN settings for a specified port.
4259 * @ds: The dsa_switch structure.
4260 * @port: The port number.
4261 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4262 *
4263 * This function configures Wake-on-LAN (WoL) settings for a specified
4264 * port. It validates the provided WoL options, checks if PME is
4265 * enabled and supported, clears any previous wake reasons, and sets
4266 * the Magic Packet flag in the port's PME control register if
4267 * specified.
4268 *
4269 * Return: 0 on success, or other error codes on failure.
4270 */
4271static int ksz_set_wol(struct dsa_switch *ds, int port,
4272 struct ethtool_wolinfo *wol)
4273{
4274 u8 pme_ctrl = 0, pme_ctrl_old = 0;
4275 struct ksz_device *dev = ds->priv;
4276 const u16 *regs = dev->info->regs;
4277 bool magic_switched_off;
4278 bool magic_switched_on;
4279 int ret;
4280
4281 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
4282 return -EINVAL;
4283
4284 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4285 return -EOPNOTSUPP;
4286
4287 if (!dev->wakeup_source)
4288 return -EOPNOTSUPP;
4289
4290 ret = ksz_handle_wake_reason(dev, port);
4291 if (ret)
4292 return ret;
4293
4294 if (wol->wolopts & WAKE_MAGIC)
4295 pme_ctrl |= PME_WOL_MAGICPKT;
4296 if (wol->wolopts & WAKE_PHY)
4297 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
4298
4299 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4300 &pme_ctrl_old);
4301 if (ret)
4302 return ret;
4303
4304 if (pme_ctrl_old == pme_ctrl)
4305 return 0;
4306
4307 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
4308 !(pme_ctrl & PME_WOL_MAGICPKT);
4309 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
4310 (pme_ctrl & PME_WOL_MAGICPKT);
4311
4312 /* To keep reference count of MAC address, we should do this
4313 * operation only on change of WOL settings.
4314 */
4315 if (magic_switched_on) {
4316 ret = ksz_switch_macaddr_get(dev->ds, port, NULL);
4317 if (ret)
4318 return ret;
4319 } else if (magic_switched_off) {
4320 ksz_switch_macaddr_put(dev->ds);
4321 }
4322
4323 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
4324 pme_ctrl);
4325 if (ret) {
4326 if (magic_switched_on)
4327 ksz_switch_macaddr_put(dev->ds);
4328 return ret;
4329 }
4330
4331 return 0;
4332}
4333
4334/**
4335 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
4336 * considering Wake-on-LAN (WoL) settings.
4337 * @dev: The switch device structure.
4338 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is
4339 * enabled on any port.
4340 *
4341 * This function prepares the switch device for a safe shutdown while taking
4342 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates
4343 * the wol_enabled flag accordingly to reflect whether WoL is active on any
4344 * port.
4345 */
4346static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled)
4347{
4348 const struct ksz_dev_ops *ops = dev->dev_ops;
4349 const u16 *regs = dev->info->regs;
4350 u8 pme_pin_en = PME_ENABLE;
4351 struct dsa_port *dp;
4352 int ret;
4353
4354 *wol_enabled = false;
4355
4356 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4357 return;
4358
4359 if (!dev->wakeup_source)
4360 return;
4361
4362 dsa_switch_for_each_user_port(dp, dev->ds) {
4363 u8 pme_ctrl = 0;
4364
4365 ret = ops->pme_pread8(dev, dp->index,
4366 regs[REG_PORT_PME_CTRL], &pme_ctrl);
4367 if (!ret && pme_ctrl)
4368 *wol_enabled = true;
4369
4370 /* make sure there are no pending wake events which would
4371 * prevent the device from going to sleep/shutdown.
4372 */
4373 ksz_handle_wake_reason(dev, dp->index);
4374 }
4375
4376 /* Now we are save to enable PME pin. */
4377 if (*wol_enabled) {
4378 if (dev->pme_active_high)
4379 pme_pin_en |= PME_POLARITY;
4380 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
4381 if (ksz_is_ksz87xx(dev))
4382 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
4383 }
4384}
4385
4386static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
4387 const unsigned char *addr)
4388{
4389 struct dsa_port *dp = dsa_to_port(ds, port);
4390 struct ethtool_wolinfo wol;
4391
4392 if (dp->hsr_dev) {
4393 dev_err(ds->dev,
4394 "Cannot change MAC address on port %d with active HSR offload\n",
4395 port);
4396 return -EBUSY;
4397 }
4398
4399 /* Need to initialize variable as the code to fill in settings may
4400 * not be executed.
4401 */
4402 wol.wolopts = 0;
4403
4404 ksz_get_wol(ds, dp->index, &wol);
4405 if (wol.wolopts & WAKE_MAGIC) {
4406 dev_err(ds->dev,
4407 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
4408 port);
4409 return -EBUSY;
4410 }
4411
4412 return 0;
4413}
4414
4415/**
4416 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
4417 * can be used as a global address.
4418 * @ds: Pointer to the DSA switch structure.
4419 * @port: The port number on which the MAC address is to be checked.
4420 *
4421 * This function examines the MAC address set on the specified port and
4422 * determines if it can be used as a global address for the switch.
4423 *
4424 * Return: true if the port's MAC address can be used as a global address, false
4425 * otherwise.
4426 */
4427bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
4428{
4429 struct net_device *user = dsa_to_port(ds, port)->user;
4430 const unsigned char *addr = user->dev_addr;
4431 struct ksz_switch_macaddr *switch_macaddr;
4432 struct ksz_device *dev = ds->priv;
4433
4434 ASSERT_RTNL();
4435
4436 switch_macaddr = dev->switch_macaddr;
4437 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
4438 return false;
4439
4440 return true;
4441}
4442
4443/**
4444 * ksz_switch_macaddr_get - Program the switch's MAC address register.
4445 * @ds: DSA switch instance.
4446 * @port: Port number.
4447 * @extack: Netlink extended acknowledgment.
4448 *
4449 * This function programs the switch's MAC address register with the MAC address
4450 * of the requesting user port. This single address is used by the switch for
4451 * multiple features like HSR self-address filtering and WoL. Other user ports
4452 * can share ownership of this address as long as their MAC address is the same.
4453 * The MAC addresses of user ports must not change while they have ownership of
4454 * the switch MAC address.
4455 *
4456 * Return: 0 on success, or other error codes on failure.
4457 */
4458int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
4459 struct netlink_ext_ack *extack)
4460{
4461 struct net_device *user = dsa_to_port(ds, port)->user;
4462 const unsigned char *addr = user->dev_addr;
4463 struct ksz_switch_macaddr *switch_macaddr;
4464 struct ksz_device *dev = ds->priv;
4465 const u16 *regs = dev->info->regs;
4466 int i, ret;
4467
4468 /* Make sure concurrent MAC address changes are blocked */
4469 ASSERT_RTNL();
4470
4471 switch_macaddr = dev->switch_macaddr;
4472 if (switch_macaddr) {
4473 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
4474 NL_SET_ERR_MSG_FMT_MOD(extack,
4475 "Switch already configured for MAC address %pM",
4476 switch_macaddr->addr);
4477 return -EBUSY;
4478 }
4479
4480 refcount_inc(&switch_macaddr->refcount);
4481 return 0;
4482 }
4483
4484 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
4485 if (!switch_macaddr)
4486 return -ENOMEM;
4487
4488 ether_addr_copy(switch_macaddr->addr, addr);
4489 refcount_set(&switch_macaddr->refcount, 1);
4490 dev->switch_macaddr = switch_macaddr;
4491
4492 /* Program the switch MAC address to hardware */
4493 for (i = 0; i < ETH_ALEN; i++) {
4494 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]);
4495 if (ret)
4496 goto macaddr_drop;
4497 }
4498
4499 return 0;
4500
4501macaddr_drop:
4502 dev->switch_macaddr = NULL;
4503 refcount_set(&switch_macaddr->refcount, 0);
4504 kfree(switch_macaddr);
4505
4506 return ret;
4507}
4508
4509void ksz_switch_macaddr_put(struct dsa_switch *ds)
4510{
4511 struct ksz_switch_macaddr *switch_macaddr;
4512 struct ksz_device *dev = ds->priv;
4513 const u16 *regs = dev->info->regs;
4514 int i;
4515
4516 /* Make sure concurrent MAC address changes are blocked */
4517 ASSERT_RTNL();
4518
4519 switch_macaddr = dev->switch_macaddr;
4520 if (!refcount_dec_and_test(&switch_macaddr->refcount))
4521 return;
4522
4523 for (i = 0; i < ETH_ALEN; i++)
4524 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
4525
4526 dev->switch_macaddr = NULL;
4527 kfree(switch_macaddr);
4528}
4529
4530static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
4531 struct netlink_ext_ack *extack)
4532{
4533 struct ksz_device *dev = ds->priv;
4534 enum hsr_version ver;
4535 int ret;
4536
4537 ret = hsr_get_version(hsr, &ver);
4538 if (ret)
4539 return ret;
4540
4541 if (dev->chip_id != KSZ9477_CHIP_ID) {
4542 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
4543 return -EOPNOTSUPP;
4544 }
4545
4546 /* KSZ9477 can support HW offloading of only 1 HSR device */
4547 if (dev->hsr_dev && hsr != dev->hsr_dev) {
4548 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
4549 return -EOPNOTSUPP;
4550 }
4551
4552 /* KSZ9477 only supports HSR v0 and v1 */
4553 if (!(ver == HSR_V0 || ver == HSR_V1)) {
4554 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
4555 return -EOPNOTSUPP;
4556 }
4557
4558 /* KSZ9477 can only perform HSR offloading for up to two ports */
4559 if (hweight8(dev->hsr_ports) >= 2) {
4560 NL_SET_ERR_MSG_MOD(extack,
4561 "Cannot offload more than two ports - using software HSR");
4562 return -EOPNOTSUPP;
4563 }
4564
4565 /* Self MAC address filtering, to avoid frames traversing
4566 * the HSR ring more than once.
4567 */
4568 ret = ksz_switch_macaddr_get(ds, port, extack);
4569 if (ret)
4570 return ret;
4571
4572 ksz9477_hsr_join(ds, port, hsr);
4573 dev->hsr_dev = hsr;
4574 dev->hsr_ports |= BIT(port);
4575
4576 return 0;
4577}
4578
4579static int ksz_hsr_leave(struct dsa_switch *ds, int port,
4580 struct net_device *hsr)
4581{
4582 struct ksz_device *dev = ds->priv;
4583
4584 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
4585
4586 ksz9477_hsr_leave(ds, port, hsr);
4587 dev->hsr_ports &= ~BIT(port);
4588 if (!dev->hsr_ports)
4589 dev->hsr_dev = NULL;
4590
4591 ksz_switch_macaddr_put(ds);
4592
4593 return 0;
4594}
4595
4596static const struct dsa_switch_ops ksz_switch_ops = {
4597 .get_tag_protocol = ksz_get_tag_protocol,
4598 .connect_tag_protocol = ksz_connect_tag_protocol,
4599 .get_phy_flags = ksz_get_phy_flags,
4600 .setup = ksz_setup,
4601 .teardown = ksz_teardown,
4602 .phy_read = ksz_phy_read16,
4603 .phy_write = ksz_phy_write16,
4604 .phylink_get_caps = ksz_phylink_get_caps,
4605 .port_setup = ksz_port_setup,
4606 .set_ageing_time = ksz_set_ageing_time,
4607 .get_strings = ksz_get_strings,
4608 .get_ethtool_stats = ksz_get_ethtool_stats,
4609 .get_sset_count = ksz_sset_count,
4610 .port_bridge_join = ksz_port_bridge_join,
4611 .port_bridge_leave = ksz_port_bridge_leave,
4612 .port_hsr_join = ksz_hsr_join,
4613 .port_hsr_leave = ksz_hsr_leave,
4614 .port_set_mac_address = ksz_port_set_mac_address,
4615 .port_stp_state_set = ksz_port_stp_state_set,
4616 .port_teardown = ksz_port_teardown,
4617 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
4618 .port_bridge_flags = ksz_port_bridge_flags,
4619 .port_fast_age = ksz_port_fast_age,
4620 .port_vlan_filtering = ksz_port_vlan_filtering,
4621 .port_vlan_add = ksz_port_vlan_add,
4622 .port_vlan_del = ksz_port_vlan_del,
4623 .port_fdb_dump = ksz_port_fdb_dump,
4624 .port_fdb_add = ksz_port_fdb_add,
4625 .port_fdb_del = ksz_port_fdb_del,
4626 .port_mdb_add = ksz_port_mdb_add,
4627 .port_mdb_del = ksz_port_mdb_del,
4628 .port_mirror_add = ksz_port_mirror_add,
4629 .port_mirror_del = ksz_port_mirror_del,
4630 .get_stats64 = ksz_get_stats64,
4631 .get_pause_stats = ksz_get_pause_stats,
4632 .port_change_mtu = ksz_change_mtu,
4633 .port_max_mtu = ksz_max_mtu,
4634 .get_wol = ksz_get_wol,
4635 .set_wol = ksz_set_wol,
4636 .get_ts_info = ksz_get_ts_info,
4637 .port_hwtstamp_get = ksz_hwtstamp_get,
4638 .port_hwtstamp_set = ksz_hwtstamp_set,
4639 .port_txtstamp = ksz_port_txtstamp,
4640 .port_rxtstamp = ksz_port_rxtstamp,
4641 .cls_flower_add = ksz_cls_flower_add,
4642 .cls_flower_del = ksz_cls_flower_del,
4643 .port_setup_tc = ksz_setup_tc,
4644 .get_mac_eee = ksz_get_mac_eee,
4645 .set_mac_eee = ksz_set_mac_eee,
4646 .port_get_default_prio = ksz_port_get_default_prio,
4647 .port_set_default_prio = ksz_port_set_default_prio,
4648 .port_get_dscp_prio = ksz_port_get_dscp_prio,
4649 .port_add_dscp_prio = ksz_port_add_dscp_prio,
4650 .port_del_dscp_prio = ksz_port_del_dscp_prio,
4651 .port_get_apptrust = ksz_port_get_apptrust,
4652 .port_set_apptrust = ksz_port_set_apptrust,
4653};
4654
4655struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
4656{
4657 struct dsa_switch *ds;
4658 struct ksz_device *swdev;
4659
4660 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
4661 if (!ds)
4662 return NULL;
4663
4664 ds->dev = base;
4665 ds->num_ports = DSA_MAX_PORTS;
4666 ds->ops = &ksz_switch_ops;
4667
4668 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
4669 if (!swdev)
4670 return NULL;
4671
4672 ds->priv = swdev;
4673 swdev->dev = base;
4674
4675 swdev->ds = ds;
4676 swdev->priv = priv;
4677
4678 return swdev;
4679}
4680EXPORT_SYMBOL(ksz_switch_alloc);
4681
4682/**
4683 * ksz_switch_shutdown - Shutdown routine for the switch device.
4684 * @dev: The switch device structure.
4685 *
4686 * This function is responsible for initiating a shutdown sequence for the
4687 * switch device. It invokes the reset operation defined in the device
4688 * operations, if available, to reset the switch. Subsequently, it calls the
4689 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
4690 * switch.
4691 */
4692void ksz_switch_shutdown(struct ksz_device *dev)
4693{
4694 bool wol_enabled = false;
4695
4696 ksz_wol_pre_shutdown(dev, &wol_enabled);
4697
4698 if (dev->dev_ops->reset && !wol_enabled)
4699 dev->dev_ops->reset(dev);
4700
4701 dsa_switch_shutdown(dev->ds);
4702}
4703EXPORT_SYMBOL(ksz_switch_shutdown);
4704
4705static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
4706 struct device_node *port_dn)
4707{
4708 phy_interface_t phy_mode = dev->ports[port_num].interface;
4709 int rx_delay = -1, tx_delay = -1;
4710
4711 if (!phy_interface_mode_is_rgmii(phy_mode))
4712 return;
4713
4714 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
4715 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
4716
4717 if (rx_delay == -1 && tx_delay == -1) {
4718 dev_warn(dev->dev,
4719 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
4720 "please update device tree to specify \"rx-internal-delay-ps\" and "
4721 "\"tx-internal-delay-ps\"",
4722 port_num);
4723
4724 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
4725 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4726 rx_delay = 2000;
4727
4728 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
4729 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4730 tx_delay = 2000;
4731 }
4732
4733 if (rx_delay < 0)
4734 rx_delay = 0;
4735 if (tx_delay < 0)
4736 tx_delay = 0;
4737
4738 dev->ports[port_num].rgmii_rx_val = rx_delay;
4739 dev->ports[port_num].rgmii_tx_val = tx_delay;
4740}
4741
4742/**
4743 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
4744 * register value.
4745 * @array: The array of drive strength values to search.
4746 * @array_size: The size of the array.
4747 * @microamp: The drive strength value in microamp to be converted.
4748 *
4749 * This function searches the array of drive strength values for the given
4750 * microamp value and returns the corresponding register value for that drive.
4751 *
4752 * Returns: If found, the corresponding register value for that drive strength
4753 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
4754 */
4755static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
4756 size_t array_size, int microamp)
4757{
4758 int i;
4759
4760 for (i = 0; i < array_size; i++) {
4761 if (array[i].microamp == microamp)
4762 return array[i].reg_val;
4763 }
4764
4765 return -EINVAL;
4766}
4767
4768/**
4769 * ksz_drive_strength_error() - Report invalid drive strength value
4770 * @dev: ksz device
4771 * @array: The array of drive strength values to search.
4772 * @array_size: The size of the array.
4773 * @microamp: Invalid drive strength value in microamp
4774 *
4775 * This function logs an error message when an unsupported drive strength value
4776 * is detected. It lists out all the supported drive strength values for
4777 * reference in the error message.
4778 */
4779static void ksz_drive_strength_error(struct ksz_device *dev,
4780 const struct ksz_drive_strength *array,
4781 size_t array_size, int microamp)
4782{
4783 char supported_values[100];
4784 size_t remaining_size;
4785 int added_len;
4786 char *ptr;
4787 int i;
4788
4789 remaining_size = sizeof(supported_values);
4790 ptr = supported_values;
4791
4792 for (i = 0; i < array_size; i++) {
4793 added_len = snprintf(ptr, remaining_size,
4794 i == 0 ? "%d" : ", %d", array[i].microamp);
4795
4796 if (added_len >= remaining_size)
4797 break;
4798
4799 ptr += added_len;
4800 remaining_size -= added_len;
4801 }
4802
4803 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
4804 microamp, supported_values);
4805}
4806
4807/**
4808 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
4809 * chip variants.
4810 * @dev: ksz device
4811 * @props: Array of drive strength properties to be applied
4812 * @num_props: Number of properties in the array
4813 *
4814 * This function configures the drive strength for various KSZ9477 chip variants
4815 * based on the provided properties. It handles chip-specific nuances and
4816 * ensures only valid drive strengths are written to the respective chip.
4817 *
4818 * Return: 0 on successful configuration, a negative error code on failure.
4819 */
4820static int ksz9477_drive_strength_write(struct ksz_device *dev,
4821 struct ksz_driver_strength_prop *props,
4822 int num_props)
4823{
4824 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
4825 int i, ret, reg;
4826 u8 mask = 0;
4827 u8 val = 0;
4828
4829 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
4830 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4831 props[KSZ_DRIVER_STRENGTH_IO].name);
4832
4833 if (dev->chip_id == KSZ8795_CHIP_ID ||
4834 dev->chip_id == KSZ8794_CHIP_ID ||
4835 dev->chip_id == KSZ8765_CHIP_ID)
4836 reg = KSZ8795_REG_SW_CTRL_20;
4837 else
4838 reg = KSZ9477_REG_SW_IO_STRENGTH;
4839
4840 for (i = 0; i < num_props; i++) {
4841 if (props[i].value == -1)
4842 continue;
4843
4844 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
4845 array_size, props[i].value);
4846 if (ret < 0) {
4847 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
4848 array_size, props[i].value);
4849 return ret;
4850 }
4851
4852 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
4853 val |= ret << props[i].offset;
4854 }
4855
4856 return ksz_rmw8(dev, reg, mask, val);
4857}
4858
4859/**
4860 * ksz88x3_drive_strength_write() - Set the drive strength configuration for
4861 * KSZ8863 compatible chip variants.
4862 * @dev: ksz device
4863 * @props: Array of drive strength properties to be set
4864 * @num_props: Number of properties in the array
4865 *
4866 * This function applies the specified drive strength settings to KSZ88X3 chip
4867 * variants (KSZ8873, KSZ8863).
4868 * It ensures the configurations align with what the chip variant supports and
4869 * warns or errors out on unsupported settings.
4870 *
4871 * Return: 0 on success, error code otherwise
4872 */
4873static int ksz88x3_drive_strength_write(struct ksz_device *dev,
4874 struct ksz_driver_strength_prop *props,
4875 int num_props)
4876{
4877 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
4878 int microamp;
4879 int i, ret;
4880
4881 for (i = 0; i < num_props; i++) {
4882 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
4883 continue;
4884
4885 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4886 props[i].name);
4887 }
4888
4889 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
4890 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size,
4891 microamp);
4892 if (ret < 0) {
4893 ksz_drive_strength_error(dev, ksz88x3_drive_strengths,
4894 array_size, microamp);
4895 return ret;
4896 }
4897
4898 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
4899 KSZ8873_DRIVE_STRENGTH_16MA, ret);
4900}
4901
4902/**
4903 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
4904 * from device tree properties.
4905 * @dev: ksz device
4906 *
4907 * This function reads the specified drive strength properties from the
4908 * device tree, validates against the supported chip variants, and sets
4909 * them accordingly. An error should be critical here, as the drive strength
4910 * settings are crucial for EMI compliance.
4911 *
4912 * Return: 0 on success, error code otherwise
4913 */
4914static int ksz_parse_drive_strength(struct ksz_device *dev)
4915{
4916 struct ksz_driver_strength_prop of_props[] = {
4917 [KSZ_DRIVER_STRENGTH_HI] = {
4918 .name = "microchip,hi-drive-strength-microamp",
4919 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
4920 .value = -1,
4921 },
4922 [KSZ_DRIVER_STRENGTH_LO] = {
4923 .name = "microchip,lo-drive-strength-microamp",
4924 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
4925 .value = -1,
4926 },
4927 [KSZ_DRIVER_STRENGTH_IO] = {
4928 .name = "microchip,io-drive-strength-microamp",
4929 .offset = 0, /* don't care */
4930 .value = -1,
4931 },
4932 };
4933 struct device_node *np = dev->dev->of_node;
4934 bool have_any_prop = false;
4935 int i, ret;
4936
4937 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4938 ret = of_property_read_u32(np, of_props[i].name,
4939 &of_props[i].value);
4940 if (ret && ret != -EINVAL)
4941 dev_warn(dev->dev, "Failed to read %s\n",
4942 of_props[i].name);
4943 if (ret)
4944 continue;
4945
4946 have_any_prop = true;
4947 }
4948
4949 if (!have_any_prop)
4950 return 0;
4951
4952 switch (dev->chip_id) {
4953 case KSZ88X3_CHIP_ID:
4954 return ksz88x3_drive_strength_write(dev, of_props,
4955 ARRAY_SIZE(of_props));
4956 case KSZ8795_CHIP_ID:
4957 case KSZ8794_CHIP_ID:
4958 case KSZ8765_CHIP_ID:
4959 case KSZ8563_CHIP_ID:
4960 case KSZ8567_CHIP_ID:
4961 case KSZ9477_CHIP_ID:
4962 case KSZ9563_CHIP_ID:
4963 case KSZ9567_CHIP_ID:
4964 case KSZ9893_CHIP_ID:
4965 case KSZ9896_CHIP_ID:
4966 case KSZ9897_CHIP_ID:
4967 case LAN9646_CHIP_ID:
4968 return ksz9477_drive_strength_write(dev, of_props,
4969 ARRAY_SIZE(of_props));
4970 default:
4971 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4972 if (of_props[i].value == -1)
4973 continue;
4974
4975 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4976 of_props[i].name);
4977 }
4978 }
4979
4980 return 0;
4981}
4982
4983int ksz_switch_register(struct ksz_device *dev)
4984{
4985 const struct ksz_chip_data *info;
4986 struct device_node *ports;
4987 phy_interface_t interface;
4988 unsigned int port_num;
4989 int ret;
4990 int i;
4991
4992 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
4993 GPIOD_OUT_LOW);
4994 if (IS_ERR(dev->reset_gpio))
4995 return PTR_ERR(dev->reset_gpio);
4996
4997 if (dev->reset_gpio) {
4998 gpiod_set_value_cansleep(dev->reset_gpio, 1);
4999 usleep_range(10000, 12000);
5000 gpiod_set_value_cansleep(dev->reset_gpio, 0);
5001 msleep(100);
5002 }
5003
5004 mutex_init(&dev->dev_mutex);
5005 mutex_init(&dev->regmap_mutex);
5006 mutex_init(&dev->alu_mutex);
5007 mutex_init(&dev->vlan_mutex);
5008
5009 ret = ksz_switch_detect(dev);
5010 if (ret)
5011 return ret;
5012
5013 info = ksz_lookup_info(dev->chip_id);
5014 if (!info)
5015 return -ENODEV;
5016
5017 /* Update the compatible info with the probed one */
5018 dev->info = info;
5019
5020 dev_info(dev->dev, "found switch: %s, rev %i\n",
5021 dev->info->dev_name, dev->chip_rev);
5022
5023 ret = ksz_check_device_id(dev);
5024 if (ret)
5025 return ret;
5026
5027 dev->dev_ops = dev->info->ops;
5028
5029 ret = dev->dev_ops->init(dev);
5030 if (ret)
5031 return ret;
5032
5033 dev->ports = devm_kzalloc(dev->dev,
5034 dev->info->port_cnt * sizeof(struct ksz_port),
5035 GFP_KERNEL);
5036 if (!dev->ports)
5037 return -ENOMEM;
5038
5039 for (i = 0; i < dev->info->port_cnt; i++) {
5040 spin_lock_init(&dev->ports[i].mib.stats64_lock);
5041 mutex_init(&dev->ports[i].mib.cnt_mutex);
5042 dev->ports[i].mib.counters =
5043 devm_kzalloc(dev->dev,
5044 sizeof(u64) * (dev->info->mib_cnt + 1),
5045 GFP_KERNEL);
5046 if (!dev->ports[i].mib.counters)
5047 return -ENOMEM;
5048
5049 dev->ports[i].ksz_dev = dev;
5050 dev->ports[i].num = i;
5051 }
5052
5053 /* set the real number of ports */
5054 dev->ds->num_ports = dev->info->port_cnt;
5055
5056 /* set the phylink ops */
5057 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
5058
5059 /* Host port interface will be self detected, or specifically set in
5060 * device tree.
5061 */
5062 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
5063 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
5064 if (dev->dev->of_node) {
5065 ret = of_get_phy_mode(dev->dev->of_node, &interface);
5066 if (ret == 0)
5067 dev->compat_interface = interface;
5068 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
5069 if (!ports)
5070 ports = of_get_child_by_name(dev->dev->of_node, "ports");
5071 if (ports) {
5072 for_each_available_child_of_node_scoped(ports, port) {
5073 if (of_property_read_u32(port, "reg",
5074 &port_num))
5075 continue;
5076 if (!(dev->port_mask & BIT(port_num))) {
5077 of_node_put(ports);
5078 return -EINVAL;
5079 }
5080 of_get_phy_mode(port,
5081 &dev->ports[port_num].interface);
5082
5083 ksz_parse_rgmii_delay(dev, port_num, port);
5084 }
5085 of_node_put(ports);
5086 }
5087 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
5088 "microchip,synclko-125");
5089 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
5090 "microchip,synclko-disable");
5091 if (dev->synclko_125 && dev->synclko_disable) {
5092 dev_err(dev->dev, "inconsistent synclko settings\n");
5093 return -EINVAL;
5094 }
5095
5096 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
5097 "wakeup-source");
5098 dev->pme_active_high = of_property_read_bool(dev->dev->of_node,
5099 "microchip,pme-active-high");
5100 }
5101
5102 ret = dsa_register_switch(dev->ds);
5103 if (ret) {
5104 dev->dev_ops->exit(dev);
5105 return ret;
5106 }
5107
5108 /* Read MIB counters every 30 seconds to avoid overflow. */
5109 dev->mib_read_interval = msecs_to_jiffies(5000);
5110
5111 /* Start the MIB timer. */
5112 schedule_delayed_work(&dev->mib_read, 0);
5113
5114 return ret;
5115}
5116EXPORT_SYMBOL(ksz_switch_register);
5117
5118void ksz_switch_remove(struct ksz_device *dev)
5119{
5120 /* timer started */
5121 if (dev->mib_read_interval) {
5122 dev->mib_read_interval = 0;
5123 cancel_delayed_work_sync(&dev->mib_read);
5124 }
5125
5126 dev->dev_ops->exit(dev);
5127 dsa_unregister_switch(dev->ds);
5128
5129 if (dev->reset_gpio)
5130 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5131
5132}
5133EXPORT_SYMBOL(ksz_switch_remove);
5134
5135MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
5136MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
5137MODULE_LICENSE("GPL");
1/*
2 * Microchip switch driver main logic
3 *
4 * Copyright (C) 2017
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#include <linux/delay.h>
20#include <linux/export.h>
21#include <linux/gpio.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_data/microchip-ksz.h>
25#include <linux/phy.h>
26#include <linux/etherdevice.h>
27#include <linux/if_bridge.h>
28#include <net/dsa.h>
29#include <net/switchdev.h>
30
31#include "ksz_priv.h"
32
33static const struct {
34 int index;
35 char string[ETH_GSTRING_LEN];
36} mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
37 { 0x00, "rx_hi" },
38 { 0x01, "rx_undersize" },
39 { 0x02, "rx_fragments" },
40 { 0x03, "rx_oversize" },
41 { 0x04, "rx_jabbers" },
42 { 0x05, "rx_symbol_err" },
43 { 0x06, "rx_crc_err" },
44 { 0x07, "rx_align_err" },
45 { 0x08, "rx_mac_ctrl" },
46 { 0x09, "rx_pause" },
47 { 0x0A, "rx_bcast" },
48 { 0x0B, "rx_mcast" },
49 { 0x0C, "rx_ucast" },
50 { 0x0D, "rx_64_or_less" },
51 { 0x0E, "rx_65_127" },
52 { 0x0F, "rx_128_255" },
53 { 0x10, "rx_256_511" },
54 { 0x11, "rx_512_1023" },
55 { 0x12, "rx_1024_1522" },
56 { 0x13, "rx_1523_2000" },
57 { 0x14, "rx_2001" },
58 { 0x15, "tx_hi" },
59 { 0x16, "tx_late_col" },
60 { 0x17, "tx_pause" },
61 { 0x18, "tx_bcast" },
62 { 0x19, "tx_mcast" },
63 { 0x1A, "tx_ucast" },
64 { 0x1B, "tx_deferred" },
65 { 0x1C, "tx_total_col" },
66 { 0x1D, "tx_exc_col" },
67 { 0x1E, "tx_single_col" },
68 { 0x1F, "tx_mult_col" },
69 { 0x80, "rx_total" },
70 { 0x81, "tx_total" },
71 { 0x82, "rx_discards" },
72 { 0x83, "tx_discards" },
73};
74
75static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
76{
77 u8 data;
78
79 ksz_read8(dev, addr, &data);
80 if (set)
81 data |= bits;
82 else
83 data &= ~bits;
84 ksz_write8(dev, addr, data);
85}
86
87static void ksz_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
88{
89 u32 data;
90
91 ksz_read32(dev, addr, &data);
92 if (set)
93 data |= bits;
94 else
95 data &= ~bits;
96 ksz_write32(dev, addr, data);
97}
98
99static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
100 bool set)
101{
102 u32 addr;
103 u8 data;
104
105 addr = PORT_CTRL_ADDR(port, offset);
106 ksz_read8(dev, addr, &data);
107
108 if (set)
109 data |= bits;
110 else
111 data &= ~bits;
112
113 ksz_write8(dev, addr, data);
114}
115
116static void ksz_port_cfg32(struct ksz_device *dev, int port, int offset,
117 u32 bits, bool set)
118{
119 u32 addr;
120 u32 data;
121
122 addr = PORT_CTRL_ADDR(port, offset);
123 ksz_read32(dev, addr, &data);
124
125 if (set)
126 data |= bits;
127 else
128 data &= ~bits;
129
130 ksz_write32(dev, addr, data);
131}
132
133static int wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, int timeout)
134{
135 u8 data;
136
137 do {
138 ksz_read8(dev, REG_SW_VLAN_CTRL, &data);
139 if (!(data & waiton))
140 break;
141 usleep_range(1, 10);
142 } while (timeout-- > 0);
143
144 if (timeout <= 0)
145 return -ETIMEDOUT;
146
147 return 0;
148}
149
150static int get_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table)
151{
152 struct ksz_device *dev = ds->priv;
153 int ret;
154
155 mutex_lock(&dev->vlan_mutex);
156
157 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
158 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
159
160 /* wait to be cleared */
161 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
162 if (ret < 0) {
163 dev_dbg(dev->dev, "Failed to read vlan table\n");
164 goto exit;
165 }
166
167 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
168 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
169 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
170
171 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
172
173exit:
174 mutex_unlock(&dev->vlan_mutex);
175
176 return ret;
177}
178
179static int set_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table)
180{
181 struct ksz_device *dev = ds->priv;
182 int ret;
183
184 mutex_lock(&dev->vlan_mutex);
185
186 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
187 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
188 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
189
190 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
191 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
192
193 /* wait to be cleared */
194 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
195 if (ret < 0) {
196 dev_dbg(dev->dev, "Failed to write vlan table\n");
197 goto exit;
198 }
199
200 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
201
202 /* update vlan cache table */
203 dev->vlan_cache[vid].table[0] = vlan_table[0];
204 dev->vlan_cache[vid].table[1] = vlan_table[1];
205 dev->vlan_cache[vid].table[2] = vlan_table[2];
206
207exit:
208 mutex_unlock(&dev->vlan_mutex);
209
210 return ret;
211}
212
213static void read_table(struct dsa_switch *ds, u32 *table)
214{
215 struct ksz_device *dev = ds->priv;
216
217 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
218 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
219 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
220 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
221}
222
223static void write_table(struct dsa_switch *ds, u32 *table)
224{
225 struct ksz_device *dev = ds->priv;
226
227 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
228 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
229 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
230 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
231}
232
233static int wait_alu_ready(struct ksz_device *dev, u32 waiton, int timeout)
234{
235 u32 data;
236
237 do {
238 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
239 if (!(data & waiton))
240 break;
241 usleep_range(1, 10);
242 } while (timeout-- > 0);
243
244 if (timeout <= 0)
245 return -ETIMEDOUT;
246
247 return 0;
248}
249
250static int wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, int timeout)
251{
252 u32 data;
253
254 do {
255 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data);
256 if (!(data & waiton))
257 break;
258 usleep_range(1, 10);
259 } while (timeout-- > 0);
260
261 if (timeout <= 0)
262 return -ETIMEDOUT;
263
264 return 0;
265}
266
267static int ksz_reset_switch(struct dsa_switch *ds)
268{
269 struct ksz_device *dev = ds->priv;
270 u8 data8;
271 u16 data16;
272 u32 data32;
273
274 /* reset switch */
275 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
276
277 /* turn off SPI DO Edge select */
278 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
279 data8 &= ~SPI_AUTO_EDGE_DETECTION;
280 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
281
282 /* default configuration */
283 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
284 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
285 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
286 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
287
288 /* disable interrupts */
289 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
290 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
291 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
292
293 /* set broadcast storm protection 10% rate */
294 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16);
295 data16 &= ~BROADCAST_STORM_RATE;
296 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
297 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16);
298
299 return 0;
300}
301
302static void port_setup(struct ksz_device *dev, int port, bool cpu_port)
303{
304 u8 data8;
305 u16 data16;
306
307 /* enable tag tail for host port */
308 if (cpu_port)
309 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
310 true);
311
312 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
313
314 /* set back pressure */
315 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
316
317 /* set flow control */
318 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
319 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, true);
320
321 /* enable broadcast storm limit */
322 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
323
324 /* disable DiffServ priority */
325 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
326
327 /* replace priority */
328 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
329 false);
330 ksz_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
331 MTI_PVID_REPLACE, false);
332
333 /* enable 802.1p priority */
334 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
335
336 /* configure MAC to 1G & RGMII mode */
337 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
338 data8 |= PORT_RGMII_ID_EG_ENABLE;
339 data8 &= ~PORT_MII_NOT_1GBIT;
340 data8 &= ~PORT_MII_SEL_M;
341 data8 |= PORT_RGMII_SEL;
342 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
343
344 /* clear pending interrupts */
345 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
346}
347
348static void ksz_config_cpu_port(struct dsa_switch *ds)
349{
350 struct ksz_device *dev = ds->priv;
351 int i;
352
353 ds->num_ports = dev->port_cnt;
354
355 for (i = 0; i < ds->num_ports; i++) {
356 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
357 dev->cpu_port = i;
358
359 /* enable cpu port */
360 port_setup(dev, i, true);
361 }
362 }
363}
364
365static int ksz_setup(struct dsa_switch *ds)
366{
367 struct ksz_device *dev = ds->priv;
368 int ret = 0;
369
370 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
371 dev->num_vlans, GFP_KERNEL);
372 if (!dev->vlan_cache)
373 return -ENOMEM;
374
375 ret = ksz_reset_switch(ds);
376 if (ret) {
377 dev_err(ds->dev, "failed to reset switch\n");
378 return ret;
379 }
380
381 /* accept packet up to 2000bytes */
382 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
383
384 ksz_config_cpu_port(ds);
385
386 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
387
388 /* queue based egress rate limit */
389 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
390
391 /* start switch */
392 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
393
394 return 0;
395}
396
397static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
398 int port)
399{
400 return DSA_TAG_PROTO_KSZ;
401}
402
403static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
404{
405 struct ksz_device *dev = ds->priv;
406 u16 val = 0;
407
408 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
409
410 return val;
411}
412
413static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
414{
415 struct ksz_device *dev = ds->priv;
416
417 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
418
419 return 0;
420}
421
422static int ksz_enable_port(struct dsa_switch *ds, int port,
423 struct phy_device *phy)
424{
425 struct ksz_device *dev = ds->priv;
426
427 /* setup slave port */
428 port_setup(dev, port, false);
429
430 return 0;
431}
432
433static void ksz_disable_port(struct dsa_switch *ds, int port,
434 struct phy_device *phy)
435{
436 struct ksz_device *dev = ds->priv;
437
438 /* there is no port disable */
439 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, true);
440}
441
442static int ksz_sset_count(struct dsa_switch *ds, int port)
443{
444 return TOTAL_SWITCH_COUNTER_NUM;
445}
446
447static void ksz_get_strings(struct dsa_switch *ds, int port, uint8_t *buf)
448{
449 int i;
450
451 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
452 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string,
453 ETH_GSTRING_LEN);
454 }
455}
456
457static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
458 uint64_t *buf)
459{
460 struct ksz_device *dev = ds->priv;
461 int i;
462 u32 data;
463 int timeout;
464
465 mutex_lock(&dev->stats_mutex);
466
467 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
468 data = MIB_COUNTER_READ;
469 data |= ((mib_names[i].index & 0xFF) << MIB_COUNTER_INDEX_S);
470 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
471
472 timeout = 1000;
473 do {
474 ksz_pread32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
475 &data);
476 usleep_range(1, 10);
477 if (!(data & MIB_COUNTER_READ))
478 break;
479 } while (timeout-- > 0);
480
481 /* failed to read MIB. get out of loop */
482 if (!timeout) {
483 dev_dbg(dev->dev, "Failed to get MIB\n");
484 break;
485 }
486
487 /* count resets upon read */
488 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
489
490 dev->mib_value[i] += (uint64_t)data;
491 buf[i] = dev->mib_value[i];
492 }
493
494 mutex_unlock(&dev->stats_mutex);
495}
496
497static void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
498{
499 struct ksz_device *dev = ds->priv;
500 u8 data;
501
502 ksz_pread8(dev, port, P_STP_CTRL, &data);
503 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
504
505 switch (state) {
506 case BR_STATE_DISABLED:
507 data |= PORT_LEARN_DISABLE;
508 break;
509 case BR_STATE_LISTENING:
510 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
511 break;
512 case BR_STATE_LEARNING:
513 data |= PORT_RX_ENABLE;
514 break;
515 case BR_STATE_FORWARDING:
516 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
517 break;
518 case BR_STATE_BLOCKING:
519 data |= PORT_LEARN_DISABLE;
520 break;
521 default:
522 dev_err(ds->dev, "invalid STP state: %d\n", state);
523 return;
524 }
525
526 ksz_pwrite8(dev, port, P_STP_CTRL, data);
527}
528
529static void ksz_port_fast_age(struct dsa_switch *ds, int port)
530{
531 struct ksz_device *dev = ds->priv;
532 u8 data8;
533
534 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
535 data8 |= SW_FAST_AGING;
536 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
537
538 data8 &= ~SW_FAST_AGING;
539 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
540}
541
542static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag)
543{
544 struct ksz_device *dev = ds->priv;
545
546 if (flag) {
547 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
548 PORT_VLAN_LOOKUP_VID_0, true);
549 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, true);
550 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
551 } else {
552 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
553 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, false);
554 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
555 PORT_VLAN_LOOKUP_VID_0, false);
556 }
557
558 return 0;
559}
560
561static int ksz_port_vlan_prepare(struct dsa_switch *ds, int port,
562 const struct switchdev_obj_port_vlan *vlan)
563{
564 /* nothing needed */
565
566 return 0;
567}
568
569static void ksz_port_vlan_add(struct dsa_switch *ds, int port,
570 const struct switchdev_obj_port_vlan *vlan)
571{
572 struct ksz_device *dev = ds->priv;
573 u32 vlan_table[3];
574 u16 vid;
575 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
576
577 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
578 if (get_vlan_table(ds, vid, vlan_table)) {
579 dev_dbg(dev->dev, "Failed to get vlan table\n");
580 return;
581 }
582
583 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
584 if (untagged)
585 vlan_table[1] |= BIT(port);
586 else
587 vlan_table[1] &= ~BIT(port);
588 vlan_table[1] &= ~(BIT(dev->cpu_port));
589
590 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
591
592 if (set_vlan_table(ds, vid, vlan_table)) {
593 dev_dbg(dev->dev, "Failed to set vlan table\n");
594 return;
595 }
596
597 /* change PVID */
598 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
599 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
600 }
601}
602
603static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
604 const struct switchdev_obj_port_vlan *vlan)
605{
606 struct ksz_device *dev = ds->priv;
607 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
608 u32 vlan_table[3];
609 u16 vid;
610 u16 pvid;
611
612 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
613 pvid = pvid & 0xFFF;
614
615 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
616 if (get_vlan_table(ds, vid, vlan_table)) {
617 dev_dbg(dev->dev, "Failed to get vlan table\n");
618 return -ETIMEDOUT;
619 }
620
621 vlan_table[2] &= ~BIT(port);
622
623 if (pvid == vid)
624 pvid = 1;
625
626 if (untagged)
627 vlan_table[1] &= ~BIT(port);
628
629 if (set_vlan_table(ds, vid, vlan_table)) {
630 dev_dbg(dev->dev, "Failed to set vlan table\n");
631 return -ETIMEDOUT;
632 }
633 }
634
635 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
636
637 return 0;
638}
639
640struct alu_struct {
641 /* entry 1 */
642 u8 is_static:1;
643 u8 is_src_filter:1;
644 u8 is_dst_filter:1;
645 u8 prio_age:3;
646 u32 _reserv_0_1:23;
647 u8 mstp:3;
648 /* entry 2 */
649 u8 is_override:1;
650 u8 is_use_fid:1;
651 u32 _reserv_1_1:23;
652 u8 port_forward:7;
653 /* entry 3 & 4*/
654 u32 _reserv_2_1:9;
655 u8 fid:7;
656 u8 mac[ETH_ALEN];
657};
658
659static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
660 const unsigned char *addr, u16 vid)
661{
662 struct ksz_device *dev = ds->priv;
663 u32 alu_table[4];
664 u32 data;
665 int ret = 0;
666
667 mutex_lock(&dev->alu_mutex);
668
669 /* find any entry with mac & vid */
670 data = vid << ALU_FID_INDEX_S;
671 data |= ((addr[0] << 8) | addr[1]);
672 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
673
674 data = ((addr[2] << 24) | (addr[3] << 16));
675 data |= ((addr[4] << 8) | addr[5]);
676 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
677
678 /* start read operation */
679 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
680
681 /* wait to be finished */
682 ret = wait_alu_ready(dev, ALU_START, 1000);
683 if (ret < 0) {
684 dev_dbg(dev->dev, "Failed to read ALU\n");
685 goto exit;
686 }
687
688 /* read ALU entry */
689 read_table(ds, alu_table);
690
691 /* update ALU entry */
692 alu_table[0] = ALU_V_STATIC_VALID;
693 alu_table[1] |= BIT(port);
694 if (vid)
695 alu_table[1] |= ALU_V_USE_FID;
696 alu_table[2] = (vid << ALU_V_FID_S);
697 alu_table[2] |= ((addr[0] << 8) | addr[1]);
698 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
699 alu_table[3] |= ((addr[4] << 8) | addr[5]);
700
701 write_table(ds, alu_table);
702
703 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
704
705 /* wait to be finished */
706 ret = wait_alu_ready(dev, ALU_START, 1000);
707 if (ret < 0)
708 dev_dbg(dev->dev, "Failed to write ALU\n");
709
710exit:
711 mutex_unlock(&dev->alu_mutex);
712
713 return ret;
714}
715
716static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
717 const unsigned char *addr, u16 vid)
718{
719 struct ksz_device *dev = ds->priv;
720 u32 alu_table[4];
721 u32 data;
722 int ret = 0;
723
724 mutex_lock(&dev->alu_mutex);
725
726 /* read any entry with mac & vid */
727 data = vid << ALU_FID_INDEX_S;
728 data |= ((addr[0] << 8) | addr[1]);
729 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
730
731 data = ((addr[2] << 24) | (addr[3] << 16));
732 data |= ((addr[4] << 8) | addr[5]);
733 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
734
735 /* start read operation */
736 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
737
738 /* wait to be finished */
739 ret = wait_alu_ready(dev, ALU_START, 1000);
740 if (ret < 0) {
741 dev_dbg(dev->dev, "Failed to read ALU\n");
742 goto exit;
743 }
744
745 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
746 if (alu_table[0] & ALU_V_STATIC_VALID) {
747 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
748 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
749 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
750
751 /* clear forwarding port */
752 alu_table[2] &= ~BIT(port);
753
754 /* if there is no port to forward, clear table */
755 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
756 alu_table[0] = 0;
757 alu_table[1] = 0;
758 alu_table[2] = 0;
759 alu_table[3] = 0;
760 }
761 } else {
762 alu_table[0] = 0;
763 alu_table[1] = 0;
764 alu_table[2] = 0;
765 alu_table[3] = 0;
766 }
767
768 write_table(ds, alu_table);
769
770 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
771
772 /* wait to be finished */
773 ret = wait_alu_ready(dev, ALU_START, 1000);
774 if (ret < 0)
775 dev_dbg(dev->dev, "Failed to write ALU\n");
776
777exit:
778 mutex_unlock(&dev->alu_mutex);
779
780 return ret;
781}
782
783static void convert_alu(struct alu_struct *alu, u32 *alu_table)
784{
785 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
786 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
787 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
788 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
789 ALU_V_PRIO_AGE_CNT_M;
790 alu->mstp = alu_table[0] & ALU_V_MSTP_M;
791
792 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
793 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
794 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
795
796 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
797
798 alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
799 alu->mac[1] = alu_table[2] & 0xFF;
800 alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
801 alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
802 alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
803 alu->mac[5] = alu_table[3] & 0xFF;
804}
805
806static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
807 dsa_fdb_dump_cb_t *cb, void *data)
808{
809 struct ksz_device *dev = ds->priv;
810 int ret = 0;
811 u32 ksz_data;
812 u32 alu_table[4];
813 struct alu_struct alu;
814 int timeout;
815
816 mutex_lock(&dev->alu_mutex);
817
818 /* start ALU search */
819 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
820
821 do {
822 timeout = 1000;
823 do {
824 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
825 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
826 break;
827 usleep_range(1, 10);
828 } while (timeout-- > 0);
829
830 if (!timeout) {
831 dev_dbg(dev->dev, "Failed to search ALU\n");
832 ret = -ETIMEDOUT;
833 goto exit;
834 }
835
836 /* read ALU table */
837 read_table(ds, alu_table);
838
839 convert_alu(&alu, alu_table);
840
841 if (alu.port_forward & BIT(port)) {
842 ret = cb(alu.mac, alu.fid, alu.is_static, data);
843 if (ret)
844 goto exit;
845 }
846 } while (ksz_data & ALU_START);
847
848exit:
849
850 /* stop ALU search */
851 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
852
853 mutex_unlock(&dev->alu_mutex);
854
855 return ret;
856}
857
858static int ksz_port_mdb_prepare(struct dsa_switch *ds, int port,
859 const struct switchdev_obj_port_mdb *mdb)
860{
861 /* nothing to do */
862 return 0;
863}
864
865static void ksz_port_mdb_add(struct dsa_switch *ds, int port,
866 const struct switchdev_obj_port_mdb *mdb)
867{
868 struct ksz_device *dev = ds->priv;
869 u32 static_table[4];
870 u32 data;
871 int index;
872 u32 mac_hi, mac_lo;
873
874 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
875 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
876 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
877
878 mutex_lock(&dev->alu_mutex);
879
880 for (index = 0; index < dev->num_statics; index++) {
881 /* find empty slot first */
882 data = (index << ALU_STAT_INDEX_S) |
883 ALU_STAT_READ | ALU_STAT_START;
884 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
885
886 /* wait to be finished */
887 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) {
888 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
889 goto exit;
890 }
891
892 /* read ALU static table */
893 read_table(ds, static_table);
894
895 if (static_table[0] & ALU_V_STATIC_VALID) {
896 /* check this has same vid & mac address */
897 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) &&
898 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
899 (static_table[3] == mac_lo)) {
900 /* found matching one */
901 break;
902 }
903 } else {
904 /* found empty one */
905 break;
906 }
907 }
908
909 /* no available entry */
910 if (index == dev->num_statics)
911 goto exit;
912
913 /* add entry */
914 static_table[0] = ALU_V_STATIC_VALID;
915 static_table[1] |= BIT(port);
916 if (mdb->vid)
917 static_table[1] |= ALU_V_USE_FID;
918 static_table[2] = (mdb->vid << ALU_V_FID_S);
919 static_table[2] |= mac_hi;
920 static_table[3] = mac_lo;
921
922 write_table(ds, static_table);
923
924 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
925 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
926
927 /* wait to be finished */
928 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0)
929 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
930
931exit:
932 mutex_unlock(&dev->alu_mutex);
933}
934
935static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
936 const struct switchdev_obj_port_mdb *mdb)
937{
938 struct ksz_device *dev = ds->priv;
939 u32 static_table[4];
940 u32 data;
941 int index;
942 int ret = 0;
943 u32 mac_hi, mac_lo;
944
945 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
946 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
947 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
948
949 mutex_lock(&dev->alu_mutex);
950
951 for (index = 0; index < dev->num_statics; index++) {
952 /* find empty slot first */
953 data = (index << ALU_STAT_INDEX_S) |
954 ALU_STAT_READ | ALU_STAT_START;
955 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
956
957 /* wait to be finished */
958 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
959 if (ret < 0) {
960 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
961 goto exit;
962 }
963
964 /* read ALU static table */
965 read_table(ds, static_table);
966
967 if (static_table[0] & ALU_V_STATIC_VALID) {
968 /* check this has same vid & mac address */
969
970 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) &&
971 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
972 (static_table[3] == mac_lo)) {
973 /* found matching one */
974 break;
975 }
976 }
977 }
978
979 /* no available entry */
980 if (index == dev->num_statics) {
981 ret = -EINVAL;
982 goto exit;
983 }
984
985 /* clear port */
986 static_table[1] &= ~BIT(port);
987
988 if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
989 /* delete entry */
990 static_table[0] = 0;
991 static_table[1] = 0;
992 static_table[2] = 0;
993 static_table[3] = 0;
994 }
995
996 write_table(ds, static_table);
997
998 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
999 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
1000
1001 /* wait to be finished */
1002 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
1003 if (ret < 0)
1004 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
1005
1006exit:
1007 mutex_unlock(&dev->alu_mutex);
1008
1009 return ret;
1010}
1011
1012static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
1013 struct dsa_mall_mirror_tc_entry *mirror,
1014 bool ingress)
1015{
1016 struct ksz_device *dev = ds->priv;
1017
1018 if (ingress)
1019 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1020 else
1021 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1022
1023 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1024
1025 /* configure mirror port */
1026 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1027 PORT_MIRROR_SNIFFER, true);
1028
1029 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1030
1031 return 0;
1032}
1033
1034static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
1035 struct dsa_mall_mirror_tc_entry *mirror)
1036{
1037 struct ksz_device *dev = ds->priv;
1038 u8 data;
1039
1040 if (mirror->ingress)
1041 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1042 else
1043 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1044
1045 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1046
1047 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
1048 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1049 PORT_MIRROR_SNIFFER, false);
1050}
1051
1052static const struct dsa_switch_ops ksz_switch_ops = {
1053 .get_tag_protocol = ksz_get_tag_protocol,
1054 .setup = ksz_setup,
1055 .phy_read = ksz_phy_read16,
1056 .phy_write = ksz_phy_write16,
1057 .port_enable = ksz_enable_port,
1058 .port_disable = ksz_disable_port,
1059 .get_strings = ksz_get_strings,
1060 .get_ethtool_stats = ksz_get_ethtool_stats,
1061 .get_sset_count = ksz_sset_count,
1062 .port_stp_state_set = ksz_port_stp_state_set,
1063 .port_fast_age = ksz_port_fast_age,
1064 .port_vlan_filtering = ksz_port_vlan_filtering,
1065 .port_vlan_prepare = ksz_port_vlan_prepare,
1066 .port_vlan_add = ksz_port_vlan_add,
1067 .port_vlan_del = ksz_port_vlan_del,
1068 .port_fdb_dump = ksz_port_fdb_dump,
1069 .port_fdb_add = ksz_port_fdb_add,
1070 .port_fdb_del = ksz_port_fdb_del,
1071 .port_mdb_prepare = ksz_port_mdb_prepare,
1072 .port_mdb_add = ksz_port_mdb_add,
1073 .port_mdb_del = ksz_port_mdb_del,
1074 .port_mirror_add = ksz_port_mirror_add,
1075 .port_mirror_del = ksz_port_mirror_del,
1076};
1077
1078struct ksz_chip_data {
1079 u32 chip_id;
1080 const char *dev_name;
1081 int num_vlans;
1082 int num_alus;
1083 int num_statics;
1084 int cpu_ports;
1085 int port_cnt;
1086};
1087
1088static const struct ksz_chip_data ksz_switch_chips[] = {
1089 {
1090 .chip_id = 0x00947700,
1091 .dev_name = "KSZ9477",
1092 .num_vlans = 4096,
1093 .num_alus = 4096,
1094 .num_statics = 16,
1095 .cpu_ports = 0x7F, /* can be configured as cpu port */
1096 .port_cnt = 7, /* total physical port count */
1097 },
1098};
1099
1100static int ksz_switch_init(struct ksz_device *dev)
1101{
1102 int i;
1103
1104 mutex_init(&dev->reg_mutex);
1105 mutex_init(&dev->stats_mutex);
1106 mutex_init(&dev->alu_mutex);
1107 mutex_init(&dev->vlan_mutex);
1108
1109 dev->ds->ops = &ksz_switch_ops;
1110
1111 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1112 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1113
1114 if (dev->chip_id == chip->chip_id) {
1115 dev->name = chip->dev_name;
1116 dev->num_vlans = chip->num_vlans;
1117 dev->num_alus = chip->num_alus;
1118 dev->num_statics = chip->num_statics;
1119 dev->port_cnt = chip->port_cnt;
1120 dev->cpu_ports = chip->cpu_ports;
1121
1122 break;
1123 }
1124 }
1125
1126 /* no switch found */
1127 if (!dev->port_cnt)
1128 return -ENODEV;
1129
1130 return 0;
1131}
1132
1133struct ksz_device *ksz_switch_alloc(struct device *base,
1134 const struct ksz_io_ops *ops,
1135 void *priv)
1136{
1137 struct dsa_switch *ds;
1138 struct ksz_device *swdev;
1139
1140 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
1141 if (!ds)
1142 return NULL;
1143
1144 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
1145 if (!swdev)
1146 return NULL;
1147
1148 ds->priv = swdev;
1149 swdev->dev = base;
1150
1151 swdev->ds = ds;
1152 swdev->priv = priv;
1153 swdev->ops = ops;
1154
1155 return swdev;
1156}
1157EXPORT_SYMBOL(ksz_switch_alloc);
1158
1159int ksz_switch_detect(struct ksz_device *dev)
1160{
1161 u8 data8;
1162 u32 id32;
1163 int ret;
1164
1165 /* turn off SPI DO Edge select */
1166 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1167 if (ret)
1168 return ret;
1169
1170 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1171 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1172 if (ret)
1173 return ret;
1174
1175 /* read chip id */
1176 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1177 if (ret)
1178 return ret;
1179
1180 dev->chip_id = id32;
1181
1182 return 0;
1183}
1184EXPORT_SYMBOL(ksz_switch_detect);
1185
1186int ksz_switch_register(struct ksz_device *dev)
1187{
1188 int ret;
1189
1190 if (dev->pdata)
1191 dev->chip_id = dev->pdata->chip_id;
1192
1193 if (ksz_switch_detect(dev))
1194 return -EINVAL;
1195
1196 ret = ksz_switch_init(dev);
1197 if (ret)
1198 return ret;
1199
1200 return dsa_register_switch(dev->ds);
1201}
1202EXPORT_SYMBOL(ksz_switch_register);
1203
1204void ksz_switch_remove(struct ksz_device *dev)
1205{
1206 dsa_unregister_switch(dev->ds);
1207}
1208EXPORT_SYMBOL(ksz_switch_remove);
1209
1210MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1211MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
1212MODULE_LICENSE("GPL");