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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
4 *
5 * Copyright (C) 2014-2024 Broadcom
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip.h>
23#include <linux/irqchip/chained_irq.h>
24
25struct brcmstb_intc_init_params {
26 irq_flow_handler_t handler;
27 int cpu_status;
28 int cpu_clear;
29 int cpu_mask_status;
30 int cpu_mask_set;
31 int cpu_mask_clear;
32};
33
34/* Register offsets in the L2 latched interrupt controller */
35static const struct brcmstb_intc_init_params l2_edge_intc_init = {
36 .handler = handle_edge_irq,
37 .cpu_status = 0x00,
38 .cpu_clear = 0x08,
39 .cpu_mask_status = 0x0c,
40 .cpu_mask_set = 0x10,
41 .cpu_mask_clear = 0x14
42};
43
44/* Register offsets in the L2 level interrupt controller */
45static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
46 .handler = handle_level_irq,
47 .cpu_status = 0x00,
48 .cpu_clear = -1, /* Register not present */
49 .cpu_mask_status = 0x04,
50 .cpu_mask_set = 0x08,
51 .cpu_mask_clear = 0x0C
52};
53
54/* L2 intc private data structure */
55struct brcmstb_l2_intc_data {
56 struct irq_domain *domain;
57 struct irq_chip_generic *gc;
58 int status_offset;
59 int mask_offset;
60 bool can_wake;
61 u32 saved_mask; /* for suspend/resume */
62};
63
64/**
65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
66 * @d: irq_data
67 *
68 * Chip has separate enable/disable registers instead of a single mask
69 * register and pending interrupt is acknowledged by setting a bit.
70 *
71 * Note: This function is generic and could easily be added to the
72 * generic irqchip implementation if there ever becomes a will to do so.
73 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
74 *
75 * e.g.: https://patchwork.kernel.org/patch/9831047/
76 */
77static void brcmstb_l2_mask_and_ack(struct irq_data *d)
78{
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
80 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 u32 mask = d->mask;
82
83 irq_gc_lock(gc);
84 irq_reg_writel(gc, mask, ct->regs.disable);
85 *ct->mask_cache &= ~mask;
86 irq_reg_writel(gc, mask, ct->regs.ack);
87 irq_gc_unlock(gc);
88}
89
90static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
91{
92 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
93 struct irq_chip *chip = irq_desc_get_chip(desc);
94 unsigned int irq;
95 u32 status;
96
97 chained_irq_enter(chip, desc);
98
99 status = irq_reg_readl(b->gc, b->status_offset) &
100 ~(irq_reg_readl(b->gc, b->mask_offset));
101
102 if (status == 0) {
103 raw_spin_lock(&desc->lock);
104 handle_bad_irq(desc);
105 raw_spin_unlock(&desc->lock);
106 goto out;
107 }
108
109 do {
110 irq = ffs(status) - 1;
111 status &= ~(1 << irq);
112 generic_handle_domain_irq(b->domain, irq);
113 } while (status);
114out:
115 /* Don't ack parent before all device writes are done */
116 wmb();
117
118 chained_irq_exit(chip, desc);
119}
120
121static void __brcmstb_l2_intc_suspend(struct irq_data *d, bool save)
122{
123 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124 struct irq_chip_type *ct = irq_data_get_chip_type(d);
125 struct brcmstb_l2_intc_data *b = gc->private;
126 unsigned long flags;
127
128 irq_gc_lock_irqsave(gc, flags);
129 /* Save the current mask */
130 if (save)
131 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
132
133 if (b->can_wake) {
134 /* Program the wakeup mask */
135 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
136 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
137 }
138 irq_gc_unlock_irqrestore(gc, flags);
139}
140
141static void brcmstb_l2_intc_shutdown(struct irq_data *d)
142{
143 __brcmstb_l2_intc_suspend(d, false);
144}
145
146static void brcmstb_l2_intc_suspend(struct irq_data *d)
147{
148 __brcmstb_l2_intc_suspend(d, true);
149}
150
151static void brcmstb_l2_intc_resume(struct irq_data *d)
152{
153 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
154 struct irq_chip_type *ct = irq_data_get_chip_type(d);
155 struct brcmstb_l2_intc_data *b = gc->private;
156 unsigned long flags;
157
158 irq_gc_lock_irqsave(gc, flags);
159 if (ct->chip.irq_ack) {
160 /* Clear unmasked non-wakeup interrupts */
161 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
162 ct->regs.ack);
163 }
164
165 /* Restore the saved mask */
166 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
167 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
168 irq_gc_unlock_irqrestore(gc, flags);
169}
170
171static int __init brcmstb_l2_intc_of_init(struct device_node *np,
172 struct device_node *parent,
173 const struct brcmstb_intc_init_params
174 *init_params)
175{
176 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
177 unsigned int set = 0;
178 struct brcmstb_l2_intc_data *data;
179 struct irq_chip_type *ct;
180 int ret;
181 unsigned int flags;
182 int parent_irq;
183 void __iomem *base;
184
185 data = kzalloc(sizeof(*data), GFP_KERNEL);
186 if (!data)
187 return -ENOMEM;
188
189 base = of_iomap(np, 0);
190 if (!base) {
191 pr_err("failed to remap intc L2 registers\n");
192 ret = -ENOMEM;
193 goto out_free;
194 }
195
196 /* Disable all interrupts by default */
197 writel(0xffffffff, base + init_params->cpu_mask_set);
198
199 /* Wakeup interrupts may be retained from S5 (cold boot) */
200 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
201 if (!data->can_wake && (init_params->cpu_clear >= 0))
202 writel(0xffffffff, base + init_params->cpu_clear);
203
204 parent_irq = irq_of_parse_and_map(np, 0);
205 if (!parent_irq) {
206 pr_err("failed to find parent interrupt\n");
207 ret = -EINVAL;
208 goto out_unmap;
209 }
210
211 data->domain = irq_domain_add_linear(np, 32,
212 &irq_generic_chip_ops, NULL);
213 if (!data->domain) {
214 ret = -ENOMEM;
215 goto out_unmap;
216 }
217
218 /* MIPS chips strapped for BE will automagically configure the
219 * peripheral registers for CPU-native byte order.
220 */
221 flags = 0;
222 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
223 flags |= IRQ_GC_BE_IO;
224
225 if (init_params->handler == handle_level_irq)
226 set |= IRQ_LEVEL;
227
228 /* Allocate a single Generic IRQ chip for this node */
229 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
230 np->full_name, init_params->handler, clr, set, flags);
231 if (ret) {
232 pr_err("failed to allocate generic irq chip\n");
233 goto out_free_domain;
234 }
235
236 /* Set the IRQ chaining logic */
237 irq_set_chained_handler_and_data(parent_irq,
238 brcmstb_l2_intc_irq_handle, data);
239
240 data->gc = irq_get_domain_generic_chip(data->domain, 0);
241 data->gc->reg_base = base;
242 data->gc->private = data;
243 data->status_offset = init_params->cpu_status;
244 data->mask_offset = init_params->cpu_mask_status;
245
246 ct = data->gc->chip_types;
247
248 if (init_params->cpu_clear >= 0) {
249 ct->regs.ack = init_params->cpu_clear;
250 ct->chip.irq_ack = irq_gc_ack_set_bit;
251 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
252 } else {
253 /* No Ack - but still slightly more efficient to define this */
254 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
255 }
256
257 ct->chip.irq_mask = irq_gc_mask_disable_reg;
258 ct->regs.disable = init_params->cpu_mask_set;
259 ct->regs.mask = init_params->cpu_mask_status;
260
261 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
262 ct->regs.enable = init_params->cpu_mask_clear;
263
264 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
265 ct->chip.irq_resume = brcmstb_l2_intc_resume;
266 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_shutdown;
267
268 if (data->can_wake) {
269 /* This IRQ chip can wake the system, set all child interrupts
270 * in wake_enabled mask
271 */
272 data->gc->wake_enabled = 0xffffffff;
273 ct->chip.irq_set_wake = irq_gc_set_wake;
274 enable_irq_wake(parent_irq);
275 }
276
277 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
278
279 return 0;
280
281out_free_domain:
282 irq_domain_remove(data->domain);
283out_unmap:
284 iounmap(base);
285out_free:
286 kfree(data);
287 return ret;
288}
289
290static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
291 struct device_node *parent)
292{
293 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
294}
295
296static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
297 struct device_node *parent)
298{
299 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
300}
301
302IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
303IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
304IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
305IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
306IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
307IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
308MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
309MODULE_LICENSE("GPL v2");
1/*
2 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
3 *
4 * Copyright (C) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/init.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/of.h>
24#include <linux/of_irq.h>
25#include <linux/of_address.h>
26#include <linux/of_platform.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/io.h>
30#include <linux/irqdomain.h>
31#include <linux/irqchip.h>
32#include <linux/irqchip/chained_irq.h>
33
34struct brcmstb_intc_init_params {
35 irq_flow_handler_t handler;
36 int cpu_status;
37 int cpu_clear;
38 int cpu_mask_status;
39 int cpu_mask_set;
40 int cpu_mask_clear;
41};
42
43/* Register offsets in the L2 latched interrupt controller */
44static const struct brcmstb_intc_init_params l2_edge_intc_init = {
45 .handler = handle_edge_irq,
46 .cpu_status = 0x00,
47 .cpu_clear = 0x08,
48 .cpu_mask_status = 0x0c,
49 .cpu_mask_set = 0x10,
50 .cpu_mask_clear = 0x14
51};
52
53/* Register offsets in the L2 level interrupt controller */
54static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
55 .handler = handle_level_irq,
56 .cpu_status = 0x00,
57 .cpu_clear = -1, /* Register not present */
58 .cpu_mask_status = 0x04,
59 .cpu_mask_set = 0x08,
60 .cpu_mask_clear = 0x0C
61};
62
63/* L2 intc private data structure */
64struct brcmstb_l2_intc_data {
65 struct irq_domain *domain;
66 struct irq_chip_generic *gc;
67 int status_offset;
68 int mask_offset;
69 bool can_wake;
70 u32 saved_mask; /* for suspend/resume */
71};
72
73/**
74 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
75 * @d: irq_data
76 *
77 * Chip has separate enable/disable registers instead of a single mask
78 * register and pending interrupt is acknowledged by setting a bit.
79 *
80 * Note: This function is generic and could easily be added to the
81 * generic irqchip implementation if there ever becomes a will to do so.
82 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
83 *
84 * e.g.: https://patchwork.kernel.org/patch/9831047/
85 */
86static void brcmstb_l2_mask_and_ack(struct irq_data *d)
87{
88 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
89 struct irq_chip_type *ct = irq_data_get_chip_type(d);
90 u32 mask = d->mask;
91
92 irq_gc_lock(gc);
93 irq_reg_writel(gc, mask, ct->regs.disable);
94 *ct->mask_cache &= ~mask;
95 irq_reg_writel(gc, mask, ct->regs.ack);
96 irq_gc_unlock(gc);
97}
98
99static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
100{
101 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
102 struct irq_chip *chip = irq_desc_get_chip(desc);
103 unsigned int irq;
104 u32 status;
105
106 chained_irq_enter(chip, desc);
107
108 status = irq_reg_readl(b->gc, b->status_offset) &
109 ~(irq_reg_readl(b->gc, b->mask_offset));
110
111 if (status == 0) {
112 raw_spin_lock(&desc->lock);
113 handle_bad_irq(desc);
114 raw_spin_unlock(&desc->lock);
115 goto out;
116 }
117
118 do {
119 irq = ffs(status) - 1;
120 status &= ~(1 << irq);
121 generic_handle_irq(irq_linear_revmap(b->domain, irq));
122 } while (status);
123out:
124 chained_irq_exit(chip, desc);
125}
126
127static void brcmstb_l2_intc_suspend(struct irq_data *d)
128{
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = irq_data_get_chip_type(d);
131 struct brcmstb_l2_intc_data *b = gc->private;
132
133 irq_gc_lock(gc);
134 /* Save the current mask */
135 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
136
137 if (b->can_wake) {
138 /* Program the wakeup mask */
139 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
140 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
141 }
142 irq_gc_unlock(gc);
143}
144
145static void brcmstb_l2_intc_resume(struct irq_data *d)
146{
147 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
148 struct irq_chip_type *ct = irq_data_get_chip_type(d);
149 struct brcmstb_l2_intc_data *b = gc->private;
150
151 irq_gc_lock(gc);
152 if (ct->chip.irq_ack) {
153 /* Clear unmasked non-wakeup interrupts */
154 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
155 ct->regs.ack);
156 }
157
158 /* Restore the saved mask */
159 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
160 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
161 irq_gc_unlock(gc);
162}
163
164static int __init brcmstb_l2_intc_of_init(struct device_node *np,
165 struct device_node *parent,
166 const struct brcmstb_intc_init_params
167 *init_params)
168{
169 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
170 struct brcmstb_l2_intc_data *data;
171 struct irq_chip_type *ct;
172 int ret;
173 unsigned int flags;
174 int parent_irq;
175 void __iomem *base;
176
177 data = kzalloc(sizeof(*data), GFP_KERNEL);
178 if (!data)
179 return -ENOMEM;
180
181 base = of_iomap(np, 0);
182 if (!base) {
183 pr_err("failed to remap intc L2 registers\n");
184 ret = -ENOMEM;
185 goto out_free;
186 }
187
188 /* Disable all interrupts by default */
189 writel(0xffffffff, base + init_params->cpu_mask_set);
190
191 /* Wakeup interrupts may be retained from S5 (cold boot) */
192 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
193 if (!data->can_wake && (init_params->cpu_clear >= 0))
194 writel(0xffffffff, base + init_params->cpu_clear);
195
196 parent_irq = irq_of_parse_and_map(np, 0);
197 if (!parent_irq) {
198 pr_err("failed to find parent interrupt\n");
199 ret = -EINVAL;
200 goto out_unmap;
201 }
202
203 data->domain = irq_domain_add_linear(np, 32,
204 &irq_generic_chip_ops, NULL);
205 if (!data->domain) {
206 ret = -ENOMEM;
207 goto out_unmap;
208 }
209
210 /* MIPS chips strapped for BE will automagically configure the
211 * peripheral registers for CPU-native byte order.
212 */
213 flags = 0;
214 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
215 flags |= IRQ_GC_BE_IO;
216
217 /* Allocate a single Generic IRQ chip for this node */
218 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
219 np->full_name, init_params->handler, clr, 0, flags);
220 if (ret) {
221 pr_err("failed to allocate generic irq chip\n");
222 goto out_free_domain;
223 }
224
225 /* Set the IRQ chaining logic */
226 irq_set_chained_handler_and_data(parent_irq,
227 brcmstb_l2_intc_irq_handle, data);
228
229 data->gc = irq_get_domain_generic_chip(data->domain, 0);
230 data->gc->reg_base = base;
231 data->gc->private = data;
232 data->status_offset = init_params->cpu_status;
233 data->mask_offset = init_params->cpu_mask_status;
234
235 ct = data->gc->chip_types;
236
237 if (init_params->cpu_clear >= 0) {
238 ct->regs.ack = init_params->cpu_clear;
239 ct->chip.irq_ack = irq_gc_ack_set_bit;
240 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
241 } else {
242 /* No Ack - but still slightly more efficient to define this */
243 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
244 }
245
246 ct->chip.irq_mask = irq_gc_mask_disable_reg;
247 ct->regs.disable = init_params->cpu_mask_set;
248 ct->regs.mask = init_params->cpu_mask_status;
249
250 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
251 ct->regs.enable = init_params->cpu_mask_clear;
252
253 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
254 ct->chip.irq_resume = brcmstb_l2_intc_resume;
255 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
256
257 if (data->can_wake) {
258 /* This IRQ chip can wake the system, set all child interrupts
259 * in wake_enabled mask
260 */
261 data->gc->wake_enabled = 0xffffffff;
262 ct->chip.irq_set_wake = irq_gc_set_wake;
263 }
264
265 return 0;
266
267out_free_domain:
268 irq_domain_remove(data->domain);
269out_unmap:
270 iounmap(base);
271out_free:
272 kfree(data);
273 return ret;
274}
275
276int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
277 struct device_node *parent)
278{
279 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
280}
281IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
282
283int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
284 struct device_node *parent)
285{
286 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
287}
288IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
289 brcmstb_l2_lvl_intc_of_init);