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1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie
7 * Alon Levy
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28#include <linux/file.h>
29#include <linux/sync_file.h>
30#include <linux/uaccess.h>
31
32#include <drm/drm_file.h>
33#include <drm/virtgpu_drm.h>
34
35#include "virtgpu_drv.h"
36
37#define VIRTGPU_BLOB_FLAG_USE_MASK (VIRTGPU_BLOB_FLAG_USE_MAPPABLE | \
38 VIRTGPU_BLOB_FLAG_USE_SHAREABLE | \
39 VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE)
40
41/* Must be called with &virtio_gpu_fpriv.struct_mutex held. */
42static void virtio_gpu_create_context_locked(struct virtio_gpu_device *vgdev,
43 struct virtio_gpu_fpriv *vfpriv)
44{
45 if (vfpriv->explicit_debug_name) {
46 virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
47 vfpriv->context_init,
48 strlen(vfpriv->debug_name),
49 vfpriv->debug_name);
50 } else {
51 char dbgname[TASK_COMM_LEN];
52
53 get_task_comm(dbgname, current);
54 virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
55 vfpriv->context_init, strlen(dbgname),
56 dbgname);
57 }
58
59 vfpriv->context_created = true;
60}
61
62void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
63{
64 struct virtio_gpu_device *vgdev = dev->dev_private;
65 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
66
67 mutex_lock(&vfpriv->context_lock);
68 if (vfpriv->context_created)
69 goto out_unlock;
70
71 virtio_gpu_create_context_locked(vgdev, vfpriv);
72
73out_unlock:
74 mutex_unlock(&vfpriv->context_lock);
75}
76
77static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
78 struct drm_file *file)
79{
80 struct virtio_gpu_device *vgdev = dev->dev_private;
81 struct drm_virtgpu_map *virtio_gpu_map = data;
82
83 return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
84 virtio_gpu_map->handle,
85 &virtio_gpu_map->offset);
86}
87
88static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
89 struct drm_file *file)
90{
91 struct virtio_gpu_device *vgdev = dev->dev_private;
92 struct drm_virtgpu_getparam *param = data;
93 int value;
94
95 switch (param->param) {
96 case VIRTGPU_PARAM_3D_FEATURES:
97 value = vgdev->has_virgl_3d ? 1 : 0;
98 break;
99 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
100 value = 1;
101 break;
102 case VIRTGPU_PARAM_RESOURCE_BLOB:
103 value = vgdev->has_resource_blob ? 1 : 0;
104 break;
105 case VIRTGPU_PARAM_HOST_VISIBLE:
106 value = vgdev->has_host_visible ? 1 : 0;
107 break;
108 case VIRTGPU_PARAM_CROSS_DEVICE:
109 value = vgdev->has_resource_assign_uuid ? 1 : 0;
110 break;
111 case VIRTGPU_PARAM_CONTEXT_INIT:
112 value = vgdev->has_context_init ? 1 : 0;
113 break;
114 case VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs:
115 value = vgdev->capset_id_mask;
116 break;
117 case VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME:
118 value = vgdev->has_context_init ? 1 : 0;
119 break;
120 default:
121 return -EINVAL;
122 }
123 if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
124 return -EFAULT;
125
126 return 0;
127}
128
129static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file)
131{
132 struct virtio_gpu_device *vgdev = dev->dev_private;
133 struct drm_virtgpu_resource_create *rc = data;
134 struct virtio_gpu_fence *fence;
135 int ret;
136 struct virtio_gpu_object *qobj;
137 struct drm_gem_object *obj;
138 uint32_t handle = 0;
139 struct virtio_gpu_object_params params = { 0 };
140
141 if (vgdev->has_virgl_3d) {
142 virtio_gpu_create_context(dev, file);
143 params.virgl = true;
144 params.target = rc->target;
145 params.bind = rc->bind;
146 params.depth = rc->depth;
147 params.array_size = rc->array_size;
148 params.last_level = rc->last_level;
149 params.nr_samples = rc->nr_samples;
150 params.flags = rc->flags;
151 } else {
152 if (rc->depth > 1)
153 return -EINVAL;
154 if (rc->nr_samples > 1)
155 return -EINVAL;
156 if (rc->last_level > 1)
157 return -EINVAL;
158 if (rc->target != 2)
159 return -EINVAL;
160 if (rc->array_size > 1)
161 return -EINVAL;
162 }
163
164 params.format = rc->format;
165 params.width = rc->width;
166 params.height = rc->height;
167 params.size = rc->size;
168 /* allocate a single page size object */
169 if (params.size == 0)
170 params.size = PAGE_SIZE;
171
172 fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0);
173 if (!fence)
174 return -ENOMEM;
175 ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence);
176 dma_fence_put(&fence->f);
177 if (ret < 0)
178 return ret;
179 obj = &qobj->base.base;
180
181 ret = drm_gem_handle_create(file, obj, &handle);
182 if (ret) {
183 drm_gem_object_release(obj);
184 return ret;
185 }
186
187 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
188 rc->bo_handle = handle;
189
190 /*
191 * The handle owns the reference now. But we must drop our
192 * remaining reference *after* we no longer need to dereference
193 * the obj. Otherwise userspace could guess the handle and
194 * race closing it from another thread.
195 */
196 drm_gem_object_put(obj);
197
198 return 0;
199}
200
201static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
202 struct drm_file *file)
203{
204 struct drm_virtgpu_resource_info *ri = data;
205 struct drm_gem_object *gobj = NULL;
206 struct virtio_gpu_object *qobj = NULL;
207
208 gobj = drm_gem_object_lookup(file, ri->bo_handle);
209 if (gobj == NULL)
210 return -ENOENT;
211
212 qobj = gem_to_virtio_gpu_obj(gobj);
213
214 ri->size = qobj->base.base.size;
215 ri->res_handle = qobj->hw_res_handle;
216 if (qobj->host3d_blob || qobj->guest_blob)
217 ri->blob_mem = qobj->blob_mem;
218
219 drm_gem_object_put(gobj);
220 return 0;
221}
222
223static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
224 void *data,
225 struct drm_file *file)
226{
227 struct virtio_gpu_device *vgdev = dev->dev_private;
228 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
229 struct drm_virtgpu_3d_transfer_from_host *args = data;
230 struct virtio_gpu_object *bo;
231 struct virtio_gpu_object_array *objs;
232 struct virtio_gpu_fence *fence;
233 int ret;
234 u32 offset = args->offset;
235
236 if (vgdev->has_virgl_3d == false)
237 return -ENOSYS;
238
239 virtio_gpu_create_context(dev, file);
240 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
241 if (objs == NULL)
242 return -ENOENT;
243
244 bo = gem_to_virtio_gpu_obj(objs->objs[0]);
245 if (bo->guest_blob && !bo->host3d_blob) {
246 ret = -EINVAL;
247 goto err_put_free;
248 }
249
250 if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
251 ret = -EINVAL;
252 goto err_put_free;
253 }
254
255 ret = virtio_gpu_array_lock_resv(objs);
256 if (ret != 0)
257 goto err_put_free;
258
259 fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0);
260 if (!fence) {
261 ret = -ENOMEM;
262 goto err_unlock;
263 }
264
265 virtio_gpu_cmd_transfer_from_host_3d
266 (vgdev, vfpriv->ctx_id, offset, args->level, args->stride,
267 args->layer_stride, &args->box, objs, fence);
268 dma_fence_put(&fence->f);
269 virtio_gpu_notify(vgdev);
270 return 0;
271
272err_unlock:
273 virtio_gpu_array_unlock_resv(objs);
274err_put_free:
275 virtio_gpu_array_put_free(objs);
276 return ret;
277}
278
279static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
280 struct drm_file *file)
281{
282 struct virtio_gpu_device *vgdev = dev->dev_private;
283 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
284 struct drm_virtgpu_3d_transfer_to_host *args = data;
285 struct virtio_gpu_object *bo;
286 struct virtio_gpu_object_array *objs;
287 struct virtio_gpu_fence *fence;
288 int ret;
289 u32 offset = args->offset;
290
291 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
292 if (objs == NULL)
293 return -ENOENT;
294
295 bo = gem_to_virtio_gpu_obj(objs->objs[0]);
296 if (bo->guest_blob && !bo->host3d_blob) {
297 ret = -EINVAL;
298 goto err_put_free;
299 }
300
301 if (!vgdev->has_virgl_3d) {
302 virtio_gpu_cmd_transfer_to_host_2d
303 (vgdev, offset,
304 args->box.w, args->box.h, args->box.x, args->box.y,
305 objs, NULL);
306 } else {
307 virtio_gpu_create_context(dev, file);
308
309 if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
310 ret = -EINVAL;
311 goto err_put_free;
312 }
313
314 ret = virtio_gpu_array_lock_resv(objs);
315 if (ret != 0)
316 goto err_put_free;
317
318 ret = -ENOMEM;
319 fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context,
320 0);
321 if (!fence)
322 goto err_unlock;
323
324 virtio_gpu_cmd_transfer_to_host_3d
325 (vgdev,
326 vfpriv ? vfpriv->ctx_id : 0, offset, args->level,
327 args->stride, args->layer_stride, &args->box, objs,
328 fence);
329 dma_fence_put(&fence->f);
330 }
331 virtio_gpu_notify(vgdev);
332 return 0;
333
334err_unlock:
335 virtio_gpu_array_unlock_resv(objs);
336err_put_free:
337 virtio_gpu_array_put_free(objs);
338 return ret;
339}
340
341static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
342 struct drm_file *file)
343{
344 struct drm_virtgpu_3d_wait *args = data;
345 struct drm_gem_object *obj;
346 long timeout = 15 * HZ;
347 int ret;
348
349 obj = drm_gem_object_lookup(file, args->handle);
350 if (obj == NULL)
351 return -ENOENT;
352
353 if (args->flags & VIRTGPU_WAIT_NOWAIT) {
354 ret = dma_resv_test_signaled(obj->resv, DMA_RESV_USAGE_READ);
355 } else {
356 ret = dma_resv_wait_timeout(obj->resv, DMA_RESV_USAGE_READ,
357 true, timeout);
358 }
359 if (ret == 0)
360 ret = -EBUSY;
361 else if (ret > 0)
362 ret = 0;
363
364 drm_gem_object_put(obj);
365 return ret;
366}
367
368static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
369 void *data, struct drm_file *file)
370{
371 struct virtio_gpu_device *vgdev = dev->dev_private;
372 struct drm_virtgpu_get_caps *args = data;
373 unsigned size, host_caps_size;
374 int i;
375 int found_valid = -1;
376 int ret;
377 struct virtio_gpu_drv_cap_cache *cache_ent;
378 void *ptr;
379
380 if (vgdev->num_capsets == 0)
381 return -ENOSYS;
382
383 /* don't allow userspace to pass 0 */
384 if (args->size == 0)
385 return -EINVAL;
386
387 spin_lock(&vgdev->display_info_lock);
388 for (i = 0; i < vgdev->num_capsets; i++) {
389 if (vgdev->capsets[i].id == args->cap_set_id) {
390 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
391 found_valid = i;
392 break;
393 }
394 }
395 }
396
397 if (found_valid == -1) {
398 spin_unlock(&vgdev->display_info_lock);
399 return -EINVAL;
400 }
401
402 host_caps_size = vgdev->capsets[found_valid].max_size;
403 /* only copy to user the minimum of the host caps size or the guest caps size */
404 size = min(args->size, host_caps_size);
405
406 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
407 if (cache_ent->id == args->cap_set_id &&
408 cache_ent->version == args->cap_set_ver) {
409 spin_unlock(&vgdev->display_info_lock);
410 goto copy_exit;
411 }
412 }
413 spin_unlock(&vgdev->display_info_lock);
414
415 /* not in cache - need to talk to hw */
416 ret = virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
417 &cache_ent);
418 if (ret)
419 return ret;
420 virtio_gpu_notify(vgdev);
421
422copy_exit:
423 ret = wait_event_timeout(vgdev->resp_wq,
424 atomic_read(&cache_ent->is_valid), 5 * HZ);
425 if (!ret)
426 return -EBUSY;
427
428 /* is_valid check must proceed before copy of the cache entry. */
429 smp_rmb();
430
431 ptr = cache_ent->caps_cache;
432
433 if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
434 return -EFAULT;
435
436 return 0;
437}
438
439static int verify_blob(struct virtio_gpu_device *vgdev,
440 struct virtio_gpu_fpriv *vfpriv,
441 struct virtio_gpu_object_params *params,
442 struct drm_virtgpu_resource_create_blob *rc_blob,
443 bool *guest_blob, bool *host3d_blob)
444{
445 if (!vgdev->has_resource_blob)
446 return -EINVAL;
447
448 if (rc_blob->blob_flags & ~VIRTGPU_BLOB_FLAG_USE_MASK)
449 return -EINVAL;
450
451 if (rc_blob->blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
452 if (!vgdev->has_resource_assign_uuid)
453 return -EINVAL;
454 }
455
456 switch (rc_blob->blob_mem) {
457 case VIRTGPU_BLOB_MEM_GUEST:
458 *guest_blob = true;
459 break;
460 case VIRTGPU_BLOB_MEM_HOST3D_GUEST:
461 *guest_blob = true;
462 fallthrough;
463 case VIRTGPU_BLOB_MEM_HOST3D:
464 *host3d_blob = true;
465 break;
466 default:
467 return -EINVAL;
468 }
469
470 if (*host3d_blob) {
471 if (!vgdev->has_virgl_3d)
472 return -EINVAL;
473
474 /* Must be dword aligned. */
475 if (rc_blob->cmd_size % 4 != 0)
476 return -EINVAL;
477
478 params->ctx_id = vfpriv->ctx_id;
479 params->blob_id = rc_blob->blob_id;
480 } else {
481 if (rc_blob->blob_id != 0)
482 return -EINVAL;
483
484 if (rc_blob->cmd_size != 0)
485 return -EINVAL;
486 }
487
488 params->blob_mem = rc_blob->blob_mem;
489 params->size = rc_blob->size;
490 params->blob = true;
491 params->blob_flags = rc_blob->blob_flags;
492 return 0;
493}
494
495static int virtio_gpu_resource_create_blob_ioctl(struct drm_device *dev,
496 void *data,
497 struct drm_file *file)
498{
499 int ret = 0;
500 uint32_t handle = 0;
501 bool guest_blob = false;
502 bool host3d_blob = false;
503 struct drm_gem_object *obj;
504 struct virtio_gpu_object *bo;
505 struct virtio_gpu_object_params params = { 0 };
506 struct virtio_gpu_device *vgdev = dev->dev_private;
507 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
508 struct drm_virtgpu_resource_create_blob *rc_blob = data;
509
510 if (verify_blob(vgdev, vfpriv, ¶ms, rc_blob,
511 &guest_blob, &host3d_blob))
512 return -EINVAL;
513
514 if (vgdev->has_virgl_3d)
515 virtio_gpu_create_context(dev, file);
516
517 if (rc_blob->cmd_size) {
518 void *buf;
519
520 buf = memdup_user(u64_to_user_ptr(rc_blob->cmd),
521 rc_blob->cmd_size);
522
523 if (IS_ERR(buf))
524 return PTR_ERR(buf);
525
526 virtio_gpu_cmd_submit(vgdev, buf, rc_blob->cmd_size,
527 vfpriv->ctx_id, NULL, NULL);
528 }
529
530 if (guest_blob)
531 ret = virtio_gpu_object_create(vgdev, ¶ms, &bo, NULL);
532 else if (!guest_blob && host3d_blob)
533 ret = virtio_gpu_vram_create(vgdev, ¶ms, &bo);
534 else
535 return -EINVAL;
536
537 if (ret < 0)
538 return ret;
539
540 bo->guest_blob = guest_blob;
541 bo->host3d_blob = host3d_blob;
542 bo->blob_mem = rc_blob->blob_mem;
543 bo->blob_flags = rc_blob->blob_flags;
544
545 obj = &bo->base.base;
546 if (params.blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
547 ret = virtio_gpu_resource_assign_uuid(vgdev, bo);
548 if (ret) {
549 drm_gem_object_release(obj);
550 return ret;
551 }
552 }
553
554 ret = drm_gem_handle_create(file, obj, &handle);
555 if (ret) {
556 drm_gem_object_release(obj);
557 return ret;
558 }
559
560 rc_blob->res_handle = bo->hw_res_handle;
561 rc_blob->bo_handle = handle;
562
563 /*
564 * The handle owns the reference now. But we must drop our
565 * remaining reference *after* we no longer need to dereference
566 * the obj. Otherwise userspace could guess the handle and
567 * race closing it from another thread.
568 */
569 drm_gem_object_put(obj);
570
571 return 0;
572}
573
574static int virtio_gpu_context_init_ioctl(struct drm_device *dev,
575 void *data, struct drm_file *file)
576{
577 int ret = 0;
578 uint32_t num_params, i;
579 uint64_t valid_ring_mask, param, value;
580 size_t len;
581 struct drm_virtgpu_context_set_param *ctx_set_params = NULL;
582 struct virtio_gpu_device *vgdev = dev->dev_private;
583 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
584 struct drm_virtgpu_context_init *args = data;
585
586 num_params = args->num_params;
587 len = num_params * sizeof(struct drm_virtgpu_context_set_param);
588
589 if (!vgdev->has_context_init || !vgdev->has_virgl_3d)
590 return -EINVAL;
591
592 /* Number of unique parameters supported at this time. */
593 if (num_params > 4)
594 return -EINVAL;
595
596 ctx_set_params = memdup_user(u64_to_user_ptr(args->ctx_set_params),
597 len);
598
599 if (IS_ERR(ctx_set_params))
600 return PTR_ERR(ctx_set_params);
601
602 mutex_lock(&vfpriv->context_lock);
603 if (vfpriv->context_created) {
604 ret = -EEXIST;
605 goto out_unlock;
606 }
607
608 for (i = 0; i < num_params; i++) {
609 param = ctx_set_params[i].param;
610 value = ctx_set_params[i].value;
611
612 switch (param) {
613 case VIRTGPU_CONTEXT_PARAM_CAPSET_ID:
614 if (value > MAX_CAPSET_ID) {
615 ret = -EINVAL;
616 goto out_unlock;
617 }
618
619 if ((vgdev->capset_id_mask & (1ULL << value)) == 0) {
620 ret = -EINVAL;
621 goto out_unlock;
622 }
623
624 /* Context capset ID already set */
625 if (vfpriv->context_init &
626 VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK) {
627 ret = -EINVAL;
628 goto out_unlock;
629 }
630
631 vfpriv->context_init |= value;
632 break;
633 case VIRTGPU_CONTEXT_PARAM_NUM_RINGS:
634 if (vfpriv->base_fence_ctx) {
635 ret = -EINVAL;
636 goto out_unlock;
637 }
638
639 if (value > MAX_RINGS) {
640 ret = -EINVAL;
641 goto out_unlock;
642 }
643
644 vfpriv->base_fence_ctx = dma_fence_context_alloc(value);
645 vfpriv->num_rings = value;
646 break;
647 case VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK:
648 if (vfpriv->ring_idx_mask) {
649 ret = -EINVAL;
650 goto out_unlock;
651 }
652
653 vfpriv->ring_idx_mask = value;
654 break;
655 case VIRTGPU_CONTEXT_PARAM_DEBUG_NAME:
656 if (vfpriv->explicit_debug_name) {
657 ret = -EINVAL;
658 goto out_unlock;
659 }
660
661 ret = strncpy_from_user(vfpriv->debug_name,
662 u64_to_user_ptr(value),
663 DEBUG_NAME_MAX_LEN - 1);
664 if (ret < 0)
665 goto out_unlock;
666
667 vfpriv->explicit_debug_name = true;
668 ret = 0;
669 break;
670 default:
671 ret = -EINVAL;
672 goto out_unlock;
673 }
674 }
675
676 if (vfpriv->ring_idx_mask) {
677 valid_ring_mask = 0;
678 for (i = 0; i < vfpriv->num_rings; i++)
679 valid_ring_mask |= 1ULL << i;
680
681 if (~valid_ring_mask & vfpriv->ring_idx_mask) {
682 ret = -EINVAL;
683 goto out_unlock;
684 }
685 }
686
687 virtio_gpu_create_context_locked(vgdev, vfpriv);
688 virtio_gpu_notify(vgdev);
689
690out_unlock:
691 mutex_unlock(&vfpriv->context_lock);
692 kfree(ctx_set_params);
693 return ret;
694}
695
696struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
697 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
698 DRM_RENDER_ALLOW),
699
700 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
701 DRM_RENDER_ALLOW),
702
703 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
704 DRM_RENDER_ALLOW),
705
706 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
707 virtio_gpu_resource_create_ioctl,
708 DRM_RENDER_ALLOW),
709
710 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
711 DRM_RENDER_ALLOW),
712
713 /* make transfer async to the main ring? - no sure, can we
714 * thread these in the underlying GL
715 */
716 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
717 virtio_gpu_transfer_from_host_ioctl,
718 DRM_RENDER_ALLOW),
719 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
720 virtio_gpu_transfer_to_host_ioctl,
721 DRM_RENDER_ALLOW),
722
723 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
724 DRM_RENDER_ALLOW),
725
726 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
727 DRM_RENDER_ALLOW),
728
729 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE_BLOB,
730 virtio_gpu_resource_create_blob_ioctl,
731 DRM_RENDER_ALLOW),
732
733 DRM_IOCTL_DEF_DRV(VIRTGPU_CONTEXT_INIT, virtio_gpu_context_init_ioctl,
734 DRM_RENDER_ALLOW),
735};
1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie
7 * Alon Levy
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28#include <drm/drmP.h>
29#include <drm/virtgpu_drm.h>
30#include <drm/ttm/ttm_execbuf_util.h>
31
32#include "virtgpu_drv.h"
33
34static void convert_to_hw_box(struct virtio_gpu_box *dst,
35 const struct drm_virtgpu_3d_box *src)
36{
37 dst->x = cpu_to_le32(src->x);
38 dst->y = cpu_to_le32(src->y);
39 dst->z = cpu_to_le32(src->z);
40 dst->w = cpu_to_le32(src->w);
41 dst->h = cpu_to_le32(src->h);
42 dst->d = cpu_to_le32(src->d);
43}
44
45static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
46 struct drm_file *file_priv)
47{
48 struct virtio_gpu_device *vgdev = dev->dev_private;
49 struct drm_virtgpu_map *virtio_gpu_map = data;
50
51 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
52 virtio_gpu_map->handle,
53 &virtio_gpu_map->offset);
54}
55
56static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
57 struct list_head *head)
58{
59 struct ttm_operation_ctx ctx = { false, false };
60 struct ttm_validate_buffer *buf;
61 struct ttm_buffer_object *bo;
62 struct virtio_gpu_object *qobj;
63 int ret;
64
65 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL);
66 if (ret != 0)
67 return ret;
68
69 list_for_each_entry(buf, head, head) {
70 bo = buf->bo;
71 qobj = container_of(bo, struct virtio_gpu_object, tbo);
72 ret = ttm_bo_validate(bo, &qobj->placement, &ctx);
73 if (ret) {
74 ttm_eu_backoff_reservation(ticket, head);
75 return ret;
76 }
77 }
78 return 0;
79}
80
81static void virtio_gpu_unref_list(struct list_head *head)
82{
83 struct ttm_validate_buffer *buf;
84 struct ttm_buffer_object *bo;
85 struct virtio_gpu_object *qobj;
86
87 list_for_each_entry(buf, head, head) {
88 bo = buf->bo;
89 qobj = container_of(bo, struct virtio_gpu_object, tbo);
90
91 drm_gem_object_put_unlocked(&qobj->gem_base);
92 }
93}
94
95/*
96 * Usage of execbuffer:
97 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
98 * However, the command as passed from user space must *not* contain the initial
99 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
100 */
101static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
102 struct drm_file *drm_file)
103{
104 struct drm_virtgpu_execbuffer *exbuf = data;
105 struct virtio_gpu_device *vgdev = dev->dev_private;
106 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
107 struct drm_gem_object *gobj;
108 struct virtio_gpu_fence *fence;
109 struct virtio_gpu_object *qobj;
110 int ret;
111 uint32_t *bo_handles = NULL;
112 void __user *user_bo_handles = NULL;
113 struct list_head validate_list;
114 struct ttm_validate_buffer *buflist = NULL;
115 int i;
116 struct ww_acquire_ctx ticket;
117 void *buf;
118
119 if (vgdev->has_virgl_3d == false)
120 return -ENOSYS;
121
122 INIT_LIST_HEAD(&validate_list);
123 if (exbuf->num_bo_handles) {
124
125 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
126 sizeof(uint32_t), GFP_KERNEL);
127 buflist = kvmalloc_array(exbuf->num_bo_handles,
128 sizeof(struct ttm_validate_buffer),
129 GFP_KERNEL | __GFP_ZERO);
130 if (!bo_handles || !buflist) {
131 kvfree(bo_handles);
132 kvfree(buflist);
133 return -ENOMEM;
134 }
135
136 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles;
137 if (copy_from_user(bo_handles, user_bo_handles,
138 exbuf->num_bo_handles * sizeof(uint32_t))) {
139 ret = -EFAULT;
140 kvfree(bo_handles);
141 kvfree(buflist);
142 return ret;
143 }
144
145 for (i = 0; i < exbuf->num_bo_handles; i++) {
146 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]);
147 if (!gobj) {
148 kvfree(bo_handles);
149 kvfree(buflist);
150 return -ENOENT;
151 }
152
153 qobj = gem_to_virtio_gpu_obj(gobj);
154 buflist[i].bo = &qobj->tbo;
155
156 list_add(&buflist[i].head, &validate_list);
157 }
158 kvfree(bo_handles);
159 }
160
161 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
162 if (ret)
163 goto out_free;
164
165 buf = memdup_user((void __user *)(uintptr_t)exbuf->command,
166 exbuf->size);
167 if (IS_ERR(buf)) {
168 ret = PTR_ERR(buf);
169 goto out_unresv;
170 }
171 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
172 vfpriv->ctx_id, &fence);
173
174 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
175
176 /* fence the command bo */
177 virtio_gpu_unref_list(&validate_list);
178 kvfree(buflist);
179 dma_fence_put(&fence->f);
180 return 0;
181
182out_unresv:
183 ttm_eu_backoff_reservation(&ticket, &validate_list);
184out_free:
185 virtio_gpu_unref_list(&validate_list);
186 kvfree(buflist);
187 return ret;
188}
189
190static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
191 struct drm_file *file_priv)
192{
193 struct virtio_gpu_device *vgdev = dev->dev_private;
194 struct drm_virtgpu_getparam *param = data;
195 int value;
196
197 switch (param->param) {
198 case VIRTGPU_PARAM_3D_FEATURES:
199 value = vgdev->has_virgl_3d == true ? 1 : 0;
200 break;
201 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
202 value = 1;
203 break;
204 default:
205 return -EINVAL;
206 }
207 if (copy_to_user((void __user *)(unsigned long)param->value,
208 &value, sizeof(int))) {
209 return -EFAULT;
210 }
211 return 0;
212}
213
214static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
215 struct drm_file *file_priv)
216{
217 struct virtio_gpu_device *vgdev = dev->dev_private;
218 struct drm_virtgpu_resource_create *rc = data;
219 int ret;
220 uint32_t res_id;
221 struct virtio_gpu_object *qobj;
222 struct drm_gem_object *obj;
223 uint32_t handle = 0;
224 uint32_t size;
225 struct list_head validate_list;
226 struct ttm_validate_buffer mainbuf;
227 struct virtio_gpu_fence *fence = NULL;
228 struct ww_acquire_ctx ticket;
229 struct virtio_gpu_resource_create_3d rc_3d;
230
231 if (vgdev->has_virgl_3d == false) {
232 if (rc->depth > 1)
233 return -EINVAL;
234 if (rc->nr_samples > 1)
235 return -EINVAL;
236 if (rc->last_level > 1)
237 return -EINVAL;
238 if (rc->target != 2)
239 return -EINVAL;
240 if (rc->array_size > 1)
241 return -EINVAL;
242 }
243
244 INIT_LIST_HEAD(&validate_list);
245 memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
246
247 virtio_gpu_resource_id_get(vgdev, &res_id);
248
249 size = rc->size;
250
251 /* allocate a single page size object */
252 if (size == 0)
253 size = PAGE_SIZE;
254
255 qobj = virtio_gpu_alloc_object(dev, size, false, false);
256 if (IS_ERR(qobj)) {
257 ret = PTR_ERR(qobj);
258 goto fail_id;
259 }
260 obj = &qobj->gem_base;
261
262 if (!vgdev->has_virgl_3d) {
263 virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format,
264 rc->width, rc->height);
265
266 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL);
267 } else {
268 /* use a gem reference since unref list undoes them */
269 drm_gem_object_get(&qobj->gem_base);
270 mainbuf.bo = &qobj->tbo;
271 list_add(&mainbuf.head, &validate_list);
272
273 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
274 if (ret) {
275 DRM_DEBUG("failed to validate\n");
276 goto fail_unref;
277 }
278
279 rc_3d.resource_id = cpu_to_le32(res_id);
280 rc_3d.target = cpu_to_le32(rc->target);
281 rc_3d.format = cpu_to_le32(rc->format);
282 rc_3d.bind = cpu_to_le32(rc->bind);
283 rc_3d.width = cpu_to_le32(rc->width);
284 rc_3d.height = cpu_to_le32(rc->height);
285 rc_3d.depth = cpu_to_le32(rc->depth);
286 rc_3d.array_size = cpu_to_le32(rc->array_size);
287 rc_3d.last_level = cpu_to_le32(rc->last_level);
288 rc_3d.nr_samples = cpu_to_le32(rc->nr_samples);
289 rc_3d.flags = cpu_to_le32(rc->flags);
290
291 virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL);
292 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence);
293 if (ret) {
294 ttm_eu_backoff_reservation(&ticket, &validate_list);
295 goto fail_unref;
296 }
297 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
298 }
299
300 qobj->hw_res_handle = res_id;
301
302 ret = drm_gem_handle_create(file_priv, obj, &handle);
303 if (ret) {
304
305 drm_gem_object_release(obj);
306 if (vgdev->has_virgl_3d) {
307 virtio_gpu_unref_list(&validate_list);
308 dma_fence_put(&fence->f);
309 }
310 return ret;
311 }
312 drm_gem_object_put_unlocked(obj);
313
314 rc->res_handle = res_id; /* similiar to a VM address */
315 rc->bo_handle = handle;
316
317 if (vgdev->has_virgl_3d) {
318 virtio_gpu_unref_list(&validate_list);
319 dma_fence_put(&fence->f);
320 }
321 return 0;
322fail_unref:
323 if (vgdev->has_virgl_3d) {
324 virtio_gpu_unref_list(&validate_list);
325 dma_fence_put(&fence->f);
326 }
327//fail_obj:
328// drm_gem_object_handle_unreference_unlocked(obj);
329fail_id:
330 virtio_gpu_resource_id_put(vgdev, res_id);
331 return ret;
332}
333
334static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
335 struct drm_file *file_priv)
336{
337 struct drm_virtgpu_resource_info *ri = data;
338 struct drm_gem_object *gobj = NULL;
339 struct virtio_gpu_object *qobj = NULL;
340
341 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
342 if (gobj == NULL)
343 return -ENOENT;
344
345 qobj = gem_to_virtio_gpu_obj(gobj);
346
347 ri->size = qobj->gem_base.size;
348 ri->res_handle = qobj->hw_res_handle;
349 drm_gem_object_put_unlocked(gobj);
350 return 0;
351}
352
353static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
354 void *data,
355 struct drm_file *file)
356{
357 struct virtio_gpu_device *vgdev = dev->dev_private;
358 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
359 struct drm_virtgpu_3d_transfer_from_host *args = data;
360 struct ttm_operation_ctx ctx = { true, false };
361 struct drm_gem_object *gobj = NULL;
362 struct virtio_gpu_object *qobj = NULL;
363 struct virtio_gpu_fence *fence;
364 int ret;
365 u32 offset = args->offset;
366 struct virtio_gpu_box box;
367
368 if (vgdev->has_virgl_3d == false)
369 return -ENOSYS;
370
371 gobj = drm_gem_object_lookup(file, args->bo_handle);
372 if (gobj == NULL)
373 return -ENOENT;
374
375 qobj = gem_to_virtio_gpu_obj(gobj);
376
377 ret = virtio_gpu_object_reserve(qobj, false);
378 if (ret)
379 goto out;
380
381 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
382 if (unlikely(ret))
383 goto out_unres;
384
385 convert_to_hw_box(&box, &args->box);
386 virtio_gpu_cmd_transfer_from_host_3d
387 (vgdev, qobj->hw_res_handle,
388 vfpriv->ctx_id, offset, args->level,
389 &box, &fence);
390 reservation_object_add_excl_fence(qobj->tbo.resv,
391 &fence->f);
392
393 dma_fence_put(&fence->f);
394out_unres:
395 virtio_gpu_object_unreserve(qobj);
396out:
397 drm_gem_object_put_unlocked(gobj);
398 return ret;
399}
400
401static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
402 struct drm_file *file)
403{
404 struct virtio_gpu_device *vgdev = dev->dev_private;
405 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
406 struct drm_virtgpu_3d_transfer_to_host *args = data;
407 struct ttm_operation_ctx ctx = { true, false };
408 struct drm_gem_object *gobj = NULL;
409 struct virtio_gpu_object *qobj = NULL;
410 struct virtio_gpu_fence *fence;
411 struct virtio_gpu_box box;
412 int ret;
413 u32 offset = args->offset;
414
415 gobj = drm_gem_object_lookup(file, args->bo_handle);
416 if (gobj == NULL)
417 return -ENOENT;
418
419 qobj = gem_to_virtio_gpu_obj(gobj);
420
421 ret = virtio_gpu_object_reserve(qobj, false);
422 if (ret)
423 goto out;
424
425 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
426 if (unlikely(ret))
427 goto out_unres;
428
429 convert_to_hw_box(&box, &args->box);
430 if (!vgdev->has_virgl_3d) {
431 virtio_gpu_cmd_transfer_to_host_2d
432 (vgdev, qobj->hw_res_handle, offset,
433 box.w, box.h, box.x, box.y, NULL);
434 } else {
435 virtio_gpu_cmd_transfer_to_host_3d
436 (vgdev, qobj->hw_res_handle,
437 vfpriv ? vfpriv->ctx_id : 0, offset,
438 args->level, &box, &fence);
439 reservation_object_add_excl_fence(qobj->tbo.resv,
440 &fence->f);
441 dma_fence_put(&fence->f);
442 }
443
444out_unres:
445 virtio_gpu_object_unreserve(qobj);
446out:
447 drm_gem_object_put_unlocked(gobj);
448 return ret;
449}
450
451static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
452 struct drm_file *file)
453{
454 struct drm_virtgpu_3d_wait *args = data;
455 struct drm_gem_object *gobj = NULL;
456 struct virtio_gpu_object *qobj = NULL;
457 int ret;
458 bool nowait = false;
459
460 gobj = drm_gem_object_lookup(file, args->handle);
461 if (gobj == NULL)
462 return -ENOENT;
463
464 qobj = gem_to_virtio_gpu_obj(gobj);
465
466 if (args->flags & VIRTGPU_WAIT_NOWAIT)
467 nowait = true;
468 ret = virtio_gpu_object_wait(qobj, nowait);
469
470 drm_gem_object_put_unlocked(gobj);
471 return ret;
472}
473
474static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
475 void *data, struct drm_file *file)
476{
477 struct virtio_gpu_device *vgdev = dev->dev_private;
478 struct drm_virtgpu_get_caps *args = data;
479 unsigned size, host_caps_size;
480 int i;
481 int found_valid = -1;
482 int ret;
483 struct virtio_gpu_drv_cap_cache *cache_ent;
484 void *ptr;
485
486 if (vgdev->num_capsets == 0)
487 return -ENOSYS;
488
489 /* don't allow userspace to pass 0 */
490 if (args->size == 0)
491 return -EINVAL;
492
493 spin_lock(&vgdev->display_info_lock);
494 for (i = 0; i < vgdev->num_capsets; i++) {
495 if (vgdev->capsets[i].id == args->cap_set_id) {
496 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
497 found_valid = i;
498 break;
499 }
500 }
501 }
502
503 if (found_valid == -1) {
504 spin_unlock(&vgdev->display_info_lock);
505 return -EINVAL;
506 }
507
508 host_caps_size = vgdev->capsets[found_valid].max_size;
509 /* only copy to user the minimum of the host caps size or the guest caps size */
510 size = min(args->size, host_caps_size);
511
512 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
513 if (cache_ent->id == args->cap_set_id &&
514 cache_ent->version == args->cap_set_ver) {
515 ptr = cache_ent->caps_cache;
516 spin_unlock(&vgdev->display_info_lock);
517 goto copy_exit;
518 }
519 }
520 spin_unlock(&vgdev->display_info_lock);
521
522 /* not in cache - need to talk to hw */
523 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
524 &cache_ent);
525
526 ret = wait_event_timeout(vgdev->resp_wq,
527 atomic_read(&cache_ent->is_valid), 5 * HZ);
528 if (!ret)
529 return -EBUSY;
530
531 ptr = cache_ent->caps_cache;
532
533copy_exit:
534 if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size))
535 return -EFAULT;
536
537 return 0;
538}
539
540struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
541 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
542 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
543
544 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
545 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
546
547 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
548 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
549
550 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
551 virtio_gpu_resource_create_ioctl,
552 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
553
554 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
555 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
556
557 /* make transfer async to the main ring? - no sure, can we
558 * thread these in the underlying GL
559 */
560 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
561 virtio_gpu_transfer_from_host_ioctl,
562 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
563 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
564 virtio_gpu_transfer_to_host_ioctl,
565 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
566
567 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
568 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
569
570 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
571 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
572};