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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Novatek NT35510 panel driver
4 * Copyright (C) 2020 Linus Walleij <linus.walleij@linaro.org>
5 * Based on code by Robert Teather (C) 2012 Samsung
6 *
7 * This display driver (and I refer to the physical component NT35510,
8 * not this Linux kernel software driver) can handle:
9 * 480x864, 480x854, 480x800, 480x720 and 480x640 pixel displays.
10 * It has 480x840x24bit SRAM embedded for storing a frame.
11 * When powered on the display is by default in 480x800 mode.
12 *
13 * The actual panels using this component have different names, but
14 * the code needed to set up and configure the panel will be similar,
15 * so they should all use the NT35510 driver with appropriate configuration
16 * per-panel, e.g. for physical size.
17 *
18 * This driver is for the DSI interface to panels using the NT35510.
19 *
20 * The NT35510 can also use an RGB (DPI) interface combined with an
21 * I2C or SPI interface for setting up the NT35510. If this is needed
22 * this panel driver should be refactored to also support that use
23 * case.
24 */
25#include <linux/backlight.h>
26#include <linux/bitops.h>
27#include <linux/gpio/consumer.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/regmap.h>
31#include <linux/regulator/consumer.h>
32
33#include <video/mipi_display.h>
34
35#include <drm/drm_mipi_dsi.h>
36#include <drm/drm_modes.h>
37#include <drm/drm_panel.h>
38
39#define NT35510_CMD_CORRECT_GAMMA BIT(0)
40#define NT35510_CMD_CONTROL_DISPLAY BIT(1)
41#define NT35510_CMD_SETVCMOFF BIT(2)
42
43#define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */
44#define MCS_CMD_READ_ID1 0xDA
45#define MCS_CMD_READ_ID2 0xDB
46#define MCS_CMD_READ_ID3 0xDC
47#define MCS_CMD_MTP_READ_SETTING 0xF8 /* Uncertain about name */
48#define MCS_CMD_MTP_READ_PARAM 0xFF /* Uncertain about name */
49
50/*
51 * These manufacturer commands are available after we enable manufacturer
52 * command set (MCS) for page 0.
53 */
54#define NT35510_P0_DOPCTR 0xB1
55#define NT35510_P0_SDHDTCTR 0xB6
56#define NT35510_P0_GSEQCTR 0xB7
57#define NT35510_P0_SDEQCTR 0xB8
58#define NT35510_P0_SDVPCTR 0xBA
59#define NT35510_P0_DPFRCTR1 0xBD
60#define NT35510_P0_DPFRCTR2 0xBE
61#define NT35510_P0_DPFRCTR3 0xBF
62#define NT35510_P0_DPMCTR12 0xCC
63
64#define NT35510_P0_DOPCTR_LEN 2
65#define NT35510_P0_GSEQCTR_LEN 2
66#define NT35510_P0_SDEQCTR_LEN 4
67#define NT35510_P0_SDVPCTR_LEN 1
68#define NT35510_P0_DPFRCTR1_LEN 5
69#define NT35510_P0_DPFRCTR2_LEN 5
70#define NT35510_P0_DPFRCTR3_LEN 5
71#define NT35510_P0_DPMCTR12_LEN 3
72
73#define NT35510_DOPCTR_0_RAMKP BIT(7) /* Contents kept in sleep */
74#define NT35510_DOPCTR_0_DSITE BIT(6) /* Enable TE signal */
75#define NT35510_DOPCTR_0_DSIG BIT(5) /* Enable generic read/write */
76#define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */
77#define NT35510_DOPCTR_0_EOTP BIT(3) /* Support EoTP */
78#define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */
79#define NT35510_DOPCTR_1_TW_PWR_SEL BIT(4) /* TE power selector */
80#define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */
81#define NT35510_DOPCTR_1_CTB BIT(2) /* Vertical scanning direction */
82#define NT35510_DOPCTR_1_CRL BIT(1) /* Source driver data shift */
83#define NT35510_P0_SDVPCTR_PRG BIT(2) /* 0 = normal operation, 1 = VGLO */
84#define NT35510_P0_SDVPCTR_AVDD 0 /* source driver output = AVDD */
85#define NT35510_P0_SDVPCTR_OFFCOL 1 /* source driver output = off color */
86#define NT35510_P0_SDVPCTR_AVSS 2 /* source driver output = AVSS */
87#define NT35510_P0_SDVPCTR_HI_Z 3 /* source driver output = High impedance */
88
89/*
90 * These manufacturer commands are available after we enable manufacturer
91 * command set (MCS) for page 1.
92 */
93#define NT35510_P1_SETAVDD 0xB0
94#define NT35510_P1_SETAVEE 0xB1
95#define NT35510_P1_SETVCL 0xB2
96#define NT35510_P1_SETVGH 0xB3
97#define NT35510_P1_SETVRGH 0xB4
98#define NT35510_P1_SETVGL 0xB5
99#define NT35510_P1_BT1CTR 0xB6
100#define NT35510_P1_BT2CTR 0xB7
101#define NT35510_P1_BT3CTR 0xB8
102#define NT35510_P1_BT4CTR 0xB9 /* VGH boosting times/freq */
103#define NT35510_P1_BT5CTR 0xBA
104#define NT35510_P1_PFMCTR 0xBB
105#define NT35510_P1_SETVGP 0xBC
106#define NT35510_P1_SETVGN 0xBD
107#define NT35510_P1_SETVCMOFF 0xBE
108#define NT35510_P1_VGHCTR 0xBF /* VGH output ctrl */
109#define NT35510_P1_SET_GAMMA_RED_POS 0xD1
110#define NT35510_P1_SET_GAMMA_GREEN_POS 0xD2
111#define NT35510_P1_SET_GAMMA_BLUE_POS 0xD3
112#define NT35510_P1_SET_GAMMA_RED_NEG 0xD4
113#define NT35510_P1_SET_GAMMA_GREEN_NEG 0xD5
114#define NT35510_P1_SET_GAMMA_BLUE_NEG 0xD6
115
116/* AVDD and AVEE setting 3 bytes */
117#define NT35510_P1_AVDD_LEN 3
118#define NT35510_P1_AVEE_LEN 3
119#define NT35510_P1_VCL_LEN 3
120#define NT35510_P1_VGH_LEN 3
121#define NT35510_P1_VGL_LEN 3
122#define NT35510_P1_VGP_LEN 3
123#define NT35510_P1_VGN_LEN 3
124#define NT35510_P1_VCMOFF_LEN 2
125/* BT1CTR thru BT5CTR setting 3 bytes */
126#define NT35510_P1_BT1CTR_LEN 3
127#define NT35510_P1_BT2CTR_LEN 3
128#define NT35510_P1_BT3CTR_LEN 3
129#define NT35510_P1_BT4CTR_LEN 3
130#define NT35510_P1_BT5CTR_LEN 3
131/* 52 gamma parameters times two per color: positive and negative */
132#define NT35510_P1_GAMMA_LEN 52
133
134#define NT35510_WRCTRLD_BCTRL BIT(5)
135#define NT35510_WRCTRLD_A BIT(4)
136#define NT35510_WRCTRLD_DD BIT(3)
137#define NT35510_WRCTRLD_BL BIT(2)
138#define NT35510_WRCTRLD_DB BIT(1)
139#define NT35510_WRCTRLD_G BIT(0)
140
141#define NT35510_WRCABC_OFF 0
142#define NT35510_WRCABC_UI_MODE 1
143#define NT35510_WRCABC_STILL_MODE 2
144#define NT35510_WRCABC_MOVING_MODE 3
145
146/**
147 * struct nt35510_config - the display-specific NT35510 configuration
148 *
149 * Some of the settings provide an array of bytes, A, B C which mean:
150 * A = normal / idle off mode
151 * B = idle on mode
152 * C = partial / idle off mode
153 *
154 * Gamma correction arrays are 10bit numbers, two consecutive bytes
155 * makes out one point on the gamma correction curve. The points are
156 * not linearly placed along the X axis, we get points 0, 1, 3, 5
157 * 7, 11, 15, 23, 31, 47, 63, 95, 127, 128, 160, 192, 208, 224, 232,
158 * 240, 244, 248, 250, 252, 254, 255. The voltages tuples form
159 * V0, V1, V3 ... V255, with 0x0000 being the lowest voltage and
160 * 0x03FF being the highest voltage.
161 *
162 * Each value must be strictly higher than the previous value forming
163 * a rising curve like this:
164 *
165 * ^
166 * | V255
167 * | V254
168 * | ....
169 * | V5
170 * | V3
171 * | V1
172 * | V0
173 * +------------------------------------------->
174 *
175 * The details about all settings can be found in the NT35510 Application
176 * Note.
177 */
178struct nt35510_config {
179 /**
180 * @width_mm: physical panel width [mm]
181 */
182 u32 width_mm;
183 /**
184 * @height_mm: physical panel height [mm]
185 */
186 u32 height_mm;
187 /**
188 * @mode: the display mode. This is only relevant outside the panel
189 * in video mode: in command mode this is configuring the internal
190 * timing in the display controller.
191 */
192 const struct drm_display_mode mode;
193 /**
194 * @mode_flags: DSI operation mode related flags
195 */
196 unsigned long mode_flags;
197 /**
198 * @cmds: enable DSI commands
199 */
200 u32 cmds;
201 /**
202 * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
203 * in 0.1V steps the default is 0x05 which means 6.0V
204 */
205 u8 avdd[NT35510_P1_AVDD_LEN];
206 /**
207 * @bt1ctr: setting for boost power control for the AVDD step-up
208 * circuit (1)
209 * bits 0..2 in the lower nibble controls PCK, the booster clock
210 * frequency for the step-up circuit:
211 * 0 = Hsync/32
212 * 1 = Hsync/16
213 * 2 = Hsync/8
214 * 3 = Hsync/4
215 * 4 = Hsync/2
216 * 5 = Hsync
217 * 6 = Hsync x 2
218 * 7 = Hsync x 4
219 * bits 4..6 in the upper nibble controls BTP, the boosting
220 * amplification for the step-up circuit:
221 * 0 = Disable
222 * 1 = 1.5 x VDDB
223 * 2 = 1.66 x VDDB
224 * 3 = 2 x VDDB
225 * 4 = 2.5 x VDDB
226 * 5 = 3 x VDDB
227 * The defaults are 4 and 4 yielding 0x44
228 */
229 u8 bt1ctr[NT35510_P1_BT1CTR_LEN];
230 /**
231 * @avee: setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V
232 * in 0.1V steps the default is 0x05 which means -6.0V
233 */
234 u8 avee[NT35510_P1_AVEE_LEN];
235 /**
236 * @bt2ctr: setting for boost power control for the AVEE step-up
237 * circuit (2)
238 * bits 0..2 in the lower nibble controls NCK, the booster clock
239 * frequency, the values are the same as for PCK in @bt1ctr.
240 * bits 4..5 in the upper nibble controls BTN, the boosting
241 * amplification for the step-up circuit.
242 * 0 = Disable
243 * 1 = -1.5 x VDDB
244 * 2 = -2 x VDDB
245 * 3 = -2.5 x VDDB
246 * 4 = -3 x VDDB
247 * The defaults are 4 and 3 yielding 0x34
248 */
249 u8 bt2ctr[NT35510_P1_BT2CTR_LEN];
250 /**
251 * @vcl: setting for VCL ranging from 0x00 = -2.5V to 0x11 = -4.0V
252 * in 1V steps, the default is 0x00 which means -2.5V
253 */
254 u8 vcl[NT35510_P1_VCL_LEN];
255 /**
256 * @bt3ctr: setting for boost power control for the VCL step-up
257 * circuit (3)
258 * bits 0..2 in the lower nibble controls CLCK, the booster clock
259 * frequency, the values are the same as for PCK in @bt1ctr.
260 * bits 4..5 in the upper nibble controls BTCL, the boosting
261 * amplification for the step-up circuit.
262 * 0 = Disable
263 * 1 = -0.5 x VDDB
264 * 2 = -1 x VDDB
265 * 3 = -2 x VDDB
266 * The defaults are 4 and 2 yielding 0x24
267 */
268 u8 bt3ctr[NT35510_P1_BT3CTR_LEN];
269 /**
270 * @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V
271 * in 1V steps, the default is 0x08 which means 15V
272 */
273 u8 vgh[NT35510_P1_VGH_LEN];
274 /**
275 * @bt4ctr: setting for boost power control for the VGH step-up
276 * circuit (4)
277 * bits 0..2 in the lower nibble controls HCK, the booster clock
278 * frequency, the values are the same as for PCK in @bt1ctr.
279 * bits 4..5 in the upper nibble controls BTH, the boosting
280 * amplification for the step-up circuit.
281 * 0 = AVDD + VDDB
282 * 1 = AVDD - AVEE
283 * 2 = AVDD - AVEE + VDDB
284 * 3 = AVDD x 2 - AVEE
285 * The defaults are 4 and 3 yielding 0x34
286 */
287 u8 bt4ctr[NT35510_P1_BT4CTR_LEN];
288 /**
289 * @vgl: setting for VGL ranging from 0x00 = -2V to 0x0f = -15V in
290 * 1V steps, the default is 0x08 which means -10V
291 */
292 u8 vgl[NT35510_P1_VGL_LEN];
293 /**
294 * @bt5ctr: setting for boost power control for the VGL step-up
295 * circuit (5)
296 * bits 0..2 in the lower nibble controls LCK, the booster clock
297 * frequency, the values are the same as for PCK in @bt1ctr.
298 * bits 4..5 in the upper nibble controls BTL, the boosting
299 * amplification for the step-up circuit.
300 * 0 = AVEE + VCL
301 * 1 = AVEE - AVDD
302 * 2 = AVEE + VCL - AVDD
303 * 3 = AVEE x 2 - AVDD
304 * The defaults are 3 and 2 yielding 0x32
305 */
306 u8 bt5ctr[NT35510_P1_BT5CTR_LEN];
307 /**
308 * @vgp: setting for VGP, the positive gamma divider voltages
309 * VGMP the high voltage and VGSP the low voltage.
310 * The first byte contains bit 8 of VGMP and VGSP in bits 4 and 0
311 * The second byte contains bit 0..7 of VGMP
312 * The third byte contains bit 0..7 of VGSP
313 * VGMP 0x00 = 3.0V .. 0x108 = 6.3V in steps of 12.5mV
314 * VGSP 0x00 = 0V .. 0x111 = 3.7V in steps of 12.5mV
315 */
316 u8 vgp[NT35510_P1_VGP_LEN];
317 /**
318 * @vgn: setting for VGN, the negative gamma divider voltages,
319 * same layout of bytes as @vgp.
320 */
321 u8 vgn[NT35510_P1_VGN_LEN];
322 /**
323 * @vcmoff: setting the DC VCOM offset voltage
324 * The first byte contains bit 8 of VCM in bit 0 and VCMOFFSEL in bit 4.
325 * The second byte contains bits 0..7 of VCM.
326 * VCMOFFSEL the common voltage offset mode.
327 * VCMOFFSEL 0x00 = VCOM .. 0x01 Gamma.
328 * The default is 0x00.
329 * VCM the VCOM output voltage (VCMOFFSEL = 0) or the internal register
330 * offset for gamma voltage (VCMOFFSEL = 1).
331 * VCM 0x00 = 0V/0 .. 0x118 = 3.5V/280 in steps of 12.5mV/1step
332 * The default is 0x00 = 0V/0.
333 */
334 u8 vcmoff[NT35510_P1_VCMOFF_LEN];
335 /**
336 * @dopctr: setting optional control for display
337 * ERR bits 0..1 in the first byte is the ERR pin output signal setting.
338 * 0 = Disable, ERR pin output low
339 * 1 = ERR pin output CRC error only
340 * 2 = ERR pin output ECC error only
341 * 3 = ERR pin output CRC and ECC error
342 * The default is 0.
343 * N565 bit 2 in the first byte is the 16-bit/pixel format selection.
344 * 0 = R[4:0] + G[5:3] & G[2:0] + B[4:0]
345 * 1 = G[2:0] + R[4:0] & B[4:0] + G[5:3]
346 * The default is 0.
347 * DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error
348 * reporting.
349 * 0 = reporting when error
350 * 1 = not reporting when error
351 * DSIM bit 4 in the first byte is the video mode data type enable
352 * 0 = Video mode data type disable
353 * 1 = Video mode data type enable
354 * The default is 0.
355 * DSIG bit 5 int the first byte is the generic r/w data type enable
356 * 0 = Generic r/w disable
357 * 1 = Generic r/w enable
358 * The default is 0.
359 * DSITE bit 6 in the first byte is TE line enable
360 * 0 = TE line is disabled
361 * 1 = TE line is enabled
362 * The default is 0.
363 * RAMKP bit 7 in the first byte is the frame memory keep/loss in
364 * sleep-in mode
365 * 0 = contents loss in sleep-in
366 * 1 = contents keep in sleep-in
367 * The default is 0.
368 * CRL bit 1 in the second byte is the source driver data shift
369 * direction selection. This bit is XOR operation with bit RSMX
370 * of 3600h command.
371 * 0 (RMSX = 0) = S1 -> S1440
372 * 0 (RMSX = 1) = S1440 -> S1
373 * 1 (RMSX = 0) = S1440 -> S1
374 * 1 (RMSX = 1) = S1 -> S1440
375 * The default is 0.
376 * CTB bit 2 in the second byte is the vertical scanning direction
377 * selection for gate control signals. This bit is XOR operation
378 * with bit ML of 3600h command.
379 * 0 (ML = 0) = Forward (top -> bottom)
380 * 0 (ML = 1) = Reverse (bottom -> top)
381 * 1 (ML = 0) = Reverse (bottom -> top)
382 * 1 (ML = 1) = Forward (top -> bottom)
383 * The default is 0.
384 * CRGB bit 3 in the second byte is RGB-BGR order selection. This
385 * bit is XOR operation with bit RGB of 3600h command.
386 * 0 (RGB = 0) = RGB/Normal
387 * 0 (RGB = 1) = BGR/RB swap
388 * 1 (RGB = 0) = BGR/RB swap
389 * 1 (RGB = 1) = RGB/Normal
390 * The default is 0.
391 * TE_PWR_SEL bit 4 in the second byte is the TE output voltage
392 * level selection (only valid when DSTB_SEL = 0 or DSTB_SEL = 1,
393 * VSEL = High and VDDI = 1.665~3.3V).
394 * 0 = TE output voltage level is VDDI
395 * 1 = TE output voltage level is VDDA
396 * The default is 0.
397 */
398 u8 dopctr[NT35510_P0_DOPCTR_LEN];
399 /**
400 * @madctl: Memory data access control
401 * RSMY bit 0 is flip vertical. Flips the display image top to down.
402 * RSMX bit 1 is flip horizontal. Flips the display image left to right.
403 * MH bit 2 is the horizontal refresh order.
404 * RGB bit 3 is the RGB-BGR order.
405 * 0 = RGB color sequence
406 * 1 = BGR color sequence
407 * ML bit 4 is the vertical refresh order.
408 * MV bit 5 is the row/column exchange.
409 * MX bit 6 is the column address order.
410 * MY bit 7 is the row address order.
411 */
412 u8 madctl;
413 /**
414 * @sdhdtctr: source output data hold time
415 * 0x00..0x3F = 0..31.5us in steps of 0.5us
416 * The default is 0x05 = 2.5us.
417 */
418 u8 sdhdtctr;
419 /**
420 * @gseqctr: EQ control for gate signals
421 * GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps
422 * of 0.5us.
423 * The default is 0x07 = 3.5us
424 * GREQ_XX[7:4]: time setting of EQ step for rising edge in steps
425 * of 0.5us.
426 * The default is 0x07 = 3.5us
427 */
428 u8 gseqctr[NT35510_P0_GSEQCTR_LEN];
429 /**
430 * @sdeqctr: Source driver control settings, first byte is
431 * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and
432 * mode 2 uses three steps meaning EQS3 is not used in mode
433 * 1. Mode 2 is default. The last three parameters are EQS1, EQS2
434 * and EQS3, setting the rise time for each equalizer step:
435 * 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default
436 * is 0x07 = 3.5 us.
437 */
438 u8 sdeqctr[NT35510_P0_SDEQCTR_LEN];
439 /**
440 * @sdvpctr: power/voltage behaviour during vertical porch time
441 */
442 u8 sdvpctr;
443 /**
444 * @t1: the number of pixel clocks on one scanline, range
445 * 0x100 (258 ticks) .. 0x3FF (1024 ticks) so the value + 1
446 * clock ticks.
447 */
448 u16 t1;
449 /**
450 * @vbp: vertical back porch toward the PANEL note: not toward
451 * the DSI host; these are separate interfaces, in from DSI host
452 * and out to the panel.
453 */
454 u8 vbp;
455 /**
456 * @vfp: vertical front porch toward the PANEL.
457 */
458 u8 vfp;
459 /**
460 * @psel: pixel clock divisor: 0 = 1, 1 = 2, 2 = 4, 3 = 8.
461 */
462 u8 psel;
463 /**
464 * @dpmctr12: Display timing control 12
465 * Byte 1 bit 4 selects LVGL voltage level: 0 = VGLX, 1 = VGL_REG
466 * Byte 1 bit 1 selects gate signal mode: 0 = non-overlap, 1 = overlap
467 * Byte 1 bit 0 selects output signal control R/L swap, 0 = normal
468 * 1 = swap all O->E, L->R
469 * Byte 2 is CLW delay clock for CK O/E and CKB O/E signals:
470 * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
471 * Byte 3 is FTI_H0 delay time for STP O/E signals:
472 * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
473 */
474 u8 dpmctr12[NT35510_P0_DPMCTR12_LEN];
475 /**
476 * @gamma_corr_pos_r: Red gamma correction parameters, positive
477 */
478 u8 gamma_corr_pos_r[NT35510_P1_GAMMA_LEN];
479 /**
480 * @gamma_corr_pos_g: Green gamma correction parameters, positive
481 */
482 u8 gamma_corr_pos_g[NT35510_P1_GAMMA_LEN];
483 /**
484 * @gamma_corr_pos_b: Blue gamma correction parameters, positive
485 */
486 u8 gamma_corr_pos_b[NT35510_P1_GAMMA_LEN];
487 /**
488 * @gamma_corr_neg_r: Red gamma correction parameters, negative
489 */
490 u8 gamma_corr_neg_r[NT35510_P1_GAMMA_LEN];
491 /**
492 * @gamma_corr_neg_g: Green gamma correction parameters, negative
493 */
494 u8 gamma_corr_neg_g[NT35510_P1_GAMMA_LEN];
495 /**
496 * @gamma_corr_neg_b: Blue gamma correction parameters, negative
497 */
498 u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN];
499 /**
500 * @wrdisbv: write display brightness
501 * 0x00 value means the lowest brightness and 0xff value means
502 * the highest brightness.
503 * The default is 0x00.
504 */
505 u8 wrdisbv;
506 /**
507 * @wrctrld: write control display
508 * G bit 0 selects gamma curve: 0 = Manual, 1 = Automatic
509 * DB bit 1 selects display brightness: 0 = Manual, 1 = Automatic
510 * BL bit 2 controls backlight control: 0 = Off, 1 = On
511 * DD bit 3 controls display dimming: 0 = Off, 1 = On
512 * A bit 4 controls LABC block: 0 = Off, 1 = On
513 * BCTRL bit 5 controls brightness block: 0 = Off, 1 = On
514 */
515 u8 wrctrld;
516 /**
517 * @wrcabc: write content adaptive brightness control
518 * There is possible to use 4 different modes for content adaptive
519 * image functionality:
520 * 0: Off
521 * 1: User Interface Image (UI-Mode)
522 * 2: Still Picture Image (Still-Mode)
523 * 3: Moving Picture Image (Moving-Mode)
524 * The default is 0
525 */
526 u8 wrcabc;
527 /**
528 * @wrcabcmb: write CABC minimum brightness
529 * Set the minimum brightness value of the display for CABC
530 * function.
531 * 0x00 value means the lowest brightness for CABC and 0xff
532 * value means the highest brightness for CABC.
533 * The default is 0x00.
534 */
535 u8 wrcabcmb;
536};
537
538/**
539 * struct nt35510 - state container for the NT35510 panel
540 */
541struct nt35510 {
542 /**
543 * @dev: the container device
544 */
545 struct device *dev;
546 /**
547 * @conf: the specific panel configuration, as the NT35510
548 * can be combined with many physical panels, they can have
549 * different physical dimensions and gamma correction etc,
550 * so this is stored in the config.
551 */
552 const struct nt35510_config *conf;
553 /**
554 * @panel: the DRM panel object for the instance
555 */
556 struct drm_panel panel;
557 /**
558 * @supplies: regulators supplying the panel
559 */
560 struct regulator_bulk_data supplies[2];
561 /**
562 * @reset_gpio: the reset line
563 */
564 struct gpio_desc *reset_gpio;
565};
566
567/* Manufacturer command has strictly this byte sequence */
568static const u8 nt35510_mauc_mtp_read_param[] = { 0xAA, 0x55, 0x25, 0x01 };
569static const u8 nt35510_mauc_mtp_read_setting[] = { 0x01, 0x02, 0x00, 0x20,
570 0x33, 0x13, 0x00, 0x40,
571 0x00, 0x00, 0x23, 0x02 };
572static const u8 nt35510_mauc_select_page_0[] = { 0x55, 0xAA, 0x52, 0x08, 0x00 };
573static const u8 nt35510_mauc_select_page_1[] = { 0x55, 0xAA, 0x52, 0x08, 0x01 };
574static const u8 nt35510_vgh_on[] = { 0x01 };
575
576static inline struct nt35510 *panel_to_nt35510(struct drm_panel *panel)
577{
578 return container_of(panel, struct nt35510, panel);
579}
580
581#define NT35510_ROTATE_0_SETTING 0x02
582#define NT35510_ROTATE_180_SETTING 0x00
583
584static int nt35510_send_long(struct nt35510 *nt, struct mipi_dsi_device *dsi,
585 u8 cmd, u8 cmdlen, const u8 *seq)
586{
587 const u8 *seqp = seq;
588 int cmdwritten = 0;
589 int chunk = cmdlen;
590 int ret;
591
592 if (chunk > 15)
593 chunk = 15;
594 ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk);
595 if (ret < 0) {
596 dev_err(nt->dev, "error sending DCS command seq cmd %02x\n", cmd);
597 return ret;
598 }
599 cmdwritten += chunk;
600 seqp += chunk;
601
602 while (cmdwritten < cmdlen) {
603 chunk = cmdlen - cmdwritten;
604 if (chunk > 15)
605 chunk = 15;
606 ret = mipi_dsi_generic_write(dsi, seqp, chunk);
607 if (ret < 0) {
608 dev_err(nt->dev, "error sending generic write seq %02x\n", cmd);
609 return ret;
610 }
611 cmdwritten += chunk;
612 seqp += chunk;
613 }
614 dev_dbg(nt->dev, "sent command %02x %02x bytes\n", cmd, cmdlen);
615 return 0;
616}
617
618static int nt35510_read_id(struct nt35510 *nt)
619{
620 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
621 u8 id1, id2, id3;
622 int ret;
623
624 ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID1, &id1, 1);
625 if (ret < 0) {
626 dev_err(nt->dev, "could not read MTP ID1\n");
627 return ret;
628 }
629 ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID2, &id2, 1);
630 if (ret < 0) {
631 dev_err(nt->dev, "could not read MTP ID2\n");
632 return ret;
633 }
634 ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID3, &id3, 1);
635 if (ret < 0) {
636 dev_err(nt->dev, "could not read MTP ID3\n");
637 return ret;
638 }
639
640 /*
641 * Multi-Time Programmable (?) memory contains manufacturer
642 * ID (e.g. Hydis 0x55), driver ID (e.g. NT35510 0xc0) and
643 * version.
644 */
645 dev_info(nt->dev, "MTP ID manufacturer: %02x version: %02x driver: %02x\n", id1, id2, id3);
646
647 return 0;
648}
649
650/**
651 * nt35510_setup_power() - set up power config in page 1
652 * @nt: the display instance to set up
653 */
654static int nt35510_setup_power(struct nt35510 *nt)
655{
656 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
657 int ret;
658
659 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVDD,
660 NT35510_P1_AVDD_LEN,
661 nt->conf->avdd);
662 if (ret)
663 return ret;
664 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT1CTR,
665 NT35510_P1_BT1CTR_LEN,
666 nt->conf->bt1ctr);
667 if (ret)
668 return ret;
669 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVEE,
670 NT35510_P1_AVEE_LEN,
671 nt->conf->avee);
672 if (ret)
673 return ret;
674 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT2CTR,
675 NT35510_P1_BT2CTR_LEN,
676 nt->conf->bt2ctr);
677 if (ret)
678 return ret;
679 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVCL,
680 NT35510_P1_VCL_LEN,
681 nt->conf->vcl);
682 if (ret)
683 return ret;
684 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT3CTR,
685 NT35510_P1_BT3CTR_LEN,
686 nt->conf->bt3ctr);
687 if (ret)
688 return ret;
689 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGH,
690 NT35510_P1_VGH_LEN,
691 nt->conf->vgh);
692 if (ret)
693 return ret;
694 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT4CTR,
695 NT35510_P1_BT4CTR_LEN,
696 nt->conf->bt4ctr);
697 if (ret)
698 return ret;
699 ret = nt35510_send_long(nt, dsi, NT35510_P1_VGHCTR,
700 ARRAY_SIZE(nt35510_vgh_on),
701 nt35510_vgh_on);
702 if (ret)
703 return ret;
704 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGL,
705 NT35510_P1_VGL_LEN,
706 nt->conf->vgl);
707 if (ret)
708 return ret;
709 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT5CTR,
710 NT35510_P1_BT5CTR_LEN,
711 nt->conf->bt5ctr);
712 if (ret)
713 return ret;
714 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGP,
715 NT35510_P1_VGP_LEN,
716 nt->conf->vgp);
717 if (ret)
718 return ret;
719 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGN,
720 NT35510_P1_VGN_LEN,
721 nt->conf->vgn);
722 if (ret)
723 return ret;
724
725 if (nt->conf->cmds & NT35510_CMD_SETVCMOFF) {
726 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVCMOFF,
727 NT35510_P1_VCMOFF_LEN,
728 nt->conf->vcmoff);
729 if (ret)
730 return ret;
731 }
732
733 /* Typically 10 ms */
734 usleep_range(10000, 20000);
735
736 return 0;
737}
738
739/**
740 * nt35510_setup_display() - set up display config in page 0
741 * @nt: the display instance to set up
742 */
743static int nt35510_setup_display(struct nt35510 *nt)
744{
745 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
746 const struct nt35510_config *conf = nt->conf;
747 u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN];
748 int ret;
749
750 ret = nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR,
751 NT35510_P0_DOPCTR_LEN,
752 conf->dopctr);
753 if (ret)
754 return ret;
755
756 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl,
757 sizeof(conf->madctl));
758 if (ret < 0)
759 return ret;
760
761 ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &conf->sdhdtctr,
762 sizeof(conf->sdhdtctr));
763 if (ret < 0)
764 return ret;
765
766 ret = nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR,
767 NT35510_P0_GSEQCTR_LEN,
768 conf->gseqctr);
769 if (ret)
770 return ret;
771
772 ret = nt35510_send_long(nt, dsi, NT35510_P0_SDEQCTR,
773 NT35510_P0_SDEQCTR_LEN,
774 conf->sdeqctr);
775 if (ret)
776 return ret;
777
778 ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDVPCTR,
779 &conf->sdvpctr, 1);
780 if (ret < 0)
781 return ret;
782
783 /*
784 * Display timing control for active and idle off mode:
785 * the first byte contains
786 * the two high bits of T1A and second byte the low 8 bits, and
787 * the valid range is 0x100 (257) to 0x3ff (1023) representing
788 * 258..1024 (+1) pixel clock ticks for one scanline. At 20MHz pixel
789 * clock this covers the range of 12.90us .. 51.20us in steps of
790 * 0.05us, the default is 0x184 (388) representing 389 ticks.
791 * The third byte is VBPDA, vertical back porch display active
792 * and the fourth VFPDA, vertical front porch display active,
793 * both given in number of scanlines in the range 0x02..0xff
794 * for 2..255 scanlines. The fifth byte is 2 bits selecting
795 * PSEL for active and idle off mode, how much the 20MHz clock
796 * is divided by 0..3. This needs to be adjusted to get the right
797 * frame rate.
798 */
799 dpfrctr[0] = (conf->t1 >> 8) & 0xFF;
800 dpfrctr[1] = conf->t1 & 0xFF;
801 /* Vertical back porch */
802 dpfrctr[2] = conf->vbp;
803 /* Vertical front porch */
804 dpfrctr[3] = conf->vfp;
805 dpfrctr[4] = conf->psel;
806 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR1,
807 NT35510_P0_DPFRCTR1_LEN,
808 dpfrctr);
809 if (ret)
810 return ret;
811 /* For idle and partial idle off mode we decrease front porch by one */
812 dpfrctr[3]--;
813 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR2,
814 NT35510_P0_DPFRCTR2_LEN,
815 dpfrctr);
816 if (ret)
817 return ret;
818 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR3,
819 NT35510_P0_DPFRCTR3_LEN,
820 dpfrctr);
821 if (ret)
822 return ret;
823
824 /* Enable TE on vblank */
825 ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
826 if (ret)
827 return ret;
828
829 /* Turn on the pads? */
830 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPMCTR12,
831 NT35510_P0_DPMCTR12_LEN,
832 conf->dpmctr12);
833 if (ret)
834 return ret;
835
836 return 0;
837}
838
839static int nt35510_set_brightness(struct backlight_device *bl)
840{
841 struct nt35510 *nt = bl_get_data(bl);
842 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
843 u8 brightness = bl->props.brightness;
844 int ret;
845
846 dev_dbg(nt->dev, "set brightness %d\n", brightness);
847 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
848 &brightness,
849 sizeof(brightness));
850 if (ret < 0)
851 return ret;
852
853 return 0;
854}
855
856static const struct backlight_ops nt35510_bl_ops = {
857 .update_status = nt35510_set_brightness,
858};
859
860/*
861 * This power-on sequence
862 */
863static int nt35510_power_on(struct nt35510 *nt)
864{
865 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
866 int ret;
867
868 ret = regulator_bulk_enable(ARRAY_SIZE(nt->supplies), nt->supplies);
869 if (ret < 0) {
870 dev_err(nt->dev, "unable to enable regulators\n");
871 return ret;
872 }
873
874 /* Toggle RESET in accordance with datasheet page 370 */
875 if (nt->reset_gpio) {
876 gpiod_set_value(nt->reset_gpio, 1);
877 /* Active min 10 us according to datasheet, let's say 20 */
878 usleep_range(20, 1000);
879 gpiod_set_value(nt->reset_gpio, 0);
880 /*
881 * 5 ms during sleep mode, 120 ms during sleep out mode
882 * according to datasheet, let's use 120-140 ms.
883 */
884 usleep_range(120000, 140000);
885 }
886
887 ret = nt35510_send_long(nt, dsi, MCS_CMD_MTP_READ_PARAM,
888 ARRAY_SIZE(nt35510_mauc_mtp_read_param),
889 nt35510_mauc_mtp_read_param);
890 if (ret)
891 return ret;
892
893 ret = nt35510_send_long(nt, dsi, MCS_CMD_MTP_READ_SETTING,
894 ARRAY_SIZE(nt35510_mauc_mtp_read_setting),
895 nt35510_mauc_mtp_read_setting);
896 if (ret)
897 return ret;
898
899 nt35510_read_id(nt);
900
901 /* Set up stuff in manufacturer control, page 1 */
902 ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR,
903 ARRAY_SIZE(nt35510_mauc_select_page_1),
904 nt35510_mauc_select_page_1);
905 if (ret)
906 return ret;
907
908 ret = nt35510_setup_power(nt);
909 if (ret)
910 return ret;
911
912 if (nt->conf->cmds & NT35510_CMD_CORRECT_GAMMA) {
913 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS,
914 NT35510_P1_GAMMA_LEN,
915 nt->conf->gamma_corr_pos_r);
916 if (ret)
917 return ret;
918 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS,
919 NT35510_P1_GAMMA_LEN,
920 nt->conf->gamma_corr_pos_g);
921 if (ret)
922 return ret;
923 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS,
924 NT35510_P1_GAMMA_LEN,
925 nt->conf->gamma_corr_pos_b);
926 if (ret)
927 return ret;
928 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG,
929 NT35510_P1_GAMMA_LEN,
930 nt->conf->gamma_corr_neg_r);
931 if (ret)
932 return ret;
933 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG,
934 NT35510_P1_GAMMA_LEN,
935 nt->conf->gamma_corr_neg_g);
936 if (ret)
937 return ret;
938 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG,
939 NT35510_P1_GAMMA_LEN,
940 nt->conf->gamma_corr_neg_b);
941 if (ret)
942 return ret;
943 }
944
945 /* Set up stuff in manufacturer control, page 0 */
946 ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR,
947 ARRAY_SIZE(nt35510_mauc_select_page_0),
948 nt35510_mauc_select_page_0);
949 if (ret)
950 return ret;
951
952 ret = nt35510_setup_display(nt);
953 if (ret)
954 return ret;
955
956 return 0;
957}
958
959static int nt35510_power_off(struct nt35510 *nt)
960{
961 int ret;
962
963 ret = regulator_bulk_disable(ARRAY_SIZE(nt->supplies), nt->supplies);
964 if (ret)
965 return ret;
966
967 if (nt->reset_gpio)
968 gpiod_set_value(nt->reset_gpio, 1);
969
970 return 0;
971}
972
973static int nt35510_unprepare(struct drm_panel *panel)
974{
975 struct nt35510 *nt = panel_to_nt35510(panel);
976 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
977 int ret;
978
979 ret = mipi_dsi_dcs_set_display_off(dsi);
980 if (ret) {
981 dev_err(nt->dev, "failed to turn display off (%d)\n", ret);
982 return ret;
983 }
984 usleep_range(10000, 20000);
985
986 /* Enter sleep mode */
987 ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
988 if (ret) {
989 dev_err(nt->dev, "failed to enter sleep mode (%d)\n", ret);
990 return ret;
991 }
992
993 /* Wait 4 frames, how much is that 5ms in the vendor driver */
994 usleep_range(5000, 10000);
995
996 ret = nt35510_power_off(nt);
997 if (ret)
998 return ret;
999
1000 return 0;
1001}
1002
1003static int nt35510_prepare(struct drm_panel *panel)
1004{
1005 struct nt35510 *nt = panel_to_nt35510(panel);
1006 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
1007 int ret;
1008
1009 ret = nt35510_power_on(nt);
1010 if (ret)
1011 return ret;
1012
1013 /* Exit sleep mode */
1014 ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
1015 if (ret) {
1016 dev_err(nt->dev, "failed to exit sleep mode (%d)\n", ret);
1017 return ret;
1018 }
1019 /* Up to 120 ms */
1020 usleep_range(120000, 150000);
1021
1022 if (nt->conf->cmds & NT35510_CMD_CONTROL_DISPLAY) {
1023 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY,
1024 &nt->conf->wrctrld,
1025 sizeof(nt->conf->wrctrld));
1026 if (ret < 0)
1027 return ret;
1028
1029 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE,
1030 &nt->conf->wrcabc,
1031 sizeof(nt->conf->wrcabc));
1032 if (ret < 0)
1033 return ret;
1034
1035 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS,
1036 &nt->conf->wrcabcmb,
1037 sizeof(nt->conf->wrcabcmb));
1038 if (ret < 0)
1039 return ret;
1040 }
1041
1042 ret = mipi_dsi_dcs_set_display_on(dsi);
1043 if (ret) {
1044 dev_err(nt->dev, "failed to turn display on (%d)\n", ret);
1045 return ret;
1046 }
1047 /* Some 10 ms */
1048 usleep_range(10000, 20000);
1049
1050 return 0;
1051}
1052
1053static int nt35510_get_modes(struct drm_panel *panel,
1054 struct drm_connector *connector)
1055{
1056 struct nt35510 *nt = panel_to_nt35510(panel);
1057 struct drm_display_mode *mode;
1058 struct drm_display_info *info;
1059
1060 info = &connector->display_info;
1061 info->width_mm = nt->conf->width_mm;
1062 info->height_mm = nt->conf->height_mm;
1063 mode = drm_mode_duplicate(connector->dev, &nt->conf->mode);
1064 if (!mode) {
1065 dev_err(panel->dev, "bad mode or failed to add mode\n");
1066 return -EINVAL;
1067 }
1068 drm_mode_set_name(mode);
1069 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
1070
1071 mode->width_mm = nt->conf->width_mm;
1072 mode->height_mm = nt->conf->height_mm;
1073 drm_mode_probed_add(connector, mode);
1074
1075 return 1; /* Number of modes */
1076}
1077
1078static const struct drm_panel_funcs nt35510_drm_funcs = {
1079 .unprepare = nt35510_unprepare,
1080 .prepare = nt35510_prepare,
1081 .get_modes = nt35510_get_modes,
1082};
1083
1084static int nt35510_probe(struct mipi_dsi_device *dsi)
1085{
1086 struct device *dev = &dsi->dev;
1087 struct nt35510 *nt;
1088 int ret;
1089
1090 nt = devm_kzalloc(dev, sizeof(struct nt35510), GFP_KERNEL);
1091 if (!nt)
1092 return -ENOMEM;
1093 mipi_dsi_set_drvdata(dsi, nt);
1094 nt->dev = dev;
1095
1096 dsi->lanes = 2;
1097 dsi->format = MIPI_DSI_FMT_RGB888;
1098 /*
1099 * Datasheet suggests max HS rate for NT35510 is 250 MHz
1100 * (period time 4ns, see figure 7.6.4 page 365) and max LP rate is
1101 * 20 MHz (period time 50ns, see figure 7.6.6. page 366).
1102 * However these frequencies appear in source code for the Hydis
1103 * HVA40WV1 panel and setting up the LP frequency makes the panel
1104 * not work.
1105 *
1106 * TODO: if other panels prove to be closer to the datasheet,
1107 * maybe make this a per-panel config in struct nt35510_config?
1108 */
1109 dsi->hs_rate = 349440000;
1110 dsi->lp_rate = 9600000;
1111
1112 /*
1113 * Every new incarnation of this display must have a unique
1114 * data entry for the system in this driver.
1115 */
1116 nt->conf = of_device_get_match_data(dev);
1117 if (!nt->conf) {
1118 dev_err(dev, "missing device configuration\n");
1119 return -ENODEV;
1120 }
1121
1122 dsi->mode_flags = nt->conf->mode_flags;
1123
1124 nt->supplies[0].supply = "vdd"; /* 2.3-4.8 V */
1125 nt->supplies[1].supply = "vddi"; /* 1.65-3.3V */
1126 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies),
1127 nt->supplies);
1128 if (ret < 0)
1129 return ret;
1130 ret = regulator_set_voltage(nt->supplies[0].consumer,
1131 2300000, 4800000);
1132 if (ret)
1133 return ret;
1134 ret = regulator_set_voltage(nt->supplies[1].consumer,
1135 1650000, 3300000);
1136 if (ret)
1137 return ret;
1138
1139 nt->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1140 if (IS_ERR(nt->reset_gpio)) {
1141 dev_err(dev, "error getting RESET GPIO\n");
1142 return PTR_ERR(nt->reset_gpio);
1143 }
1144
1145 drm_panel_init(&nt->panel, dev, &nt35510_drm_funcs,
1146 DRM_MODE_CONNECTOR_DSI);
1147
1148 /*
1149 * First, try to locate an external backlight (such as on GPIO)
1150 * if this fails, assume we will want to use the internal backlight
1151 * control.
1152 */
1153 ret = drm_panel_of_backlight(&nt->panel);
1154 if (ret) {
1155 dev_err(dev, "error getting external backlight %d\n", ret);
1156 return ret;
1157 }
1158 if (!nt->panel.backlight) {
1159 struct backlight_device *bl;
1160
1161 bl = devm_backlight_device_register(dev, "nt35510", dev, nt,
1162 &nt35510_bl_ops, NULL);
1163 if (IS_ERR(bl)) {
1164 dev_err(dev, "failed to register backlight device\n");
1165 return PTR_ERR(bl);
1166 }
1167 bl->props.max_brightness = 255;
1168 if (nt->conf->cmds & NT35510_CMD_CONTROL_DISPLAY)
1169 bl->props.brightness = nt->conf->wrdisbv;
1170 else
1171 bl->props.brightness = 255;
1172 bl->props.power = BACKLIGHT_POWER_OFF;
1173 nt->panel.backlight = bl;
1174 }
1175
1176 drm_panel_add(&nt->panel);
1177
1178 ret = mipi_dsi_attach(dsi);
1179 if (ret < 0)
1180 drm_panel_remove(&nt->panel);
1181
1182 return 0;
1183}
1184
1185static void nt35510_remove(struct mipi_dsi_device *dsi)
1186{
1187 struct nt35510 *nt = mipi_dsi_get_drvdata(dsi);
1188 int ret;
1189
1190 mipi_dsi_detach(dsi);
1191 /* Power off */
1192 ret = nt35510_power_off(nt);
1193 if (ret)
1194 dev_err(&dsi->dev, "Failed to power off\n");
1195
1196 drm_panel_remove(&nt->panel);
1197}
1198
1199/*
1200 * These gamma correction values are 10bit tuples, so only bits 0 and 1 is
1201 * ever used in the first byte. They form a positive and negative gamma
1202 * correction curve for each color, values must be strictly higher for each
1203 * step on the curve. As can be seen these default curves goes from 0x0001
1204 * to 0x03FE.
1205 */
1206#define NT35510_GAMMA_POS_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \
1207 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \
1208 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \
1209 0x83, 0x02, 0x78, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \
1210 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \
1211 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE
1212
1213#define NT35510_GAMMA_NEG_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \
1214 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \
1215 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \
1216 0x43, 0x02, 0x50, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \
1217 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \
1218 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE
1219
1220/*
1221 * The Hydis HVA40WV1 panel
1222 */
1223static const struct nt35510_config nt35510_hydis_hva40wv1 = {
1224 .width_mm = 52,
1225 .height_mm = 86,
1226 /**
1227 * As the Hydis panel is used in command mode, the porches etc
1228 * are settings programmed internally into the NT35510 controller
1229 * and generated toward the physical display. As the panel is not
1230 * used in video mode, these are not really exposed to the DSI
1231 * host.
1232 *
1233 * Display frame rate control:
1234 * Frame rate = (20 MHz / 1) / (389 * (7 + 50 + 800)) ~= 60 Hz
1235 */
1236 .mode = {
1237 /* The internal pixel clock of the NT35510 is 20 MHz */
1238 .clock = 20000,
1239 .hdisplay = 480,
1240 .hsync_start = 480 + 2, /* HFP = 2 */
1241 .hsync_end = 480 + 2 + 0, /* HSync = 0 */
1242 .htotal = 480 + 2 + 0 + 5, /* HBP = 5 */
1243 .vdisplay = 800,
1244 .vsync_start = 800 + 2, /* VFP = 2 */
1245 .vsync_end = 800 + 2 + 0, /* VSync = 0 */
1246 .vtotal = 800 + 2 + 0 + 5, /* VBP = 5 */
1247 .flags = 0,
1248 },
1249 .mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS,
1250 .cmds = NT35510_CMD_CORRECT_GAMMA,
1251 /* 0x09: AVDD = 5.6V */
1252 .avdd = { 0x09, 0x09, 0x09 },
1253 /* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */
1254 .bt1ctr = { 0x34, 0x34, 0x34 },
1255 /* 0x09: AVEE = -5.6V */
1256 .avee = { 0x09, 0x09, 0x09 },
1257 /* 0x24: NCK = Hsync/2, BTN = -2 x VDDB */
1258 .bt2ctr = { 0x24, 0x24, 0x24 },
1259 /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -2.5V */
1260 .vcl = { 0x00, 0x00, 0x00 },
1261 /* 0x24: CLCK = Hsync/2, BTN = -1 x VDDB */
1262 .bt3ctr = { 0x24, 0x24, 0x24 },
1263 /* 0x05 = 12V */
1264 .vgh = { 0x05, 0x05, 0x05 },
1265 /* 0x24: NCKA = Hsync/2, VGH = 2 x AVDD - AVEE */
1266 .bt4ctr = { 0x24, 0x24, 0x24 },
1267 /* 0x0B = -13V */
1268 .vgl = { 0x0B, 0x0B, 0x0B },
1269 /* 0x24: LCKA = Hsync, VGL = AVDD + VCL - AVDD */
1270 .bt5ctr = { 0x24, 0x24, 0x24 },
1271 /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
1272 .vgp = { 0x00, 0xA3, 0x00 },
1273 /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
1274 .vgn = { 0x00, 0xA3, 0x00 },
1275 /* VCMOFFSEL = VCOM voltage offset mode, VCM = 0V */
1276 .vcmoff = { 0x00, 0x00 },
1277 /* Enable TE, EoTP and RGB pixel format */
1278 .dopctr = { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP |
1279 NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB },
1280 .madctl = NT35510_ROTATE_0_SETTING,
1281 /* 0x0A: SDT = 5 us */
1282 .sdhdtctr = 0x0A,
1283 /* EQ control for gate signals, 0x00 = 0 us */
1284 .gseqctr = { 0x00, 0x00 },
1285 /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */
1286 .sdeqctr = { 0x01, 0x05, 0x05, 0x05 },
1287 /* SDVPCTR: Normal operation off color during v porch */
1288 .sdvpctr = 0x01,
1289 /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */
1290 .t1 = 0x0184,
1291 /* VBP: vertical back porch toward the panel */
1292 .vbp = 7,
1293 /* VFP: vertical front porch toward the panel */
1294 .vfp = 50,
1295 /* PSEL: divide pixel clock 20MHz with 1 (no clock downscaling) */
1296 .psel = 0,
1297 /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */
1298 .dpmctr12 = { 0x03, 0x00, 0x00, },
1299 /* Default gamma correction values */
1300 .gamma_corr_pos_r = { NT35510_GAMMA_POS_DEFAULT },
1301 .gamma_corr_pos_g = { NT35510_GAMMA_POS_DEFAULT },
1302 .gamma_corr_pos_b = { NT35510_GAMMA_POS_DEFAULT },
1303 .gamma_corr_neg_r = { NT35510_GAMMA_NEG_DEFAULT },
1304 .gamma_corr_neg_g = { NT35510_GAMMA_NEG_DEFAULT },
1305 .gamma_corr_neg_b = { NT35510_GAMMA_NEG_DEFAULT },
1306};
1307
1308static const struct nt35510_config nt35510_frida_frd400b25025 = {
1309 .width_mm = 52,
1310 .height_mm = 86,
1311 .mode = {
1312 .clock = 23000,
1313 .hdisplay = 480,
1314 .hsync_start = 480 + 34, /* HFP = 34 */
1315 .hsync_end = 480 + 34 + 2, /* HSync = 2 */
1316 .htotal = 480 + 34 + 2 + 34, /* HBP = 34 */
1317 .vdisplay = 800,
1318 .vsync_start = 800 + 15, /* VFP = 15 */
1319 .vsync_end = 800 + 15 + 12, /* VSync = 12 */
1320 .vtotal = 800 + 15 + 12 + 15, /* VBP = 15 */
1321 .flags = 0,
1322 },
1323 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1324 MIPI_DSI_MODE_LPM,
1325 .cmds = NT35510_CMD_CONTROL_DISPLAY | NT35510_CMD_SETVCMOFF,
1326 /* 0x03: AVDD = 6.2V */
1327 .avdd = { 0x03, 0x03, 0x03 },
1328 /* 0x46: PCK = 2 x Hsync, BTP = 2.5 x VDDB */
1329 .bt1ctr = { 0x46, 0x46, 0x46 },
1330 /* 0x03: AVEE = -6.2V */
1331 .avee = { 0x03, 0x03, 0x03 },
1332 /* 0x36: PCK = 2 x Hsync, BTP = 2 x VDDB */
1333 .bt2ctr = { 0x36, 0x36, 0x36 },
1334 /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -3.5V */
1335 .vcl = { 0x00, 0x00, 0x02 },
1336 /* 0x26: CLCK = 2 x Hsync, BTN = -1 x VDDB */
1337 .bt3ctr = { 0x26, 0x26, 0x26 },
1338 /* 0x09 = 16V */
1339 .vgh = { 0x09, 0x09, 0x09 },
1340 /* 0x36: HCK = 2 x Hsync, VGH = 2 x AVDD - AVEE */
1341 .bt4ctr = { 0x36, 0x36, 0x36 },
1342 /* 0x08 = -10V */
1343 .vgl = { 0x08, 0x08, 0x08 },
1344 /* 0x26: LCK = 2 x Hsync, VGL = AVDD + VCL - AVDD */
1345 .bt5ctr = { 0x26, 0x26, 0x26 },
1346 /* VGMP: 0x080 = 4.6V, VGSP = 0V */
1347 .vgp = { 0x00, 0x80, 0x00 },
1348 /* VGMP: 0x080 = 4.6V, VGSP = 0V */
1349 .vgn = { 0x00, 0x80, 0x00 },
1350 /* VCMOFFSEL = VCOM voltage offset mode, VCM = -1V */
1351 .vcmoff = { 0x00, 0x50 },
1352 .dopctr = { NT35510_DOPCTR_0_RAMKP | NT35510_DOPCTR_0_DSITE |
1353 NT35510_DOPCTR_0_DSIG | NT35510_DOPCTR_0_DSIM |
1354 NT35510_DOPCTR_0_EOTP | NT35510_DOPCTR_0_N565, 0 },
1355 .madctl = NT35510_ROTATE_180_SETTING,
1356 /* 0x03: SDT = 1.5 us */
1357 .sdhdtctr = 0x03,
1358 /* EQ control for gate signals, 0x00 = 0 us */
1359 .gseqctr = { 0x00, 0x00 },
1360 /* SDEQCTR: source driver EQ mode 2, 1 us rise time on each step */
1361 .sdeqctr = { 0x01, 0x02, 0x02, 0x02 },
1362 /* SDVPCTR: Normal operation off color during v porch */
1363 .sdvpctr = 0x01,
1364 /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */
1365 .t1 = 0x0184,
1366 /* VBP: vertical back porch toward the panel */
1367 .vbp = 0x1C,
1368 /* VFP: vertical front porch toward the panel */
1369 .vfp = 0x1C,
1370 /* PSEL: divide pixel clock 23MHz with 1 (no clock downscaling) */
1371 .psel = 0,
1372 /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */
1373 .dpmctr12 = { 0x03, 0x00, 0x00, },
1374 /* write display brightness */
1375 .wrdisbv = 0x7f,
1376 /* write control display */
1377 .wrctrld = NT35510_WRCTRLD_BCTRL | NT35510_WRCTRLD_DD |
1378 NT35510_WRCTRLD_BL,
1379 /* write content adaptive brightness control */
1380 .wrcabc = NT35510_WRCABC_STILL_MODE,
1381 /* write CABC minimum brightness */
1382 .wrcabcmb = 0xff,
1383};
1384
1385static const struct of_device_id nt35510_of_match[] = {
1386 {
1387 .compatible = "frida,frd400b25025",
1388 .data = &nt35510_frida_frd400b25025,
1389 },
1390 {
1391 .compatible = "hydis,hva40wv1",
1392 .data = &nt35510_hydis_hva40wv1,
1393 },
1394 { }
1395};
1396MODULE_DEVICE_TABLE(of, nt35510_of_match);
1397
1398static struct mipi_dsi_driver nt35510_driver = {
1399 .probe = nt35510_probe,
1400 .remove = nt35510_remove,
1401 .driver = {
1402 .name = "panel-novatek-nt35510",
1403 .of_match_table = nt35510_of_match,
1404 },
1405};
1406module_mipi_dsi_driver(nt35510_driver);
1407
1408MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1409MODULE_DESCRIPTION("NT35510-based panel driver");
1410MODULE_LICENSE("GPL v2");