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1/* SPDX-License-Identifier: MIT */
2#ifndef __NVIF_CLASS_H__
3#define __NVIF_CLASS_H__
4
5/* these class numbers are made up by us, and not nvidia-assigned */
6#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
7
8#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
9
10#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
11#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
12#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
13#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
14
15#define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
16#define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
17#define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
18#define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
19
20#define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a
21#define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b
22#define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b
23#define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b
24
25#define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
26#define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
27#define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
28#define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
29#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
30#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
31
32#define NVIF_CLASS_EVENT /* if000e.h */ 0x8000000e
33
34#define NVIF_CLASS_DISP /* if0010.h */ 0x80000010
35#define NVIF_CLASS_CONN /* if0011.h */ 0x80000011
36#define NVIF_CLASS_OUTP /* if0012.h */ 0x80000012
37#define NVIF_CLASS_HEAD /* if0013.h */ 0x80000013
38#define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014
39
40#define NVIF_CLASS_CHAN /* if0020.h */ 0x80000020
41#define NVIF_CLASS_CGRP /* if0021.h */ 0x80000021
42
43/* the below match nvidia-assigned (either in hw, or sw) class numbers */
44#define NV_NULL_CLASS 0x00000030
45
46#define NV_DEVICE /* cl0080.h */ 0x00000080
47
48#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
49#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
50#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
51
52#define NV50_TWOD 0x0000502d
53#define FERMI_TWOD_A 0x0000902d
54
55#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
56#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
57
58#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
59#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
60
61#define NV04_DISP /* cl0046.h */ 0x00000046
62
63#define VOLTA_USERMODE_A 0x0000c361
64#define TURING_USERMODE_A 0x0000c461
65#define AMPERE_USERMODE_A 0x0000c561
66
67#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
68#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
69
70#define NV03_CHANNEL_DMA /* if0020.h */ 0x0000006b
71#define NV10_CHANNEL_DMA /* if0020.h */ 0x0000006e
72#define NV17_CHANNEL_DMA /* if0020.h */ 0x0000176e
73#define NV40_CHANNEL_DMA /* if0020.h */ 0x0000406e
74
75#define KEPLER_CHANNEL_GROUP_A /* if0021.h */ 0x0000a06c
76
77#define NV50_CHANNEL_GPFIFO /* if0020.h */ 0x0000506f
78#define G82_CHANNEL_GPFIFO /* if0020.h */ 0x0000826f
79#define FERMI_CHANNEL_GPFIFO /* if0020.h */ 0x0000906f
80#define KEPLER_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000a06f
81#define KEPLER_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000a16f
82#define MAXWELL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000b06f
83#define PASCAL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c06f
84#define VOLTA_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c36f
85#define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f
86#define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f
87#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
88
89#define NV50_DISP /* if0010.h */ 0x00005070
90#define G82_DISP /* if0010.h */ 0x00008270
91#define GT200_DISP /* if0010.h */ 0x00008370
92#define GT214_DISP /* if0010.h */ 0x00008570
93#define GT206_DISP /* if0010.h */ 0x00008870
94#define GF110_DISP /* if0010.h */ 0x00009070
95#define GK104_DISP /* if0010.h */ 0x00009170
96#define GK110_DISP /* if0010.h */ 0x00009270
97#define GM107_DISP /* if0010.h */ 0x00009470
98#define GM200_DISP /* if0010.h */ 0x00009570
99#define GP100_DISP /* if0010.h */ 0x00009770
100#define GP102_DISP /* if0010.h */ 0x00009870
101#define GV100_DISP /* if0010.h */ 0x0000c370
102#define TU102_DISP /* if0010.h */ 0x0000c570
103#define GA102_DISP /* if0010.h */ 0x0000c670
104#define AD102_DISP /* if0010.h */ 0x0000c770
105
106#define GV100_DISP_CAPS 0x0000c373
107
108#define NV31_MPEG 0x00003174
109#define G82_MPEG 0x00008274
110
111#define NV74_VP2 0x00007476
112
113#define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a
114#define G82_DISP_CURSOR /* if0014.h */ 0x0000827a
115#define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a
116#define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a
117#define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a
118#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
119#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
120#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
121
122#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
123#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
124#define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b
125#define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b
126#define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b
127
128#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
129#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
130#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
131
132#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
133#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
134#define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c
135#define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c
136#define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c
137#define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c
138#define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c
139
140#define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d
141#define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d
142#define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d
143#define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d
144#define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d
145#define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d
146#define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d
147#define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d
148#define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d
149#define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d
150#define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d
151#define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d
152#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d
153#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
154#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
155#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
156
157#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
158#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
159#define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e
160#define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e
161#define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e
162#define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e
163
164#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
165#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
166#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
167
168#define NV50_TESLA 0x00005097
169#define G82_TESLA 0x00008297
170#define GT200_TESLA 0x00008397
171#define GT214_TESLA 0x00008597
172#define GT21A_TESLA 0x00008697
173
174#define FERMI_A /* cl9097.h */ 0x00009097
175#define FERMI_B /* cl9097.h */ 0x00009197
176#define FERMI_C /* cl9097.h */ 0x00009297
177
178#define KEPLER_A /* cl9097.h */ 0x0000a097
179#define KEPLER_B /* cl9097.h */ 0x0000a197
180#define KEPLER_C /* cl9097.h */ 0x0000a297
181
182#define MAXWELL_A /* cl9097.h */ 0x0000b097
183#define MAXWELL_B /* cl9097.h */ 0x0000b197
184
185#define PASCAL_A /* cl9097.h */ 0x0000c097
186#define PASCAL_B /* cl9097.h */ 0x0000c197
187
188#define VOLTA_A /* cl9097.h */ 0x0000c397
189
190#define TURING_A /* cl9097.h */ 0x0000c597
191
192#define AMPERE_B /* cl9097.h */ 0x0000c797
193
194#define ADA_A /* cl9097.h */ 0x0000c997
195
196#define NV74_BSP 0x000074b0
197
198#define NVC4B0_VIDEO_DECODER 0x0000c4b0
199#define NVC6B0_VIDEO_DECODER 0x0000c6b0
200#define NVC7B0_VIDEO_DECODER 0x0000c7b0
201#define NVC9B0_VIDEO_DECODER 0x0000c9b0
202
203#define GT212_MSVLD 0x000085b1
204#define IGT21A_MSVLD 0x000086b1
205#define G98_MSVLD 0x000088b1
206#define GF100_MSVLD 0x000090b1
207#define GK104_MSVLD 0x000095b1
208
209#define GT212_MSPDEC 0x000085b2
210#define G98_MSPDEC 0x000088b2
211#define GF100_MSPDEC 0x000090b2
212#define GK104_MSPDEC 0x000095b2
213
214#define GT212_MSPPP 0x000085b3
215#define G98_MSPPP 0x000088b3
216#define GF100_MSPPP 0x000090b3
217
218#define G98_SEC 0x000088b4
219
220#define GT212_DMA 0x000085b5
221#define FERMI_DMA 0x000090b5
222#define KEPLER_DMA_COPY_A 0x0000a0b5
223#define MAXWELL_DMA_COPY_A 0x0000b0b5
224#define PASCAL_DMA_COPY_A 0x0000c0b5
225#define PASCAL_DMA_COPY_B 0x0000c1b5
226#define VOLTA_DMA_COPY_A 0x0000c3b5
227#define TURING_DMA_COPY_A 0x0000c5b5
228#define AMPERE_DMA_COPY_A 0x0000c6b5
229#define AMPERE_DMA_COPY_B 0x0000c7b5
230
231#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
232#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
233#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
234
235#define FERMI_DECOMPRESS 0x000090b8
236
237#define NV50_COMPUTE 0x000050c0
238#define GT214_COMPUTE 0x000085c0
239#define FERMI_COMPUTE_A 0x000090c0
240#define FERMI_COMPUTE_B 0x000091c0
241#define KEPLER_COMPUTE_A 0x0000a0c0
242#define KEPLER_COMPUTE_B 0x0000a1c0
243#define MAXWELL_COMPUTE_A 0x0000b0c0
244#define MAXWELL_COMPUTE_B 0x0000b1c0
245#define PASCAL_COMPUTE_A 0x0000c0c0
246#define PASCAL_COMPUTE_B 0x0000c1c0
247#define VOLTA_COMPUTE_A 0x0000c3c0
248#define TURING_COMPUTE_A 0x0000c5c0
249#define AMPERE_COMPUTE_B 0x0000c7c0
250#define ADA_COMPUTE_A 0x0000c9c0
251
252#define NV74_CIPHER 0x000074c1
253
254#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
255#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
256
257#define NVC6FA_VIDEO_OFA 0x0000c6fa
258#define NVC7FA_VIDEO_OFA 0x0000c7fa
259#define NVC9FA_VIDEO_OFA 0x0000c9fa
260#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __NVIF_CLASS_H__
3#define __NVIF_CLASS_H__
4
5/* these class numbers are made up by us, and not nvidia-assigned */
6#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
7
8#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
9
10#define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
11#define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
12
13#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
14#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
15#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
16#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
17
18#define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
19#define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
20#define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
21#define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
22
23#define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a
24#define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b
25#define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b
26#define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b
27
28#define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
29#define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
30#define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
31#define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
32#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
33#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
34
35/* the below match nvidia-assigned (either in hw, or sw) class numbers */
36#define NV_NULL_CLASS 0x00000030
37
38#define NV_DEVICE /* cl0080.h */ 0x00000080
39
40#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
41#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
42#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
43
44#define NV50_TWOD 0x0000502d
45#define FERMI_TWOD_A 0x0000902d
46
47#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
48#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
49
50#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
51#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
52
53#define NV04_DISP /* cl0046.h */ 0x00000046
54
55#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
56#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
57#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
58#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
59#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
60#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
61
62#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
63#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
64#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
65#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
66#define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
67#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
68#define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
69
70#define NV50_DISP /* cl5070.h */ 0x00005070
71#define G82_DISP /* cl5070.h */ 0x00008270
72#define GT200_DISP /* cl5070.h */ 0x00008370
73#define GT214_DISP /* cl5070.h */ 0x00008570
74#define GT206_DISP /* cl5070.h */ 0x00008870
75#define GF110_DISP /* cl5070.h */ 0x00009070
76#define GK104_DISP /* cl5070.h */ 0x00009170
77#define GK110_DISP /* cl5070.h */ 0x00009270
78#define GM107_DISP /* cl5070.h */ 0x00009470
79#define GM200_DISP /* cl5070.h */ 0x00009570
80#define GP100_DISP /* cl5070.h */ 0x00009770
81#define GP102_DISP /* cl5070.h */ 0x00009870
82
83#define NV31_MPEG 0x00003174
84#define G82_MPEG 0x00008274
85
86#define NV74_VP2 0x00007476
87
88#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
89#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
90#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
91#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
92#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
93
94#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
95#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
96#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
97#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
98#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
99
100#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
101#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
102#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
103#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
104#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
105#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
106#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
107
108#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
109#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
110#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
111#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
112#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
113#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
114#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
115#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
116#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
117#define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
118#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
119#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
120
121#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
122#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
123#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
124#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
125#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
126#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
127
128#define NV50_TESLA 0x00005097
129#define G82_TESLA 0x00008297
130#define GT200_TESLA 0x00008397
131#define GT214_TESLA 0x00008597
132#define GT21A_TESLA 0x00008697
133
134#define FERMI_A /* cl9097.h */ 0x00009097
135#define FERMI_B /* cl9097.h */ 0x00009197
136#define FERMI_C /* cl9097.h */ 0x00009297
137
138#define KEPLER_A /* cl9097.h */ 0x0000a097
139#define KEPLER_B /* cl9097.h */ 0x0000a197
140#define KEPLER_C /* cl9097.h */ 0x0000a297
141
142#define MAXWELL_A /* cl9097.h */ 0x0000b097
143#define MAXWELL_B /* cl9097.h */ 0x0000b197
144
145#define PASCAL_A /* cl9097.h */ 0x0000c097
146#define PASCAL_B /* cl9097.h */ 0x0000c197
147
148#define NV74_BSP 0x000074b0
149
150#define GT212_MSVLD 0x000085b1
151#define IGT21A_MSVLD 0x000086b1
152#define G98_MSVLD 0x000088b1
153#define GF100_MSVLD 0x000090b1
154#define GK104_MSVLD 0x000095b1
155
156#define GT212_MSPDEC 0x000085b2
157#define G98_MSPDEC 0x000088b2
158#define GF100_MSPDEC 0x000090b2
159#define GK104_MSPDEC 0x000095b2
160
161#define GT212_MSPPP 0x000085b3
162#define G98_MSPPP 0x000088b3
163#define GF100_MSPPP 0x000090b3
164
165#define G98_SEC 0x000088b4
166
167#define GT212_DMA 0x000085b5
168#define FERMI_DMA 0x000090b5
169#define KEPLER_DMA_COPY_A 0x0000a0b5
170#define MAXWELL_DMA_COPY_A 0x0000b0b5
171#define PASCAL_DMA_COPY_A 0x0000c0b5
172#define PASCAL_DMA_COPY_B 0x0000c1b5
173
174#define FERMI_DECOMPRESS 0x000090b8
175
176#define NV50_COMPUTE 0x000050c0
177#define GT214_COMPUTE 0x000085c0
178#define FERMI_COMPUTE_A 0x000090c0
179#define FERMI_COMPUTE_B 0x000091c0
180#define KEPLER_COMPUTE_A 0x0000a0c0
181#define KEPLER_COMPUTE_B 0x0000a1c0
182#define MAXWELL_COMPUTE_A 0x0000b0c0
183#define MAXWELL_COMPUTE_B 0x0000b1c0
184#define PASCAL_COMPUTE_A 0x0000c0c0
185#define PASCAL_COMPUTE_B 0x0000c1c0
186
187#define NV74_CIPHER 0x000074c1
188#endif