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1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/debugfs.h>
25#include <linux/time.h>
26
27#include <drm/drm_fixed.h>
28
29#include "soc/intel_dram.h"
30
31#include "hsw_ips.h"
32#include "i915_reg.h"
33#include "intel_atomic.h"
34#include "intel_atomic_plane.h"
35#include "intel_audio.h"
36#include "intel_bw.h"
37#include "intel_cdclk.h"
38#include "intel_crtc.h"
39#include "intel_de.h"
40#include "intel_dp.h"
41#include "intel_display_types.h"
42#include "intel_mchbar_regs.h"
43#include "intel_pci_config.h"
44#include "intel_pcode.h"
45#include "intel_psr.h"
46#include "intel_vdsc.h"
47#include "skl_watermark.h"
48#include "skl_watermark_regs.h"
49#include "vlv_sideband.h"
50
51/**
52 * DOC: CDCLK / RAWCLK
53 *
54 * The display engine uses several different clocks to do its work. There
55 * are two main clocks involved that aren't directly related to the actual
56 * pixel clock or any symbol/bit clock of the actual output port. These
57 * are the core display clock (CDCLK) and RAWCLK.
58 *
59 * CDCLK clocks most of the display pipe logic, and thus its frequency
60 * must be high enough to support the rate at which pixels are flowing
61 * through the pipes. Downscaling must also be accounted as that increases
62 * the effective pixel rate.
63 *
64 * On several platforms the CDCLK frequency can be changed dynamically
65 * to minimize power consumption for a given display configuration.
66 * Typically changes to the CDCLK frequency require all the display pipes
67 * to be shut down while the frequency is being changed.
68 *
69 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
70 * DMC will not change the active CDCLK frequency however, so that part
71 * will still be performed by the driver directly.
72 *
73 * There are multiple components involved in the generation of the CDCLK
74 * frequency:
75 *
76 * - We have the CDCLK PLL, which generates an output clock based on a
77 * reference clock and a ratio parameter.
78 * - The CD2X Divider, which divides the output of the PLL based on a
79 * divisor selected from a set of pre-defined choices.
80 * - The CD2X Squasher, which further divides the output based on a
81 * waveform represented as a sequence of bits where each zero
82 * "squashes out" a clock cycle.
83 * - And, finally, a fixed divider that divides the output frequency by 2.
84 *
85 * As such, the resulting CDCLK frequency can be calculated with the
86 * following formula:
87 *
88 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
89 *
90 * , where vco is the frequency generated by the PLL; cd2x_div
91 * represents the CD2X Divider; sq_len and sq_div are the bit length
92 * and the number of high bits for the CD2X Squasher waveform, respectively;
93 * and 2 represents the fixed divider.
94 *
95 * Note that some older platforms do not contain the CD2X Divider
96 * and/or CD2X Squasher, in which case we can ignore their respective
97 * factors in the formula above.
98 *
99 * Several methods exist to change the CDCLK frequency, which ones are
100 * supported depends on the platform:
101 *
102 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
103 * - CD2X divider update. Single pipe can be active as the divider update
104 * can be synchronized with the pipe's start of vblank.
105 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
106 * - Squash waveform update. Pipes can be active.
107 * - Crawl and squash can also be done back to back. Pipes can be active.
108 *
109 * RAWCLK is a fixed frequency clock, often used by various auxiliary
110 * blocks such as AUX CH or backlight PWM. Hence the only thing we
111 * really need to know about RAWCLK is its frequency so that various
112 * dividers can be programmed correctly.
113 */
114
115struct intel_cdclk_funcs {
116 void (*get_cdclk)(struct intel_display *display,
117 struct intel_cdclk_config *cdclk_config);
118 void (*set_cdclk)(struct intel_display *display,
119 const struct intel_cdclk_config *cdclk_config,
120 enum pipe pipe);
121 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
122 u8 (*calc_voltage_level)(int cdclk);
123};
124
125void intel_cdclk_get_cdclk(struct intel_display *display,
126 struct intel_cdclk_config *cdclk_config)
127{
128 display->funcs.cdclk->get_cdclk(display, cdclk_config);
129}
130
131static void intel_cdclk_set_cdclk(struct intel_display *display,
132 const struct intel_cdclk_config *cdclk_config,
133 enum pipe pipe)
134{
135 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
136}
137
138static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
139{
140 struct intel_display *display = to_intel_display(state);
141
142 return display->funcs.cdclk->modeset_calc_cdclk(state);
143}
144
145static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
146 int cdclk)
147{
148 return display->funcs.cdclk->calc_voltage_level(cdclk);
149}
150
151static void fixed_133mhz_get_cdclk(struct intel_display *display,
152 struct intel_cdclk_config *cdclk_config)
153{
154 cdclk_config->cdclk = 133333;
155}
156
157static void fixed_200mhz_get_cdclk(struct intel_display *display,
158 struct intel_cdclk_config *cdclk_config)
159{
160 cdclk_config->cdclk = 200000;
161}
162
163static void fixed_266mhz_get_cdclk(struct intel_display *display,
164 struct intel_cdclk_config *cdclk_config)
165{
166 cdclk_config->cdclk = 266667;
167}
168
169static void fixed_333mhz_get_cdclk(struct intel_display *display,
170 struct intel_cdclk_config *cdclk_config)
171{
172 cdclk_config->cdclk = 333333;
173}
174
175static void fixed_400mhz_get_cdclk(struct intel_display *display,
176 struct intel_cdclk_config *cdclk_config)
177{
178 cdclk_config->cdclk = 400000;
179}
180
181static void fixed_450mhz_get_cdclk(struct intel_display *display,
182 struct intel_cdclk_config *cdclk_config)
183{
184 cdclk_config->cdclk = 450000;
185}
186
187static void i85x_get_cdclk(struct intel_display *display,
188 struct intel_cdclk_config *cdclk_config)
189{
190 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
191 u16 hpllcc = 0;
192
193 /*
194 * 852GM/852GMV only supports 133 MHz and the HPLLCC
195 * encoding is different :(
196 * FIXME is this the right way to detect 852GM/852GMV?
197 */
198 if (pdev->revision == 0x1) {
199 cdclk_config->cdclk = 133333;
200 return;
201 }
202
203 pci_bus_read_config_word(pdev->bus,
204 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
205
206 /* Assume that the hardware is in the high speed state. This
207 * should be the default.
208 */
209 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
210 case GC_CLOCK_133_200:
211 case GC_CLOCK_133_200_2:
212 case GC_CLOCK_100_200:
213 cdclk_config->cdclk = 200000;
214 break;
215 case GC_CLOCK_166_250:
216 cdclk_config->cdclk = 250000;
217 break;
218 case GC_CLOCK_100_133:
219 cdclk_config->cdclk = 133333;
220 break;
221 case GC_CLOCK_133_266:
222 case GC_CLOCK_133_266_2:
223 case GC_CLOCK_166_266:
224 cdclk_config->cdclk = 266667;
225 break;
226 }
227}
228
229static void i915gm_get_cdclk(struct intel_display *display,
230 struct intel_cdclk_config *cdclk_config)
231{
232 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
233 u16 gcfgc = 0;
234
235 pci_read_config_word(pdev, GCFGC, &gcfgc);
236
237 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
238 cdclk_config->cdclk = 133333;
239 return;
240 }
241
242 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
243 case GC_DISPLAY_CLOCK_333_320_MHZ:
244 cdclk_config->cdclk = 333333;
245 break;
246 default:
247 case GC_DISPLAY_CLOCK_190_200_MHZ:
248 cdclk_config->cdclk = 190000;
249 break;
250 }
251}
252
253static void i945gm_get_cdclk(struct intel_display *display,
254 struct intel_cdclk_config *cdclk_config)
255{
256 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
257 u16 gcfgc = 0;
258
259 pci_read_config_word(pdev, GCFGC, &gcfgc);
260
261 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
262 cdclk_config->cdclk = 133333;
263 return;
264 }
265
266 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
267 case GC_DISPLAY_CLOCK_333_320_MHZ:
268 cdclk_config->cdclk = 320000;
269 break;
270 default:
271 case GC_DISPLAY_CLOCK_190_200_MHZ:
272 cdclk_config->cdclk = 200000;
273 break;
274 }
275}
276
277static unsigned int intel_hpll_vco(struct intel_display *display)
278{
279 static const unsigned int blb_vco[8] = {
280 [0] = 3200000,
281 [1] = 4000000,
282 [2] = 5333333,
283 [3] = 4800000,
284 [4] = 6400000,
285 };
286 static const unsigned int pnv_vco[8] = {
287 [0] = 3200000,
288 [1] = 4000000,
289 [2] = 5333333,
290 [3] = 4800000,
291 [4] = 2666667,
292 };
293 static const unsigned int cl_vco[8] = {
294 [0] = 3200000,
295 [1] = 4000000,
296 [2] = 5333333,
297 [3] = 6400000,
298 [4] = 3333333,
299 [5] = 3566667,
300 [6] = 4266667,
301 };
302 static const unsigned int elk_vco[8] = {
303 [0] = 3200000,
304 [1] = 4000000,
305 [2] = 5333333,
306 [3] = 4800000,
307 };
308 static const unsigned int ctg_vco[8] = {
309 [0] = 3200000,
310 [1] = 4000000,
311 [2] = 5333333,
312 [3] = 6400000,
313 [4] = 2666667,
314 [5] = 4266667,
315 };
316 struct drm_i915_private *dev_priv = to_i915(display->drm);
317 const unsigned int *vco_table;
318 unsigned int vco;
319 u8 tmp = 0;
320
321 /* FIXME other chipsets? */
322 if (IS_GM45(dev_priv))
323 vco_table = ctg_vco;
324 else if (IS_G45(dev_priv))
325 vco_table = elk_vco;
326 else if (IS_I965GM(dev_priv))
327 vco_table = cl_vco;
328 else if (IS_PINEVIEW(dev_priv))
329 vco_table = pnv_vco;
330 else if (IS_G33(dev_priv))
331 vco_table = blb_vco;
332 else
333 return 0;
334
335 tmp = intel_de_read(display,
336 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
337
338 vco = vco_table[tmp & 0x7];
339 if (vco == 0)
340 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
341 tmp);
342 else
343 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
344
345 return vco;
346}
347
348static void g33_get_cdclk(struct intel_display *display,
349 struct intel_cdclk_config *cdclk_config)
350{
351 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
352 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
353 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
354 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
355 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
356 const u8 *div_table;
357 unsigned int cdclk_sel;
358 u16 tmp = 0;
359
360 cdclk_config->vco = intel_hpll_vco(display);
361
362 pci_read_config_word(pdev, GCFGC, &tmp);
363
364 cdclk_sel = (tmp >> 4) & 0x7;
365
366 if (cdclk_sel >= ARRAY_SIZE(div_3200))
367 goto fail;
368
369 switch (cdclk_config->vco) {
370 case 3200000:
371 div_table = div_3200;
372 break;
373 case 4000000:
374 div_table = div_4000;
375 break;
376 case 4800000:
377 div_table = div_4800;
378 break;
379 case 5333333:
380 div_table = div_5333;
381 break;
382 default:
383 goto fail;
384 }
385
386 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
387 div_table[cdclk_sel]);
388 return;
389
390fail:
391 drm_err(display->drm,
392 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
393 cdclk_config->vco, tmp);
394 cdclk_config->cdclk = 190476;
395}
396
397static void pnv_get_cdclk(struct intel_display *display,
398 struct intel_cdclk_config *cdclk_config)
399{
400 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
401 u16 gcfgc = 0;
402
403 pci_read_config_word(pdev, GCFGC, &gcfgc);
404
405 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
406 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
407 cdclk_config->cdclk = 266667;
408 break;
409 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
410 cdclk_config->cdclk = 333333;
411 break;
412 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
413 cdclk_config->cdclk = 444444;
414 break;
415 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
416 cdclk_config->cdclk = 200000;
417 break;
418 default:
419 drm_err(display->drm,
420 "Unknown pnv display core clock 0x%04x\n", gcfgc);
421 fallthrough;
422 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
423 cdclk_config->cdclk = 133333;
424 break;
425 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
426 cdclk_config->cdclk = 166667;
427 break;
428 }
429}
430
431static void i965gm_get_cdclk(struct intel_display *display,
432 struct intel_cdclk_config *cdclk_config)
433{
434 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
435 static const u8 div_3200[] = { 16, 10, 8 };
436 static const u8 div_4000[] = { 20, 12, 10 };
437 static const u8 div_5333[] = { 24, 16, 14 };
438 const u8 *div_table;
439 unsigned int cdclk_sel;
440 u16 tmp = 0;
441
442 cdclk_config->vco = intel_hpll_vco(display);
443
444 pci_read_config_word(pdev, GCFGC, &tmp);
445
446 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
447
448 if (cdclk_sel >= ARRAY_SIZE(div_3200))
449 goto fail;
450
451 switch (cdclk_config->vco) {
452 case 3200000:
453 div_table = div_3200;
454 break;
455 case 4000000:
456 div_table = div_4000;
457 break;
458 case 5333333:
459 div_table = div_5333;
460 break;
461 default:
462 goto fail;
463 }
464
465 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
466 div_table[cdclk_sel]);
467 return;
468
469fail:
470 drm_err(display->drm,
471 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
472 cdclk_config->vco, tmp);
473 cdclk_config->cdclk = 200000;
474}
475
476static void gm45_get_cdclk(struct intel_display *display,
477 struct intel_cdclk_config *cdclk_config)
478{
479 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
480 unsigned int cdclk_sel;
481 u16 tmp = 0;
482
483 cdclk_config->vco = intel_hpll_vco(display);
484
485 pci_read_config_word(pdev, GCFGC, &tmp);
486
487 cdclk_sel = (tmp >> 12) & 0x1;
488
489 switch (cdclk_config->vco) {
490 case 2666667:
491 case 4000000:
492 case 5333333:
493 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
494 break;
495 case 3200000:
496 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
497 break;
498 default:
499 drm_err(display->drm,
500 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
501 cdclk_config->vco, tmp);
502 cdclk_config->cdclk = 222222;
503 break;
504 }
505}
506
507static void hsw_get_cdclk(struct intel_display *display,
508 struct intel_cdclk_config *cdclk_config)
509{
510 struct drm_i915_private *dev_priv = to_i915(display->drm);
511 u32 lcpll = intel_de_read(display, LCPLL_CTL);
512 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
513
514 if (lcpll & LCPLL_CD_SOURCE_FCLK)
515 cdclk_config->cdclk = 800000;
516 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
517 cdclk_config->cdclk = 450000;
518 else if (freq == LCPLL_CLK_FREQ_450)
519 cdclk_config->cdclk = 450000;
520 else if (IS_HASWELL_ULT(dev_priv))
521 cdclk_config->cdclk = 337500;
522 else
523 cdclk_config->cdclk = 540000;
524}
525
526static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
527{
528 struct drm_i915_private *dev_priv = to_i915(display->drm);
529 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
530 333333 : 320000;
531
532 /*
533 * We seem to get an unstable or solid color picture at 200MHz.
534 * Not sure what's wrong. For now use 200MHz only when all pipes
535 * are off.
536 */
537 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
538 return 400000;
539 else if (min_cdclk > 266667)
540 return freq_320;
541 else if (min_cdclk > 0)
542 return 266667;
543 else
544 return 200000;
545}
546
547static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
548{
549 struct drm_i915_private *dev_priv = to_i915(display->drm);
550
551 if (IS_VALLEYVIEW(dev_priv)) {
552 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
553 return 2;
554 else if (cdclk >= 266667)
555 return 1;
556 else
557 return 0;
558 } else {
559 /*
560 * Specs are full of misinformation, but testing on actual
561 * hardware has shown that we just need to write the desired
562 * CCK divider into the Punit register.
563 */
564 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
565 }
566}
567
568static void vlv_get_cdclk(struct intel_display *display,
569 struct intel_cdclk_config *cdclk_config)
570{
571 struct drm_i915_private *dev_priv = to_i915(display->drm);
572 u32 val;
573
574 vlv_iosf_sb_get(dev_priv,
575 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
576
577 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
578 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
579 CCK_DISPLAY_CLOCK_CONTROL,
580 cdclk_config->vco);
581
582 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
583
584 vlv_iosf_sb_put(dev_priv,
585 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
586
587 if (IS_VALLEYVIEW(dev_priv))
588 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
589 DSPFREQGUAR_SHIFT;
590 else
591 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
592 DSPFREQGUAR_SHIFT_CHV;
593}
594
595static void vlv_program_pfi_credits(struct intel_display *display)
596{
597 struct drm_i915_private *dev_priv = to_i915(display->drm);
598 unsigned int credits, default_credits;
599
600 if (IS_CHERRYVIEW(dev_priv))
601 default_credits = PFI_CREDIT(12);
602 else
603 default_credits = PFI_CREDIT(8);
604
605 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
606 /* CHV suggested value is 31 or 63 */
607 if (IS_CHERRYVIEW(dev_priv))
608 credits = PFI_CREDIT_63;
609 else
610 credits = PFI_CREDIT(15);
611 } else {
612 credits = default_credits;
613 }
614
615 /*
616 * WA - write default credits before re-programming
617 * FIXME: should we also set the resend bit here?
618 */
619 intel_de_write(display, GCI_CONTROL,
620 VGA_FAST_MODE_DISABLE | default_credits);
621
622 intel_de_write(display, GCI_CONTROL,
623 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
624
625 /*
626 * FIXME is this guaranteed to clear
627 * immediately or should we poll for it?
628 */
629 drm_WARN_ON(display->drm,
630 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
631}
632
633static void vlv_set_cdclk(struct intel_display *display,
634 const struct intel_cdclk_config *cdclk_config,
635 enum pipe pipe)
636{
637 struct drm_i915_private *dev_priv = to_i915(display->drm);
638 int cdclk = cdclk_config->cdclk;
639 u32 val, cmd = cdclk_config->voltage_level;
640 intel_wakeref_t wakeref;
641
642 switch (cdclk) {
643 case 400000:
644 case 333333:
645 case 320000:
646 case 266667:
647 case 200000:
648 break;
649 default:
650 MISSING_CASE(cdclk);
651 return;
652 }
653
654 /* There are cases where we can end up here with power domains
655 * off and a CDCLK frequency other than the minimum, like when
656 * issuing a modeset without actually changing any display after
657 * a system suspend. So grab the display core domain, which covers
658 * the HW blocks needed for the following programming.
659 */
660 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
661
662 vlv_iosf_sb_get(dev_priv,
663 BIT(VLV_IOSF_SB_CCK) |
664 BIT(VLV_IOSF_SB_BUNIT) |
665 BIT(VLV_IOSF_SB_PUNIT));
666
667 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
668 val &= ~DSPFREQGUAR_MASK;
669 val |= (cmd << DSPFREQGUAR_SHIFT);
670 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
671 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
672 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
673 50)) {
674 drm_err(display->drm,
675 "timed out waiting for CDclk change\n");
676 }
677
678 if (cdclk == 400000) {
679 u32 divider;
680
681 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
682 cdclk) - 1;
683
684 /* adjust cdclk divider */
685 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
686 val &= ~CCK_FREQUENCY_VALUES;
687 val |= divider;
688 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
689
690 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
691 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
692 50))
693 drm_err(display->drm,
694 "timed out waiting for CDclk change\n");
695 }
696
697 /* adjust self-refresh exit latency value */
698 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
699 val &= ~0x7f;
700
701 /*
702 * For high bandwidth configs, we set a higher latency in the bunit
703 * so that the core display fetch happens in time to avoid underruns.
704 */
705 if (cdclk == 400000)
706 val |= 4500 / 250; /* 4.5 usec */
707 else
708 val |= 3000 / 250; /* 3.0 usec */
709 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
710
711 vlv_iosf_sb_put(dev_priv,
712 BIT(VLV_IOSF_SB_CCK) |
713 BIT(VLV_IOSF_SB_BUNIT) |
714 BIT(VLV_IOSF_SB_PUNIT));
715
716 intel_update_cdclk(display);
717
718 vlv_program_pfi_credits(display);
719
720 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
721}
722
723static void chv_set_cdclk(struct intel_display *display,
724 const struct intel_cdclk_config *cdclk_config,
725 enum pipe pipe)
726{
727 struct drm_i915_private *dev_priv = to_i915(display->drm);
728 int cdclk = cdclk_config->cdclk;
729 u32 val, cmd = cdclk_config->voltage_level;
730 intel_wakeref_t wakeref;
731
732 switch (cdclk) {
733 case 333333:
734 case 320000:
735 case 266667:
736 case 200000:
737 break;
738 default:
739 MISSING_CASE(cdclk);
740 return;
741 }
742
743 /* There are cases where we can end up here with power domains
744 * off and a CDCLK frequency other than the minimum, like when
745 * issuing a modeset without actually changing any display after
746 * a system suspend. So grab the display core domain, which covers
747 * the HW blocks needed for the following programming.
748 */
749 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
750
751 vlv_punit_get(dev_priv);
752 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
753 val &= ~DSPFREQGUAR_MASK_CHV;
754 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
755 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
756 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
757 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
758 50)) {
759 drm_err(display->drm,
760 "timed out waiting for CDclk change\n");
761 }
762
763 vlv_punit_put(dev_priv);
764
765 intel_update_cdclk(display);
766
767 vlv_program_pfi_credits(display);
768
769 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
770}
771
772static int bdw_calc_cdclk(int min_cdclk)
773{
774 if (min_cdclk > 540000)
775 return 675000;
776 else if (min_cdclk > 450000)
777 return 540000;
778 else if (min_cdclk > 337500)
779 return 450000;
780 else
781 return 337500;
782}
783
784static u8 bdw_calc_voltage_level(int cdclk)
785{
786 switch (cdclk) {
787 default:
788 case 337500:
789 return 2;
790 case 450000:
791 return 0;
792 case 540000:
793 return 1;
794 case 675000:
795 return 3;
796 }
797}
798
799static void bdw_get_cdclk(struct intel_display *display,
800 struct intel_cdclk_config *cdclk_config)
801{
802 u32 lcpll = intel_de_read(display, LCPLL_CTL);
803 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
804
805 if (lcpll & LCPLL_CD_SOURCE_FCLK)
806 cdclk_config->cdclk = 800000;
807 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
808 cdclk_config->cdclk = 450000;
809 else if (freq == LCPLL_CLK_FREQ_450)
810 cdclk_config->cdclk = 450000;
811 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
812 cdclk_config->cdclk = 540000;
813 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
814 cdclk_config->cdclk = 337500;
815 else
816 cdclk_config->cdclk = 675000;
817
818 /*
819 * Can't read this out :( Let's assume it's
820 * at least what the CDCLK frequency requires.
821 */
822 cdclk_config->voltage_level =
823 bdw_calc_voltage_level(cdclk_config->cdclk);
824}
825
826static u32 bdw_cdclk_freq_sel(int cdclk)
827{
828 switch (cdclk) {
829 default:
830 MISSING_CASE(cdclk);
831 fallthrough;
832 case 337500:
833 return LCPLL_CLK_FREQ_337_5_BDW;
834 case 450000:
835 return LCPLL_CLK_FREQ_450;
836 case 540000:
837 return LCPLL_CLK_FREQ_54O_BDW;
838 case 675000:
839 return LCPLL_CLK_FREQ_675_BDW;
840 }
841}
842
843static void bdw_set_cdclk(struct intel_display *display,
844 const struct intel_cdclk_config *cdclk_config,
845 enum pipe pipe)
846{
847 struct drm_i915_private *dev_priv = to_i915(display->drm);
848 int cdclk = cdclk_config->cdclk;
849 int ret;
850
851 if (drm_WARN(display->drm,
852 (intel_de_read(display, LCPLL_CTL) &
853 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
854 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
855 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
856 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
857 "trying to change cdclk frequency with cdclk not enabled\n"))
858 return;
859
860 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
861 if (ret) {
862 drm_err(display->drm,
863 "failed to inform pcode about cdclk change\n");
864 return;
865 }
866
867 intel_de_rmw(display, LCPLL_CTL,
868 0, LCPLL_CD_SOURCE_FCLK);
869
870 /*
871 * According to the spec, it should be enough to poll for this 1 us.
872 * However, extensive testing shows that this can take longer.
873 */
874 if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
875 LCPLL_CD_SOURCE_FCLK_DONE, 100))
876 drm_err(display->drm, "Switching to FCLK failed\n");
877
878 intel_de_rmw(display, LCPLL_CTL,
879 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
880
881 intel_de_rmw(display, LCPLL_CTL,
882 LCPLL_CD_SOURCE_FCLK, 0);
883
884 if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
885 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
886 drm_err(display->drm, "Switching back to LCPLL failed\n");
887
888 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
889 cdclk_config->voltage_level);
890
891 intel_de_write(display, CDCLK_FREQ,
892 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
893
894 intel_update_cdclk(display);
895}
896
897static int skl_calc_cdclk(int min_cdclk, int vco)
898{
899 if (vco == 8640000) {
900 if (min_cdclk > 540000)
901 return 617143;
902 else if (min_cdclk > 432000)
903 return 540000;
904 else if (min_cdclk > 308571)
905 return 432000;
906 else
907 return 308571;
908 } else {
909 if (min_cdclk > 540000)
910 return 675000;
911 else if (min_cdclk > 450000)
912 return 540000;
913 else if (min_cdclk > 337500)
914 return 450000;
915 else
916 return 337500;
917 }
918}
919
920static u8 skl_calc_voltage_level(int cdclk)
921{
922 if (cdclk > 540000)
923 return 3;
924 else if (cdclk > 450000)
925 return 2;
926 else if (cdclk > 337500)
927 return 1;
928 else
929 return 0;
930}
931
932static void skl_dpll0_update(struct intel_display *display,
933 struct intel_cdclk_config *cdclk_config)
934{
935 u32 val;
936
937 cdclk_config->ref = 24000;
938 cdclk_config->vco = 0;
939
940 val = intel_de_read(display, LCPLL1_CTL);
941 if ((val & LCPLL_PLL_ENABLE) == 0)
942 return;
943
944 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
945 return;
946
947 val = intel_de_read(display, DPLL_CTRL1);
948
949 if (drm_WARN_ON(display->drm,
950 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
951 DPLL_CTRL1_SSC(SKL_DPLL0) |
952 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
953 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
954 return;
955
956 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
957 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
958 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
959 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
960 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
961 cdclk_config->vco = 8100000;
962 break;
963 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
964 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
965 cdclk_config->vco = 8640000;
966 break;
967 default:
968 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
969 break;
970 }
971}
972
973static void skl_get_cdclk(struct intel_display *display,
974 struct intel_cdclk_config *cdclk_config)
975{
976 u32 cdctl;
977
978 skl_dpll0_update(display, cdclk_config);
979
980 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
981
982 if (cdclk_config->vco == 0)
983 goto out;
984
985 cdctl = intel_de_read(display, CDCLK_CTL);
986
987 if (cdclk_config->vco == 8640000) {
988 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
989 case CDCLK_FREQ_450_432:
990 cdclk_config->cdclk = 432000;
991 break;
992 case CDCLK_FREQ_337_308:
993 cdclk_config->cdclk = 308571;
994 break;
995 case CDCLK_FREQ_540:
996 cdclk_config->cdclk = 540000;
997 break;
998 case CDCLK_FREQ_675_617:
999 cdclk_config->cdclk = 617143;
1000 break;
1001 default:
1002 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1003 break;
1004 }
1005 } else {
1006 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1007 case CDCLK_FREQ_450_432:
1008 cdclk_config->cdclk = 450000;
1009 break;
1010 case CDCLK_FREQ_337_308:
1011 cdclk_config->cdclk = 337500;
1012 break;
1013 case CDCLK_FREQ_540:
1014 cdclk_config->cdclk = 540000;
1015 break;
1016 case CDCLK_FREQ_675_617:
1017 cdclk_config->cdclk = 675000;
1018 break;
1019 default:
1020 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1021 break;
1022 }
1023 }
1024
1025 out:
1026 /*
1027 * Can't read this out :( Let's assume it's
1028 * at least what the CDCLK frequency requires.
1029 */
1030 cdclk_config->voltage_level =
1031 skl_calc_voltage_level(cdclk_config->cdclk);
1032}
1033
1034/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1035static int skl_cdclk_decimal(int cdclk)
1036{
1037 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1038}
1039
1040static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1041{
1042 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1043
1044 display->cdclk.skl_preferred_vco_freq = vco;
1045
1046 if (changed)
1047 intel_update_max_cdclk(display);
1048}
1049
1050static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1051{
1052 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1053
1054 /*
1055 * We always enable DPLL0 with the lowest link rate possible, but still
1056 * taking into account the VCO required to operate the eDP panel at the
1057 * desired frequency. The usual DP link rates operate with a VCO of
1058 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1059 * The modeset code is responsible for the selection of the exact link
1060 * rate later on, with the constraint of choosing a frequency that
1061 * works with vco.
1062 */
1063 if (vco == 8640000)
1064 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1065 else
1066 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1067}
1068
1069static void skl_dpll0_enable(struct intel_display *display, int vco)
1070{
1071 intel_de_rmw(display, DPLL_CTRL1,
1072 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1073 DPLL_CTRL1_SSC(SKL_DPLL0) |
1074 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1075 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1076 skl_dpll0_link_rate(display, vco));
1077 intel_de_posting_read(display, DPLL_CTRL1);
1078
1079 intel_de_rmw(display, LCPLL1_CTL,
1080 0, LCPLL_PLL_ENABLE);
1081
1082 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1083 drm_err(display->drm, "DPLL0 not locked\n");
1084
1085 display->cdclk.hw.vco = vco;
1086
1087 /* We'll want to keep using the current vco from now on. */
1088 skl_set_preferred_cdclk_vco(display, vco);
1089}
1090
1091static void skl_dpll0_disable(struct intel_display *display)
1092{
1093 intel_de_rmw(display, LCPLL1_CTL,
1094 LCPLL_PLL_ENABLE, 0);
1095
1096 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1097 drm_err(display->drm, "Couldn't disable DPLL0\n");
1098
1099 display->cdclk.hw.vco = 0;
1100}
1101
1102static u32 skl_cdclk_freq_sel(struct intel_display *display,
1103 int cdclk, int vco)
1104{
1105 switch (cdclk) {
1106 default:
1107 drm_WARN_ON(display->drm,
1108 cdclk != display->cdclk.hw.bypass);
1109 drm_WARN_ON(display->drm, vco != 0);
1110 fallthrough;
1111 case 308571:
1112 case 337500:
1113 return CDCLK_FREQ_337_308;
1114 case 450000:
1115 case 432000:
1116 return CDCLK_FREQ_450_432;
1117 case 540000:
1118 return CDCLK_FREQ_540;
1119 case 617143:
1120 case 675000:
1121 return CDCLK_FREQ_675_617;
1122 }
1123}
1124
1125static void skl_set_cdclk(struct intel_display *display,
1126 const struct intel_cdclk_config *cdclk_config,
1127 enum pipe pipe)
1128{
1129 struct drm_i915_private *dev_priv = to_i915(display->drm);
1130 int cdclk = cdclk_config->cdclk;
1131 int vco = cdclk_config->vco;
1132 u32 freq_select, cdclk_ctl;
1133 int ret;
1134
1135 /*
1136 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1137 * unsupported on SKL. In theory this should never happen since only
1138 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1139 * supported on SKL either, see the above WA. WARN whenever trying to
1140 * use the corresponding VCO freq as that always leads to using the
1141 * minimum 308MHz CDCLK.
1142 */
1143 drm_WARN_ON_ONCE(display->drm,
1144 IS_SKYLAKE(dev_priv) && vco == 8640000);
1145
1146 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1147 SKL_CDCLK_PREPARE_FOR_CHANGE,
1148 SKL_CDCLK_READY_FOR_CHANGE,
1149 SKL_CDCLK_READY_FOR_CHANGE, 3);
1150 if (ret) {
1151 drm_err(display->drm,
1152 "Failed to inform PCU about cdclk change (%d)\n", ret);
1153 return;
1154 }
1155
1156 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1157
1158 if (display->cdclk.hw.vco != 0 &&
1159 display->cdclk.hw.vco != vco)
1160 skl_dpll0_disable(display);
1161
1162 cdclk_ctl = intel_de_read(display, CDCLK_CTL);
1163
1164 if (display->cdclk.hw.vco != vco) {
1165 /* Wa Display #1183: skl,kbl,cfl */
1166 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1167 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1168 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1169 }
1170
1171 /* Wa Display #1183: skl,kbl,cfl */
1172 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1173 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1174 intel_de_posting_read(display, CDCLK_CTL);
1175
1176 if (display->cdclk.hw.vco != vco)
1177 skl_dpll0_enable(display, vco);
1178
1179 /* Wa Display #1183: skl,kbl,cfl */
1180 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1181 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1182
1183 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1184 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1185
1186 /* Wa Display #1183: skl,kbl,cfl */
1187 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1188 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1189 intel_de_posting_read(display, CDCLK_CTL);
1190
1191 /* inform PCU of the change */
1192 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1193 cdclk_config->voltage_level);
1194
1195 intel_update_cdclk(display);
1196}
1197
1198static void skl_sanitize_cdclk(struct intel_display *display)
1199{
1200 u32 cdctl, expected;
1201
1202 /*
1203 * check if the pre-os initialized the display
1204 * There is SWF18 scratchpad register defined which is set by the
1205 * pre-os which can be used by the OS drivers to check the status
1206 */
1207 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1208 goto sanitize;
1209
1210 intel_update_cdclk(display);
1211 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1212
1213 /* Is PLL enabled and locked ? */
1214 if (display->cdclk.hw.vco == 0 ||
1215 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1216 goto sanitize;
1217
1218 /* DPLL okay; verify the cdclock
1219 *
1220 * Noticed in some instances that the freq selection is correct but
1221 * decimal part is programmed wrong from BIOS where pre-os does not
1222 * enable display. Verify the same as well.
1223 */
1224 cdctl = intel_de_read(display, CDCLK_CTL);
1225 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1226 skl_cdclk_decimal(display->cdclk.hw.cdclk);
1227 if (cdctl == expected)
1228 /* All well; nothing to sanitize */
1229 return;
1230
1231sanitize:
1232 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1233
1234 /* force cdclk programming */
1235 display->cdclk.hw.cdclk = 0;
1236 /* force full PLL disable + enable */
1237 display->cdclk.hw.vco = ~0;
1238}
1239
1240static void skl_cdclk_init_hw(struct intel_display *display)
1241{
1242 struct intel_cdclk_config cdclk_config;
1243
1244 skl_sanitize_cdclk(display);
1245
1246 if (display->cdclk.hw.cdclk != 0 &&
1247 display->cdclk.hw.vco != 0) {
1248 /*
1249 * Use the current vco as our initial
1250 * guess as to what the preferred vco is.
1251 */
1252 if (display->cdclk.skl_preferred_vco_freq == 0)
1253 skl_set_preferred_cdclk_vco(display,
1254 display->cdclk.hw.vco);
1255 return;
1256 }
1257
1258 cdclk_config = display->cdclk.hw;
1259
1260 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1261 if (cdclk_config.vco == 0)
1262 cdclk_config.vco = 8100000;
1263 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1264 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1265
1266 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1267}
1268
1269static void skl_cdclk_uninit_hw(struct intel_display *display)
1270{
1271 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1272
1273 cdclk_config.cdclk = cdclk_config.bypass;
1274 cdclk_config.vco = 0;
1275 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1276
1277 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1278}
1279
1280struct intel_cdclk_vals {
1281 u32 cdclk;
1282 u16 refclk;
1283 u16 waveform;
1284 u8 ratio;
1285};
1286
1287static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1288 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1289 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1290 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1291 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1292 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1293 {}
1294};
1295
1296static const struct intel_cdclk_vals glk_cdclk_table[] = {
1297 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1298 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1299 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1300 {}
1301};
1302
1303static const struct intel_cdclk_vals icl_cdclk_table[] = {
1304 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1305 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1306 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1307 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1308 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1309 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1310
1311 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1312 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1313 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1314 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1315 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1316 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1317
1318 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1319 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1320 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1321 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1322 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1323 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1324 {}
1325};
1326
1327static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1328 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1329 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1330 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1331 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1332 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1333 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1334
1335 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1336 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1337 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1338 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1339 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1340 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1341
1342 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1343 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1344 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1345 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1346 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1347 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1348 {}
1349};
1350
1351static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1352 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1353 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1354 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1355
1356 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1357 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1358 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1359
1360 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1361 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1362 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1363 {}
1364};
1365
1366static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1367 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1368 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1369 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1370 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1371 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1372
1373 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1374 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1375 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1376 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1377 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1378
1379 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1380 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1381 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1382 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1383 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1384 {}
1385};
1386
1387static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1388 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1389 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1390 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1391 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1392 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1393 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1394
1395 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1396 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1397 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1398 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1399 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1400 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1401
1402 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1403 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1404 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1405 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1406 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1407 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1408 {}
1409};
1410
1411static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1412 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1413 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1414 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1415 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1416 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1417 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1418 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1419 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1420 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1421 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1422 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1423 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1424 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1425 {}
1426};
1427
1428static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1429 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1430 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1431 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1432 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1433 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1434 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1435 {}
1436};
1437
1438static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
1439 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1440 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1441 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1442 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1443 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1444 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1445 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1446 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1447 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1448 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1449 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1450 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1451 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1452 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1453 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1454 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1455 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1456 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1457 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1458 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1459 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1460 {}
1461};
1462
1463/*
1464 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1465 */
1466static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
1467 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1468 {}
1469};
1470
1471static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
1472 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1473 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1474 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1475 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1476 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1477 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1478 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1479 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1480 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1481 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1482 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1483 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1484 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1485 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1486 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1487 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1488 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1489 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1490 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1491 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1492 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1493 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1494 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1495 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1496 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1497 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1498 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1499 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1500 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1501 {}
1502};
1503
1504static const int cdclk_squash_len = 16;
1505
1506static int cdclk_squash_divider(u16 waveform)
1507{
1508 return hweight16(waveform ?: 0xffff);
1509}
1510
1511static int cdclk_divider(int cdclk, int vco, u16 waveform)
1512{
1513 /* 2 * cd2x divider */
1514 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1515 cdclk * cdclk_squash_len);
1516}
1517
1518static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
1519{
1520 const struct intel_cdclk_vals *table = display->cdclk.table;
1521 int i;
1522
1523 for (i = 0; table[i].refclk; i++)
1524 if (table[i].refclk == display->cdclk.hw.ref &&
1525 table[i].cdclk >= min_cdclk)
1526 return table[i].cdclk;
1527
1528 drm_WARN(display->drm, 1,
1529 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1530 min_cdclk, display->cdclk.hw.ref);
1531 return 0;
1532}
1533
1534static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
1535{
1536 const struct intel_cdclk_vals *table = display->cdclk.table;
1537 int i;
1538
1539 if (cdclk == display->cdclk.hw.bypass)
1540 return 0;
1541
1542 for (i = 0; table[i].refclk; i++)
1543 if (table[i].refclk == display->cdclk.hw.ref &&
1544 table[i].cdclk == cdclk)
1545 return display->cdclk.hw.ref * table[i].ratio;
1546
1547 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1548 cdclk, display->cdclk.hw.ref);
1549 return 0;
1550}
1551
1552static u8 bxt_calc_voltage_level(int cdclk)
1553{
1554 return DIV_ROUND_UP(cdclk, 25000);
1555}
1556
1557static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1558 const int voltage_level_max_cdclk[])
1559{
1560 int voltage_level;
1561
1562 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1563 if (cdclk <= voltage_level_max_cdclk[voltage_level])
1564 return voltage_level;
1565 }
1566
1567 MISSING_CASE(cdclk);
1568 return num_voltage_levels - 1;
1569}
1570
1571static u8 icl_calc_voltage_level(int cdclk)
1572{
1573 static const int icl_voltage_level_max_cdclk[] = {
1574 [0] = 312000,
1575 [1] = 556800,
1576 [2] = 652800,
1577 };
1578
1579 return calc_voltage_level(cdclk,
1580 ARRAY_SIZE(icl_voltage_level_max_cdclk),
1581 icl_voltage_level_max_cdclk);
1582}
1583
1584static u8 ehl_calc_voltage_level(int cdclk)
1585{
1586 static const int ehl_voltage_level_max_cdclk[] = {
1587 [0] = 180000,
1588 [1] = 312000,
1589 [2] = 326400,
1590 /*
1591 * Bspec lists the limit as 556.8 MHz, but some JSL
1592 * development boards (at least) boot with 652.8 MHz
1593 */
1594 [3] = 652800,
1595 };
1596
1597 return calc_voltage_level(cdclk,
1598 ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1599 ehl_voltage_level_max_cdclk);
1600}
1601
1602static u8 tgl_calc_voltage_level(int cdclk)
1603{
1604 static const int tgl_voltage_level_max_cdclk[] = {
1605 [0] = 312000,
1606 [1] = 326400,
1607 [2] = 556800,
1608 [3] = 652800,
1609 };
1610
1611 return calc_voltage_level(cdclk,
1612 ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1613 tgl_voltage_level_max_cdclk);
1614}
1615
1616static u8 rplu_calc_voltage_level(int cdclk)
1617{
1618 static const int rplu_voltage_level_max_cdclk[] = {
1619 [0] = 312000,
1620 [1] = 480000,
1621 [2] = 556800,
1622 [3] = 652800,
1623 };
1624
1625 return calc_voltage_level(cdclk,
1626 ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1627 rplu_voltage_level_max_cdclk);
1628}
1629
1630static u8 xe3lpd_calc_voltage_level(int cdclk)
1631{
1632 /*
1633 * Starting with xe3lpd power controller does not need the voltage
1634 * index when doing the modeset update. This function is best left
1635 * defined but returning 0 to the mask.
1636 */
1637 return 0;
1638}
1639
1640static void icl_readout_refclk(struct intel_display *display,
1641 struct intel_cdclk_config *cdclk_config)
1642{
1643 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1644
1645 switch (dssm) {
1646 default:
1647 MISSING_CASE(dssm);
1648 fallthrough;
1649 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1650 cdclk_config->ref = 24000;
1651 break;
1652 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1653 cdclk_config->ref = 19200;
1654 break;
1655 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1656 cdclk_config->ref = 38400;
1657 break;
1658 }
1659}
1660
1661static void bxt_de_pll_readout(struct intel_display *display,
1662 struct intel_cdclk_config *cdclk_config)
1663{
1664 struct drm_i915_private *dev_priv = to_i915(display->drm);
1665 u32 val, ratio;
1666
1667 if (IS_DG2(dev_priv))
1668 cdclk_config->ref = 38400;
1669 else if (DISPLAY_VER(display) >= 11)
1670 icl_readout_refclk(display, cdclk_config);
1671 else
1672 cdclk_config->ref = 19200;
1673
1674 val = intel_de_read(display, BXT_DE_PLL_ENABLE);
1675 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1676 (val & BXT_DE_PLL_LOCK) == 0) {
1677 /*
1678 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1679 * setting it to zero is a way to signal that.
1680 */
1681 cdclk_config->vco = 0;
1682 return;
1683 }
1684
1685 /*
1686 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1687 * gen9lp had it in a separate PLL control register.
1688 */
1689 if (DISPLAY_VER(display) >= 11)
1690 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1691 else
1692 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1693
1694 cdclk_config->vco = ratio * cdclk_config->ref;
1695}
1696
1697static void bxt_get_cdclk(struct intel_display *display,
1698 struct intel_cdclk_config *cdclk_config)
1699{
1700 u32 squash_ctl = 0;
1701 u32 divider;
1702 int div;
1703
1704 bxt_de_pll_readout(display, cdclk_config);
1705
1706 if (DISPLAY_VER(display) >= 12)
1707 cdclk_config->bypass = cdclk_config->ref / 2;
1708 else if (DISPLAY_VER(display) >= 11)
1709 cdclk_config->bypass = 50000;
1710 else
1711 cdclk_config->bypass = cdclk_config->ref;
1712
1713 if (cdclk_config->vco == 0) {
1714 cdclk_config->cdclk = cdclk_config->bypass;
1715 goto out;
1716 }
1717
1718 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1719
1720 switch (divider) {
1721 case BXT_CDCLK_CD2X_DIV_SEL_1:
1722 div = 2;
1723 break;
1724 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1725 div = 3;
1726 break;
1727 case BXT_CDCLK_CD2X_DIV_SEL_2:
1728 div = 4;
1729 break;
1730 case BXT_CDCLK_CD2X_DIV_SEL_4:
1731 div = 8;
1732 break;
1733 default:
1734 MISSING_CASE(divider);
1735 return;
1736 }
1737
1738 if (HAS_CDCLK_SQUASH(display))
1739 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
1740
1741 if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1742 u16 waveform;
1743 int size;
1744
1745 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1746 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1747
1748 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1749 cdclk_config->vco, size * div);
1750 } else {
1751 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1752 }
1753
1754 out:
1755 if (DISPLAY_VER(display) >= 20)
1756 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1757 /*
1758 * Can't read this out :( Let's assume it's
1759 * at least what the CDCLK frequency requires.
1760 */
1761 cdclk_config->voltage_level =
1762 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
1763}
1764
1765static void bxt_de_pll_disable(struct intel_display *display)
1766{
1767 intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
1768
1769 /* Timeout 200us */
1770 if (intel_de_wait_for_clear(display,
1771 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1772 drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1773
1774 display->cdclk.hw.vco = 0;
1775}
1776
1777static void bxt_de_pll_enable(struct intel_display *display, int vco)
1778{
1779 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1780
1781 intel_de_rmw(display, BXT_DE_PLL_CTL,
1782 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1783
1784 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1785
1786 /* Timeout 200us */
1787 if (intel_de_wait_for_set(display,
1788 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1789 drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1790
1791 display->cdclk.hw.vco = vco;
1792}
1793
1794static void icl_cdclk_pll_disable(struct intel_display *display)
1795{
1796 intel_de_rmw(display, BXT_DE_PLL_ENABLE,
1797 BXT_DE_PLL_PLL_ENABLE, 0);
1798
1799 /* Timeout 200us */
1800 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1801 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1802
1803 display->cdclk.hw.vco = 0;
1804}
1805
1806static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1807{
1808 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1809 u32 val;
1810
1811 val = ICL_CDCLK_PLL_RATIO(ratio);
1812 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1813
1814 val |= BXT_DE_PLL_PLL_ENABLE;
1815 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1816
1817 /* Timeout 200us */
1818 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1819 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1820
1821 display->cdclk.hw.vco = vco;
1822}
1823
1824static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1825{
1826 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1827 u32 val;
1828
1829 /* Write PLL ratio without disabling */
1830 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1831 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1832
1833 /* Submit freq change request */
1834 val |= BXT_DE_PLL_FREQ_REQ;
1835 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1836
1837 /* Timeout 200us */
1838 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
1839 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1840 drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1841
1842 val &= ~BXT_DE_PLL_FREQ_REQ;
1843 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1844
1845 display->cdclk.hw.vco = vco;
1846}
1847
1848static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
1849{
1850 if (DISPLAY_VER(display) >= 12) {
1851 if (pipe == INVALID_PIPE)
1852 return TGL_CDCLK_CD2X_PIPE_NONE;
1853 else
1854 return TGL_CDCLK_CD2X_PIPE(pipe);
1855 } else if (DISPLAY_VER(display) >= 11) {
1856 if (pipe == INVALID_PIPE)
1857 return ICL_CDCLK_CD2X_PIPE_NONE;
1858 else
1859 return ICL_CDCLK_CD2X_PIPE(pipe);
1860 } else {
1861 if (pipe == INVALID_PIPE)
1862 return BXT_CDCLK_CD2X_PIPE_NONE;
1863 else
1864 return BXT_CDCLK_CD2X_PIPE(pipe);
1865 }
1866}
1867
1868static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
1869 int cdclk, int vco, u16 waveform)
1870{
1871 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1872 switch (cdclk_divider(cdclk, vco, waveform)) {
1873 default:
1874 drm_WARN_ON(display->drm,
1875 cdclk != display->cdclk.hw.bypass);
1876 drm_WARN_ON(display->drm, vco != 0);
1877 fallthrough;
1878 case 2:
1879 return BXT_CDCLK_CD2X_DIV_SEL_1;
1880 case 3:
1881 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1882 case 4:
1883 return BXT_CDCLK_CD2X_DIV_SEL_2;
1884 case 8:
1885 return BXT_CDCLK_CD2X_DIV_SEL_4;
1886 }
1887}
1888
1889static u16 cdclk_squash_waveform(struct intel_display *display,
1890 int cdclk)
1891{
1892 const struct intel_cdclk_vals *table = display->cdclk.table;
1893 int i;
1894
1895 if (cdclk == display->cdclk.hw.bypass)
1896 return 0;
1897
1898 for (i = 0; table[i].refclk; i++)
1899 if (table[i].refclk == display->cdclk.hw.ref &&
1900 table[i].cdclk == cdclk)
1901 return table[i].waveform;
1902
1903 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1904 cdclk, display->cdclk.hw.ref);
1905
1906 return 0xffff;
1907}
1908
1909static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1910{
1911 if (display->cdclk.hw.vco != 0 &&
1912 display->cdclk.hw.vco != vco)
1913 icl_cdclk_pll_disable(display);
1914
1915 if (display->cdclk.hw.vco != vco)
1916 icl_cdclk_pll_enable(display, vco);
1917}
1918
1919static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1920{
1921 if (display->cdclk.hw.vco != 0 &&
1922 display->cdclk.hw.vco != vco)
1923 bxt_de_pll_disable(display);
1924
1925 if (display->cdclk.hw.vco != vco)
1926 bxt_de_pll_enable(display, vco);
1927}
1928
1929static void dg2_cdclk_squash_program(struct intel_display *display,
1930 u16 waveform)
1931{
1932 u32 squash_ctl = 0;
1933
1934 if (waveform)
1935 squash_ctl = CDCLK_SQUASH_ENABLE |
1936 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1937
1938 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
1939}
1940
1941static bool cdclk_pll_is_unknown(unsigned int vco)
1942{
1943 /*
1944 * Ensure driver does not take the crawl path for the
1945 * case when the vco is set to ~0 in the
1946 * sanitize path.
1947 */
1948 return vco == ~0;
1949}
1950
1951static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
1952{
1953 return DISPLAY_VER(display) >= 20;
1954}
1955
1956static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
1957{
1958 if (mdclk_source_is_cdclk_pll(display))
1959 return MDCLK_SOURCE_SEL_CDCLK_PLL;
1960
1961 return MDCLK_SOURCE_SEL_CD2XCLK;
1962}
1963
1964int intel_mdclk_cdclk_ratio(struct intel_display *display,
1965 const struct intel_cdclk_config *cdclk_config)
1966{
1967 if (mdclk_source_is_cdclk_pll(display))
1968 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
1969
1970 /* Otherwise, source for MDCLK is CD2XCLK. */
1971 return 2;
1972}
1973
1974static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
1975 const struct intel_cdclk_config *cdclk_config)
1976{
1977 struct drm_i915_private *i915 = to_i915(display->drm);
1978
1979 intel_dbuf_mdclk_cdclk_ratio_update(i915,
1980 intel_mdclk_cdclk_ratio(display, cdclk_config),
1981 cdclk_config->joined_mbus);
1982}
1983
1984static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
1985 const struct intel_cdclk_config *old_cdclk_config,
1986 const struct intel_cdclk_config *new_cdclk_config,
1987 struct intel_cdclk_config *mid_cdclk_config)
1988{
1989 u16 old_waveform, new_waveform, mid_waveform;
1990 int old_div, new_div, mid_div;
1991
1992 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1993 if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1994 return false;
1995
1996 /* Return if both Squash and Crawl are not present */
1997 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
1998 return false;
1999
2000 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
2001 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
2002
2003 /* Return if Squash only or Crawl only is the desired action */
2004 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2005 old_cdclk_config->vco == new_cdclk_config->vco ||
2006 old_waveform == new_waveform)
2007 return false;
2008
2009 old_div = cdclk_divider(old_cdclk_config->cdclk,
2010 old_cdclk_config->vco, old_waveform);
2011 new_div = cdclk_divider(new_cdclk_config->cdclk,
2012 new_cdclk_config->vco, new_waveform);
2013
2014 /*
2015 * Should not happen currently. We might need more midpoint
2016 * transitions if we need to also change the cd2x divider.
2017 */
2018 if (drm_WARN_ON(display->drm, old_div != new_div))
2019 return false;
2020
2021 *mid_cdclk_config = *new_cdclk_config;
2022
2023 /*
2024 * Populate the mid_cdclk_config accordingly.
2025 * - If moving to a higher cdclk, the desired action is squashing.
2026 * The mid cdclk config should have the new (squash) waveform.
2027 * - If moving to a lower cdclk, the desired action is crawling.
2028 * The mid cdclk config should have the new vco.
2029 */
2030
2031 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
2032 mid_cdclk_config->vco = old_cdclk_config->vco;
2033 mid_div = old_div;
2034 mid_waveform = new_waveform;
2035 } else {
2036 mid_cdclk_config->vco = new_cdclk_config->vco;
2037 mid_div = new_div;
2038 mid_waveform = old_waveform;
2039 }
2040
2041 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
2042 mid_cdclk_config->vco,
2043 cdclk_squash_len * mid_div);
2044
2045 /* make sure the mid clock came out sane */
2046
2047 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2048 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
2049 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2050 display->cdclk.max_cdclk_freq);
2051 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2052 mid_waveform);
2053
2054 return true;
2055}
2056
2057static bool pll_enable_wa_needed(struct intel_display *display)
2058{
2059 struct drm_i915_private *dev_priv = to_i915(display->drm);
2060
2061 return (DISPLAY_VERx100(display) == 2000 ||
2062 DISPLAY_VERx100(display) == 1400 ||
2063 IS_DG2(dev_priv)) &&
2064 display->cdclk.hw.vco > 0;
2065}
2066
2067static u32 bxt_cdclk_ctl(struct intel_display *display,
2068 const struct intel_cdclk_config *cdclk_config,
2069 enum pipe pipe)
2070{
2071 struct drm_i915_private *i915 = to_i915(display->drm);
2072 int cdclk = cdclk_config->cdclk;
2073 int vco = cdclk_config->vco;
2074 u16 waveform;
2075 u32 val;
2076
2077 waveform = cdclk_squash_waveform(display, cdclk);
2078
2079 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2080 bxt_cdclk_cd2x_pipe(display, pipe);
2081
2082 /*
2083 * Disable SSA Precharge when CD clock frequency < 500 MHz,
2084 * enable otherwise.
2085 */
2086 if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) &&
2087 cdclk >= 500000)
2088 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
2089
2090 if (DISPLAY_VER(display) >= 20)
2091 val |= xe2lpd_mdclk_source_sel(display);
2092 else
2093 val |= skl_cdclk_decimal(cdclk);
2094
2095 return val;
2096}
2097
2098static void _bxt_set_cdclk(struct intel_display *display,
2099 const struct intel_cdclk_config *cdclk_config,
2100 enum pipe pipe)
2101{
2102 int cdclk = cdclk_config->cdclk;
2103 int vco = cdclk_config->vco;
2104
2105 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2106 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2107 if (display->cdclk.hw.vco != vco)
2108 adlp_cdclk_pll_crawl(display, vco);
2109 } else if (DISPLAY_VER(display) >= 11) {
2110 /* wa_15010685871: dg2, mtl */
2111 if (pll_enable_wa_needed(display))
2112 dg2_cdclk_squash_program(display, 0);
2113
2114 icl_cdclk_pll_update(display, vco);
2115 } else {
2116 bxt_cdclk_pll_update(display, vco);
2117 }
2118
2119 if (HAS_CDCLK_SQUASH(display)) {
2120 u16 waveform = cdclk_squash_waveform(display, cdclk);
2121
2122 dg2_cdclk_squash_program(display, waveform);
2123 }
2124
2125 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
2126
2127 if (pipe != INVALID_PIPE)
2128 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
2129}
2130
2131static void bxt_set_cdclk(struct intel_display *display,
2132 const struct intel_cdclk_config *cdclk_config,
2133 enum pipe pipe)
2134{
2135 struct drm_i915_private *dev_priv = to_i915(display->drm);
2136 struct intel_cdclk_config mid_cdclk_config;
2137 int cdclk = cdclk_config->cdclk;
2138 int ret = 0;
2139
2140 /*
2141 * Inform power controller of upcoming frequency change.
2142 * Display versions 14 and beyond do not follow the PUnit
2143 * mailbox communication, skip
2144 * this step.
2145 */
2146 if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv))
2147 /* NOOP */;
2148 else if (DISPLAY_VER(display) >= 11)
2149 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2150 SKL_CDCLK_PREPARE_FOR_CHANGE,
2151 SKL_CDCLK_READY_FOR_CHANGE,
2152 SKL_CDCLK_READY_FOR_CHANGE, 3);
2153 else
2154 /*
2155 * BSpec requires us to wait up to 150usec, but that leads to
2156 * timeouts; the 2ms used here is based on experiment.
2157 */
2158 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2159 HSW_PCODE_DE_WRITE_FREQ_REQ,
2160 0x80000000, 150, 2);
2161
2162 if (ret) {
2163 drm_err(display->drm,
2164 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2165 ret, cdclk);
2166 return;
2167 }
2168
2169 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2170 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2171
2172 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
2173 cdclk_config, &mid_cdclk_config)) {
2174 _bxt_set_cdclk(display, &mid_cdclk_config, pipe);
2175 _bxt_set_cdclk(display, cdclk_config, pipe);
2176 } else {
2177 _bxt_set_cdclk(display, cdclk_config, pipe);
2178 }
2179
2180 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2181 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2182
2183 if (DISPLAY_VER(display) >= 14)
2184 /*
2185 * NOOP - No Pcode communication needed for
2186 * Display versions 14 and beyond
2187 */;
2188 else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv))
2189 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2190 cdclk_config->voltage_level);
2191 if (DISPLAY_VER(display) < 11) {
2192 /*
2193 * The timeout isn't specified, the 2ms used here is based on
2194 * experiment.
2195 * FIXME: Waiting for the request completion could be delayed
2196 * until the next PCODE request based on BSpec.
2197 */
2198 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2199 HSW_PCODE_DE_WRITE_FREQ_REQ,
2200 cdclk_config->voltage_level,
2201 150, 2);
2202 }
2203 if (ret) {
2204 drm_err(display->drm,
2205 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
2206 ret, cdclk);
2207 return;
2208 }
2209
2210 intel_update_cdclk(display);
2211
2212 if (DISPLAY_VER(display) >= 11)
2213 /*
2214 * Can't read out the voltage level :(
2215 * Let's just assume everything is as expected.
2216 */
2217 display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2218}
2219
2220static void bxt_sanitize_cdclk(struct intel_display *display)
2221{
2222 u32 cdctl, expected;
2223 int cdclk, vco;
2224
2225 intel_update_cdclk(display);
2226 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
2227
2228 if (display->cdclk.hw.vco == 0 ||
2229 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2230 goto sanitize;
2231
2232 /* Make sure this is a legal cdclk value for the platform */
2233 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
2234 if (cdclk != display->cdclk.hw.cdclk)
2235 goto sanitize;
2236
2237 /* Make sure the VCO is correct for the cdclk */
2238 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2239 if (vco != display->cdclk.hw.vco)
2240 goto sanitize;
2241
2242 /*
2243 * Some BIOS versions leave an incorrect decimal frequency value and
2244 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2245 * so sanitize this register.
2246 */
2247 cdctl = intel_de_read(display, CDCLK_CTL);
2248 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
2249
2250 /*
2251 * Let's ignore the pipe field, since BIOS could have configured the
2252 * dividers both synching to an active pipe, or asynchronously
2253 * (PIPE_NONE).
2254 */
2255 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2256 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2257
2258 if (cdctl == expected)
2259 /* All well; nothing to sanitize */
2260 return;
2261
2262sanitize:
2263 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2264
2265 /* force cdclk programming */
2266 display->cdclk.hw.cdclk = 0;
2267
2268 /* force full PLL disable + enable */
2269 display->cdclk.hw.vco = ~0;
2270}
2271
2272static void bxt_cdclk_init_hw(struct intel_display *display)
2273{
2274 struct intel_cdclk_config cdclk_config;
2275
2276 bxt_sanitize_cdclk(display);
2277
2278 if (display->cdclk.hw.cdclk != 0 &&
2279 display->cdclk.hw.vco != 0)
2280 return;
2281
2282 cdclk_config = display->cdclk.hw;
2283
2284 /*
2285 * FIXME:
2286 * - The initial CDCLK needs to be read from VBT.
2287 * Need to make this change after VBT has changes for BXT.
2288 */
2289 cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
2290 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2291 cdclk_config.voltage_level =
2292 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2293
2294 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2295}
2296
2297static void bxt_cdclk_uninit_hw(struct intel_display *display)
2298{
2299 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2300
2301 cdclk_config.cdclk = cdclk_config.bypass;
2302 cdclk_config.vco = 0;
2303 cdclk_config.voltage_level =
2304 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2305
2306 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2307}
2308
2309/**
2310 * intel_cdclk_init_hw - Initialize CDCLK hardware
2311 * @display: display instance
2312 *
2313 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2314 * sanitizing the state of the hardware if needed. This is generally done only
2315 * during the display core initialization sequence, after which the DMC will
2316 * take care of turning CDCLK off/on as needed.
2317 */
2318void intel_cdclk_init_hw(struct intel_display *display)
2319{
2320 struct drm_i915_private *i915 = to_i915(display->drm);
2321
2322 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915))
2323 bxt_cdclk_init_hw(display);
2324 else if (DISPLAY_VER(display) == 9)
2325 skl_cdclk_init_hw(display);
2326}
2327
2328/**
2329 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2330 * @display: display instance
2331 *
2332 * Uninitialize CDCLK. This is done only during the display core
2333 * uninitialization sequence.
2334 */
2335void intel_cdclk_uninit_hw(struct intel_display *display)
2336{
2337 struct drm_i915_private *i915 = to_i915(display->drm);
2338
2339 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915))
2340 bxt_cdclk_uninit_hw(display);
2341 else if (DISPLAY_VER(display) == 9)
2342 skl_cdclk_uninit_hw(display);
2343}
2344
2345static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
2346 const struct intel_cdclk_config *a,
2347 const struct intel_cdclk_config *b)
2348{
2349 u16 old_waveform;
2350 u16 new_waveform;
2351
2352 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2353
2354 if (a->vco == 0 || b->vco == 0)
2355 return false;
2356
2357 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2358 return false;
2359
2360 old_waveform = cdclk_squash_waveform(display, a->cdclk);
2361 new_waveform = cdclk_squash_waveform(display, b->cdclk);
2362
2363 return a->vco != b->vco &&
2364 old_waveform != new_waveform;
2365}
2366
2367static bool intel_cdclk_can_crawl(struct intel_display *display,
2368 const struct intel_cdclk_config *a,
2369 const struct intel_cdclk_config *b)
2370{
2371 int a_div, b_div;
2372
2373 if (!HAS_CDCLK_CRAWL(display))
2374 return false;
2375
2376 /*
2377 * The vco and cd2x divider will change independently
2378 * from each, so we disallow cd2x change when crawling.
2379 */
2380 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2381 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2382
2383 return a->vco != 0 && b->vco != 0 &&
2384 a->vco != b->vco &&
2385 a_div == b_div &&
2386 a->ref == b->ref;
2387}
2388
2389static bool intel_cdclk_can_squash(struct intel_display *display,
2390 const struct intel_cdclk_config *a,
2391 const struct intel_cdclk_config *b)
2392{
2393 /*
2394 * FIXME should store a bit more state in intel_cdclk_config
2395 * to differentiate squasher vs. cd2x divider properly. For
2396 * the moment all platforms with squasher use a fixed cd2x
2397 * divider.
2398 */
2399 if (!HAS_CDCLK_SQUASH(display))
2400 return false;
2401
2402 return a->cdclk != b->cdclk &&
2403 a->vco != 0 &&
2404 a->vco == b->vco &&
2405 a->ref == b->ref;
2406}
2407
2408/**
2409 * intel_cdclk_clock_changed - Check whether the clock changed
2410 * @a: first CDCLK configuration
2411 * @b: second CDCLK configuration
2412 *
2413 * Returns:
2414 * True if CDCLK changed in a way that requires re-programming and
2415 * False otherwise.
2416 */
2417bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
2418 const struct intel_cdclk_config *b)
2419{
2420 return a->cdclk != b->cdclk ||
2421 a->vco != b->vco ||
2422 a->ref != b->ref;
2423}
2424
2425/**
2426 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2427 * configurations requires only a cd2x divider update
2428 * @display: display instance
2429 * @a: first CDCLK configuration
2430 * @b: second CDCLK configuration
2431 *
2432 * Returns:
2433 * True if changing between the two CDCLK configurations
2434 * can be done with just a cd2x divider update, false if not.
2435 */
2436static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
2437 const struct intel_cdclk_config *a,
2438 const struct intel_cdclk_config *b)
2439{
2440 struct drm_i915_private *dev_priv = to_i915(display->drm);
2441
2442 /* Older hw doesn't have the capability */
2443 if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv))
2444 return false;
2445
2446 /*
2447 * FIXME should store a bit more state in intel_cdclk_config
2448 * to differentiate squasher vs. cd2x divider properly. For
2449 * the moment all platforms with squasher use a fixed cd2x
2450 * divider.
2451 */
2452 if (HAS_CDCLK_SQUASH(display))
2453 return false;
2454
2455 return a->cdclk != b->cdclk &&
2456 a->vco != 0 &&
2457 a->vco == b->vco &&
2458 a->ref == b->ref;
2459}
2460
2461/**
2462 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2463 * @a: first CDCLK configuration
2464 * @b: second CDCLK configuration
2465 *
2466 * Returns:
2467 * True if the CDCLK configurations don't match, false if they do.
2468 */
2469static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2470 const struct intel_cdclk_config *b)
2471{
2472 return intel_cdclk_clock_changed(a, b) ||
2473 a->voltage_level != b->voltage_level;
2474}
2475
2476void intel_cdclk_dump_config(struct intel_display *display,
2477 const struct intel_cdclk_config *cdclk_config,
2478 const char *context)
2479{
2480 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2481 context, cdclk_config->cdclk, cdclk_config->vco,
2482 cdclk_config->ref, cdclk_config->bypass,
2483 cdclk_config->voltage_level);
2484}
2485
2486static void intel_pcode_notify(struct intel_display *display,
2487 u8 voltage_level,
2488 u8 active_pipe_count,
2489 u16 cdclk,
2490 bool cdclk_update_valid,
2491 bool pipe_count_update_valid)
2492{
2493 struct drm_i915_private *i915 = to_i915(display->drm);
2494 int ret;
2495 u32 update_mask = 0;
2496
2497 if (!IS_DG2(i915))
2498 return;
2499
2500 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2501
2502 if (cdclk_update_valid)
2503 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2504
2505 if (pipe_count_update_valid)
2506 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2507
2508 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2509 SKL_CDCLK_PREPARE_FOR_CHANGE |
2510 update_mask,
2511 SKL_CDCLK_READY_FOR_CHANGE,
2512 SKL_CDCLK_READY_FOR_CHANGE, 3);
2513 if (ret)
2514 drm_err(display->drm,
2515 "Failed to inform PCU about display config (err %d)\n",
2516 ret);
2517}
2518
2519static void intel_set_cdclk(struct intel_display *display,
2520 const struct intel_cdclk_config *cdclk_config,
2521 enum pipe pipe, const char *context)
2522{
2523 struct drm_i915_private *dev_priv = to_i915(display->drm);
2524 struct intel_encoder *encoder;
2525
2526 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
2527 return;
2528
2529 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2530 return;
2531
2532 intel_cdclk_dump_config(display, cdclk_config, context);
2533
2534 for_each_intel_encoder_with_psr(display->drm, encoder) {
2535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2536
2537 intel_psr_pause(intel_dp);
2538 }
2539
2540 intel_audio_cdclk_change_pre(dev_priv);
2541
2542 /*
2543 * Lock aux/gmbus while we change cdclk in case those
2544 * functions use cdclk. Not all platforms/ports do,
2545 * but we'll lock them all for simplicity.
2546 */
2547 mutex_lock(&display->gmbus.mutex);
2548 for_each_intel_dp(display->drm, encoder) {
2549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2550
2551 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2552 &display->gmbus.mutex);
2553 }
2554
2555 intel_cdclk_set_cdclk(display, cdclk_config, pipe);
2556
2557 for_each_intel_dp(display->drm, encoder) {
2558 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2559
2560 mutex_unlock(&intel_dp->aux.hw_mutex);
2561 }
2562 mutex_unlock(&display->gmbus.mutex);
2563
2564 for_each_intel_encoder_with_psr(display->drm, encoder) {
2565 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2566
2567 intel_psr_resume(intel_dp);
2568 }
2569
2570 intel_audio_cdclk_change_post(dev_priv);
2571
2572 if (drm_WARN(display->drm,
2573 intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2574 "cdclk state doesn't match!\n")) {
2575 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
2576 intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
2577 }
2578}
2579
2580static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2581{
2582 struct intel_display *display = to_intel_display(state);
2583 const struct intel_cdclk_state *old_cdclk_state =
2584 intel_atomic_get_old_cdclk_state(state);
2585 const struct intel_cdclk_state *new_cdclk_state =
2586 intel_atomic_get_new_cdclk_state(state);
2587 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2588 bool change_cdclk, update_pipe_count;
2589
2590 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2591 &new_cdclk_state->actual) &&
2592 new_cdclk_state->active_pipes ==
2593 old_cdclk_state->active_pipes)
2594 return;
2595
2596 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2597 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2598
2599 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2600 update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2601 hweight8(old_cdclk_state->active_pipes);
2602
2603 /*
2604 * According to "Sequence Before Frequency Change",
2605 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2606 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2607 * which basically means we choose the maximum of old and new CDCLK, if we know both
2608 */
2609 if (change_cdclk)
2610 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2611
2612 /*
2613 * According to "Sequence For Pipe Count Change",
2614 * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2615 * (power well is enabled)
2616 * no action if it is decreasing, before the change
2617 */
2618 if (update_pipe_count)
2619 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2620
2621 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2622 change_cdclk, update_pipe_count);
2623}
2624
2625static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2626{
2627 struct intel_display *display = to_intel_display(state);
2628 const struct intel_cdclk_state *new_cdclk_state =
2629 intel_atomic_get_new_cdclk_state(state);
2630 const struct intel_cdclk_state *old_cdclk_state =
2631 intel_atomic_get_old_cdclk_state(state);
2632 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2633 bool update_cdclk, update_pipe_count;
2634
2635 /* According to "Sequence After Frequency Change", set voltage to used level */
2636 voltage_level = new_cdclk_state->actual.voltage_level;
2637
2638 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2639 update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2640 hweight8(old_cdclk_state->active_pipes);
2641
2642 /*
2643 * According to "Sequence After Frequency Change",
2644 * set bits 25:16 to current CDCLK
2645 */
2646 if (update_cdclk)
2647 cdclk = new_cdclk_state->actual.cdclk;
2648
2649 /*
2650 * According to "Sequence For Pipe Count Change",
2651 * if pipe count is decreasing, set bits 25:16 to current pipe count,
2652 * after the change(power well is disabled)
2653 * no action if it is increasing, after the change
2654 */
2655 if (update_pipe_count)
2656 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2657
2658 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2659 update_cdclk, update_pipe_count);
2660}
2661
2662bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
2663{
2664 const struct intel_cdclk_state *old_cdclk_state =
2665 intel_atomic_get_old_cdclk_state(state);
2666 const struct intel_cdclk_state *new_cdclk_state =
2667 intel_atomic_get_new_cdclk_state(state);
2668
2669 return new_cdclk_state && !new_cdclk_state->disable_pipes &&
2670 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2671}
2672
2673/**
2674 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2675 * @state: intel atomic state
2676 *
2677 * Program the hardware before updating the HW plane state based on the
2678 * new CDCLK state, if necessary.
2679 */
2680void
2681intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2682{
2683 struct intel_display *display = to_intel_display(state);
2684 struct drm_i915_private *i915 = to_i915(display->drm);
2685 const struct intel_cdclk_state *old_cdclk_state =
2686 intel_atomic_get_old_cdclk_state(state);
2687 const struct intel_cdclk_state *new_cdclk_state =
2688 intel_atomic_get_new_cdclk_state(state);
2689 struct intel_cdclk_config cdclk_config;
2690 enum pipe pipe;
2691
2692 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2693 &new_cdclk_state->actual))
2694 return;
2695
2696 if (IS_DG2(i915))
2697 intel_cdclk_pcode_pre_notify(state);
2698
2699 if (new_cdclk_state->disable_pipes) {
2700 cdclk_config = new_cdclk_state->actual;
2701 pipe = INVALID_PIPE;
2702 } else {
2703 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2704 cdclk_config = new_cdclk_state->actual;
2705 pipe = new_cdclk_state->pipe;
2706 } else {
2707 cdclk_config = old_cdclk_state->actual;
2708 pipe = INVALID_PIPE;
2709 }
2710
2711 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2712 old_cdclk_state->actual.voltage_level);
2713 }
2714
2715 /*
2716 * mbus joining will be changed later by
2717 * intel_dbuf_mbus_{pre,post}_ddb_update()
2718 */
2719 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2720
2721 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2722
2723 intel_set_cdclk(display, &cdclk_config, pipe,
2724 "Pre changing CDCLK to");
2725}
2726
2727/**
2728 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2729 * @state: intel atomic state
2730 *
2731 * Program the hardware after updating the HW plane state based on the
2732 * new CDCLK state, if necessary.
2733 */
2734void
2735intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2736{
2737 struct intel_display *display = to_intel_display(state);
2738 struct drm_i915_private *i915 = to_i915(display->drm);
2739 const struct intel_cdclk_state *old_cdclk_state =
2740 intel_atomic_get_old_cdclk_state(state);
2741 const struct intel_cdclk_state *new_cdclk_state =
2742 intel_atomic_get_new_cdclk_state(state);
2743 enum pipe pipe;
2744
2745 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2746 &new_cdclk_state->actual))
2747 return;
2748
2749 if (IS_DG2(i915))
2750 intel_cdclk_pcode_post_notify(state);
2751
2752 if (!new_cdclk_state->disable_pipes &&
2753 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2754 pipe = new_cdclk_state->pipe;
2755 else
2756 pipe = INVALID_PIPE;
2757
2758 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2759
2760 intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
2761 "Post changing CDCLK to");
2762}
2763
2764static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2765{
2766 struct intel_display *display = to_intel_display(crtc_state);
2767 struct drm_i915_private *dev_priv = to_i915(display->drm);
2768 int pixel_rate = crtc_state->pixel_rate;
2769
2770 if (DISPLAY_VER(display) >= 10)
2771 return DIV_ROUND_UP(pixel_rate, 2);
2772 else if (DISPLAY_VER(display) == 9 ||
2773 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2774 return pixel_rate;
2775 else if (IS_CHERRYVIEW(dev_priv))
2776 return DIV_ROUND_UP(pixel_rate * 100, 95);
2777 else if (crtc_state->double_wide)
2778 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2779 else
2780 return DIV_ROUND_UP(pixel_rate * 100, 90);
2781}
2782
2783static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2784{
2785 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2786 struct intel_display *display = to_intel_display(crtc);
2787 struct intel_plane *plane;
2788 int min_cdclk = 0;
2789
2790 for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2791 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2792
2793 return min_cdclk;
2794}
2795
2796static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
2797{
2798 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2799 struct intel_display *display = to_intel_display(crtc);
2800 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
2801 int min_cdclk = 0;
2802
2803 /*
2804 * When we decide to use only one VDSC engine, since
2805 * each VDSC operates with 1 ppc throughput, pixel clock
2806 * cannot be higher than the VDSC clock (cdclk)
2807 * If there 2 VDSC engines, then pixel clock can't be higher than
2808 * VDSC clock(cdclk) * 2 and so on.
2809 */
2810 min_cdclk = max_t(int, min_cdclk,
2811 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
2812
2813 if (crtc_state->joiner_pipes) {
2814 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
2815
2816 /*
2817 * According to Bigjoiner bw check:
2818 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
2819 *
2820 * We have already computed compressed_bpp, so now compute the min CDCLK that
2821 * is required to support this compressed_bpp.
2822 *
2823 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
2824 *
2825 * Since PPC = 2 with bigjoiner
2826 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
2827 */
2828 int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
2829 int min_cdclk_bj =
2830 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
2831 pixel_clock) / (2 * bigjoiner_interface_bits);
2832
2833 min_cdclk = max(min_cdclk, min_cdclk_bj);
2834 }
2835
2836 return min_cdclk;
2837}
2838
2839int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2840{
2841 struct intel_display *display = to_intel_display(crtc_state);
2842 struct drm_i915_private *dev_priv = to_i915(display->drm);
2843 int min_cdclk;
2844
2845 if (!crtc_state->hw.enable)
2846 return 0;
2847
2848 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2849
2850 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2851 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2852 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2853
2854 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2855 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2856 * there may be audio corruption or screen corruption." This cdclk
2857 * restriction for GLK is 316.8 MHz.
2858 */
2859 if (intel_crtc_has_dp_encoder(crtc_state) &&
2860 crtc_state->has_audio &&
2861 crtc_state->port_clock >= 540000 &&
2862 crtc_state->lane_count == 4) {
2863 if (DISPLAY_VER(display) == 10) {
2864 /* Display WA #1145: glk */
2865 min_cdclk = max(316800, min_cdclk);
2866 } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
2867 /* Display WA #1144: skl,bxt */
2868 min_cdclk = max(432000, min_cdclk);
2869 }
2870 }
2871
2872 /*
2873 * According to BSpec, "The CD clock frequency must be at least twice
2874 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2875 */
2876 if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
2877 min_cdclk = max(2 * 96000, min_cdclk);
2878
2879 /*
2880 * "For DP audio configuration, cdclk frequency shall be set to
2881 * meet the following requirements:
2882 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
2883 * 270 | 320 or higher
2884 * 162 | 200 or higher"
2885 */
2886 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2887 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2888 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2889
2890 /*
2891 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2892 * than 320000KHz.
2893 */
2894 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2895 IS_VALLEYVIEW(dev_priv))
2896 min_cdclk = max(320000, min_cdclk);
2897
2898 /*
2899 * On Geminilake once the CDCLK gets as low as 79200
2900 * picture gets unstable, despite that values are
2901 * correct for DSI PLL and DE PLL.
2902 */
2903 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2904 IS_GEMINILAKE(dev_priv))
2905 min_cdclk = max(158400, min_cdclk);
2906
2907 /* Account for additional needs from the planes */
2908 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2909
2910 if (crtc_state->dsc.compression_enable)
2911 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2912
2913 return min_cdclk;
2914}
2915
2916static int intel_compute_min_cdclk(struct intel_atomic_state *state)
2917{
2918 struct intel_display *display = to_intel_display(state);
2919 struct drm_i915_private *dev_priv = to_i915(display->drm);
2920 struct intel_cdclk_state *cdclk_state =
2921 intel_atomic_get_new_cdclk_state(state);
2922 const struct intel_bw_state *bw_state;
2923 struct intel_crtc *crtc;
2924 struct intel_crtc_state *crtc_state;
2925 int min_cdclk, i;
2926 enum pipe pipe;
2927
2928 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2929 int ret;
2930
2931 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2932 if (min_cdclk < 0)
2933 return min_cdclk;
2934
2935 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2936 continue;
2937
2938 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2939
2940 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2941 if (ret)
2942 return ret;
2943 }
2944
2945 bw_state = intel_atomic_get_new_bw_state(state);
2946 if (bw_state) {
2947 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
2948
2949 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2950 int ret;
2951
2952 cdclk_state->bw_min_cdclk = min_cdclk;
2953
2954 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2955 if (ret)
2956 return ret;
2957 }
2958 }
2959
2960 min_cdclk = max(cdclk_state->force_min_cdclk,
2961 cdclk_state->bw_min_cdclk);
2962 for_each_pipe(display, pipe)
2963 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2964
2965 /*
2966 * Avoid glk_force_audio_cdclk() causing excessive screen
2967 * blinking when multiple pipes are active by making sure
2968 * CDCLK frequency is always high enough for audio. With a
2969 * single active pipe we can always change CDCLK frequency
2970 * by changing the cd2x divider (see glk_cdclk_table[]) and
2971 * thus a full modeset won't be needed then.
2972 */
2973 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
2974 !is_power_of_2(cdclk_state->active_pipes))
2975 min_cdclk = max(2 * 96000, min_cdclk);
2976
2977 if (min_cdclk > display->cdclk.max_cdclk_freq) {
2978 drm_dbg_kms(display->drm,
2979 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2980 min_cdclk, display->cdclk.max_cdclk_freq);
2981 return -EINVAL;
2982 }
2983
2984 return min_cdclk;
2985}
2986
2987/*
2988 * Account for port clock min voltage level requirements.
2989 * This only really does something on DISPLA_VER >= 11 but can be
2990 * called on earlier platforms as well.
2991 *
2992 * Note that this functions assumes that 0 is
2993 * the lowest voltage value, and higher values
2994 * correspond to increasingly higher voltages.
2995 *
2996 * Should that relationship no longer hold on
2997 * future platforms this code will need to be
2998 * adjusted.
2999 */
3000static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
3001{
3002 struct intel_display *display = to_intel_display(state);
3003 struct intel_cdclk_state *cdclk_state =
3004 intel_atomic_get_new_cdclk_state(state);
3005 struct intel_crtc *crtc;
3006 struct intel_crtc_state *crtc_state;
3007 u8 min_voltage_level;
3008 int i;
3009 enum pipe pipe;
3010
3011 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3012 int ret;
3013
3014 if (crtc_state->hw.enable)
3015 min_voltage_level = crtc_state->min_voltage_level;
3016 else
3017 min_voltage_level = 0;
3018
3019 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
3020 continue;
3021
3022 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
3023
3024 ret = intel_atomic_lock_global_state(&cdclk_state->base);
3025 if (ret)
3026 return ret;
3027 }
3028
3029 min_voltage_level = 0;
3030 for_each_pipe(display, pipe)
3031 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
3032 min_voltage_level);
3033
3034 return min_voltage_level;
3035}
3036
3037static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
3038{
3039 struct intel_display *display = to_intel_display(state);
3040 struct intel_cdclk_state *cdclk_state =
3041 intel_atomic_get_new_cdclk_state(state);
3042 int min_cdclk, cdclk;
3043
3044 min_cdclk = intel_compute_min_cdclk(state);
3045 if (min_cdclk < 0)
3046 return min_cdclk;
3047
3048 cdclk = vlv_calc_cdclk(display, min_cdclk);
3049
3050 cdclk_state->logical.cdclk = cdclk;
3051 cdclk_state->logical.voltage_level =
3052 vlv_calc_voltage_level(display, cdclk);
3053
3054 if (!cdclk_state->active_pipes) {
3055 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
3056
3057 cdclk_state->actual.cdclk = cdclk;
3058 cdclk_state->actual.voltage_level =
3059 vlv_calc_voltage_level(display, cdclk);
3060 } else {
3061 cdclk_state->actual = cdclk_state->logical;
3062 }
3063
3064 return 0;
3065}
3066
3067static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
3068{
3069 struct intel_cdclk_state *cdclk_state =
3070 intel_atomic_get_new_cdclk_state(state);
3071 int min_cdclk, cdclk;
3072
3073 min_cdclk = intel_compute_min_cdclk(state);
3074 if (min_cdclk < 0)
3075 return min_cdclk;
3076
3077 cdclk = bdw_calc_cdclk(min_cdclk);
3078
3079 cdclk_state->logical.cdclk = cdclk;
3080 cdclk_state->logical.voltage_level =
3081 bdw_calc_voltage_level(cdclk);
3082
3083 if (!cdclk_state->active_pipes) {
3084 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
3085
3086 cdclk_state->actual.cdclk = cdclk;
3087 cdclk_state->actual.voltage_level =
3088 bdw_calc_voltage_level(cdclk);
3089 } else {
3090 cdclk_state->actual = cdclk_state->logical;
3091 }
3092
3093 return 0;
3094}
3095
3096static int skl_dpll0_vco(struct intel_atomic_state *state)
3097{
3098 struct intel_display *display = to_intel_display(state);
3099 struct intel_cdclk_state *cdclk_state =
3100 intel_atomic_get_new_cdclk_state(state);
3101 struct intel_crtc *crtc;
3102 struct intel_crtc_state *crtc_state;
3103 int vco, i;
3104
3105 vco = cdclk_state->logical.vco;
3106 if (!vco)
3107 vco = display->cdclk.skl_preferred_vco_freq;
3108
3109 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3110 if (!crtc_state->hw.enable)
3111 continue;
3112
3113 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
3114 continue;
3115
3116 /*
3117 * DPLL0 VCO may need to be adjusted to get the correct
3118 * clock for eDP. This will affect cdclk as well.
3119 */
3120 switch (crtc_state->port_clock / 2) {
3121 case 108000:
3122 case 216000:
3123 vco = 8640000;
3124 break;
3125 default:
3126 vco = 8100000;
3127 break;
3128 }
3129 }
3130
3131 return vco;
3132}
3133
3134static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
3135{
3136 struct intel_cdclk_state *cdclk_state =
3137 intel_atomic_get_new_cdclk_state(state);
3138 int min_cdclk, cdclk, vco;
3139
3140 min_cdclk = intel_compute_min_cdclk(state);
3141 if (min_cdclk < 0)
3142 return min_cdclk;
3143
3144 vco = skl_dpll0_vco(state);
3145
3146 cdclk = skl_calc_cdclk(min_cdclk, vco);
3147
3148 cdclk_state->logical.vco = vco;
3149 cdclk_state->logical.cdclk = cdclk;
3150 cdclk_state->logical.voltage_level =
3151 skl_calc_voltage_level(cdclk);
3152
3153 if (!cdclk_state->active_pipes) {
3154 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3155
3156 cdclk_state->actual.vco = vco;
3157 cdclk_state->actual.cdclk = cdclk;
3158 cdclk_state->actual.voltage_level =
3159 skl_calc_voltage_level(cdclk);
3160 } else {
3161 cdclk_state->actual = cdclk_state->logical;
3162 }
3163
3164 return 0;
3165}
3166
3167static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
3168{
3169 struct intel_display *display = to_intel_display(state);
3170 struct intel_cdclk_state *cdclk_state =
3171 intel_atomic_get_new_cdclk_state(state);
3172 int min_cdclk, min_voltage_level, cdclk, vco;
3173
3174 min_cdclk = intel_compute_min_cdclk(state);
3175 if (min_cdclk < 0)
3176 return min_cdclk;
3177
3178 min_voltage_level = bxt_compute_min_voltage_level(state);
3179 if (min_voltage_level < 0)
3180 return min_voltage_level;
3181
3182 cdclk = bxt_calc_cdclk(display, min_cdclk);
3183 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3184
3185 cdclk_state->logical.vco = vco;
3186 cdclk_state->logical.cdclk = cdclk;
3187 cdclk_state->logical.voltage_level =
3188 max_t(int, min_voltage_level,
3189 intel_cdclk_calc_voltage_level(display, cdclk));
3190
3191 if (!cdclk_state->active_pipes) {
3192 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
3193 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3194
3195 cdclk_state->actual.vco = vco;
3196 cdclk_state->actual.cdclk = cdclk;
3197 cdclk_state->actual.voltage_level =
3198 intel_cdclk_calc_voltage_level(display, cdclk);
3199 } else {
3200 cdclk_state->actual = cdclk_state->logical;
3201 }
3202
3203 return 0;
3204}
3205
3206static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
3207{
3208 int min_cdclk;
3209
3210 /*
3211 * We can't change the cdclk frequency, but we still want to
3212 * check that the required minimum frequency doesn't exceed
3213 * the actual cdclk frequency.
3214 */
3215 min_cdclk = intel_compute_min_cdclk(state);
3216 if (min_cdclk < 0)
3217 return min_cdclk;
3218
3219 return 0;
3220}
3221
3222static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3223{
3224 struct intel_cdclk_state *cdclk_state;
3225
3226 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3227 if (!cdclk_state)
3228 return NULL;
3229
3230 cdclk_state->pipe = INVALID_PIPE;
3231 cdclk_state->disable_pipes = false;
3232
3233 return &cdclk_state->base;
3234}
3235
3236static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3237 struct intel_global_state *state)
3238{
3239 kfree(state);
3240}
3241
3242static const struct intel_global_state_funcs intel_cdclk_funcs = {
3243 .atomic_duplicate_state = intel_cdclk_duplicate_state,
3244 .atomic_destroy_state = intel_cdclk_destroy_state,
3245};
3246
3247struct intel_cdclk_state *
3248intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3249{
3250 struct intel_display *display = to_intel_display(state);
3251 struct intel_global_state *cdclk_state;
3252
3253 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
3254 if (IS_ERR(cdclk_state))
3255 return ERR_CAST(cdclk_state);
3256
3257 return to_intel_cdclk_state(cdclk_state);
3258}
3259
3260int intel_cdclk_atomic_check(struct intel_atomic_state *state,
3261 bool *need_cdclk_calc)
3262{
3263 const struct intel_cdclk_state *old_cdclk_state;
3264 const struct intel_cdclk_state *new_cdclk_state;
3265 struct intel_plane_state __maybe_unused *plane_state;
3266 struct intel_plane *plane;
3267 int ret;
3268 int i;
3269
3270 /*
3271 * active_planes bitmask has been updated, and potentially affected
3272 * planes are part of the state. We can now compute the minimum cdclk
3273 * for each plane.
3274 */
3275 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3276 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
3277 if (ret)
3278 return ret;
3279 }
3280
3281 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
3282 if (ret)
3283 return ret;
3284
3285 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3286 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3287
3288 if (new_cdclk_state &&
3289 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3290 *need_cdclk_calc = true;
3291
3292 return 0;
3293}
3294
3295int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus)
3296{
3297 struct intel_cdclk_state *cdclk_state;
3298
3299 cdclk_state = intel_atomic_get_cdclk_state(state);
3300 if (IS_ERR(cdclk_state))
3301 return PTR_ERR(cdclk_state);
3302
3303 cdclk_state->actual.joined_mbus = joined_mbus;
3304 cdclk_state->logical.joined_mbus = joined_mbus;
3305
3306 return intel_atomic_lock_global_state(&cdclk_state->base);
3307}
3308
3309int intel_cdclk_init(struct intel_display *display)
3310{
3311 struct drm_i915_private *dev_priv = to_i915(display->drm);
3312 struct intel_cdclk_state *cdclk_state;
3313
3314 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3315 if (!cdclk_state)
3316 return -ENOMEM;
3317
3318 intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj,
3319 &cdclk_state->base, &intel_cdclk_funcs);
3320
3321 return 0;
3322}
3323
3324static bool intel_cdclk_need_serialize(struct intel_display *display,
3325 const struct intel_cdclk_state *old_cdclk_state,
3326 const struct intel_cdclk_state *new_cdclk_state)
3327{
3328 struct drm_i915_private *i915 = to_i915(display->drm);
3329 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3330 hweight8(new_cdclk_state->active_pipes);
3331 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3332 &new_cdclk_state->actual);
3333 /*
3334 * We need to poke hw for gen >= 12, because we notify PCode if
3335 * pipe power well count changes.
3336 */
3337 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed);
3338}
3339
3340int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3341{
3342 struct intel_display *display = to_intel_display(state);
3343 const struct intel_cdclk_state *old_cdclk_state;
3344 struct intel_cdclk_state *new_cdclk_state;
3345 enum pipe pipe = INVALID_PIPE;
3346 int ret;
3347
3348 new_cdclk_state = intel_atomic_get_cdclk_state(state);
3349 if (IS_ERR(new_cdclk_state))
3350 return PTR_ERR(new_cdclk_state);
3351
3352 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3353
3354 new_cdclk_state->active_pipes =
3355 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3356
3357 ret = intel_cdclk_modeset_calc_cdclk(state);
3358 if (ret)
3359 return ret;
3360
3361 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
3362 /*
3363 * Also serialize commits across all crtcs
3364 * if the actual hw needs to be poked.
3365 */
3366 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3367 if (ret)
3368 return ret;
3369 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3370 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3371 intel_cdclk_changed(&old_cdclk_state->logical,
3372 &new_cdclk_state->logical)) {
3373 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3374 if (ret)
3375 return ret;
3376 } else {
3377 return 0;
3378 }
3379
3380 if (is_power_of_2(new_cdclk_state->active_pipes) &&
3381 intel_cdclk_can_cd2x_update(display,
3382 &old_cdclk_state->actual,
3383 &new_cdclk_state->actual)) {
3384 struct intel_crtc *crtc;
3385 struct intel_crtc_state *crtc_state;
3386
3387 pipe = ilog2(new_cdclk_state->active_pipes);
3388 crtc = intel_crtc_for_pipe(display, pipe);
3389
3390 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3391 if (IS_ERR(crtc_state))
3392 return PTR_ERR(crtc_state);
3393
3394 if (intel_crtc_needs_modeset(crtc_state))
3395 pipe = INVALID_PIPE;
3396 }
3397
3398 if (intel_cdclk_can_crawl_and_squash(display,
3399 &old_cdclk_state->actual,
3400 &new_cdclk_state->actual)) {
3401 drm_dbg_kms(display->drm,
3402 "Can change cdclk via crawling and squashing\n");
3403 } else if (intel_cdclk_can_squash(display,
3404 &old_cdclk_state->actual,
3405 &new_cdclk_state->actual)) {
3406 drm_dbg_kms(display->drm,
3407 "Can change cdclk via squashing\n");
3408 } else if (intel_cdclk_can_crawl(display,
3409 &old_cdclk_state->actual,
3410 &new_cdclk_state->actual)) {
3411 drm_dbg_kms(display->drm,
3412 "Can change cdclk via crawling\n");
3413 } else if (pipe != INVALID_PIPE) {
3414 new_cdclk_state->pipe = pipe;
3415
3416 drm_dbg_kms(display->drm,
3417 "Can change cdclk cd2x divider with pipe %c active\n",
3418 pipe_name(pipe));
3419 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
3420 &new_cdclk_state->actual)) {
3421 /* All pipes must be switched off while we change the cdclk. */
3422 ret = intel_modeset_all_pipes_late(state, "CDCLK change");
3423 if (ret)
3424 return ret;
3425
3426 new_cdclk_state->disable_pipes = true;
3427
3428 drm_dbg_kms(display->drm,
3429 "Modeset required for cdclk change\n");
3430 }
3431
3432 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
3433 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
3434 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
3435
3436 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
3437 if (ret)
3438 return ret;
3439 }
3440
3441 drm_dbg_kms(display->drm,
3442 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3443 new_cdclk_state->logical.cdclk,
3444 new_cdclk_state->actual.cdclk);
3445 drm_dbg_kms(display->drm,
3446 "New voltage level calculated to be logical %u, actual %u\n",
3447 new_cdclk_state->logical.voltage_level,
3448 new_cdclk_state->actual.voltage_level);
3449
3450 return 0;
3451}
3452
3453static int intel_compute_max_dotclk(struct intel_display *display)
3454{
3455 struct drm_i915_private *dev_priv = to_i915(display->drm);
3456 int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3457
3458 if (DISPLAY_VER(display) >= 10)
3459 return 2 * max_cdclk_freq;
3460 else if (DISPLAY_VER(display) == 9 ||
3461 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3462 return max_cdclk_freq;
3463 else if (IS_CHERRYVIEW(dev_priv))
3464 return max_cdclk_freq*95/100;
3465 else if (DISPLAY_VER(display) < 4)
3466 return 2*max_cdclk_freq*90/100;
3467 else
3468 return max_cdclk_freq*90/100;
3469}
3470
3471/**
3472 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3473 * @display: display instance
3474 *
3475 * Determine the maximum CDCLK frequency the platform supports, and also
3476 * derive the maximum dot clock frequency the maximum CDCLK frequency
3477 * allows.
3478 */
3479void intel_update_max_cdclk(struct intel_display *display)
3480{
3481 struct drm_i915_private *dev_priv = to_i915(display->drm);
3482
3483 if (DISPLAY_VER(display) >= 30) {
3484 display->cdclk.max_cdclk_freq = 691200;
3485 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3486 if (display->cdclk.hw.ref == 24000)
3487 display->cdclk.max_cdclk_freq = 552000;
3488 else
3489 display->cdclk.max_cdclk_freq = 556800;
3490 } else if (DISPLAY_VER(display) >= 11) {
3491 if (display->cdclk.hw.ref == 24000)
3492 display->cdclk.max_cdclk_freq = 648000;
3493 else
3494 display->cdclk.max_cdclk_freq = 652800;
3495 } else if (IS_GEMINILAKE(dev_priv)) {
3496 display->cdclk.max_cdclk_freq = 316800;
3497 } else if (IS_BROXTON(dev_priv)) {
3498 display->cdclk.max_cdclk_freq = 624000;
3499 } else if (DISPLAY_VER(display) == 9) {
3500 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3501 int max_cdclk, vco;
3502
3503 vco = display->cdclk.skl_preferred_vco_freq;
3504 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3505
3506 /*
3507 * Use the lower (vco 8640) cdclk values as a
3508 * first guess. skl_calc_cdclk() will correct it
3509 * if the preferred vco is 8100 instead.
3510 */
3511 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3512 max_cdclk = 617143;
3513 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3514 max_cdclk = 540000;
3515 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3516 max_cdclk = 432000;
3517 else
3518 max_cdclk = 308571;
3519
3520 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3521 } else if (IS_BROADWELL(dev_priv)) {
3522 /*
3523 * FIXME with extra cooling we can allow
3524 * 540 MHz for ULX and 675 Mhz for ULT.
3525 * How can we know if extra cooling is
3526 * available? PCI ID, VTB, something else?
3527 */
3528 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3529 display->cdclk.max_cdclk_freq = 450000;
3530 else if (IS_BROADWELL_ULX(dev_priv))
3531 display->cdclk.max_cdclk_freq = 450000;
3532 else if (IS_BROADWELL_ULT(dev_priv))
3533 display->cdclk.max_cdclk_freq = 540000;
3534 else
3535 display->cdclk.max_cdclk_freq = 675000;
3536 } else if (IS_CHERRYVIEW(dev_priv)) {
3537 display->cdclk.max_cdclk_freq = 320000;
3538 } else if (IS_VALLEYVIEW(dev_priv)) {
3539 display->cdclk.max_cdclk_freq = 400000;
3540 } else {
3541 /* otherwise assume cdclk is fixed */
3542 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3543 }
3544
3545 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3546
3547 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3548 display->cdclk.max_cdclk_freq);
3549
3550 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3551 display->cdclk.max_dotclk_freq);
3552}
3553
3554/**
3555 * intel_update_cdclk - Determine the current CDCLK frequency
3556 * @display: display instance
3557 *
3558 * Determine the current CDCLK frequency.
3559 */
3560void intel_update_cdclk(struct intel_display *display)
3561{
3562 struct drm_i915_private *dev_priv = to_i915(display->drm);
3563
3564 intel_cdclk_get_cdclk(display, &display->cdclk.hw);
3565
3566 /*
3567 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3568 * Programmng [sic] note: bit[9:2] should be programmed to the number
3569 * of cdclk that generates 4MHz reference clock freq which is used to
3570 * generate GMBus clock. This will vary with the cdclk freq.
3571 */
3572 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3573 intel_de_write(display, GMBUSFREQ_VLV,
3574 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3575}
3576
3577static int dg1_rawclk(struct intel_display *display)
3578{
3579 /*
3580 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
3581 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3582 */
3583 intel_de_write(display, PCH_RAWCLK_FREQ,
3584 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3585
3586 return 38400;
3587}
3588
3589static int cnp_rawclk(struct intel_display *display)
3590{
3591 struct drm_i915_private *dev_priv = to_i915(display->drm);
3592 int divider, fraction;
3593 u32 rawclk;
3594
3595 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3596 /* 24 MHz */
3597 divider = 24000;
3598 fraction = 0;
3599 } else {
3600 /* 19.2 MHz */
3601 divider = 19000;
3602 fraction = 200;
3603 }
3604
3605 rawclk = CNP_RAWCLK_DIV(divider / 1000);
3606 if (fraction) {
3607 int numerator = 1;
3608
3609 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3610 fraction) - 1);
3611 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3612 rawclk |= ICP_RAWCLK_NUM(numerator);
3613 }
3614
3615 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
3616 return divider + fraction;
3617}
3618
3619static int pch_rawclk(struct intel_display *display)
3620{
3621 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3622}
3623
3624static int vlv_hrawclk(struct intel_display *display)
3625{
3626 struct drm_i915_private *dev_priv = to_i915(display->drm);
3627
3628 /* RAWCLK_FREQ_VLV register updated from power well code */
3629 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
3630 CCK_DISPLAY_REF_CLOCK_CONTROL);
3631}
3632
3633static int i9xx_hrawclk(struct intel_display *display)
3634{
3635 struct drm_i915_private *i915 = to_i915(display->drm);
3636
3637 /* hrawclock is 1/4 the FSB frequency */
3638 return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
3639}
3640
3641/**
3642 * intel_read_rawclk - Determine the current RAWCLK frequency
3643 * @display: display instance
3644 *
3645 * Determine the current RAWCLK frequency. RAWCLK is a fixed
3646 * frequency clock so this needs to done only once.
3647 */
3648u32 intel_read_rawclk(struct intel_display *display)
3649{
3650 struct drm_i915_private *dev_priv = to_i915(display->drm);
3651 u32 freq;
3652
3653 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
3654 /*
3655 * MTL always uses a 38.4 MHz rawclk. The bspec tells us
3656 * "RAWCLK_FREQ defaults to the values for 38.4 and does
3657 * not need to be programmed."
3658 */
3659 freq = 38400;
3660 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3661 freq = dg1_rawclk(display);
3662 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3663 freq = cnp_rawclk(display);
3664 else if (HAS_PCH_SPLIT(dev_priv))
3665 freq = pch_rawclk(display);
3666 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3667 freq = vlv_hrawclk(display);
3668 else if (DISPLAY_VER(display) >= 3)
3669 freq = i9xx_hrawclk(display);
3670 else
3671 /* no rawclk on other platforms, or no need to know it */
3672 return 0;
3673
3674 return freq;
3675}
3676
3677static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3678{
3679 struct intel_display *display = m->private;
3680
3681 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3682 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3683 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3684
3685 return 0;
3686}
3687
3688DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3689
3690void intel_cdclk_debugfs_register(struct intel_display *display)
3691{
3692 struct drm_minor *minor = display->drm->primary;
3693
3694 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3695 display, &i915_cdclk_info_fops);
3696}
3697
3698static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
3699 .get_cdclk = bxt_get_cdclk,
3700 .set_cdclk = bxt_set_cdclk,
3701 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3702 .calc_voltage_level = xe3lpd_calc_voltage_level,
3703};
3704
3705static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3706 .get_cdclk = bxt_get_cdclk,
3707 .set_cdclk = bxt_set_cdclk,
3708 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3709 .calc_voltage_level = rplu_calc_voltage_level,
3710};
3711
3712static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3713 .get_cdclk = bxt_get_cdclk,
3714 .set_cdclk = bxt_set_cdclk,
3715 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3716 .calc_voltage_level = tgl_calc_voltage_level,
3717};
3718
3719static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3720 .get_cdclk = bxt_get_cdclk,
3721 .set_cdclk = bxt_set_cdclk,
3722 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3723 .calc_voltage_level = ehl_calc_voltage_level,
3724};
3725
3726static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3727 .get_cdclk = bxt_get_cdclk,
3728 .set_cdclk = bxt_set_cdclk,
3729 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3730 .calc_voltage_level = icl_calc_voltage_level,
3731};
3732
3733static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3734 .get_cdclk = bxt_get_cdclk,
3735 .set_cdclk = bxt_set_cdclk,
3736 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3737 .calc_voltage_level = bxt_calc_voltage_level,
3738};
3739
3740static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3741 .get_cdclk = skl_get_cdclk,
3742 .set_cdclk = skl_set_cdclk,
3743 .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3744};
3745
3746static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3747 .get_cdclk = bdw_get_cdclk,
3748 .set_cdclk = bdw_set_cdclk,
3749 .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3750};
3751
3752static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3753 .get_cdclk = vlv_get_cdclk,
3754 .set_cdclk = chv_set_cdclk,
3755 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3756};
3757
3758static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3759 .get_cdclk = vlv_get_cdclk,
3760 .set_cdclk = vlv_set_cdclk,
3761 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3762};
3763
3764static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3765 .get_cdclk = hsw_get_cdclk,
3766 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3767};
3768
3769/* SNB, IVB, 965G, 945G */
3770static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3771 .get_cdclk = fixed_400mhz_get_cdclk,
3772 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3773};
3774
3775static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3776 .get_cdclk = fixed_450mhz_get_cdclk,
3777 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3778};
3779
3780static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3781 .get_cdclk = gm45_get_cdclk,
3782 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3783};
3784
3785/* G45 uses G33 */
3786
3787static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3788 .get_cdclk = i965gm_get_cdclk,
3789 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3790};
3791
3792/* i965G uses fixed 400 */
3793
3794static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3795 .get_cdclk = pnv_get_cdclk,
3796 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3797};
3798
3799static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3800 .get_cdclk = g33_get_cdclk,
3801 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3802};
3803
3804static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3805 .get_cdclk = i945gm_get_cdclk,
3806 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3807};
3808
3809/* i945G uses fixed 400 */
3810
3811static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3812 .get_cdclk = i915gm_get_cdclk,
3813 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3814};
3815
3816static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3817 .get_cdclk = fixed_333mhz_get_cdclk,
3818 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3819};
3820
3821static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3822 .get_cdclk = fixed_266mhz_get_cdclk,
3823 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3824};
3825
3826static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3827 .get_cdclk = i85x_get_cdclk,
3828 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3829};
3830
3831static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3832 .get_cdclk = fixed_200mhz_get_cdclk,
3833 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3834};
3835
3836static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3837 .get_cdclk = fixed_133mhz_get_cdclk,
3838 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3839};
3840
3841/**
3842 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3843 * @display: display instance
3844 */
3845void intel_init_cdclk_hooks(struct intel_display *display)
3846{
3847 struct drm_i915_private *dev_priv = to_i915(display->drm);
3848
3849 if (DISPLAY_VER(display) >= 30) {
3850 display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3851 display->cdclk.table = xe3lpd_cdclk_table;
3852 } else if (DISPLAY_VER(display) >= 20) {
3853 display->funcs.cdclk = &rplu_cdclk_funcs;
3854 display->cdclk.table = xe2lpd_cdclk_table;
3855 } else if (DISPLAY_VERx100(display) >= 1401) {
3856 display->funcs.cdclk = &rplu_cdclk_funcs;
3857 display->cdclk.table = xe2hpd_cdclk_table;
3858 } else if (DISPLAY_VER(display) >= 14) {
3859 display->funcs.cdclk = &rplu_cdclk_funcs;
3860 display->cdclk.table = mtl_cdclk_table;
3861 } else if (IS_DG2(dev_priv)) {
3862 display->funcs.cdclk = &tgl_cdclk_funcs;
3863 display->cdclk.table = dg2_cdclk_table;
3864 } else if (IS_ALDERLAKE_P(dev_priv)) {
3865 /* Wa_22011320316:adl-p[a0] */
3866 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
3867 display->cdclk.table = adlp_a_step_cdclk_table;
3868 display->funcs.cdclk = &tgl_cdclk_funcs;
3869 } else if (IS_RAPTORLAKE_U(dev_priv)) {
3870 display->cdclk.table = rplu_cdclk_table;
3871 display->funcs.cdclk = &rplu_cdclk_funcs;
3872 } else {
3873 display->cdclk.table = adlp_cdclk_table;
3874 display->funcs.cdclk = &tgl_cdclk_funcs;
3875 }
3876 } else if (IS_ROCKETLAKE(dev_priv)) {
3877 display->funcs.cdclk = &tgl_cdclk_funcs;
3878 display->cdclk.table = rkl_cdclk_table;
3879 } else if (DISPLAY_VER(display) >= 12) {
3880 display->funcs.cdclk = &tgl_cdclk_funcs;
3881 display->cdclk.table = icl_cdclk_table;
3882 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3883 display->funcs.cdclk = &ehl_cdclk_funcs;
3884 display->cdclk.table = icl_cdclk_table;
3885 } else if (DISPLAY_VER(display) >= 11) {
3886 display->funcs.cdclk = &icl_cdclk_funcs;
3887 display->cdclk.table = icl_cdclk_table;
3888 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
3889 display->funcs.cdclk = &bxt_cdclk_funcs;
3890 if (IS_GEMINILAKE(dev_priv))
3891 display->cdclk.table = glk_cdclk_table;
3892 else
3893 display->cdclk.table = bxt_cdclk_table;
3894 } else if (DISPLAY_VER(display) == 9) {
3895 display->funcs.cdclk = &skl_cdclk_funcs;
3896 } else if (IS_BROADWELL(dev_priv)) {
3897 display->funcs.cdclk = &bdw_cdclk_funcs;
3898 } else if (IS_HASWELL(dev_priv)) {
3899 display->funcs.cdclk = &hsw_cdclk_funcs;
3900 } else if (IS_CHERRYVIEW(dev_priv)) {
3901 display->funcs.cdclk = &chv_cdclk_funcs;
3902 } else if (IS_VALLEYVIEW(dev_priv)) {
3903 display->funcs.cdclk = &vlv_cdclk_funcs;
3904 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
3905 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3906 } else if (IS_IRONLAKE(dev_priv)) {
3907 display->funcs.cdclk = &ilk_cdclk_funcs;
3908 } else if (IS_GM45(dev_priv)) {
3909 display->funcs.cdclk = &gm45_cdclk_funcs;
3910 } else if (IS_G45(dev_priv)) {
3911 display->funcs.cdclk = &g33_cdclk_funcs;
3912 } else if (IS_I965GM(dev_priv)) {
3913 display->funcs.cdclk = &i965gm_cdclk_funcs;
3914 } else if (IS_I965G(dev_priv)) {
3915 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3916 } else if (IS_PINEVIEW(dev_priv)) {
3917 display->funcs.cdclk = &pnv_cdclk_funcs;
3918 } else if (IS_G33(dev_priv)) {
3919 display->funcs.cdclk = &g33_cdclk_funcs;
3920 } else if (IS_I945GM(dev_priv)) {
3921 display->funcs.cdclk = &i945gm_cdclk_funcs;
3922 } else if (IS_I945G(dev_priv)) {
3923 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3924 } else if (IS_I915GM(dev_priv)) {
3925 display->funcs.cdclk = &i915gm_cdclk_funcs;
3926 } else if (IS_I915G(dev_priv)) {
3927 display->funcs.cdclk = &i915g_cdclk_funcs;
3928 } else if (IS_I865G(dev_priv)) {
3929 display->funcs.cdclk = &i865g_cdclk_funcs;
3930 } else if (IS_I85X(dev_priv)) {
3931 display->funcs.cdclk = &i85x_cdclk_funcs;
3932 } else if (IS_I845G(dev_priv)) {
3933 display->funcs.cdclk = &i845g_cdclk_funcs;
3934 } else if (IS_I830(dev_priv)) {
3935 display->funcs.cdclk = &i830_cdclk_funcs;
3936 }
3937
3938 if (drm_WARN(display->drm, !display->funcs.cdclk,
3939 "Unknown platform. Assuming i830\n"))
3940 display->funcs.cdclk = &i830_cdclk_funcs;
3941}