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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "uvd/uvd_7_0_offset.h"
41#include "gc/gc_9_0_offset.h"
42#include "gc/gc_9_0_sh_mask.h"
43#include "sdma0/sdma0_4_0_offset.h"
44#include "sdma1/sdma1_4_0_offset.h"
45#include "nbio/nbio_7_0_default.h"
46#include "nbio/nbio_7_0_offset.h"
47#include "nbio/nbio_7_0_sh_mask.h"
48#include "nbio/nbio_7_0_smn.h"
49#include "mp/mp_9_0_offset.h"
50
51#include "soc15.h"
52#include "soc15_common.h"
53#include "gfx_v9_0.h"
54#include "gmc_v9_0.h"
55#include "gfxhub_v1_0.h"
56#include "mmhub_v1_0.h"
57#include "df_v1_7.h"
58#include "df_v3_6.h"
59#include "nbio_v6_1.h"
60#include "nbio_v7_0.h"
61#include "nbio_v7_4.h"
62#include "hdp_v4_0.h"
63#include "vega10_ih.h"
64#include "vega20_ih.h"
65#include "navi10_ih.h"
66#include "sdma_v4_0.h"
67#include "uvd_v7_0.h"
68#include "vce_v4_0.h"
69#include "vcn_v1_0.h"
70#include "vcn_v2_0.h"
71#include "jpeg_v2_0.h"
72#include "vcn_v2_5.h"
73#include "jpeg_v2_5.h"
74#include "smuio_v9_0.h"
75#include "smuio_v11_0.h"
76#include "smuio_v13_0.h"
77#include "amdgpu_vkms.h"
78#include "mxgpu_ai.h"
79#include "amdgpu_ras.h"
80#include "amdgpu_xgmi.h"
81#include <uapi/linux/kfd_ioctl.h>
82
83#define mmMP0_MISC_CGTT_CTRL0 0x01b9
84#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88static const struct amd_ip_funcs soc15_common_ip_funcs;
89
90/* Vega, Raven, Arcturus */
91static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92{
93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
95};
96
97static const struct amdgpu_video_codecs vega_video_codecs_encode =
98{
99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
100 .codec_array = vega_video_codecs_encode_array,
101};
102
103/* Vega */
104static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
105{
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
112};
113
114static const struct amdgpu_video_codecs vega_video_codecs_decode =
115{
116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
117 .codec_array = vega_video_codecs_decode_array,
118};
119
120/* Raven */
121static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
122{
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
130};
131
132static const struct amdgpu_video_codecs rv_video_codecs_decode =
133{
134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
135 .codec_array = rv_video_codecs_decode_array,
136};
137
138/* Renoir, Arcturus */
139static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
140{
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
148};
149
150static const struct amdgpu_video_codecs rn_video_codecs_decode =
151{
152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 .codec_array = rn_video_codecs_decode_array,
154};
155
156static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
162};
163
164static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = {
165 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),
166 .codec_array = vcn_4_0_3_video_codecs_decode_array,
167};
168
169static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {
170 .codec_count = 0,
171 .codec_array = NULL,
172};
173
174static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
175 const struct amdgpu_video_codecs **codecs)
176{
177 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
178 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
179 case IP_VERSION(4, 0, 0):
180 case IP_VERSION(4, 1, 0):
181 if (encode)
182 *codecs = &vega_video_codecs_encode;
183 else
184 *codecs = &vega_video_codecs_decode;
185 return 0;
186 default:
187 return -EINVAL;
188 }
189 } else {
190 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
191 case IP_VERSION(1, 0, 0):
192 case IP_VERSION(1, 0, 1):
193 if (encode)
194 *codecs = &vega_video_codecs_encode;
195 else
196 *codecs = &rv_video_codecs_decode;
197 return 0;
198 case IP_VERSION(2, 5, 0):
199 case IP_VERSION(2, 6, 0):
200 case IP_VERSION(2, 2, 0):
201 if (encode)
202 *codecs = &vega_video_codecs_encode;
203 else
204 *codecs = &rn_video_codecs_decode;
205 return 0;
206 case IP_VERSION(4, 0, 3):
207 if (encode)
208 *codecs = &vcn_4_0_3_video_codecs_encode;
209 else
210 *codecs = &vcn_4_0_3_video_codecs_decode;
211 return 0;
212 default:
213 return -EINVAL;
214 }
215 }
216}
217
218static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
219{
220 unsigned long flags, address, data;
221 u32 r;
222
223 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
224 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
225
226 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
227 WREG32(address, ((reg) & 0x1ff));
228 r = RREG32(data);
229 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
230 return r;
231}
232
233static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
234{
235 unsigned long flags, address, data;
236
237 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
238 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
239
240 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
241 WREG32(address, ((reg) & 0x1ff));
242 WREG32(data, (v));
243 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
244}
245
246static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
247{
248 unsigned long flags, address, data;
249 u32 r;
250
251 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
252 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
253
254 spin_lock_irqsave(&adev->didt_idx_lock, flags);
255 WREG32(address, (reg));
256 r = RREG32(data);
257 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
258 return r;
259}
260
261static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
262{
263 unsigned long flags, address, data;
264
265 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
266 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
267
268 spin_lock_irqsave(&adev->didt_idx_lock, flags);
269 WREG32(address, (reg));
270 WREG32(data, (v));
271 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
272}
273
274static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
275{
276 unsigned long flags;
277 u32 r;
278
279 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
280 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
281 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
282 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
283 return r;
284}
285
286static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
287{
288 unsigned long flags;
289
290 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
291 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
292 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
293 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
294}
295
296static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
297{
298 unsigned long flags;
299 u32 r;
300
301 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
302 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
303 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
304 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
305 return r;
306}
307
308static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
309{
310 unsigned long flags;
311
312 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
313 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
314 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
315 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
316}
317
318static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
319{
320 return adev->nbio.funcs->get_memsize(adev);
321}
322
323static u32 soc15_get_xclk(struct amdgpu_device *adev)
324{
325 u32 reference_clock = adev->clock.spll.reference_freq;
326
327 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) ||
328 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) ||
329 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||
330 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
331 return 10000;
332 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) ||
333 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1))
334 return reference_clock / 4;
335
336 return reference_clock;
337}
338
339
340void soc15_grbm_select(struct amdgpu_device *adev,
341 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
342{
343 u32 grbm_gfx_cntl = 0;
344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
346 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
347 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
348
349 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
350}
351
352static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
353{
354 /* todo */
355 return false;
356}
357
358static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
362 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
363 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
364 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
365 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
366 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
373 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
374 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
375 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
376 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
377 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
378 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
379};
380
381static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
382 u32 sh_num, u32 reg_offset)
383{
384 uint32_t val;
385
386 mutex_lock(&adev->grbm_idx_mutex);
387 if (se_num != 0xffffffff || sh_num != 0xffffffff)
388 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
389
390 val = RREG32(reg_offset);
391
392 if (se_num != 0xffffffff || sh_num != 0xffffffff)
393 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
394 mutex_unlock(&adev->grbm_idx_mutex);
395 return val;
396}
397
398static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
399 bool indexed, u32 se_num,
400 u32 sh_num, u32 reg_offset)
401{
402 if (indexed) {
403 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
404 } else {
405 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
406 return adev->gfx.config.gb_addr_config;
407 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
408 return adev->gfx.config.db_debug2;
409 return RREG32(reg_offset);
410 }
411}
412
413static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
414 u32 sh_num, u32 reg_offset, u32 *value)
415{
416 uint32_t i;
417 struct soc15_allowed_register_entry *en;
418
419 *value = 0;
420 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
421 en = &soc15_allowed_read_registers[i];
422 if (!adev->reg_offset[en->hwip][en->inst])
423 continue;
424 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
425 + en->reg_offset))
426 continue;
427
428 *value = soc15_get_register_value(adev,
429 soc15_allowed_read_registers[i].grbm_indexed,
430 se_num, sh_num, reg_offset);
431 return 0;
432 }
433 return -EINVAL;
434}
435
436
437/**
438 * soc15_program_register_sequence - program an array of registers.
439 *
440 * @adev: amdgpu_device pointer
441 * @regs: pointer to the register array
442 * @array_size: size of the register array
443 *
444 * Programs an array or registers with and and or masks.
445 * This is a helper for setting golden registers.
446 */
447
448void soc15_program_register_sequence(struct amdgpu_device *adev,
449 const struct soc15_reg_golden *regs,
450 const u32 array_size)
451{
452 const struct soc15_reg_golden *entry;
453 u32 tmp, reg;
454 int i;
455
456 for (i = 0; i < array_size; ++i) {
457 entry = ®s[i];
458 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
459
460 if (entry->and_mask == 0xffffffff) {
461 tmp = entry->or_mask;
462 } else {
463 tmp = (entry->hwip == GC_HWIP) ?
464 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
465
466 tmp &= ~(entry->and_mask);
467 tmp |= (entry->or_mask & entry->and_mask);
468 }
469
470 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
471 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
472 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
473 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
474 WREG32_RLC(reg, tmp);
475 else
476 (entry->hwip == GC_HWIP) ?
477 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
478
479 }
480
481}
482
483static int soc15_asic_baco_reset(struct amdgpu_device *adev)
484{
485 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
486 int ret = 0;
487
488 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
489 if (ras && adev->ras_enabled)
490 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
491
492 ret = amdgpu_dpm_baco_reset(adev);
493 if (ret)
494 return ret;
495
496 /* re-enable doorbell interrupt after BACO exit */
497 if (ras && adev->ras_enabled)
498 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
499
500 return 0;
501}
502
503static enum amd_reset_method
504soc15_asic_reset_method(struct amdgpu_device *adev)
505{
506 int baco_reset = 0;
507 bool connected_to_cpu = false;
508 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
509
510 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
511 connected_to_cpu = true;
512
513 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
514 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
515 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
516 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
517 /* If connected to cpu, driver only support mode2 */
518 if (connected_to_cpu)
519 return AMD_RESET_METHOD_MODE2;
520 return amdgpu_reset_method;
521 }
522
523 if (amdgpu_reset_method != -1)
524 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
525 amdgpu_reset_method);
526
527 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
528 case IP_VERSION(10, 0, 0):
529 case IP_VERSION(10, 0, 1):
530 case IP_VERSION(12, 0, 0):
531 case IP_VERSION(12, 0, 1):
532 return AMD_RESET_METHOD_MODE2;
533 case IP_VERSION(9, 0, 0):
534 case IP_VERSION(11, 0, 2):
535 if (adev->asic_type == CHIP_VEGA20) {
536 if (adev->psp.sos.fw_version >= 0x80067)
537 baco_reset = amdgpu_dpm_is_baco_supported(adev);
538 /*
539 * 1. PMFW version > 0x284300: all cases use baco
540 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
541 */
542 if (ras && adev->ras_enabled &&
543 adev->pm.fw_version <= 0x283400)
544 baco_reset = 0;
545 } else {
546 baco_reset = amdgpu_dpm_is_baco_supported(adev);
547 }
548 break;
549 case IP_VERSION(13, 0, 2):
550 /*
551 * 1.connected to cpu: driver issue mode2 reset
552 * 2.discret gpu: driver issue mode1 reset
553 */
554 if (connected_to_cpu)
555 return AMD_RESET_METHOD_MODE2;
556 break;
557 case IP_VERSION(13, 0, 6):
558 case IP_VERSION(13, 0, 14):
559 /* Use gpu_recovery param to target a reset method.
560 * Enable triggering of GPU reset only if specified
561 * by module parameter.
562 */
563 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)
564 return AMD_RESET_METHOD_MODE2;
565 else if (!(adev->flags & AMD_IS_APU))
566 return AMD_RESET_METHOD_MODE1;
567 else
568 return AMD_RESET_METHOD_MODE2;
569 default:
570 break;
571 }
572
573 if (baco_reset)
574 return AMD_RESET_METHOD_BACO;
575 else
576 return AMD_RESET_METHOD_MODE1;
577}
578
579static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
580{
581 /* Will reset for the following suspend abort cases.
582 * 1) Only reset on APU side, dGPU hasn't checked yet.
583 * 2) S3 suspend aborted in the normal S3 suspend or
584 * performing pm core test.
585 */
586 if (adev->flags & AMD_IS_APU && adev->in_s3 &&
587 !pm_resume_via_firmware())
588 return true;
589 else
590 return false;
591}
592
593static int soc15_asic_reset(struct amdgpu_device *adev)
594{
595 /* original raven doesn't have full asic reset */
596 /* On the latest Raven, the GPU reset can be performed
597 * successfully. So now, temporarily enable it for the
598 * S3 suspend abort case.
599 */
600
601 if ((adev->apu_flags & AMD_APU_IS_PICASSO ||
602 !(adev->apu_flags & AMD_APU_IS_RAVEN)) &&
603 soc15_need_reset_on_resume(adev))
604 goto asic_reset;
605
606 if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
607 (adev->apu_flags & AMD_APU_IS_RAVEN2))
608 return 0;
609
610asic_reset:
611 switch (soc15_asic_reset_method(adev)) {
612 case AMD_RESET_METHOD_PCI:
613 dev_info(adev->dev, "PCI reset\n");
614 return amdgpu_device_pci_reset(adev);
615 case AMD_RESET_METHOD_BACO:
616 dev_info(adev->dev, "BACO reset\n");
617 return soc15_asic_baco_reset(adev);
618 case AMD_RESET_METHOD_MODE2:
619 dev_info(adev->dev, "MODE2 reset\n");
620 return amdgpu_dpm_mode2_reset(adev);
621 default:
622 dev_info(adev->dev, "MODE1 reset\n");
623 return amdgpu_device_mode1_reset(adev);
624 }
625}
626
627static int soc15_supports_baco(struct amdgpu_device *adev)
628{
629 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
630 case IP_VERSION(9, 0, 0):
631 case IP_VERSION(11, 0, 2):
632 if (adev->asic_type == CHIP_VEGA20) {
633 if (adev->psp.sos.fw_version >= 0x80067)
634 return amdgpu_dpm_is_baco_supported(adev);
635 return 0;
636 } else {
637 return amdgpu_dpm_is_baco_supported(adev);
638 }
639 break;
640 default:
641 return 0;
642 }
643}
644
645/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
646 u32 cntl_reg, u32 status_reg)
647{
648 return 0;
649}*/
650
651static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
652{
653 /*int r;
654
655 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
656 if (r)
657 return r;
658
659 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
660 */
661 return 0;
662}
663
664static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
665{
666 /* todo */
667
668 return 0;
669}
670
671static void soc15_program_aspm(struct amdgpu_device *adev)
672{
673 if (!amdgpu_device_should_use_aspm(adev))
674 return;
675
676 if (adev->nbio.funcs->program_aspm)
677 adev->nbio.funcs->program_aspm(adev);
678}
679
680const struct amdgpu_ip_block_version vega10_common_ip_block =
681{
682 .type = AMD_IP_BLOCK_TYPE_COMMON,
683 .major = 2,
684 .minor = 0,
685 .rev = 0,
686 .funcs = &soc15_common_ip_funcs,
687};
688
689static void soc15_reg_base_init(struct amdgpu_device *adev)
690{
691 /* Set IP register base before any HW register access */
692 switch (adev->asic_type) {
693 case CHIP_VEGA10:
694 case CHIP_VEGA12:
695 case CHIP_RAVEN:
696 case CHIP_RENOIR:
697 vega10_reg_base_init(adev);
698 break;
699 case CHIP_VEGA20:
700 vega20_reg_base_init(adev);
701 break;
702 case CHIP_ARCTURUS:
703 arct_reg_base_init(adev);
704 break;
705 case CHIP_ALDEBARAN:
706 aldebaran_reg_base_init(adev);
707 break;
708 default:
709 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
710 break;
711 }
712}
713
714void soc15_set_virt_ops(struct amdgpu_device *adev)
715{
716 adev->virt.ops = &xgpu_ai_virt_ops;
717
718 /* init soc15 reg base early enough so we can
719 * request request full access for sriov before
720 * set_ip_blocks. */
721 soc15_reg_base_init(adev);
722}
723
724static bool soc15_need_full_reset(struct amdgpu_device *adev)
725{
726 /* change this when we implement soft reset */
727 return true;
728}
729
730static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
731 uint64_t *count1)
732{
733 uint32_t perfctr = 0;
734 uint64_t cnt0_of, cnt1_of;
735 int tmp;
736
737 /* This reports 0 on APUs, so return to avoid writing/reading registers
738 * that may or may not be different from their GPU counterparts
739 */
740 if (adev->flags & AMD_IS_APU)
741 return;
742
743 /* Set the 2 events that we wish to watch, defined above */
744 /* Reg 40 is # received msgs */
745 /* Reg 104 is # of posted requests sent */
746 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
747 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
748
749 /* Write to enable desired perf counters */
750 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
751 /* Zero out and enable the perf counters
752 * Write 0x5:
753 * Bit 0 = Start all counters(1)
754 * Bit 2 = Global counter reset enable(1)
755 */
756 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
757
758 msleep(1000);
759
760 /* Load the shadow and disable the perf counters
761 * Write 0x2:
762 * Bit 0 = Stop counters(0)
763 * Bit 1 = Load the shadow counters(1)
764 */
765 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
766
767 /* Read register values to get any >32bit overflow */
768 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
769 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
770 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
771
772 /* Get the values and add the overflow */
773 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
774 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
775}
776
777static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
778 uint64_t *count1)
779{
780 uint32_t perfctr = 0;
781 uint64_t cnt0_of, cnt1_of;
782 int tmp;
783
784 /* This reports 0 on APUs, so return to avoid writing/reading registers
785 * that may or may not be different from their GPU counterparts
786 */
787 if (adev->flags & AMD_IS_APU)
788 return;
789
790 /* Set the 2 events that we wish to watch, defined above */
791 /* Reg 40 is # received msgs */
792 /* Reg 108 is # of posted requests sent on VG20 */
793 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
794 EVENT0_SEL, 40);
795 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
796 EVENT1_SEL, 108);
797
798 /* Write to enable desired perf counters */
799 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
800 /* Zero out and enable the perf counters
801 * Write 0x5:
802 * Bit 0 = Start all counters(1)
803 * Bit 2 = Global counter reset enable(1)
804 */
805 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
806
807 msleep(1000);
808
809 /* Load the shadow and disable the perf counters
810 * Write 0x2:
811 * Bit 0 = Stop counters(0)
812 * Bit 1 = Load the shadow counters(1)
813 */
814 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
815
816 /* Read register values to get any >32bit overflow */
817 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
818 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
819 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
820
821 /* Get the values and add the overflow */
822 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
823 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
824}
825
826static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
827{
828 u32 sol_reg;
829
830 /* CP hangs in IGT reloading test on RN, reset to WA */
831 if (adev->asic_type == CHIP_RENOIR)
832 return true;
833
834 if (amdgpu_gmc_need_reset_on_init(adev))
835 return true;
836 if (amdgpu_psp_tos_reload_needed(adev))
837 return true;
838 /* Just return false for soc15 GPUs. Reset does not seem to
839 * be necessary.
840 */
841 if (!amdgpu_passthrough(adev))
842 return false;
843
844 if (adev->flags & AMD_IS_APU)
845 return false;
846
847 /* Check sOS sign of life register to confirm sys driver and sOS
848 * are already been loaded.
849 */
850 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
851 if (sol_reg)
852 return true;
853
854 return false;
855}
856
857static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
858{
859 uint64_t nak_r, nak_g;
860
861 /* Get the number of NAKs received and generated */
862 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
863 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
864
865 /* Add the total number of NAKs, i.e the number of replays */
866 return (nak_r + nak_g);
867}
868
869static void soc15_pre_asic_init(struct amdgpu_device *adev)
870{
871 gmc_v9_0_restore_registers(adev);
872}
873
874static const struct amdgpu_asic_funcs soc15_asic_funcs =
875{
876 .read_disabled_bios = &soc15_read_disabled_bios,
877 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
878 .read_register = &soc15_read_register,
879 .reset = &soc15_asic_reset,
880 .reset_method = &soc15_asic_reset_method,
881 .get_xclk = &soc15_get_xclk,
882 .set_uvd_clocks = &soc15_set_uvd_clocks,
883 .set_vce_clocks = &soc15_set_vce_clocks,
884 .get_config_memsize = &soc15_get_config_memsize,
885 .need_full_reset = &soc15_need_full_reset,
886 .init_doorbell_index = &vega10_doorbell_index_init,
887 .get_pcie_usage = &soc15_get_pcie_usage,
888 .need_reset_on_init = &soc15_need_reset_on_init,
889 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
890 .supports_baco = &soc15_supports_baco,
891 .pre_asic_init = &soc15_pre_asic_init,
892 .query_video_codecs = &soc15_query_video_codecs,
893};
894
895static const struct amdgpu_asic_funcs vega20_asic_funcs =
896{
897 .read_disabled_bios = &soc15_read_disabled_bios,
898 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
899 .read_register = &soc15_read_register,
900 .reset = &soc15_asic_reset,
901 .reset_method = &soc15_asic_reset_method,
902 .get_xclk = &soc15_get_xclk,
903 .set_uvd_clocks = &soc15_set_uvd_clocks,
904 .set_vce_clocks = &soc15_set_vce_clocks,
905 .get_config_memsize = &soc15_get_config_memsize,
906 .need_full_reset = &soc15_need_full_reset,
907 .init_doorbell_index = &vega20_doorbell_index_init,
908 .get_pcie_usage = &vega20_get_pcie_usage,
909 .need_reset_on_init = &soc15_need_reset_on_init,
910 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
911 .supports_baco = &soc15_supports_baco,
912 .pre_asic_init = &soc15_pre_asic_init,
913 .query_video_codecs = &soc15_query_video_codecs,
914};
915
916static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
917{
918 .read_disabled_bios = &soc15_read_disabled_bios,
919 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
920 .read_register = &soc15_read_register,
921 .reset = &soc15_asic_reset,
922 .reset_method = &soc15_asic_reset_method,
923 .get_xclk = &soc15_get_xclk,
924 .set_uvd_clocks = &soc15_set_uvd_clocks,
925 .set_vce_clocks = &soc15_set_vce_clocks,
926 .get_config_memsize = &soc15_get_config_memsize,
927 .need_full_reset = &soc15_need_full_reset,
928 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
929 .need_reset_on_init = &soc15_need_reset_on_init,
930 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
931 .supports_baco = &soc15_supports_baco,
932 .pre_asic_init = &soc15_pre_asic_init,
933 .query_video_codecs = &soc15_query_video_codecs,
934 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
935 .get_reg_state = &aqua_vanjaram_get_reg_state,
936};
937
938static int soc15_common_early_init(struct amdgpu_ip_block *ip_block)
939{
940 struct amdgpu_device *adev = ip_block->adev;
941
942 adev->nbio.funcs->set_reg_remap(adev);
943 adev->smc_rreg = NULL;
944 adev->smc_wreg = NULL;
945 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
946 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
947 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
948 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
949 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
950 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
951 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
952 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
953 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
954 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
955 adev->didt_rreg = &soc15_didt_rreg;
956 adev->didt_wreg = &soc15_didt_wreg;
957 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
958 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
959 adev->se_cac_rreg = &soc15_se_cac_rreg;
960 adev->se_cac_wreg = &soc15_se_cac_wreg;
961
962 adev->rev_id = amdgpu_device_get_rev_id(adev);
963 adev->external_rev_id = 0xFF;
964 /* TODO: split the GC and PG flags based on the relevant IP version for which
965 * they are relevant.
966 */
967 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
968 case IP_VERSION(9, 0, 1):
969 adev->asic_funcs = &soc15_asic_funcs;
970 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
971 AMD_CG_SUPPORT_GFX_MGLS |
972 AMD_CG_SUPPORT_GFX_RLC_LS |
973 AMD_CG_SUPPORT_GFX_CP_LS |
974 AMD_CG_SUPPORT_GFX_3D_CGCG |
975 AMD_CG_SUPPORT_GFX_3D_CGLS |
976 AMD_CG_SUPPORT_GFX_CGCG |
977 AMD_CG_SUPPORT_GFX_CGLS |
978 AMD_CG_SUPPORT_BIF_MGCG |
979 AMD_CG_SUPPORT_BIF_LS |
980 AMD_CG_SUPPORT_HDP_LS |
981 AMD_CG_SUPPORT_DRM_MGCG |
982 AMD_CG_SUPPORT_DRM_LS |
983 AMD_CG_SUPPORT_ROM_MGCG |
984 AMD_CG_SUPPORT_DF_MGCG |
985 AMD_CG_SUPPORT_SDMA_MGCG |
986 AMD_CG_SUPPORT_SDMA_LS |
987 AMD_CG_SUPPORT_MC_MGCG |
988 AMD_CG_SUPPORT_MC_LS;
989 adev->pg_flags = 0;
990 adev->external_rev_id = 0x1;
991 break;
992 case IP_VERSION(9, 2, 1):
993 adev->asic_funcs = &soc15_asic_funcs;
994 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
995 AMD_CG_SUPPORT_GFX_MGLS |
996 AMD_CG_SUPPORT_GFX_CGCG |
997 AMD_CG_SUPPORT_GFX_CGLS |
998 AMD_CG_SUPPORT_GFX_3D_CGCG |
999 AMD_CG_SUPPORT_GFX_3D_CGLS |
1000 AMD_CG_SUPPORT_GFX_CP_LS |
1001 AMD_CG_SUPPORT_MC_LS |
1002 AMD_CG_SUPPORT_MC_MGCG |
1003 AMD_CG_SUPPORT_SDMA_MGCG |
1004 AMD_CG_SUPPORT_SDMA_LS |
1005 AMD_CG_SUPPORT_BIF_MGCG |
1006 AMD_CG_SUPPORT_BIF_LS |
1007 AMD_CG_SUPPORT_HDP_MGCG |
1008 AMD_CG_SUPPORT_HDP_LS |
1009 AMD_CG_SUPPORT_ROM_MGCG |
1010 AMD_CG_SUPPORT_VCE_MGCG |
1011 AMD_CG_SUPPORT_UVD_MGCG;
1012 adev->pg_flags = 0;
1013 adev->external_rev_id = adev->rev_id + 0x14;
1014 break;
1015 case IP_VERSION(9, 4, 0):
1016 adev->asic_funcs = &vega20_asic_funcs;
1017 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1018 AMD_CG_SUPPORT_GFX_MGLS |
1019 AMD_CG_SUPPORT_GFX_CGCG |
1020 AMD_CG_SUPPORT_GFX_CGLS |
1021 AMD_CG_SUPPORT_GFX_3D_CGCG |
1022 AMD_CG_SUPPORT_GFX_3D_CGLS |
1023 AMD_CG_SUPPORT_GFX_CP_LS |
1024 AMD_CG_SUPPORT_MC_LS |
1025 AMD_CG_SUPPORT_MC_MGCG |
1026 AMD_CG_SUPPORT_SDMA_MGCG |
1027 AMD_CG_SUPPORT_SDMA_LS |
1028 AMD_CG_SUPPORT_BIF_MGCG |
1029 AMD_CG_SUPPORT_BIF_LS |
1030 AMD_CG_SUPPORT_HDP_MGCG |
1031 AMD_CG_SUPPORT_HDP_LS |
1032 AMD_CG_SUPPORT_ROM_MGCG |
1033 AMD_CG_SUPPORT_VCE_MGCG |
1034 AMD_CG_SUPPORT_UVD_MGCG;
1035 adev->pg_flags = 0;
1036 adev->external_rev_id = adev->rev_id + 0x28;
1037 break;
1038 case IP_VERSION(9, 1, 0):
1039 case IP_VERSION(9, 2, 2):
1040 adev->asic_funcs = &soc15_asic_funcs;
1041
1042 if (adev->rev_id >= 0x8)
1043 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1044
1045 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1046 adev->external_rev_id = adev->rev_id + 0x79;
1047 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1048 adev->external_rev_id = adev->rev_id + 0x41;
1049 else if (adev->rev_id == 1)
1050 adev->external_rev_id = adev->rev_id + 0x20;
1051 else
1052 adev->external_rev_id = adev->rev_id + 0x01;
1053
1054 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1055 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1056 AMD_CG_SUPPORT_GFX_MGLS |
1057 AMD_CG_SUPPORT_GFX_CP_LS |
1058 AMD_CG_SUPPORT_GFX_3D_CGCG |
1059 AMD_CG_SUPPORT_GFX_3D_CGLS |
1060 AMD_CG_SUPPORT_GFX_CGCG |
1061 AMD_CG_SUPPORT_GFX_CGLS |
1062 AMD_CG_SUPPORT_BIF_LS |
1063 AMD_CG_SUPPORT_HDP_LS |
1064 AMD_CG_SUPPORT_MC_MGCG |
1065 AMD_CG_SUPPORT_MC_LS |
1066 AMD_CG_SUPPORT_SDMA_MGCG |
1067 AMD_CG_SUPPORT_SDMA_LS |
1068 AMD_CG_SUPPORT_VCN_MGCG;
1069
1070 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1071 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1072 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1073 AMD_CG_SUPPORT_GFX_MGLS |
1074 AMD_CG_SUPPORT_GFX_CP_LS |
1075 AMD_CG_SUPPORT_GFX_3D_CGLS |
1076 AMD_CG_SUPPORT_GFX_CGCG |
1077 AMD_CG_SUPPORT_GFX_CGLS |
1078 AMD_CG_SUPPORT_BIF_LS |
1079 AMD_CG_SUPPORT_HDP_LS |
1080 AMD_CG_SUPPORT_MC_MGCG |
1081 AMD_CG_SUPPORT_MC_LS |
1082 AMD_CG_SUPPORT_SDMA_MGCG |
1083 AMD_CG_SUPPORT_SDMA_LS |
1084 AMD_CG_SUPPORT_VCN_MGCG;
1085
1086 /*
1087 * MMHUB PG needs to be disabled for Picasso for
1088 * stability reasons.
1089 */
1090 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1091 AMD_PG_SUPPORT_VCN;
1092 } else {
1093 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1094 AMD_CG_SUPPORT_GFX_MGLS |
1095 AMD_CG_SUPPORT_GFX_RLC_LS |
1096 AMD_CG_SUPPORT_GFX_CP_LS |
1097 AMD_CG_SUPPORT_GFX_3D_CGLS |
1098 AMD_CG_SUPPORT_GFX_CGCG |
1099 AMD_CG_SUPPORT_GFX_CGLS |
1100 AMD_CG_SUPPORT_BIF_MGCG |
1101 AMD_CG_SUPPORT_BIF_LS |
1102 AMD_CG_SUPPORT_HDP_MGCG |
1103 AMD_CG_SUPPORT_HDP_LS |
1104 AMD_CG_SUPPORT_DRM_MGCG |
1105 AMD_CG_SUPPORT_DRM_LS |
1106 AMD_CG_SUPPORT_MC_MGCG |
1107 AMD_CG_SUPPORT_MC_LS |
1108 AMD_CG_SUPPORT_SDMA_MGCG |
1109 AMD_CG_SUPPORT_SDMA_LS |
1110 AMD_CG_SUPPORT_VCN_MGCG;
1111
1112 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1113 }
1114 break;
1115 case IP_VERSION(9, 4, 1):
1116 adev->asic_funcs = &vega20_asic_funcs;
1117 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1118 AMD_CG_SUPPORT_GFX_MGLS |
1119 AMD_CG_SUPPORT_GFX_CGCG |
1120 AMD_CG_SUPPORT_GFX_CGLS |
1121 AMD_CG_SUPPORT_GFX_CP_LS |
1122 AMD_CG_SUPPORT_HDP_MGCG |
1123 AMD_CG_SUPPORT_HDP_LS |
1124 AMD_CG_SUPPORT_SDMA_MGCG |
1125 AMD_CG_SUPPORT_SDMA_LS |
1126 AMD_CG_SUPPORT_MC_MGCG |
1127 AMD_CG_SUPPORT_MC_LS |
1128 AMD_CG_SUPPORT_IH_CG |
1129 AMD_CG_SUPPORT_VCN_MGCG |
1130 AMD_CG_SUPPORT_JPEG_MGCG;
1131 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1132 adev->external_rev_id = adev->rev_id + 0x32;
1133 break;
1134 case IP_VERSION(9, 3, 0):
1135 adev->asic_funcs = &soc15_asic_funcs;
1136
1137 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1138 adev->external_rev_id = adev->rev_id + 0x91;
1139 else
1140 adev->external_rev_id = adev->rev_id + 0xa1;
1141 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1142 AMD_CG_SUPPORT_GFX_MGLS |
1143 AMD_CG_SUPPORT_GFX_3D_CGCG |
1144 AMD_CG_SUPPORT_GFX_3D_CGLS |
1145 AMD_CG_SUPPORT_GFX_CGCG |
1146 AMD_CG_SUPPORT_GFX_CGLS |
1147 AMD_CG_SUPPORT_GFX_CP_LS |
1148 AMD_CG_SUPPORT_MC_MGCG |
1149 AMD_CG_SUPPORT_MC_LS |
1150 AMD_CG_SUPPORT_SDMA_MGCG |
1151 AMD_CG_SUPPORT_SDMA_LS |
1152 AMD_CG_SUPPORT_BIF_LS |
1153 AMD_CG_SUPPORT_HDP_LS |
1154 AMD_CG_SUPPORT_VCN_MGCG |
1155 AMD_CG_SUPPORT_JPEG_MGCG |
1156 AMD_CG_SUPPORT_IH_CG |
1157 AMD_CG_SUPPORT_ATHUB_LS |
1158 AMD_CG_SUPPORT_ATHUB_MGCG |
1159 AMD_CG_SUPPORT_DF_MGCG;
1160 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1161 AMD_PG_SUPPORT_VCN |
1162 AMD_PG_SUPPORT_JPEG |
1163 AMD_PG_SUPPORT_VCN_DPG;
1164 break;
1165 case IP_VERSION(9, 4, 2):
1166 adev->asic_funcs = &vega20_asic_funcs;
1167 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1168 AMD_CG_SUPPORT_GFX_MGLS |
1169 AMD_CG_SUPPORT_GFX_CP_LS |
1170 AMD_CG_SUPPORT_HDP_LS |
1171 AMD_CG_SUPPORT_SDMA_MGCG |
1172 AMD_CG_SUPPORT_SDMA_LS |
1173 AMD_CG_SUPPORT_IH_CG |
1174 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1175 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1176 adev->external_rev_id = adev->rev_id + 0x3c;
1177 break;
1178 case IP_VERSION(9, 4, 3):
1179 case IP_VERSION(9, 4, 4):
1180 adev->asic_funcs = &aqua_vanjaram_asic_funcs;
1181 adev->cg_flags =
1182 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
1183 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
1184 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG |
1185 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG |
1186 AMD_CG_SUPPORT_IH_CG;
1187 adev->pg_flags =
1188 AMD_PG_SUPPORT_VCN |
1189 AMD_PG_SUPPORT_VCN_DPG |
1190 AMD_PG_SUPPORT_JPEG;
1191 /*TODO: need a new external_rev_id for GC 9.4.4? */
1192 adev->external_rev_id = adev->rev_id + 0x46;
1193 break;
1194 default:
1195 /* FIXME: not supported yet */
1196 return -EINVAL;
1197 }
1198
1199 if (amdgpu_sriov_vf(adev)) {
1200 amdgpu_virt_init_setting(adev);
1201 xgpu_ai_mailbox_set_irq_funcs(adev);
1202 }
1203
1204 return 0;
1205}
1206
1207static int soc15_common_late_init(struct amdgpu_ip_block *ip_block)
1208{
1209 struct amdgpu_device *adev = ip_block->adev;
1210
1211 if (amdgpu_sriov_vf(adev))
1212 xgpu_ai_mailbox_get_irq(adev);
1213
1214 /* Enable selfring doorbell aperture late because doorbell BAR
1215 * aperture will change if resize BAR successfully in gmc sw_init.
1216 */
1217 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1218
1219 return 0;
1220}
1221
1222static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block)
1223{
1224 struct amdgpu_device *adev = ip_block->adev;
1225
1226 if (amdgpu_sriov_vf(adev))
1227 xgpu_ai_mailbox_add_irq_id(adev);
1228
1229 if (adev->df.funcs &&
1230 adev->df.funcs->sw_init)
1231 adev->df.funcs->sw_init(adev);
1232
1233 return 0;
1234}
1235
1236static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block)
1237{
1238 struct amdgpu_device *adev = ip_block->adev;
1239
1240 if (adev->df.funcs &&
1241 adev->df.funcs->sw_fini)
1242 adev->df.funcs->sw_fini(adev);
1243 return 0;
1244}
1245
1246static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1247{
1248 int i;
1249
1250 /* sdma doorbell range is programed by hypervisor */
1251 if (!amdgpu_sriov_vf(adev)) {
1252 for (i = 0; i < adev->sdma.num_instances; i++) {
1253 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1254 true, adev->doorbell_index.sdma_engine[i] << 1,
1255 adev->doorbell_index.sdma_doorbell_range);
1256 }
1257 }
1258}
1259
1260static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block)
1261{
1262 struct amdgpu_device *adev = ip_block->adev;
1263
1264 /* enable aspm */
1265 soc15_program_aspm(adev);
1266 /* setup nbio registers */
1267 adev->nbio.funcs->init_registers(adev);
1268 /* remap HDP registers to a hole in mmio space,
1269 * for the purpose of expose those registers
1270 * to process space
1271 */
1272 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1273 adev->nbio.funcs->remap_hdp_registers(adev);
1274
1275 /* enable the doorbell aperture */
1276 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1277
1278 /* HW doorbell routing policy: doorbell writing not
1279 * in SDMA/IH/MM/ACV range will be routed to CP. So
1280 * we need to init SDMA doorbell range prior
1281 * to CP ip block init and ring test. IH already
1282 * happens before CP.
1283 */
1284 soc15_sdma_doorbell_range_init(adev);
1285
1286 return 0;
1287}
1288
1289static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block)
1290{
1291 struct amdgpu_device *adev = ip_block->adev;
1292
1293 /* Disable the doorbell aperture and selfring doorbell aperture
1294 * separately in hw_fini because soc15_enable_doorbell_aperture
1295 * has been removed and there is no need to delay disabling
1296 * selfring doorbell.
1297 */
1298 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1299 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1300
1301 if (amdgpu_sriov_vf(adev))
1302 xgpu_ai_mailbox_put_irq(adev);
1303
1304 /*
1305 * For minimal init, late_init is not called, hence RAS irqs are not
1306 * enabled.
1307 */
1308 if ((!amdgpu_sriov_vf(adev)) &&
1309 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &&
1310 adev->nbio.ras_if &&
1311 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1312 if (adev->nbio.ras &&
1313 adev->nbio.ras->init_ras_controller_interrupt)
1314 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1315 if (adev->nbio.ras &&
1316 adev->nbio.ras->init_ras_err_event_athub_interrupt)
1317 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1318 }
1319
1320 return 0;
1321}
1322
1323static int soc15_common_suspend(struct amdgpu_ip_block *ip_block)
1324{
1325 return soc15_common_hw_fini(ip_block);
1326}
1327
1328static int soc15_common_resume(struct amdgpu_ip_block *ip_block)
1329{
1330 struct amdgpu_device *adev = ip_block->adev;
1331
1332 if (soc15_need_reset_on_resume(adev)) {
1333 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n");
1334 soc15_asic_reset(adev);
1335 }
1336 return soc15_common_hw_init(ip_block);
1337}
1338
1339static bool soc15_common_is_idle(void *handle)
1340{
1341 return true;
1342}
1343
1344static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1345{
1346 uint32_t def, data;
1347
1348 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1349
1350 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1351 data &= ~(0x01000000 |
1352 0x02000000 |
1353 0x04000000 |
1354 0x08000000 |
1355 0x10000000 |
1356 0x20000000 |
1357 0x40000000 |
1358 0x80000000);
1359 else
1360 data |= (0x01000000 |
1361 0x02000000 |
1362 0x04000000 |
1363 0x08000000 |
1364 0x10000000 |
1365 0x20000000 |
1366 0x40000000 |
1367 0x80000000);
1368
1369 if (def != data)
1370 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1371}
1372
1373static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1374{
1375 uint32_t def, data;
1376
1377 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1378
1379 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1380 data |= 1;
1381 else
1382 data &= ~1;
1383
1384 if (def != data)
1385 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1386}
1387
1388static int soc15_common_set_clockgating_state(void *handle,
1389 enum amd_clockgating_state state)
1390{
1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1392
1393 if (amdgpu_sriov_vf(adev))
1394 return 0;
1395
1396 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1397 case IP_VERSION(6, 1, 0):
1398 case IP_VERSION(6, 2, 0):
1399 case IP_VERSION(7, 4, 0):
1400 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1401 state == AMD_CG_STATE_GATE);
1402 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1403 state == AMD_CG_STATE_GATE);
1404 adev->hdp.funcs->update_clock_gating(adev,
1405 state == AMD_CG_STATE_GATE);
1406 soc15_update_drm_clock_gating(adev,
1407 state == AMD_CG_STATE_GATE);
1408 soc15_update_drm_light_sleep(adev,
1409 state == AMD_CG_STATE_GATE);
1410 adev->smuio.funcs->update_rom_clock_gating(adev,
1411 state == AMD_CG_STATE_GATE);
1412 adev->df.funcs->update_medium_grain_clock_gating(adev,
1413 state == AMD_CG_STATE_GATE);
1414 break;
1415 case IP_VERSION(7, 0, 0):
1416 case IP_VERSION(7, 0, 1):
1417 case IP_VERSION(2, 5, 0):
1418 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1419 state == AMD_CG_STATE_GATE);
1420 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1421 state == AMD_CG_STATE_GATE);
1422 adev->hdp.funcs->update_clock_gating(adev,
1423 state == AMD_CG_STATE_GATE);
1424 soc15_update_drm_clock_gating(adev,
1425 state == AMD_CG_STATE_GATE);
1426 soc15_update_drm_light_sleep(adev,
1427 state == AMD_CG_STATE_GATE);
1428 break;
1429 case IP_VERSION(7, 4, 1):
1430 case IP_VERSION(7, 4, 4):
1431 adev->hdp.funcs->update_clock_gating(adev,
1432 state == AMD_CG_STATE_GATE);
1433 break;
1434 default:
1435 break;
1436 }
1437 return 0;
1438}
1439
1440static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1441{
1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1443 int data;
1444
1445 if (amdgpu_sriov_vf(adev))
1446 *flags = 0;
1447
1448 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1449 adev->nbio.funcs->get_clockgating_state(adev, flags);
1450
1451 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
1452 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1453
1454 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
1455 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &&
1456 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {
1457 /* AMD_CG_SUPPORT_DRM_MGCG */
1458 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1459 if (!(data & 0x01000000))
1460 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1461
1462 /* AMD_CG_SUPPORT_DRM_LS */
1463 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1464 if (data & 0x1)
1465 *flags |= AMD_CG_SUPPORT_DRM_LS;
1466 }
1467
1468 /* AMD_CG_SUPPORT_ROM_MGCG */
1469 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
1470 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1471
1472 if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
1473 adev->df.funcs->get_clockgating_state(adev, flags);
1474}
1475
1476static int soc15_common_set_powergating_state(void *handle,
1477 enum amd_powergating_state state)
1478{
1479 /* todo */
1480 return 0;
1481}
1482
1483static const struct amd_ip_funcs soc15_common_ip_funcs = {
1484 .name = "soc15_common",
1485 .early_init = soc15_common_early_init,
1486 .late_init = soc15_common_late_init,
1487 .sw_init = soc15_common_sw_init,
1488 .sw_fini = soc15_common_sw_fini,
1489 .hw_init = soc15_common_hw_init,
1490 .hw_fini = soc15_common_hw_fini,
1491 .suspend = soc15_common_suspend,
1492 .resume = soc15_common_resume,
1493 .is_idle = soc15_common_is_idle,
1494 .set_clockgating_state = soc15_common_set_clockgating_state,
1495 .set_powergating_state = soc15_common_set_powergating_state,
1496 .get_clockgating_state= soc15_common_get_clockgating_state,
1497};
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <drm/drmP.h>
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
37#include "uvd/uvd_7_0_offset.h"
38#include "gc/gc_9_0_offset.h"
39#include "gc/gc_9_0_sh_mask.h"
40#include "sdma0/sdma0_4_0_offset.h"
41#include "sdma1/sdma1_4_0_offset.h"
42#include "hdp/hdp_4_0_offset.h"
43#include "hdp/hdp_4_0_sh_mask.h"
44#include "mp/mp_9_0_offset.h"
45#include "mp/mp_9_0_sh_mask.h"
46#include "smuio/smuio_9_0_offset.h"
47#include "smuio/smuio_9_0_sh_mask.h"
48
49#include "soc15.h"
50#include "soc15_common.h"
51#include "gfx_v9_0.h"
52#include "gmc_v9_0.h"
53#include "gfxhub_v1_0.h"
54#include "mmhub_v1_0.h"
55#include "vega10_ih.h"
56#include "sdma_v4_0.h"
57#include "uvd_v7_0.h"
58#include "vce_v4_0.h"
59#include "vcn_v1_0.h"
60#include "dce_virtual.h"
61#include "mxgpu_ai.h"
62
63#define mmFabricConfigAccessControl 0x0410
64#define mmFabricConfigAccessControl_BASE_IDX 0
65#define mmFabricConfigAccessControl_DEFAULT 0x00000000
66//FabricConfigAccessControl
67#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
68#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
69#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
70#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
71#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
72#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
73
74
75#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
76#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
77//DF_PIE_AON0_DfGlobalClkGater
78#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
79#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
80
81enum {
82 DF_MGCG_DISABLE = 0,
83 DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
84 DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
85 DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
86 DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
87 DF_MGCG_ENABLE_63_CYCLE_DELAY =15
88};
89
90#define mmMP0_MISC_CGTT_CTRL0 0x01b9
91#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
92#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
93#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
94
95/*
96 * Indirect registers accessor
97 */
98static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
99{
100 unsigned long flags, address, data;
101 u32 r;
102 address = adev->nbio_funcs->get_pcie_index_offset(adev);
103 data = adev->nbio_funcs->get_pcie_data_offset(adev);
104
105 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
106 WREG32(address, reg);
107 (void)RREG32(address);
108 r = RREG32(data);
109 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
110 return r;
111}
112
113static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
114{
115 unsigned long flags, address, data;
116
117 address = adev->nbio_funcs->get_pcie_index_offset(adev);
118 data = adev->nbio_funcs->get_pcie_data_offset(adev);
119
120 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
121 WREG32(address, reg);
122 (void)RREG32(address);
123 WREG32(data, v);
124 (void)RREG32(data);
125 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
126}
127
128static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
129{
130 unsigned long flags, address, data;
131 u32 r;
132
133 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
134 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
135
136 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
137 WREG32(address, ((reg) & 0x1ff));
138 r = RREG32(data);
139 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
140 return r;
141}
142
143static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
144{
145 unsigned long flags, address, data;
146
147 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
148 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
149
150 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
151 WREG32(address, ((reg) & 0x1ff));
152 WREG32(data, (v));
153 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
154}
155
156static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
157{
158 unsigned long flags, address, data;
159 u32 r;
160
161 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
162 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
163
164 spin_lock_irqsave(&adev->didt_idx_lock, flags);
165 WREG32(address, (reg));
166 r = RREG32(data);
167 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
168 return r;
169}
170
171static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
172{
173 unsigned long flags, address, data;
174
175 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
176 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
177
178 spin_lock_irqsave(&adev->didt_idx_lock, flags);
179 WREG32(address, (reg));
180 WREG32(data, (v));
181 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
182}
183
184static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
185{
186 unsigned long flags;
187 u32 r;
188
189 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
190 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
191 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
192 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
193 return r;
194}
195
196static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
201 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
202 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
203 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
204}
205
206static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
207{
208 unsigned long flags;
209 u32 r;
210
211 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
212 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
213 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
214 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
215 return r;
216}
217
218static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
219{
220 unsigned long flags;
221
222 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
223 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
224 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
225 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
226}
227
228static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
229{
230 return adev->nbio_funcs->get_memsize(adev);
231}
232
233static u32 soc15_get_xclk(struct amdgpu_device *adev)
234{
235 return adev->clock.spll.reference_freq;
236}
237
238
239void soc15_grbm_select(struct amdgpu_device *adev,
240 u32 me, u32 pipe, u32 queue, u32 vmid)
241{
242 u32 grbm_gfx_cntl = 0;
243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
246 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
247
248 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
249}
250
251static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
252{
253 /* todo */
254}
255
256static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
257{
258 /* todo */
259 return false;
260}
261
262static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
263 u8 *bios, u32 length_bytes)
264{
265 u32 *dw_ptr;
266 u32 i, length_dw;
267
268 if (bios == NULL)
269 return false;
270 if (length_bytes == 0)
271 return false;
272 /* APU vbios image is part of sbios image */
273 if (adev->flags & AMD_IS_APU)
274 return false;
275
276 dw_ptr = (u32 *)bios;
277 length_dw = ALIGN(length_bytes, 4) / 4;
278
279 /* set rom index to 0 */
280 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
281 /* read out the rom data */
282 for (i = 0; i < length_dw; i++)
283 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
284
285 return true;
286}
287
288struct soc15_allowed_register_entry {
289 uint32_t hwip;
290 uint32_t inst;
291 uint32_t seg;
292 uint32_t reg_offset;
293 bool grbm_indexed;
294};
295
296
297static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
298 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
299 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
300 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
301 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
302 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
303 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
304 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
305 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
306 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
307 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
308 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
309 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
310 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
311 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
312 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
313 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
314 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
315 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
316};
317
318static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
319 u32 sh_num, u32 reg_offset)
320{
321 uint32_t val;
322
323 mutex_lock(&adev->grbm_idx_mutex);
324 if (se_num != 0xffffffff || sh_num != 0xffffffff)
325 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
326
327 val = RREG32(reg_offset);
328
329 if (se_num != 0xffffffff || sh_num != 0xffffffff)
330 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
331 mutex_unlock(&adev->grbm_idx_mutex);
332 return val;
333}
334
335static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
336 bool indexed, u32 se_num,
337 u32 sh_num, u32 reg_offset)
338{
339 if (indexed) {
340 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
341 } else {
342 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
343 return adev->gfx.config.gb_addr_config;
344 return RREG32(reg_offset);
345 }
346}
347
348static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
349 u32 sh_num, u32 reg_offset, u32 *value)
350{
351 uint32_t i;
352 struct soc15_allowed_register_entry *en;
353
354 *value = 0;
355 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
356 en = &soc15_allowed_read_registers[i];
357 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
358 + en->reg_offset))
359 continue;
360
361 *value = soc15_get_register_value(adev,
362 soc15_allowed_read_registers[i].grbm_indexed,
363 se_num, sh_num, reg_offset);
364 return 0;
365 }
366 return -EINVAL;
367}
368
369
370/**
371 * soc15_program_register_sequence - program an array of registers.
372 *
373 * @adev: amdgpu_device pointer
374 * @regs: pointer to the register array
375 * @array_size: size of the register array
376 *
377 * Programs an array or registers with and and or masks.
378 * This is a helper for setting golden registers.
379 */
380
381void soc15_program_register_sequence(struct amdgpu_device *adev,
382 const struct soc15_reg_golden *regs,
383 const u32 array_size)
384{
385 const struct soc15_reg_golden *entry;
386 u32 tmp, reg;
387 int i;
388
389 for (i = 0; i < array_size; ++i) {
390 entry = ®s[i];
391 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
392
393 if (entry->and_mask == 0xffffffff) {
394 tmp = entry->or_mask;
395 } else {
396 tmp = RREG32(reg);
397 tmp &= ~(entry->and_mask);
398 tmp |= entry->or_mask;
399 }
400 WREG32(reg, tmp);
401 }
402
403}
404
405
406static int soc15_asic_reset(struct amdgpu_device *adev)
407{
408 u32 i;
409
410 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
411
412 dev_info(adev->dev, "GPU reset\n");
413
414 /* disable BM */
415 pci_clear_master(adev->pdev);
416
417 pci_save_state(adev->pdev);
418
419 psp_gpu_reset(adev);
420
421 pci_restore_state(adev->pdev);
422
423 /* wait for asic to come out of reset */
424 for (i = 0; i < adev->usec_timeout; i++) {
425 u32 memsize = adev->nbio_funcs->get_memsize(adev);
426
427 if (memsize != 0xffffffff)
428 break;
429 udelay(1);
430 }
431
432 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
433
434 return 0;
435}
436
437/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
438 u32 cntl_reg, u32 status_reg)
439{
440 return 0;
441}*/
442
443static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
444{
445 /*int r;
446
447 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
448 if (r)
449 return r;
450
451 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
452 */
453 return 0;
454}
455
456static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
457{
458 /* todo */
459
460 return 0;
461}
462
463static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
464{
465 if (pci_is_root_bus(adev->pdev->bus))
466 return;
467
468 if (amdgpu_pcie_gen2 == 0)
469 return;
470
471 if (adev->flags & AMD_IS_APU)
472 return;
473
474 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
475 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
476 return;
477
478 /* todo */
479}
480
481static void soc15_program_aspm(struct amdgpu_device *adev)
482{
483
484 if (amdgpu_aspm == 0)
485 return;
486
487 /* todo */
488}
489
490static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
491 bool enable)
492{
493 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
494 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
495}
496
497static const struct amdgpu_ip_block_version vega10_common_ip_block =
498{
499 .type = AMD_IP_BLOCK_TYPE_COMMON,
500 .major = 2,
501 .minor = 0,
502 .rev = 0,
503 .funcs = &soc15_common_ip_funcs,
504};
505
506int soc15_set_ip_blocks(struct amdgpu_device *adev)
507{
508 /* Set IP register base before any HW register access */
509 switch (adev->asic_type) {
510 case CHIP_VEGA10:
511 case CHIP_VEGA12:
512 case CHIP_RAVEN:
513 vega10_reg_base_init(adev);
514 break;
515 default:
516 return -EINVAL;
517 }
518
519 if (adev->flags & AMD_IS_APU)
520 adev->nbio_funcs = &nbio_v7_0_funcs;
521 else
522 adev->nbio_funcs = &nbio_v6_1_funcs;
523
524 adev->nbio_funcs->detect_hw_virt(adev);
525
526 if (amdgpu_sriov_vf(adev))
527 adev->virt.ops = &xgpu_ai_virt_ops;
528
529 switch (adev->asic_type) {
530 case CHIP_VEGA10:
531 case CHIP_VEGA12:
532 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
533 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
534 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
535 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
536 if (!amdgpu_sriov_vf(adev))
537 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
538 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
539 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
540#if defined(CONFIG_DRM_AMD_DC)
541 else if (amdgpu_device_has_dc_support(adev))
542 amdgpu_device_ip_block_add(adev, &dm_ip_block);
543#else
544# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
545#endif
546 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
547 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
548 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
549 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
550 break;
551 case CHIP_RAVEN:
552 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
553 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
554 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
555 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
556 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
557 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
558 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
559#if defined(CONFIG_DRM_AMD_DC)
560 else if (amdgpu_device_has_dc_support(adev))
561 amdgpu_device_ip_block_add(adev, &dm_ip_block);
562#else
563# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
564#endif
565 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
566 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
567 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 return 0;
574}
575
576static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
577{
578 return adev->nbio_funcs->get_rev_id(adev);
579}
580
581static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
582{
583 adev->nbio_funcs->hdp_flush(adev, ring);
584}
585
586static void soc15_invalidate_hdp(struct amdgpu_device *adev,
587 struct amdgpu_ring *ring)
588{
589 if (!ring || !ring->funcs->emit_wreg)
590 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
591 else
592 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
593 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
594}
595
596static const struct amdgpu_asic_funcs soc15_asic_funcs =
597{
598 .read_disabled_bios = &soc15_read_disabled_bios,
599 .read_bios_from_rom = &soc15_read_bios_from_rom,
600 .read_register = &soc15_read_register,
601 .reset = &soc15_asic_reset,
602 .set_vga_state = &soc15_vga_set_state,
603 .get_xclk = &soc15_get_xclk,
604 .set_uvd_clocks = &soc15_set_uvd_clocks,
605 .set_vce_clocks = &soc15_set_vce_clocks,
606 .get_config_memsize = &soc15_get_config_memsize,
607 .flush_hdp = &soc15_flush_hdp,
608 .invalidate_hdp = &soc15_invalidate_hdp,
609};
610
611static int soc15_common_early_init(void *handle)
612{
613 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
614
615 adev->smc_rreg = NULL;
616 adev->smc_wreg = NULL;
617 adev->pcie_rreg = &soc15_pcie_rreg;
618 adev->pcie_wreg = &soc15_pcie_wreg;
619 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
620 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
621 adev->didt_rreg = &soc15_didt_rreg;
622 adev->didt_wreg = &soc15_didt_wreg;
623 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
624 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
625 adev->se_cac_rreg = &soc15_se_cac_rreg;
626 adev->se_cac_wreg = &soc15_se_cac_wreg;
627
628 adev->asic_funcs = &soc15_asic_funcs;
629
630 adev->rev_id = soc15_get_rev_id(adev);
631 adev->external_rev_id = 0xFF;
632 switch (adev->asic_type) {
633 case CHIP_VEGA10:
634 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
635 AMD_CG_SUPPORT_GFX_MGLS |
636 AMD_CG_SUPPORT_GFX_RLC_LS |
637 AMD_CG_SUPPORT_GFX_CP_LS |
638 AMD_CG_SUPPORT_GFX_3D_CGCG |
639 AMD_CG_SUPPORT_GFX_3D_CGLS |
640 AMD_CG_SUPPORT_GFX_CGCG |
641 AMD_CG_SUPPORT_GFX_CGLS |
642 AMD_CG_SUPPORT_BIF_MGCG |
643 AMD_CG_SUPPORT_BIF_LS |
644 AMD_CG_SUPPORT_HDP_LS |
645 AMD_CG_SUPPORT_DRM_MGCG |
646 AMD_CG_SUPPORT_DRM_LS |
647 AMD_CG_SUPPORT_ROM_MGCG |
648 AMD_CG_SUPPORT_DF_MGCG |
649 AMD_CG_SUPPORT_SDMA_MGCG |
650 AMD_CG_SUPPORT_SDMA_LS |
651 AMD_CG_SUPPORT_MC_MGCG |
652 AMD_CG_SUPPORT_MC_LS;
653 adev->pg_flags = 0;
654 adev->external_rev_id = 0x1;
655 break;
656 case CHIP_VEGA12:
657 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
658 AMD_CG_SUPPORT_GFX_MGLS |
659 AMD_CG_SUPPORT_GFX_CGCG |
660 AMD_CG_SUPPORT_GFX_CGLS |
661 AMD_CG_SUPPORT_GFX_3D_CGCG |
662 AMD_CG_SUPPORT_GFX_3D_CGLS |
663 AMD_CG_SUPPORT_GFX_CP_LS |
664 AMD_CG_SUPPORT_MC_LS |
665 AMD_CG_SUPPORT_MC_MGCG |
666 AMD_CG_SUPPORT_SDMA_MGCG |
667 AMD_CG_SUPPORT_SDMA_LS |
668 AMD_CG_SUPPORT_BIF_MGCG |
669 AMD_CG_SUPPORT_BIF_LS |
670 AMD_CG_SUPPORT_HDP_MGCG |
671 AMD_CG_SUPPORT_HDP_LS |
672 AMD_CG_SUPPORT_ROM_MGCG |
673 AMD_CG_SUPPORT_VCE_MGCG |
674 AMD_CG_SUPPORT_UVD_MGCG;
675 adev->pg_flags = 0;
676 adev->external_rev_id = adev->rev_id + 0x14;
677 break;
678 case CHIP_RAVEN:
679 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
680 AMD_CG_SUPPORT_GFX_MGLS |
681 AMD_CG_SUPPORT_GFX_RLC_LS |
682 AMD_CG_SUPPORT_GFX_CP_LS |
683 AMD_CG_SUPPORT_GFX_3D_CGCG |
684 AMD_CG_SUPPORT_GFX_3D_CGLS |
685 AMD_CG_SUPPORT_GFX_CGCG |
686 AMD_CG_SUPPORT_GFX_CGLS |
687 AMD_CG_SUPPORT_BIF_MGCG |
688 AMD_CG_SUPPORT_BIF_LS |
689 AMD_CG_SUPPORT_HDP_MGCG |
690 AMD_CG_SUPPORT_HDP_LS |
691 AMD_CG_SUPPORT_DRM_MGCG |
692 AMD_CG_SUPPORT_DRM_LS |
693 AMD_CG_SUPPORT_ROM_MGCG |
694 AMD_CG_SUPPORT_MC_MGCG |
695 AMD_CG_SUPPORT_MC_LS |
696 AMD_CG_SUPPORT_SDMA_MGCG |
697 AMD_CG_SUPPORT_SDMA_LS;
698 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
699
700 adev->external_rev_id = 0x1;
701 break;
702 default:
703 /* FIXME: not supported yet */
704 return -EINVAL;
705 }
706
707 if (amdgpu_sriov_vf(adev)) {
708 amdgpu_virt_init_setting(adev);
709 xgpu_ai_mailbox_set_irq_funcs(adev);
710 }
711
712 return 0;
713}
714
715static int soc15_common_late_init(void *handle)
716{
717 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
718
719 if (amdgpu_sriov_vf(adev))
720 xgpu_ai_mailbox_get_irq(adev);
721
722 return 0;
723}
724
725static int soc15_common_sw_init(void *handle)
726{
727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
728
729 if (amdgpu_sriov_vf(adev))
730 xgpu_ai_mailbox_add_irq_id(adev);
731
732 return 0;
733}
734
735static int soc15_common_sw_fini(void *handle)
736{
737 return 0;
738}
739
740static int soc15_common_hw_init(void *handle)
741{
742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743
744 /* enable pcie gen2/3 link */
745 soc15_pcie_gen3_enable(adev);
746 /* enable aspm */
747 soc15_program_aspm(adev);
748 /* setup nbio registers */
749 adev->nbio_funcs->init_registers(adev);
750 /* enable the doorbell aperture */
751 soc15_enable_doorbell_aperture(adev, true);
752
753 return 0;
754}
755
756static int soc15_common_hw_fini(void *handle)
757{
758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
759
760 /* disable the doorbell aperture */
761 soc15_enable_doorbell_aperture(adev, false);
762 if (amdgpu_sriov_vf(adev))
763 xgpu_ai_mailbox_put_irq(adev);
764
765 return 0;
766}
767
768static int soc15_common_suspend(void *handle)
769{
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 return soc15_common_hw_fini(adev);
773}
774
775static int soc15_common_resume(void *handle)
776{
777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
778
779 return soc15_common_hw_init(adev);
780}
781
782static bool soc15_common_is_idle(void *handle)
783{
784 return true;
785}
786
787static int soc15_common_wait_for_idle(void *handle)
788{
789 return 0;
790}
791
792static int soc15_common_soft_reset(void *handle)
793{
794 return 0;
795}
796
797static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
798{
799 uint32_t def, data;
800
801 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
802
803 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
804 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
805 else
806 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
807
808 if (def != data)
809 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
810}
811
812static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
813{
814 uint32_t def, data;
815
816 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
817
818 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
819 data &= ~(0x01000000 |
820 0x02000000 |
821 0x04000000 |
822 0x08000000 |
823 0x10000000 |
824 0x20000000 |
825 0x40000000 |
826 0x80000000);
827 else
828 data |= (0x01000000 |
829 0x02000000 |
830 0x04000000 |
831 0x08000000 |
832 0x10000000 |
833 0x20000000 |
834 0x40000000 |
835 0x80000000);
836
837 if (def != data)
838 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
839}
840
841static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
842{
843 uint32_t def, data;
844
845 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
846
847 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
848 data |= 1;
849 else
850 data &= ~1;
851
852 if (def != data)
853 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
854}
855
856static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
857 bool enable)
858{
859 uint32_t def, data;
860
861 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
862
863 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
864 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
865 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
866 else
867 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
868 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
869
870 if (def != data)
871 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
872}
873
874static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
875 bool enable)
876{
877 uint32_t data;
878
879 /* Put DF on broadcast mode */
880 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
881 data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
882 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
883
884 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
885 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
886 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
887 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
888 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
889 } else {
890 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
891 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
892 data |= DF_MGCG_DISABLE;
893 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
894 }
895
896 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
897 mmFabricConfigAccessControl_DEFAULT);
898}
899
900static int soc15_common_set_clockgating_state(void *handle,
901 enum amd_clockgating_state state)
902{
903 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
904
905 if (amdgpu_sriov_vf(adev))
906 return 0;
907
908 switch (adev->asic_type) {
909 case CHIP_VEGA10:
910 case CHIP_VEGA12:
911 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
912 state == AMD_CG_STATE_GATE ? true : false);
913 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
914 state == AMD_CG_STATE_GATE ? true : false);
915 soc15_update_hdp_light_sleep(adev,
916 state == AMD_CG_STATE_GATE ? true : false);
917 soc15_update_drm_clock_gating(adev,
918 state == AMD_CG_STATE_GATE ? true : false);
919 soc15_update_drm_light_sleep(adev,
920 state == AMD_CG_STATE_GATE ? true : false);
921 soc15_update_rom_medium_grain_clock_gating(adev,
922 state == AMD_CG_STATE_GATE ? true : false);
923 soc15_update_df_medium_grain_clock_gating(adev,
924 state == AMD_CG_STATE_GATE ? true : false);
925 break;
926 case CHIP_RAVEN:
927 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
928 state == AMD_CG_STATE_GATE ? true : false);
929 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
930 state == AMD_CG_STATE_GATE ? true : false);
931 soc15_update_hdp_light_sleep(adev,
932 state == AMD_CG_STATE_GATE ? true : false);
933 soc15_update_drm_clock_gating(adev,
934 state == AMD_CG_STATE_GATE ? true : false);
935 soc15_update_drm_light_sleep(adev,
936 state == AMD_CG_STATE_GATE ? true : false);
937 soc15_update_rom_medium_grain_clock_gating(adev,
938 state == AMD_CG_STATE_GATE ? true : false);
939 break;
940 default:
941 break;
942 }
943 return 0;
944}
945
946static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
947{
948 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
949 int data;
950
951 if (amdgpu_sriov_vf(adev))
952 *flags = 0;
953
954 adev->nbio_funcs->get_clockgating_state(adev, flags);
955
956 /* AMD_CG_SUPPORT_HDP_LS */
957 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
958 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
959 *flags |= AMD_CG_SUPPORT_HDP_LS;
960
961 /* AMD_CG_SUPPORT_DRM_MGCG */
962 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
963 if (!(data & 0x01000000))
964 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
965
966 /* AMD_CG_SUPPORT_DRM_LS */
967 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
968 if (data & 0x1)
969 *flags |= AMD_CG_SUPPORT_DRM_LS;
970
971 /* AMD_CG_SUPPORT_ROM_MGCG */
972 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
973 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
974 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
975
976 /* AMD_CG_SUPPORT_DF_MGCG */
977 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
978 if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
979 *flags |= AMD_CG_SUPPORT_DF_MGCG;
980}
981
982static int soc15_common_set_powergating_state(void *handle,
983 enum amd_powergating_state state)
984{
985 /* todo */
986 return 0;
987}
988
989const struct amd_ip_funcs soc15_common_ip_funcs = {
990 .name = "soc15_common",
991 .early_init = soc15_common_early_init,
992 .late_init = soc15_common_late_init,
993 .sw_init = soc15_common_sw_init,
994 .sw_fini = soc15_common_sw_fini,
995 .hw_init = soc15_common_hw_init,
996 .hw_fini = soc15_common_hw_fini,
997 .suspend = soc15_common_suspend,
998 .resume = soc15_common_resume,
999 .is_idle = soc15_common_is_idle,
1000 .wait_for_idle = soc15_common_wait_for_idle,
1001 .soft_reset = soc15_common_soft_reset,
1002 .set_clockgating_state = soc15_common_set_clockgating_state,
1003 .set_powergating_state = soc15_common_set_powergating_state,
1004 .get_clockgating_state= soc15_common_get_clockgating_state,
1005};