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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/atomic.h>
12#include <linux/bitmap.h>
13#include <linux/cleanup.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/mod_devicetable.h>
21#include <linux/module.h>
22#include <linux/mutex.h>
23#include <linux/pm.h>
24#include <linux/regmap.h>
25#include <linux/regulator/consumer.h>
26#include <linux/seq_file.h>
27#include <linux/slab.h>
28
29#include <linux/gpio/consumer.h>
30#include <linux/gpio/driver.h>
31
32#include <linux/pinctrl/pinconf-generic.h>
33
34#include <linux/platform_data/pca953x.h>
35
36#define PCA953X_INPUT 0x00
37#define PCA953X_OUTPUT 0x01
38#define PCA953X_INVERT 0x02
39#define PCA953X_DIRECTION 0x03
40
41#define REG_ADDR_MASK GENMASK(5, 0)
42#define REG_ADDR_EXT BIT(6)
43#define REG_ADDR_AI BIT(7)
44
45#define PCA957X_IN 0x00
46#define PCA957X_INVRT 0x01
47#define PCA957X_BKEN 0x02
48#define PCA957X_PUPD 0x03
49#define PCA957X_CFG 0x04
50#define PCA957X_OUT 0x05
51#define PCA957X_MSK 0x06
52#define PCA957X_INTS 0x07
53
54#define PCAL953X_OUT_STRENGTH 0x20
55#define PCAL953X_IN_LATCH 0x22
56#define PCAL953X_PULL_EN 0x23
57#define PCAL953X_PULL_SEL 0x24
58#define PCAL953X_INT_MASK 0x25
59#define PCAL953X_INT_STAT 0x26
60#define PCAL953X_OUT_CONF 0x27
61
62#define PCAL6524_INT_EDGE 0x28
63#define PCAL6524_INT_CLR 0x2a
64#define PCAL6524_IN_STATUS 0x2b
65#define PCAL6524_OUT_INDCONF 0x2c
66#define PCAL6524_DEBOUNCE 0x2d
67
68#define PCA_GPIO_MASK GENMASK(7, 0)
69
70#define PCAL_GPIO_MASK GENMASK(4, 0)
71#define PCAL_PINCTRL_MASK GENMASK(6, 5)
72
73#define PCA_INT BIT(8)
74#define PCA_PCAL BIT(9)
75#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
76#define PCA953X_TYPE BIT(12)
77#define PCA957X_TYPE BIT(13)
78#define PCAL653X_TYPE BIT(14)
79#define PCA_TYPE_MASK GENMASK(15, 12)
80
81#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
82
83static const struct i2c_device_id pca953x_id[] = {
84 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
85 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
86 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
87 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
88 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
89 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
90 { "pca9536", 4 | PCA953X_TYPE, },
91 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
92 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
93 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
94 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
95 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
96 { "pca9556", 8 | PCA953X_TYPE, },
97 { "pca9557", 8 | PCA953X_TYPE, },
98 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
99 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
100 { "pca9698", 40 | PCA953X_TYPE, },
101
102 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
103 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
104 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
105 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
106 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
107 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
108 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
109
110 { "max7310", 8 | PCA953X_TYPE, },
111 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
112 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
113 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
114 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
115 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
116 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
117 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
118 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
119 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, },
120 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
121 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
122 { "xra1202", 8 | PCA953X_TYPE },
123 { }
124};
125MODULE_DEVICE_TABLE(i2c, pca953x_id);
126
127#ifdef CONFIG_GPIO_PCA953X_IRQ
128
129#include <linux/acpi.h>
130#include <linux/dmi.h>
131
132static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
133
134static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
136 { }
137};
138
139static int pca953x_acpi_get_irq(struct device *dev)
140{
141 int ret;
142
143 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
144 if (ret)
145 dev_warn(dev, "can't add GPIO ACPI mapping\n");
146
147 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);
148 if (ret < 0)
149 return ret;
150
151 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
152 return ret;
153}
154
155static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
156 {
157 /*
158 * On Intel Galileo Gen 2 board the IRQ pin of one of
159 * the I²C GPIO expanders, which has GpioInt() resource,
160 * is provided as an absolute number instead of being
161 * relative. Since first controller (gpio-sch.c) and
162 * second (gpio-dwapb.c) are at the fixed bases, we may
163 * safely refer to the number in the global space to get
164 * an IRQ out of it.
165 */
166 .matches = {
167 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
168 },
169 },
170 {}
171};
172#endif
173
174static const struct acpi_device_id pca953x_acpi_ids[] = {
175 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
176 { }
177};
178MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
179
180#define MAX_BANK 5
181#define BANK_SZ 8
182#define MAX_LINE (MAX_BANK * BANK_SZ)
183
184#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
185
186struct pca953x_reg_config {
187 int direction;
188 int output;
189 int input;
190 int invert;
191};
192
193static const struct pca953x_reg_config pca953x_regs = {
194 .direction = PCA953X_DIRECTION,
195 .output = PCA953X_OUTPUT,
196 .input = PCA953X_INPUT,
197 .invert = PCA953X_INVERT,
198};
199
200static const struct pca953x_reg_config pca957x_regs = {
201 .direction = PCA957X_CFG,
202 .output = PCA957X_OUT,
203 .input = PCA957X_IN,
204 .invert = PCA957X_INVRT,
205};
206
207struct pca953x_chip {
208 unsigned gpio_start;
209 struct mutex i2c_lock;
210 struct regmap *regmap;
211
212#ifdef CONFIG_GPIO_PCA953X_IRQ
213 struct mutex irq_lock;
214 DECLARE_BITMAP(irq_mask, MAX_LINE);
215 DECLARE_BITMAP(irq_stat, MAX_LINE);
216 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
217 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
218#endif
219 atomic_t wakeup_path;
220
221 struct i2c_client *client;
222 struct gpio_chip gpio_chip;
223 unsigned long driver_data;
224 struct regulator *regulator;
225
226 const struct pca953x_reg_config *regs;
227
228 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
229 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
230 u32 checkbank);
231};
232
233static int pca953x_bank_shift(struct pca953x_chip *chip)
234{
235 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
236}
237
238#define PCA953x_BANK_INPUT BIT(0)
239#define PCA953x_BANK_OUTPUT BIT(1)
240#define PCA953x_BANK_POLARITY BIT(2)
241#define PCA953x_BANK_CONFIG BIT(3)
242
243#define PCA957x_BANK_INPUT BIT(0)
244#define PCA957x_BANK_POLARITY BIT(1)
245#define PCA957x_BANK_BUSHOLD BIT(2)
246#define PCA957x_BANK_CONFIG BIT(4)
247#define PCA957x_BANK_OUTPUT BIT(5)
248
249#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
250#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
251#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
252#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
253#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
254
255/*
256 * We care about the following registers:
257 * - Standard set, below 0x40, each port can be replicated up to 8 times
258 * - PCA953x standard
259 * Input port 0x00 + 0 * bank_size R
260 * Output port 0x00 + 1 * bank_size RW
261 * Polarity Inversion port 0x00 + 2 * bank_size RW
262 * Configuration port 0x00 + 3 * bank_size RW
263 * - PCA957x with mixed up registers
264 * Input port 0x00 + 0 * bank_size R
265 * Polarity Inversion port 0x00 + 1 * bank_size RW
266 * Bus hold port 0x00 + 2 * bank_size RW
267 * Configuration port 0x00 + 4 * bank_size RW
268 * Output port 0x00 + 5 * bank_size RW
269 *
270 * - Extended set, above 0x40, often chip specific.
271 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
272 * Input latch register 0x40 + 2 * bank_size RW
273 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
274 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
275 * Interrupt mask register 0x40 + 5 * bank_size RW
276 * Interrupt status register 0x40 + 6 * bank_size R
277 *
278 * - Registers with bit 0x80 set, the AI bit
279 * The bit is cleared and the registers fall into one of the
280 * categories above.
281 */
282
283static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
284 u32 checkbank)
285{
286 int bank_shift = pca953x_bank_shift(chip);
287 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
288 int offset = reg & (BIT(bank_shift) - 1);
289
290 /* Special PCAL extended register check. */
291 if (reg & REG_ADDR_EXT) {
292 if (!(chip->driver_data & PCA_PCAL))
293 return false;
294 bank += 8;
295 }
296
297 /* Register is not in the matching bank. */
298 if (!(BIT(bank) & checkbank))
299 return false;
300
301 /* Register is not within allowed range of bank. */
302 if (offset >= NBANK(chip))
303 return false;
304
305 return true;
306}
307
308/*
309 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
310 * same register layout as the PCAL6524, the spacing of the registers has been
311 * fundamentally altered by compacting them and thus does not obey the same
312 * rules, including being able to use bit shifting to determine bank. These
313 * chips hence need special handling here.
314 */
315static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
316 u32 checkbank)
317{
318 int bank_shift;
319 int bank;
320 int offset;
321
322 if (reg >= 0x54) {
323 /*
324 * Handle lack of reserved registers after output port
325 * configuration register to form a bank.
326 */
327 reg -= 0x54;
328 bank_shift = 16;
329 } else if (reg >= 0x30) {
330 /*
331 * Reserved block between 14h and 2Fh does not align on
332 * expected bank boundaries like other devices.
333 */
334 reg -= 0x30;
335 bank_shift = 8;
336 } else {
337 bank_shift = 0;
338 }
339
340 bank = bank_shift + reg / NBANK(chip);
341 offset = reg % NBANK(chip);
342
343 /* Register is not in the matching bank. */
344 if (!(BIT(bank) & checkbank))
345 return false;
346
347 /* Register is not within allowed range of bank. */
348 if (offset >= NBANK(chip))
349 return false;
350
351 return true;
352}
353
354static bool pca953x_readable_register(struct device *dev, unsigned int reg)
355{
356 struct pca953x_chip *chip = dev_get_drvdata(dev);
357 u32 bank;
358
359 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
360 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
361 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
362 PCA957x_BANK_BUSHOLD;
363 } else {
364 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
365 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
366 }
367
368 if (chip->driver_data & PCA_PCAL) {
369 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
370 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
371 PCAL9xxx_BANK_IRQ_STAT;
372 }
373
374 return chip->check_reg(chip, reg, bank);
375}
376
377static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
378{
379 struct pca953x_chip *chip = dev_get_drvdata(dev);
380 u32 bank;
381
382 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
383 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
384 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
385 } else {
386 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
387 PCA953x_BANK_CONFIG;
388 }
389
390 if (chip->driver_data & PCA_PCAL)
391 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
392 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
393
394 return chip->check_reg(chip, reg, bank);
395}
396
397static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
398{
399 struct pca953x_chip *chip = dev_get_drvdata(dev);
400 u32 bank;
401
402 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
403 bank = PCA957x_BANK_INPUT;
404 else
405 bank = PCA953x_BANK_INPUT;
406
407 if (chip->driver_data & PCA_PCAL)
408 bank |= PCAL9xxx_BANK_IRQ_STAT;
409
410 return chip->check_reg(chip, reg, bank);
411}
412
413static const struct regmap_config pca953x_i2c_regmap = {
414 .reg_bits = 8,
415 .val_bits = 8,
416
417 .use_single_read = true,
418 .use_single_write = true,
419
420 .readable_reg = pca953x_readable_register,
421 .writeable_reg = pca953x_writeable_register,
422 .volatile_reg = pca953x_volatile_register,
423
424 .disable_locking = true,
425 .cache_type = REGCACHE_MAPLE,
426 .max_register = 0x7f,
427};
428
429static const struct regmap_config pca953x_ai_i2c_regmap = {
430 .reg_bits = 8,
431 .val_bits = 8,
432
433 .read_flag_mask = REG_ADDR_AI,
434 .write_flag_mask = REG_ADDR_AI,
435
436 .readable_reg = pca953x_readable_register,
437 .writeable_reg = pca953x_writeable_register,
438 .volatile_reg = pca953x_volatile_register,
439
440 .disable_locking = true,
441 .cache_type = REGCACHE_MAPLE,
442 .max_register = 0x7f,
443};
444
445static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
446{
447 int bank_shift = pca953x_bank_shift(chip);
448 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
449 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
450 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
451
452 return regaddr;
453}
454
455/*
456 * The PCAL6534 and compatible chips have altered bank alignment that doesn't
457 * fit within the bit shifting scheme used for other devices.
458 */
459static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
460{
461 int addr;
462 int pinctrl;
463
464 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
465
466 switch (reg) {
467 case PCAL953X_OUT_STRENGTH:
468 case PCAL953X_IN_LATCH:
469 case PCAL953X_PULL_EN:
470 case PCAL953X_PULL_SEL:
471 case PCAL953X_INT_MASK:
472 case PCAL953X_INT_STAT:
473 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
474 break;
475 case PCAL6524_INT_EDGE:
476 case PCAL6524_INT_CLR:
477 case PCAL6524_IN_STATUS:
478 case PCAL6524_OUT_INDCONF:
479 case PCAL6524_DEBOUNCE:
480 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
481 break;
482 default:
483 pinctrl = 0;
484 break;
485 }
486
487 return pinctrl + addr + (off / BANK_SZ);
488}
489
490static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
491{
492 u8 regaddr = chip->recalc_addr(chip, reg, 0);
493 u8 value[MAX_BANK];
494 int i, ret;
495
496 for (i = 0; i < NBANK(chip); i++)
497 value[i] = bitmap_get_value8(val, i * BANK_SZ);
498
499 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
500 if (ret < 0) {
501 dev_err(&chip->client->dev, "failed writing register: %d\n", ret);
502 return ret;
503 }
504
505 return 0;
506}
507
508static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
509{
510 u8 regaddr = chip->recalc_addr(chip, reg, 0);
511 u8 value[MAX_BANK];
512 int i, ret;
513
514 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
515 if (ret < 0) {
516 dev_err(&chip->client->dev, "failed reading register: %d\n", ret);
517 return ret;
518 }
519
520 for (i = 0; i < NBANK(chip); i++)
521 bitmap_set_value8(val, value[i], i * BANK_SZ);
522
523 return 0;
524}
525
526static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
527{
528 struct pca953x_chip *chip = gpiochip_get_data(gc);
529 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
530 u8 bit = BIT(off % BANK_SZ);
531
532 guard(mutex)(&chip->i2c_lock);
533
534 return regmap_write_bits(chip->regmap, dirreg, bit, bit);
535}
536
537static int pca953x_gpio_direction_output(struct gpio_chip *gc,
538 unsigned off, int val)
539{
540 struct pca953x_chip *chip = gpiochip_get_data(gc);
541 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
542 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
543 u8 bit = BIT(off % BANK_SZ);
544 int ret;
545
546 guard(mutex)(&chip->i2c_lock);
547
548 /* set output level */
549 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
550 if (ret)
551 return ret;
552
553 /* then direction */
554 return regmap_write_bits(chip->regmap, dirreg, bit, 0);
555}
556
557static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
558{
559 struct pca953x_chip *chip = gpiochip_get_data(gc);
560 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
561 u8 bit = BIT(off % BANK_SZ);
562 u32 reg_val;
563 int ret;
564
565 scoped_guard(mutex, &chip->i2c_lock)
566 ret = regmap_read(chip->regmap, inreg, ®_val);
567 if (ret < 0)
568 return ret;
569
570 return !!(reg_val & bit);
571}
572
573static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
574{
575 struct pca953x_chip *chip = gpiochip_get_data(gc);
576 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
577 u8 bit = BIT(off % BANK_SZ);
578
579 guard(mutex)(&chip->i2c_lock);
580
581 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
582}
583
584static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
585{
586 struct pca953x_chip *chip = gpiochip_get_data(gc);
587 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
588 u8 bit = BIT(off % BANK_SZ);
589 u32 reg_val;
590 int ret;
591
592 scoped_guard(mutex, &chip->i2c_lock)
593 ret = regmap_read(chip->regmap, dirreg, ®_val);
594 if (ret < 0)
595 return ret;
596
597 if (reg_val & bit)
598 return GPIO_LINE_DIRECTION_IN;
599
600 return GPIO_LINE_DIRECTION_OUT;
601}
602
603static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
604 unsigned long *mask, unsigned long *bits)
605{
606 struct pca953x_chip *chip = gpiochip_get_data(gc);
607 DECLARE_BITMAP(reg_val, MAX_LINE);
608 int ret;
609
610 scoped_guard(mutex, &chip->i2c_lock)
611 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
612 if (ret)
613 return ret;
614
615 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
616 return 0;
617}
618
619static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
620 unsigned long *mask, unsigned long *bits)
621{
622 struct pca953x_chip *chip = gpiochip_get_data(gc);
623 DECLARE_BITMAP(reg_val, MAX_LINE);
624 int ret;
625
626 guard(mutex)(&chip->i2c_lock);
627
628 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
629 if (ret)
630 return;
631
632 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
633
634 pca953x_write_regs(chip, chip->regs->output, reg_val);
635}
636
637static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
638 unsigned int offset,
639 unsigned long config)
640{
641 enum pin_config_param param = pinconf_to_config_param(config);
642 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
643 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
644 u8 bit = BIT(offset % BANK_SZ);
645 int ret;
646
647 /*
648 * pull-up/pull-down configuration requires PCAL extended
649 * registers
650 */
651 if (!(chip->driver_data & PCA_PCAL))
652 return -ENOTSUPP;
653
654 guard(mutex)(&chip->i2c_lock);
655
656 /* Configure pull-up/pull-down */
657 if (param == PIN_CONFIG_BIAS_PULL_UP)
658 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
659 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
660 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
661 else
662 ret = 0;
663 if (ret)
664 return ret;
665
666 /* Disable/Enable pull-up/pull-down */
667 if (param == PIN_CONFIG_BIAS_DISABLE)
668 return regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
669 else
670 return regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
671}
672
673static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
674 unsigned long config)
675{
676 struct pca953x_chip *chip = gpiochip_get_data(gc);
677
678 switch (pinconf_to_config_param(config)) {
679 case PIN_CONFIG_BIAS_PULL_UP:
680 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
681 case PIN_CONFIG_BIAS_PULL_DOWN:
682 case PIN_CONFIG_BIAS_DISABLE:
683 return pca953x_gpio_set_pull_up_down(chip, offset, config);
684 default:
685 return -ENOTSUPP;
686 }
687}
688
689static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
690{
691 struct gpio_chip *gc = &chip->gpio_chip;
692
693 gc->direction_input = pca953x_gpio_direction_input;
694 gc->direction_output = pca953x_gpio_direction_output;
695 gc->get = pca953x_gpio_get_value;
696 gc->set = pca953x_gpio_set_value;
697 gc->get_direction = pca953x_gpio_get_direction;
698 gc->get_multiple = pca953x_gpio_get_multiple;
699 gc->set_multiple = pca953x_gpio_set_multiple;
700 gc->set_config = pca953x_gpio_set_config;
701 gc->can_sleep = true;
702
703 gc->base = chip->gpio_start;
704 gc->ngpio = gpios;
705 gc->label = dev_name(&chip->client->dev);
706 gc->parent = &chip->client->dev;
707 gc->owner = THIS_MODULE;
708}
709
710#ifdef CONFIG_GPIO_PCA953X_IRQ
711static void pca953x_irq_mask(struct irq_data *d)
712{
713 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
714 struct pca953x_chip *chip = gpiochip_get_data(gc);
715 irq_hw_number_t hwirq = irqd_to_hwirq(d);
716
717 clear_bit(hwirq, chip->irq_mask);
718 gpiochip_disable_irq(gc, hwirq);
719}
720
721static void pca953x_irq_unmask(struct irq_data *d)
722{
723 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
724 struct pca953x_chip *chip = gpiochip_get_data(gc);
725 irq_hw_number_t hwirq = irqd_to_hwirq(d);
726
727 gpiochip_enable_irq(gc, hwirq);
728 set_bit(hwirq, chip->irq_mask);
729}
730
731static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
732{
733 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
734 struct pca953x_chip *chip = gpiochip_get_data(gc);
735
736 if (on)
737 atomic_inc(&chip->wakeup_path);
738 else
739 atomic_dec(&chip->wakeup_path);
740
741 return irq_set_irq_wake(chip->client->irq, on);
742}
743
744static void pca953x_irq_bus_lock(struct irq_data *d)
745{
746 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
747 struct pca953x_chip *chip = gpiochip_get_data(gc);
748
749 mutex_lock(&chip->irq_lock);
750}
751
752static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
753{
754 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
755 struct pca953x_chip *chip = gpiochip_get_data(gc);
756 DECLARE_BITMAP(irq_mask, MAX_LINE);
757 DECLARE_BITMAP(reg_direction, MAX_LINE);
758 int level;
759
760 if (chip->driver_data & PCA_PCAL) {
761 guard(mutex)(&chip->i2c_lock);
762
763 /* Enable latch on interrupt-enabled inputs */
764 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
765
766 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
767
768 /* Unmask enabled interrupts */
769 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
770 }
771
772 /* Switch direction to input if needed */
773 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
774
775 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
776 bitmap_complement(reg_direction, reg_direction, gc->ngpio);
777 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
778
779 /* Look for any newly setup interrupt */
780 for_each_set_bit(level, irq_mask, gc->ngpio)
781 pca953x_gpio_direction_input(&chip->gpio_chip, level);
782
783 mutex_unlock(&chip->irq_lock);
784}
785
786static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
787{
788 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
789 struct pca953x_chip *chip = gpiochip_get_data(gc);
790 struct device *dev = &chip->client->dev;
791 irq_hw_number_t hwirq = irqd_to_hwirq(d);
792
793 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
794 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type);
795 return -EINVAL;
796 }
797
798 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
799 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
800
801 return 0;
802}
803
804static void pca953x_irq_shutdown(struct irq_data *d)
805{
806 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
807 struct pca953x_chip *chip = gpiochip_get_data(gc);
808 irq_hw_number_t hwirq = irqd_to_hwirq(d);
809
810 clear_bit(hwirq, chip->irq_trig_raise);
811 clear_bit(hwirq, chip->irq_trig_fall);
812}
813
814static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
815{
816 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
817
818 seq_puts(p, dev_name(gc->parent));
819}
820
821static const struct irq_chip pca953x_irq_chip = {
822 .irq_mask = pca953x_irq_mask,
823 .irq_unmask = pca953x_irq_unmask,
824 .irq_set_wake = pca953x_irq_set_wake,
825 .irq_bus_lock = pca953x_irq_bus_lock,
826 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
827 .irq_set_type = pca953x_irq_set_type,
828 .irq_shutdown = pca953x_irq_shutdown,
829 .irq_print_chip = pca953x_irq_print_chip,
830 .flags = IRQCHIP_IMMUTABLE,
831 GPIOCHIP_IRQ_RESOURCE_HELPERS,
832};
833
834static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
835{
836 struct gpio_chip *gc = &chip->gpio_chip;
837 DECLARE_BITMAP(reg_direction, MAX_LINE);
838 DECLARE_BITMAP(old_stat, MAX_LINE);
839 DECLARE_BITMAP(cur_stat, MAX_LINE);
840 DECLARE_BITMAP(new_stat, MAX_LINE);
841 DECLARE_BITMAP(trigger, MAX_LINE);
842 int ret;
843
844 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
845 if (ret)
846 return false;
847
848 /* Remove output pins from the equation */
849 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
850
851 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
852
853 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
854 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
855 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
856
857 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
858
859 if (bitmap_empty(trigger, gc->ngpio))
860 return false;
861
862 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
863 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
864 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
865 bitmap_and(pending, new_stat, trigger, gc->ngpio);
866
867 return !bitmap_empty(pending, gc->ngpio);
868}
869
870static irqreturn_t pca953x_irq_handler(int irq, void *devid)
871{
872 struct pca953x_chip *chip = devid;
873 struct gpio_chip *gc = &chip->gpio_chip;
874 DECLARE_BITMAP(pending, MAX_LINE);
875 int level;
876 bool ret;
877
878 bitmap_zero(pending, MAX_LINE);
879
880 scoped_guard(mutex, &chip->i2c_lock)
881 ret = pca953x_irq_pending(chip, pending);
882 if (ret) {
883 ret = 0;
884
885 for_each_set_bit(level, pending, gc->ngpio) {
886 int nested_irq = irq_find_mapping(gc->irq.domain, level);
887
888 if (unlikely(nested_irq <= 0)) {
889 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
890 continue;
891 }
892
893 handle_nested_irq(nested_irq);
894 ret = 1;
895 }
896 }
897
898 return IRQ_RETVAL(ret);
899}
900
901static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
902{
903 struct i2c_client *client = chip->client;
904 struct device *dev = &client->dev;
905 DECLARE_BITMAP(reg_direction, MAX_LINE);
906 DECLARE_BITMAP(irq_stat, MAX_LINE);
907 struct gpio_chip *gc = &chip->gpio_chip;
908 struct gpio_irq_chip *girq;
909 int ret;
910
911 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
912 ret = pca953x_acpi_get_irq(dev);
913 if (ret > 0)
914 client->irq = ret;
915 }
916
917 if (!client->irq)
918 return 0;
919
920 if (irq_base == -1)
921 return 0;
922
923 if (!(chip->driver_data & PCA_INT))
924 return 0;
925
926 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
927 if (ret)
928 return ret;
929
930 /*
931 * There is no way to know which GPIO line generated the
932 * interrupt. We have to rely on the previous read for
933 * this purpose.
934 */
935 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
936 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio);
937 mutex_init(&chip->irq_lock);
938
939 girq = &chip->gpio_chip.irq;
940 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);
941 /* This will let us handle the parent IRQ in the driver */
942 girq->parent_handler = NULL;
943 girq->num_parents = 0;
944 girq->parents = NULL;
945 girq->default_type = IRQ_TYPE_NONE;
946 girq->handler = handle_simple_irq;
947 girq->threaded = true;
948 girq->first = irq_base; /* FIXME: get rid of this */
949
950 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler,
951 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev),
952 chip);
953 if (ret)
954 return dev_err_probe(dev, client->irq, "failed to request irq\n");
955
956 return 0;
957}
958
959#else /* CONFIG_GPIO_PCA953X_IRQ */
960static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
961{
962 struct i2c_client *client = chip->client;
963 struct device *dev = &client->dev;
964
965 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
966 dev_warn(dev, "interrupt support not compiled in\n");
967
968 return 0;
969}
970#endif
971
972static int device_pca95xx_init(struct pca953x_chip *chip)
973{
974 DECLARE_BITMAP(val, MAX_LINE);
975 u8 regaddr;
976 int ret;
977
978 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
979 ret = regcache_sync_region(chip->regmap, regaddr,
980 regaddr + NBANK(chip) - 1);
981 if (ret)
982 return ret;
983
984 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
985 ret = regcache_sync_region(chip->regmap, regaddr,
986 regaddr + NBANK(chip) - 1);
987 if (ret)
988 return ret;
989
990 /* clear polarity inversion */
991 bitmap_zero(val, MAX_LINE);
992
993 return pca953x_write_regs(chip, chip->regs->invert, val);
994}
995
996static int device_pca957x_init(struct pca953x_chip *chip)
997{
998 DECLARE_BITMAP(val, MAX_LINE);
999 unsigned int i;
1000 int ret;
1001
1002 ret = device_pca95xx_init(chip);
1003 if (ret)
1004 return ret;
1005
1006 /* To enable register 6, 7 to control pull up and pull down */
1007 for (i = 0; i < NBANK(chip); i++)
1008 bitmap_set_value8(val, 0x02, i * BANK_SZ);
1009
1010 return pca953x_write_regs(chip, PCA957X_BKEN, val);
1011}
1012
1013static void pca953x_disable_regulator(void *reg)
1014{
1015 regulator_disable(reg);
1016}
1017
1018static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip)
1019{
1020 struct device *dev = &chip->client->dev;
1021 struct regulator *reg = chip->regulator;
1022 int ret;
1023
1024 reg = devm_regulator_get(dev, "vcc");
1025 if (IS_ERR(reg))
1026 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n");
1027
1028 ret = regulator_enable(reg);
1029 if (ret)
1030 return dev_err_probe(dev, ret, "reg en err\n");
1031
1032 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg);
1033 if (ret)
1034 return ret;
1035
1036 chip->regulator = reg;
1037 return 0;
1038}
1039
1040static int pca953x_probe(struct i2c_client *client)
1041{
1042 struct device *dev = &client->dev;
1043 struct pca953x_platform_data *pdata;
1044 struct pca953x_chip *chip;
1045 int irq_base;
1046 int ret;
1047 const struct regmap_config *regmap_config;
1048
1049 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1050 if (chip == NULL)
1051 return -ENOMEM;
1052
1053 pdata = dev_get_platdata(dev);
1054 if (pdata) {
1055 irq_base = pdata->irq_base;
1056 chip->gpio_start = pdata->gpio_base;
1057 } else {
1058 struct gpio_desc *reset_gpio;
1059
1060 chip->gpio_start = -1;
1061 irq_base = 0;
1062
1063 /*
1064 * See if we need to de-assert a reset pin.
1065 *
1066 * There is no known ACPI-enabled platforms that are
1067 * using "reset" GPIO. Otherwise any of those platform
1068 * must use _DSD method with corresponding property.
1069 */
1070 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1071 if (IS_ERR(reset_gpio))
1072 return dev_err_probe(dev, PTR_ERR(reset_gpio),
1073 "Failed to get reset gpio\n");
1074 }
1075
1076 chip->client = client;
1077 chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1078 if (!chip->driver_data)
1079 return -ENODEV;
1080
1081 ret = pca953x_get_and_enable_regulator(chip);
1082 if (ret)
1083 return ret;
1084
1085 i2c_set_clientdata(client, chip);
1086
1087 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1088
1089 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1090 dev_info(dev, "using AI\n");
1091 regmap_config = &pca953x_ai_i2c_regmap;
1092 } else {
1093 dev_info(dev, "using no AI\n");
1094 regmap_config = &pca953x_i2c_regmap;
1095 }
1096
1097 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
1098 chip->recalc_addr = pcal6534_recalc_addr;
1099 chip->check_reg = pcal6534_check_register;
1100 } else {
1101 chip->recalc_addr = pca953x_recalc_addr;
1102 chip->check_reg = pca953x_check_register;
1103 }
1104
1105 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1106 if (IS_ERR(chip->regmap))
1107 return PTR_ERR(chip->regmap);
1108
1109 regcache_mark_dirty(chip->regmap);
1110
1111 mutex_init(&chip->i2c_lock);
1112 /*
1113 * In case we have an i2c-mux controlled by a GPIO provided by an
1114 * expander using the same driver higher on the device tree, read the
1115 * i2c adapter nesting depth and use the retrieved value as lockdep
1116 * subclass for chip->i2c_lock.
1117 *
1118 * REVISIT: This solution is not complete. It protects us from lockdep
1119 * false positives when the expander controlling the i2c-mux is on
1120 * a different level on the device tree, but not when it's on the same
1121 * level on a different branch (in which case the subclass number
1122 * would be the same).
1123 *
1124 * TODO: Once a correct solution is developed, a similar fix should be
1125 * applied to all other i2c-controlled GPIO expanders (and potentially
1126 * regmap-i2c).
1127 */
1128 lockdep_set_subclass(&chip->i2c_lock,
1129 i2c_adapter_depth(client->adapter));
1130
1131 /* initialize cached registers from their original values.
1132 * we can't share this chip with another i2c master.
1133 */
1134 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1135 chip->regs = &pca957x_regs;
1136 ret = device_pca957x_init(chip);
1137 } else {
1138 chip->regs = &pca953x_regs;
1139 ret = device_pca95xx_init(chip);
1140 }
1141 if (ret)
1142 return ret;
1143
1144 ret = pca953x_irq_setup(chip, irq_base);
1145 if (ret)
1146 return ret;
1147
1148 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);
1149}
1150
1151static int pca953x_regcache_sync(struct pca953x_chip *chip)
1152{
1153 struct device *dev = &chip->client->dev;
1154 int ret;
1155 u8 regaddr;
1156
1157 /*
1158 * The ordering between direction and output is important,
1159 * sync these registers first and only then sync the rest.
1160 */
1161 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1162 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1163 if (ret) {
1164 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1165 return ret;
1166 }
1167
1168 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1169 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1170 if (ret) {
1171 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1172 return ret;
1173 }
1174
1175#ifdef CONFIG_GPIO_PCA953X_IRQ
1176 if (chip->driver_data & PCA_PCAL) {
1177 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
1178 ret = regcache_sync_region(chip->regmap, regaddr,
1179 regaddr + NBANK(chip) - 1);
1180 if (ret) {
1181 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1182 ret);
1183 return ret;
1184 }
1185
1186 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
1187 ret = regcache_sync_region(chip->regmap, regaddr,
1188 regaddr + NBANK(chip) - 1);
1189 if (ret) {
1190 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1191 ret);
1192 return ret;
1193 }
1194 }
1195#endif
1196
1197 return 0;
1198}
1199
1200static int pca953x_restore_context(struct pca953x_chip *chip)
1201{
1202 int ret;
1203
1204 guard(mutex)(&chip->i2c_lock);
1205
1206 regcache_cache_only(chip->regmap, false);
1207 regcache_mark_dirty(chip->regmap);
1208 ret = pca953x_regcache_sync(chip);
1209 if (ret)
1210 return ret;
1211
1212 return regcache_sync(chip->regmap);
1213}
1214
1215static void pca953x_save_context(struct pca953x_chip *chip)
1216{
1217 guard(mutex)(&chip->i2c_lock);
1218 regcache_cache_only(chip->regmap, true);
1219}
1220
1221static int pca953x_suspend(struct device *dev)
1222{
1223 struct pca953x_chip *chip = dev_get_drvdata(dev);
1224
1225 pca953x_save_context(chip);
1226
1227 if (atomic_read(&chip->wakeup_path))
1228 device_set_wakeup_path(dev);
1229 else
1230 regulator_disable(chip->regulator);
1231
1232 return 0;
1233}
1234
1235static int pca953x_resume(struct device *dev)
1236{
1237 struct pca953x_chip *chip = dev_get_drvdata(dev);
1238 int ret;
1239
1240 if (!atomic_read(&chip->wakeup_path)) {
1241 ret = regulator_enable(chip->regulator);
1242 if (ret) {
1243 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1244 return 0;
1245 }
1246 }
1247
1248 ret = pca953x_restore_context(chip);
1249 if (ret)
1250 dev_err(dev, "Failed to restore register map: %d\n", ret);
1251
1252 return ret;
1253}
1254
1255static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1256
1257/* convenience to stop overlong match-table lines */
1258#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
1259#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1260#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1261
1262static const struct of_device_id pca953x_dt_ids[] = {
1263 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
1264 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1265 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1266 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1267 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1268 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1269 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1270 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1271 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1272 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1273 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1274 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1275 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1276 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1277 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1278 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1279 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1280
1281 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
1282 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1283 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1284 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
1285 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1286 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1287 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1288
1289 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1290 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1291 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1292 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1293 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1294
1295 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1296 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1297 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1298 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1299 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1300 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), },
1301 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },
1302 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1303
1304 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1305 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1306 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
1307
1308 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1309 { }
1310};
1311
1312MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1313
1314static struct i2c_driver pca953x_driver = {
1315 .driver = {
1316 .name = "pca953x",
1317 .pm = pm_sleep_ptr(&pca953x_pm_ops),
1318 .of_match_table = pca953x_dt_ids,
1319 .acpi_match_table = pca953x_acpi_ids,
1320 },
1321 .probe = pca953x_probe,
1322 .id_table = pca953x_id,
1323};
1324
1325static int __init pca953x_init(void)
1326{
1327 return i2c_add_driver(&pca953x_driver);
1328}
1329/* register after i2c postcore initcall and before
1330 * subsys initcalls that may rely on these GPIOs
1331 */
1332subsys_initcall(pca953x_init);
1333
1334static void __exit pca953x_exit(void)
1335{
1336 i2c_del_driver(&pca953x_driver);
1337}
1338module_exit(pca953x_exit);
1339
1340MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1341MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1342MODULE_LICENSE("GPL");
1/*
2 * PCA953x 4/8/16/24/40 bit I/O ports
3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/acpi.h>
15#include <linux/gpio.h>
16#include <linux/gpio/consumer.h>
17#include <linux/i2c.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/of_platform.h>
22#include <linux/platform_data/pca953x.h>
23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25
26#include <asm/unaligned.h>
27
28#define PCA953X_INPUT 0
29#define PCA953X_OUTPUT 1
30#define PCA953X_INVERT 2
31#define PCA953X_DIRECTION 3
32
33#define REG_ADDR_AI 0x80
34
35#define PCA957X_IN 0
36#define PCA957X_INVRT 1
37#define PCA957X_BKEN 2
38#define PCA957X_PUPD 3
39#define PCA957X_CFG 4
40#define PCA957X_OUT 5
41#define PCA957X_MSK 6
42#define PCA957X_INTS 7
43
44#define PCAL953X_IN_LATCH 34
45#define PCAL953X_INT_MASK 37
46#define PCAL953X_INT_STAT 38
47
48#define PCA_GPIO_MASK 0x00FF
49#define PCA_INT 0x0100
50#define PCA_PCAL 0x0200
51#define PCA953X_TYPE 0x1000
52#define PCA957X_TYPE 0x2000
53#define PCA_TYPE_MASK 0xF000
54
55#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
56
57static const struct i2c_device_id pca953x_id[] = {
58 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
59 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
60 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
61 { "pca9536", 4 | PCA953X_TYPE, },
62 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
63 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
64 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
65 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
66 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
67 { "pca9556", 8 | PCA953X_TYPE, },
68 { "pca9557", 8 | PCA953X_TYPE, },
69 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
70 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
71 { "pca9698", 40 | PCA953X_TYPE, },
72
73 { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
74 { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
75
76 { "max7310", 8 | PCA953X_TYPE, },
77 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
78 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
79 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
80 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
81 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
82 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
83 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
84 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
85 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
86 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
87 { "xra1202", 8 | PCA953X_TYPE },
88 { }
89};
90MODULE_DEVICE_TABLE(i2c, pca953x_id);
91
92static const struct acpi_device_id pca953x_acpi_ids[] = {
93 { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
94 { }
95};
96MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
97
98#define MAX_BANK 5
99#define BANK_SZ 8
100
101#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
102
103struct pca953x_reg_config {
104 int direction;
105 int output;
106 int input;
107};
108
109static const struct pca953x_reg_config pca953x_regs = {
110 .direction = PCA953X_DIRECTION,
111 .output = PCA953X_OUTPUT,
112 .input = PCA953X_INPUT,
113};
114
115static const struct pca953x_reg_config pca957x_regs = {
116 .direction = PCA957X_CFG,
117 .output = PCA957X_OUT,
118 .input = PCA957X_IN,
119};
120
121struct pca953x_chip {
122 unsigned gpio_start;
123 u8 reg_output[MAX_BANK];
124 u8 reg_direction[MAX_BANK];
125 struct mutex i2c_lock;
126
127#ifdef CONFIG_GPIO_PCA953X_IRQ
128 struct mutex irq_lock;
129 u8 irq_mask[MAX_BANK];
130 u8 irq_stat[MAX_BANK];
131 u8 irq_trig_raise[MAX_BANK];
132 u8 irq_trig_fall[MAX_BANK];
133#endif
134
135 struct i2c_client *client;
136 struct gpio_chip gpio_chip;
137 const char *const *names;
138 unsigned long driver_data;
139 struct regulator *regulator;
140
141 const struct pca953x_reg_config *regs;
142
143 int (*write_regs)(struct pca953x_chip *, int, u8 *);
144 int (*read_regs)(struct pca953x_chip *, int, u8 *);
145};
146
147static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
148 int off)
149{
150 int ret;
151 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
152 int offset = off / BANK_SZ;
153
154 ret = i2c_smbus_read_byte_data(chip->client,
155 (reg << bank_shift) + offset);
156 *val = ret;
157
158 if (ret < 0) {
159 dev_err(&chip->client->dev, "failed reading register\n");
160 return ret;
161 }
162
163 return 0;
164}
165
166static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
167 int off)
168{
169 int ret;
170 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
171 int offset = off / BANK_SZ;
172
173 ret = i2c_smbus_write_byte_data(chip->client,
174 (reg << bank_shift) + offset, val);
175
176 if (ret < 0) {
177 dev_err(&chip->client->dev, "failed writing register\n");
178 return ret;
179 }
180
181 return 0;
182}
183
184static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
185{
186 return i2c_smbus_write_byte_data(chip->client, reg, *val);
187}
188
189static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
190{
191 u16 word = get_unaligned((u16 *)val);
192
193 return i2c_smbus_write_word_data(chip->client, reg << 1, word);
194}
195
196static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
197{
198 int ret;
199
200 ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]);
201 if (ret < 0)
202 return ret;
203
204 return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]);
205}
206
207static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
208{
209 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
210
211 return i2c_smbus_write_i2c_block_data(chip->client,
212 (reg << bank_shift) | REG_ADDR_AI,
213 NBANK(chip), val);
214}
215
216static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
217{
218 int ret = 0;
219
220 ret = chip->write_regs(chip, reg, val);
221 if (ret < 0) {
222 dev_err(&chip->client->dev, "failed writing register\n");
223 return ret;
224 }
225
226 return 0;
227}
228
229static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
230{
231 int ret;
232
233 ret = i2c_smbus_read_byte_data(chip->client, reg);
234 *val = ret;
235
236 return ret;
237}
238
239static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
240{
241 int ret;
242
243 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
244 put_unaligned(ret, (u16 *)val);
245
246 return ret;
247}
248
249static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
250{
251 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
252
253 return i2c_smbus_read_i2c_block_data(chip->client,
254 (reg << bank_shift) | REG_ADDR_AI,
255 NBANK(chip), val);
256}
257
258static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
259{
260 int ret;
261
262 ret = chip->read_regs(chip, reg, val);
263 if (ret < 0) {
264 dev_err(&chip->client->dev, "failed reading register\n");
265 return ret;
266 }
267
268 return 0;
269}
270
271static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
272{
273 struct pca953x_chip *chip = gpiochip_get_data(gc);
274 u8 reg_val;
275 int ret;
276
277 mutex_lock(&chip->i2c_lock);
278 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
279
280 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
281 if (ret)
282 goto exit;
283
284 chip->reg_direction[off / BANK_SZ] = reg_val;
285exit:
286 mutex_unlock(&chip->i2c_lock);
287 return ret;
288}
289
290static int pca953x_gpio_direction_output(struct gpio_chip *gc,
291 unsigned off, int val)
292{
293 struct pca953x_chip *chip = gpiochip_get_data(gc);
294 u8 reg_val;
295 int ret;
296
297 mutex_lock(&chip->i2c_lock);
298 /* set output level */
299 if (val)
300 reg_val = chip->reg_output[off / BANK_SZ]
301 | (1u << (off % BANK_SZ));
302 else
303 reg_val = chip->reg_output[off / BANK_SZ]
304 & ~(1u << (off % BANK_SZ));
305
306 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
307 if (ret)
308 goto exit;
309
310 chip->reg_output[off / BANK_SZ] = reg_val;
311
312 /* then direction */
313 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
314 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
315 if (ret)
316 goto exit;
317
318 chip->reg_direction[off / BANK_SZ] = reg_val;
319exit:
320 mutex_unlock(&chip->i2c_lock);
321 return ret;
322}
323
324static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
325{
326 struct pca953x_chip *chip = gpiochip_get_data(gc);
327 u32 reg_val;
328 int ret;
329
330 mutex_lock(&chip->i2c_lock);
331 ret = pca953x_read_single(chip, chip->regs->input, ®_val, off);
332 mutex_unlock(&chip->i2c_lock);
333 if (ret < 0) {
334 /* NOTE: diagnostic already emitted; that's all we should
335 * do unless gpio_*_value_cansleep() calls become different
336 * from their nonsleeping siblings (and report faults).
337 */
338 return 0;
339 }
340
341 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
342}
343
344static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
345{
346 struct pca953x_chip *chip = gpiochip_get_data(gc);
347 u8 reg_val;
348 int ret;
349
350 mutex_lock(&chip->i2c_lock);
351 if (val)
352 reg_val = chip->reg_output[off / BANK_SZ]
353 | (1u << (off % BANK_SZ));
354 else
355 reg_val = chip->reg_output[off / BANK_SZ]
356 & ~(1u << (off % BANK_SZ));
357
358 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
359 if (ret)
360 goto exit;
361
362 chip->reg_output[off / BANK_SZ] = reg_val;
363exit:
364 mutex_unlock(&chip->i2c_lock);
365}
366
367static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
368{
369 struct pca953x_chip *chip = gpiochip_get_data(gc);
370 u32 reg_val;
371 int ret;
372
373 mutex_lock(&chip->i2c_lock);
374 ret = pca953x_read_single(chip, chip->regs->direction, ®_val, off);
375 mutex_unlock(&chip->i2c_lock);
376 if (ret < 0)
377 return ret;
378
379 return !!(reg_val & (1u << (off % BANK_SZ)));
380}
381
382static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
383 unsigned long *mask, unsigned long *bits)
384{
385 struct pca953x_chip *chip = gpiochip_get_data(gc);
386 unsigned int bank_mask, bank_val;
387 int bank_shift, bank;
388 u8 reg_val[MAX_BANK];
389 int ret;
390
391 bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
392
393 mutex_lock(&chip->i2c_lock);
394 memcpy(reg_val, chip->reg_output, NBANK(chip));
395 for (bank = 0; bank < NBANK(chip); bank++) {
396 bank_mask = mask[bank / sizeof(*mask)] >>
397 ((bank % sizeof(*mask)) * 8);
398 if (bank_mask) {
399 bank_val = bits[bank / sizeof(*bits)] >>
400 ((bank % sizeof(*bits)) * 8);
401 bank_val &= bank_mask;
402 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
403 }
404 }
405
406 ret = i2c_smbus_write_i2c_block_data(chip->client,
407 chip->regs->output << bank_shift,
408 NBANK(chip), reg_val);
409 if (ret)
410 goto exit;
411
412 memcpy(chip->reg_output, reg_val, NBANK(chip));
413exit:
414 mutex_unlock(&chip->i2c_lock);
415}
416
417static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
418{
419 struct gpio_chip *gc;
420
421 gc = &chip->gpio_chip;
422
423 gc->direction_input = pca953x_gpio_direction_input;
424 gc->direction_output = pca953x_gpio_direction_output;
425 gc->get = pca953x_gpio_get_value;
426 gc->set = pca953x_gpio_set_value;
427 gc->get_direction = pca953x_gpio_get_direction;
428 gc->set_multiple = pca953x_gpio_set_multiple;
429 gc->can_sleep = true;
430
431 gc->base = chip->gpio_start;
432 gc->ngpio = gpios;
433 gc->label = chip->client->name;
434 gc->parent = &chip->client->dev;
435 gc->owner = THIS_MODULE;
436 gc->names = chip->names;
437}
438
439#ifdef CONFIG_GPIO_PCA953X_IRQ
440static void pca953x_irq_mask(struct irq_data *d)
441{
442 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
443 struct pca953x_chip *chip = gpiochip_get_data(gc);
444
445 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
446}
447
448static void pca953x_irq_unmask(struct irq_data *d)
449{
450 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
451 struct pca953x_chip *chip = gpiochip_get_data(gc);
452
453 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
454}
455
456static void pca953x_irq_bus_lock(struct irq_data *d)
457{
458 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
459 struct pca953x_chip *chip = gpiochip_get_data(gc);
460
461 mutex_lock(&chip->irq_lock);
462}
463
464static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
465{
466 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
467 struct pca953x_chip *chip = gpiochip_get_data(gc);
468 u8 new_irqs;
469 int level, i;
470 u8 invert_irq_mask[MAX_BANK];
471
472 if (chip->driver_data & PCA_PCAL) {
473 /* Enable latch on interrupt-enabled inputs */
474 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
475
476 for (i = 0; i < NBANK(chip); i++)
477 invert_irq_mask[i] = ~chip->irq_mask[i];
478
479 /* Unmask enabled interrupts */
480 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
481 }
482
483 /* Look for any newly setup interrupt */
484 for (i = 0; i < NBANK(chip); i++) {
485 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
486 new_irqs &= ~chip->reg_direction[i];
487
488 while (new_irqs) {
489 level = __ffs(new_irqs);
490 pca953x_gpio_direction_input(&chip->gpio_chip,
491 level + (BANK_SZ * i));
492 new_irqs &= ~(1 << level);
493 }
494 }
495
496 mutex_unlock(&chip->irq_lock);
497}
498
499static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
500{
501 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
502 struct pca953x_chip *chip = gpiochip_get_data(gc);
503 int bank_nb = d->hwirq / BANK_SZ;
504 u8 mask = 1 << (d->hwirq % BANK_SZ);
505
506 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
507 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
508 d->irq, type);
509 return -EINVAL;
510 }
511
512 if (type & IRQ_TYPE_EDGE_FALLING)
513 chip->irq_trig_fall[bank_nb] |= mask;
514 else
515 chip->irq_trig_fall[bank_nb] &= ~mask;
516
517 if (type & IRQ_TYPE_EDGE_RISING)
518 chip->irq_trig_raise[bank_nb] |= mask;
519 else
520 chip->irq_trig_raise[bank_nb] &= ~mask;
521
522 return 0;
523}
524
525static struct irq_chip pca953x_irq_chip = {
526 .name = "pca953x",
527 .irq_mask = pca953x_irq_mask,
528 .irq_unmask = pca953x_irq_unmask,
529 .irq_bus_lock = pca953x_irq_bus_lock,
530 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
531 .irq_set_type = pca953x_irq_set_type,
532};
533
534static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
535{
536 u8 cur_stat[MAX_BANK];
537 u8 old_stat[MAX_BANK];
538 bool pending_seen = false;
539 bool trigger_seen = false;
540 u8 trigger[MAX_BANK];
541 int ret, i;
542
543 if (chip->driver_data & PCA_PCAL) {
544 /* Read the current interrupt status from the device */
545 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
546 if (ret)
547 return false;
548
549 /* Check latched inputs and clear interrupt status */
550 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
551 if (ret)
552 return false;
553
554 for (i = 0; i < NBANK(chip); i++) {
555 /* Apply filter for rising/falling edge selection */
556 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
557 (cur_stat[i] & chip->irq_trig_raise[i]);
558 pending[i] &= trigger[i];
559 if (pending[i])
560 pending_seen = true;
561 }
562
563 return pending_seen;
564 }
565
566 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
567 if (ret)
568 return false;
569
570 /* Remove output pins from the equation */
571 for (i = 0; i < NBANK(chip); i++)
572 cur_stat[i] &= chip->reg_direction[i];
573
574 memcpy(old_stat, chip->irq_stat, NBANK(chip));
575
576 for (i = 0; i < NBANK(chip); i++) {
577 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
578 if (trigger[i])
579 trigger_seen = true;
580 }
581
582 if (!trigger_seen)
583 return false;
584
585 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
586
587 for (i = 0; i < NBANK(chip); i++) {
588 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
589 (cur_stat[i] & chip->irq_trig_raise[i]);
590 pending[i] &= trigger[i];
591 if (pending[i])
592 pending_seen = true;
593 }
594
595 return pending_seen;
596}
597
598static irqreturn_t pca953x_irq_handler(int irq, void *devid)
599{
600 struct pca953x_chip *chip = devid;
601 u8 pending[MAX_BANK];
602 u8 level;
603 unsigned nhandled = 0;
604 int i;
605
606 if (!pca953x_irq_pending(chip, pending))
607 return IRQ_NONE;
608
609 for (i = 0; i < NBANK(chip); i++) {
610 while (pending[i]) {
611 level = __ffs(pending[i]);
612 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
613 level + (BANK_SZ * i)));
614 pending[i] &= ~(1 << level);
615 nhandled++;
616 }
617 }
618
619 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
620}
621
622static int pca953x_irq_setup(struct pca953x_chip *chip,
623 int irq_base)
624{
625 struct i2c_client *client = chip->client;
626 int ret, i;
627
628 if (client->irq && irq_base != -1
629 && (chip->driver_data & PCA_INT)) {
630 ret = pca953x_read_regs(chip,
631 chip->regs->input, chip->irq_stat);
632 if (ret)
633 return ret;
634
635 /*
636 * There is no way to know which GPIO line generated the
637 * interrupt. We have to rely on the previous read for
638 * this purpose.
639 */
640 for (i = 0; i < NBANK(chip); i++)
641 chip->irq_stat[i] &= chip->reg_direction[i];
642 mutex_init(&chip->irq_lock);
643
644 ret = devm_request_threaded_irq(&client->dev,
645 client->irq,
646 NULL,
647 pca953x_irq_handler,
648 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
649 IRQF_SHARED,
650 dev_name(&client->dev), chip);
651 if (ret) {
652 dev_err(&client->dev, "failed to request irq %d\n",
653 client->irq);
654 return ret;
655 }
656
657 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip,
658 &pca953x_irq_chip,
659 irq_base,
660 handle_simple_irq,
661 IRQ_TYPE_NONE);
662 if (ret) {
663 dev_err(&client->dev,
664 "could not connect irqchip to gpiochip\n");
665 return ret;
666 }
667
668 gpiochip_set_nested_irqchip(&chip->gpio_chip,
669 &pca953x_irq_chip,
670 client->irq);
671 }
672
673 return 0;
674}
675
676#else /* CONFIG_GPIO_PCA953X_IRQ */
677static int pca953x_irq_setup(struct pca953x_chip *chip,
678 int irq_base)
679{
680 struct i2c_client *client = chip->client;
681
682 if (irq_base != -1 && (chip->driver_data & PCA_INT))
683 dev_warn(&client->dev, "interrupt support not compiled in\n");
684
685 return 0;
686}
687#endif
688
689static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
690{
691 int ret;
692 u8 val[MAX_BANK];
693
694 chip->regs = &pca953x_regs;
695
696 ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
697 if (ret)
698 goto out;
699
700 ret = pca953x_read_regs(chip, chip->regs->direction,
701 chip->reg_direction);
702 if (ret)
703 goto out;
704
705 /* set platform specific polarity inversion */
706 if (invert)
707 memset(val, 0xFF, NBANK(chip));
708 else
709 memset(val, 0, NBANK(chip));
710
711 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
712out:
713 return ret;
714}
715
716static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
717{
718 int ret;
719 u8 val[MAX_BANK];
720
721 chip->regs = &pca957x_regs;
722
723 ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
724 if (ret)
725 goto out;
726 ret = pca953x_read_regs(chip, chip->regs->direction,
727 chip->reg_direction);
728 if (ret)
729 goto out;
730
731 /* set platform specific polarity inversion */
732 if (invert)
733 memset(val, 0xFF, NBANK(chip));
734 else
735 memset(val, 0, NBANK(chip));
736 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
737 if (ret)
738 goto out;
739
740 /* To enable register 6, 7 to control pull up and pull down */
741 memset(val, 0x02, NBANK(chip));
742 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
743 if (ret)
744 goto out;
745
746 return 0;
747out:
748 return ret;
749}
750
751static const struct of_device_id pca953x_dt_ids[];
752
753static int pca953x_probe(struct i2c_client *client,
754 const struct i2c_device_id *i2c_id)
755{
756 struct pca953x_platform_data *pdata;
757 struct pca953x_chip *chip;
758 int irq_base = 0;
759 int ret;
760 u32 invert = 0;
761 struct regulator *reg;
762
763 chip = devm_kzalloc(&client->dev,
764 sizeof(struct pca953x_chip), GFP_KERNEL);
765 if (chip == NULL)
766 return -ENOMEM;
767
768 pdata = dev_get_platdata(&client->dev);
769 if (pdata) {
770 irq_base = pdata->irq_base;
771 chip->gpio_start = pdata->gpio_base;
772 invert = pdata->invert;
773 chip->names = pdata->names;
774 } else {
775 struct gpio_desc *reset_gpio;
776
777 chip->gpio_start = -1;
778 irq_base = 0;
779
780 /*
781 * See if we need to de-assert a reset pin.
782 *
783 * There is no known ACPI-enabled platforms that are
784 * using "reset" GPIO. Otherwise any of those platform
785 * must use _DSD method with corresponding property.
786 */
787 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
788 GPIOD_OUT_LOW);
789 if (IS_ERR(reset_gpio))
790 return PTR_ERR(reset_gpio);
791 }
792
793 chip->client = client;
794
795 reg = devm_regulator_get(&client->dev, "vcc");
796 if (IS_ERR(reg)) {
797 ret = PTR_ERR(reg);
798 if (ret != -EPROBE_DEFER)
799 dev_err(&client->dev, "reg get err: %d\n", ret);
800 return ret;
801 }
802 ret = regulator_enable(reg);
803 if (ret) {
804 dev_err(&client->dev, "reg en err: %d\n", ret);
805 return ret;
806 }
807 chip->regulator = reg;
808
809 if (i2c_id) {
810 chip->driver_data = i2c_id->driver_data;
811 } else {
812 const struct acpi_device_id *acpi_id;
813 const struct of_device_id *match;
814
815 match = of_match_device(pca953x_dt_ids, &client->dev);
816 if (match) {
817 chip->driver_data = (int)(uintptr_t)match->data;
818 } else {
819 acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
820 if (!acpi_id) {
821 ret = -ENODEV;
822 goto err_exit;
823 }
824
825 chip->driver_data = acpi_id->driver_data;
826 }
827 }
828
829 mutex_init(&chip->i2c_lock);
830 /*
831 * In case we have an i2c-mux controlled by a GPIO provided by an
832 * expander using the same driver higher on the device tree, read the
833 * i2c adapter nesting depth and use the retrieved value as lockdep
834 * subclass for chip->i2c_lock.
835 *
836 * REVISIT: This solution is not complete. It protects us from lockdep
837 * false positives when the expander controlling the i2c-mux is on
838 * a different level on the device tree, but not when it's on the same
839 * level on a different branch (in which case the subclass number
840 * would be the same).
841 *
842 * TODO: Once a correct solution is developed, a similar fix should be
843 * applied to all other i2c-controlled GPIO expanders (and potentially
844 * regmap-i2c).
845 */
846 lockdep_set_subclass(&chip->i2c_lock,
847 i2c_adapter_depth(client->adapter));
848
849 /* initialize cached registers from their original values.
850 * we can't share this chip with another i2c master.
851 */
852 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
853
854 if (chip->gpio_chip.ngpio <= 8) {
855 chip->write_regs = pca953x_write_regs_8;
856 chip->read_regs = pca953x_read_regs_8;
857 } else if (chip->gpio_chip.ngpio >= 24) {
858 chip->write_regs = pca953x_write_regs_24;
859 chip->read_regs = pca953x_read_regs_24;
860 } else {
861 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
862 chip->write_regs = pca953x_write_regs_16;
863 else
864 chip->write_regs = pca957x_write_regs_16;
865 chip->read_regs = pca953x_read_regs_16;
866 }
867
868 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
869 ret = device_pca953x_init(chip, invert);
870 else
871 ret = device_pca957x_init(chip, invert);
872 if (ret)
873 goto err_exit;
874
875 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
876 if (ret)
877 goto err_exit;
878
879 ret = pca953x_irq_setup(chip, irq_base);
880 if (ret)
881 goto err_exit;
882
883 if (pdata && pdata->setup) {
884 ret = pdata->setup(client, chip->gpio_chip.base,
885 chip->gpio_chip.ngpio, pdata->context);
886 if (ret < 0)
887 dev_warn(&client->dev, "setup failed, %d\n", ret);
888 }
889
890 i2c_set_clientdata(client, chip);
891 return 0;
892
893err_exit:
894 regulator_disable(chip->regulator);
895 return ret;
896}
897
898static int pca953x_remove(struct i2c_client *client)
899{
900 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
901 struct pca953x_chip *chip = i2c_get_clientdata(client);
902 int ret;
903
904 if (pdata && pdata->teardown) {
905 ret = pdata->teardown(client, chip->gpio_chip.base,
906 chip->gpio_chip.ngpio, pdata->context);
907 if (ret < 0)
908 dev_err(&client->dev, "%s failed, %d\n",
909 "teardown", ret);
910 } else {
911 ret = 0;
912 }
913
914 regulator_disable(chip->regulator);
915
916 return ret;
917}
918
919/* convenience to stop overlong match-table lines */
920#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
921#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
922
923static const struct of_device_id pca953x_dt_ids[] = {
924 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
925 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
926 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
927 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
928 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
929 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
930 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
931 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
932 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
933 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
934 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
935 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
936 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
937 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
938
939 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_INT), },
940 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_INT), },
941
942 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
943 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
944 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
945 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
946 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
947
948 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
949 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
950 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
951 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
952 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
953
954 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
955
956 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
957 { }
958};
959
960MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
961
962static struct i2c_driver pca953x_driver = {
963 .driver = {
964 .name = "pca953x",
965 .of_match_table = pca953x_dt_ids,
966 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
967 },
968 .probe = pca953x_probe,
969 .remove = pca953x_remove,
970 .id_table = pca953x_id,
971};
972
973static int __init pca953x_init(void)
974{
975 return i2c_add_driver(&pca953x_driver);
976}
977/* register after i2c postcore initcall and before
978 * subsys initcalls that may rely on these GPIOs
979 */
980subsys_initcall(pca953x_init);
981
982static void __exit pca953x_exit(void)
983{
984 i2c_del_driver(&pca953x_driver);
985}
986module_exit(pca953x_exit);
987
988MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
989MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
990MODULE_LICENSE("GPL");