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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * GPIO driver for Fintek and Nuvoton Super-I/O chips
4 *
5 * Copyright (C) 2010-2013 LaCie
6 *
7 * Author: Simon Guinot <simon.guinot@sequanux.org>
8 */
9
10#define DRVNAME "gpio-f7188x"
11#define pr_fmt(fmt) DRVNAME ": " fmt
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/gpio/driver.h>
18#include <linux/bitops.h>
19
20/*
21 * Super-I/O registers
22 */
23#define SIO_LDSEL 0x07 /* Logical device select */
24#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
25
26#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
27#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
28
29/*
30 * Fintek devices.
31 */
32#define SIO_FINTEK_DEVREV 0x22 /* Fintek Device revision */
33#define SIO_FINTEK_MANID 0x23 /* Fintek ID (2 bytes) */
34
35#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
36
37#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
38#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
39#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
40#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
41#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
42#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
43#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for F81966 */
44#define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
45
46#define SIO_LD_GPIO_FINTEK 0x06 /* GPIO logical device */
47
48/*
49 * Nuvoton devices.
50 */
51#define SIO_NCT6126D_ID 0xD283 /* NCT6126D chipset ID */
52
53#define SIO_LD_GPIO_NUVOTON 0x07 /* GPIO logical device */
54
55
56enum chips {
57 f71869,
58 f71869a,
59 f71882fg,
60 f71889a,
61 f71889f,
62 f81866,
63 f81804,
64 f81865,
65 nct6126d,
66};
67
68static const char * const f7188x_names[] = {
69 "f71869",
70 "f71869a",
71 "f71882fg",
72 "f71889a",
73 "f71889f",
74 "f81866",
75 "f81804",
76 "f81865",
77 "nct6126d",
78};
79
80struct f7188x_sio {
81 int addr;
82 int device;
83 enum chips type;
84};
85
86struct f7188x_gpio_bank {
87 struct gpio_chip chip;
88 unsigned int regbase;
89 struct f7188x_gpio_data *data;
90};
91
92struct f7188x_gpio_data {
93 struct f7188x_sio *sio;
94 int nr_bank;
95 struct f7188x_gpio_bank *bank;
96};
97
98/*
99 * Super-I/O functions.
100 */
101
102static inline int superio_inb(int base, int reg)
103{
104 outb(reg, base);
105 return inb(base + 1);
106}
107
108static int superio_inw(int base, int reg)
109{
110 int val;
111
112 outb(reg++, base);
113 val = inb(base + 1) << 8;
114 outb(reg, base);
115 val |= inb(base + 1);
116
117 return val;
118}
119
120static inline void superio_outb(int base, int reg, int val)
121{
122 outb(reg, base);
123 outb(val, base + 1);
124}
125
126static inline int superio_enter(int base)
127{
128 /* Don't step on other drivers' I/O space by accident. */
129 if (!request_muxed_region(base, 2, DRVNAME)) {
130 pr_err("I/O address 0x%04x already in use\n", base);
131 return -EBUSY;
132 }
133
134 /* According to the datasheet the key must be send twice. */
135 outb(SIO_UNLOCK_KEY, base);
136 outb(SIO_UNLOCK_KEY, base);
137
138 return 0;
139}
140
141static inline void superio_select(int base, int ld)
142{
143 outb(SIO_LDSEL, base);
144 outb(ld, base + 1);
145}
146
147static inline void superio_exit(int base)
148{
149 outb(SIO_LOCK_KEY, base);
150 release_region(base, 2);
151}
152
153/*
154 * GPIO chip.
155 */
156
157static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
158static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
159static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
160static int f7188x_gpio_direction_out(struct gpio_chip *chip,
161 unsigned offset, int value);
162static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
163static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
164 unsigned long config);
165
166#define F7188X_GPIO_BANK(_ngpio, _regbase, _label) \
167 { \
168 .chip = { \
169 .label = _label, \
170 .owner = THIS_MODULE, \
171 .get_direction = f7188x_gpio_get_direction, \
172 .direction_input = f7188x_gpio_direction_in, \
173 .get = f7188x_gpio_get, \
174 .direction_output = f7188x_gpio_direction_out, \
175 .set = f7188x_gpio_set, \
176 .set_config = f7188x_gpio_set_config, \
177 .base = -1, \
178 .ngpio = _ngpio, \
179 .can_sleep = true, \
180 }, \
181 .regbase = _regbase, \
182 }
183
184#define f7188x_gpio_dir(base) ((base) + 0)
185#define f7188x_gpio_data_out(base) ((base) + 1)
186#define f7188x_gpio_data_in(base) ((base) + 2)
187/* Output mode register (0:open drain 1:push-pull). */
188#define f7188x_gpio_out_mode(base) ((base) + 3)
189
190#define f7188x_gpio_dir_invert(type) ((type) == nct6126d)
191#define f7188x_gpio_data_single(type) ((type) == nct6126d)
192
193static struct f7188x_gpio_bank f71869_gpio_bank[] = {
194 F7188X_GPIO_BANK(6, 0xF0, DRVNAME "-0"),
195 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
196 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
197 F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
198 F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
199 F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
200 F7188X_GPIO_BANK(6, 0x90, DRVNAME "-6"),
201};
202
203static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
204 F7188X_GPIO_BANK(6, 0xF0, DRVNAME "-0"),
205 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
206 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
207 F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
208 F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
209 F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
210 F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
211 F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
212};
213
214static struct f7188x_gpio_bank f71882_gpio_bank[] = {
215 F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
216 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
217 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
218 F7188X_GPIO_BANK(4, 0xC0, DRVNAME "-3"),
219 F7188X_GPIO_BANK(4, 0xB0, DRVNAME "-4"),
220};
221
222static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
223 F7188X_GPIO_BANK(7, 0xF0, DRVNAME "-0"),
224 F7188X_GPIO_BANK(7, 0xE0, DRVNAME "-1"),
225 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
226 F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
227 F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
228 F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
229 F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
230 F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
231};
232
233static struct f7188x_gpio_bank f71889_gpio_bank[] = {
234 F7188X_GPIO_BANK(7, 0xF0, DRVNAME "-0"),
235 F7188X_GPIO_BANK(7, 0xE0, DRVNAME "-1"),
236 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
237 F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
238 F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
239 F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
240 F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
241 F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
242};
243
244static struct f7188x_gpio_bank f81866_gpio_bank[] = {
245 F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
246 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
247 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
248 F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
249 F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
250 F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-5"),
251 F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
252 F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
253 F7188X_GPIO_BANK(8, 0x88, DRVNAME "-8"),
254};
255
256
257static struct f7188x_gpio_bank f81804_gpio_bank[] = {
258 F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
259 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
260 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
261 F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-3"),
262 F7188X_GPIO_BANK(8, 0x90, DRVNAME "-4"),
263 F7188X_GPIO_BANK(8, 0x80, DRVNAME "-5"),
264 F7188X_GPIO_BANK(8, 0x98, DRVNAME "-6"),
265};
266
267static struct f7188x_gpio_bank f81865_gpio_bank[] = {
268 F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
269 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
270 F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
271 F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
272 F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
273 F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-5"),
274 F7188X_GPIO_BANK(5, 0x90, DRVNAME "-6"),
275};
276
277static struct f7188x_gpio_bank nct6126d_gpio_bank[] = {
278 F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-0"),
279 F7188X_GPIO_BANK(8, 0xE4, DRVNAME "-1"),
280 F7188X_GPIO_BANK(8, 0xE8, DRVNAME "-2"),
281 F7188X_GPIO_BANK(8, 0xEC, DRVNAME "-3"),
282 F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-4"),
283 F7188X_GPIO_BANK(8, 0xF4, DRVNAME "-5"),
284 F7188X_GPIO_BANK(8, 0xF8, DRVNAME "-6"),
285 F7188X_GPIO_BANK(8, 0xFC, DRVNAME "-7"),
286};
287
288static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
289{
290 int err;
291 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
292 struct f7188x_sio *sio = bank->data->sio;
293 u8 dir;
294
295 err = superio_enter(sio->addr);
296 if (err)
297 return err;
298 superio_select(sio->addr, sio->device);
299
300 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
301
302 superio_exit(sio->addr);
303
304 if (f7188x_gpio_dir_invert(sio->type))
305 dir = ~dir;
306
307 if (dir & BIT(offset))
308 return GPIO_LINE_DIRECTION_OUT;
309
310 return GPIO_LINE_DIRECTION_IN;
311}
312
313static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
314{
315 int err;
316 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
317 struct f7188x_sio *sio = bank->data->sio;
318 u8 dir;
319
320 err = superio_enter(sio->addr);
321 if (err)
322 return err;
323 superio_select(sio->addr, sio->device);
324
325 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
326
327 if (f7188x_gpio_dir_invert(sio->type))
328 dir |= BIT(offset);
329 else
330 dir &= ~BIT(offset);
331 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
332
333 superio_exit(sio->addr);
334
335 return 0;
336}
337
338static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
339{
340 int err;
341 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
342 struct f7188x_sio *sio = bank->data->sio;
343 u8 dir, data;
344
345 err = superio_enter(sio->addr);
346 if (err)
347 return err;
348 superio_select(sio->addr, sio->device);
349
350 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
351 dir = !!(dir & BIT(offset));
352 if (f7188x_gpio_data_single(sio->type) || dir)
353 data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
354 else
355 data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase));
356
357 superio_exit(sio->addr);
358
359 return !!(data & BIT(offset));
360}
361
362static int f7188x_gpio_direction_out(struct gpio_chip *chip,
363 unsigned offset, int value)
364{
365 int err;
366 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
367 struct f7188x_sio *sio = bank->data->sio;
368 u8 dir, data_out;
369
370 err = superio_enter(sio->addr);
371 if (err)
372 return err;
373 superio_select(sio->addr, sio->device);
374
375 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
376 if (value)
377 data_out |= BIT(offset);
378 else
379 data_out &= ~BIT(offset);
380 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
381
382 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
383 if (f7188x_gpio_dir_invert(sio->type))
384 dir &= ~BIT(offset);
385 else
386 dir |= BIT(offset);
387 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
388
389 superio_exit(sio->addr);
390
391 return 0;
392}
393
394static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
395{
396 int err;
397 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
398 struct f7188x_sio *sio = bank->data->sio;
399 u8 data_out;
400
401 err = superio_enter(sio->addr);
402 if (err)
403 return;
404 superio_select(sio->addr, sio->device);
405
406 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
407 if (value)
408 data_out |= BIT(offset);
409 else
410 data_out &= ~BIT(offset);
411 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
412
413 superio_exit(sio->addr);
414}
415
416static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
417 unsigned long config)
418{
419 int err;
420 enum pin_config_param param = pinconf_to_config_param(config);
421 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
422 struct f7188x_sio *sio = bank->data->sio;
423 u8 data;
424
425 if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
426 param != PIN_CONFIG_DRIVE_PUSH_PULL)
427 return -ENOTSUPP;
428
429 err = superio_enter(sio->addr);
430 if (err)
431 return err;
432 superio_select(sio->addr, sio->device);
433
434 data = superio_inb(sio->addr, f7188x_gpio_out_mode(bank->regbase));
435 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
436 data &= ~BIT(offset);
437 else
438 data |= BIT(offset);
439 superio_outb(sio->addr, f7188x_gpio_out_mode(bank->regbase), data);
440
441 superio_exit(sio->addr);
442 return 0;
443}
444
445/*
446 * Platform device and driver.
447 */
448
449static int f7188x_gpio_probe(struct platform_device *pdev)
450{
451 int err;
452 int i;
453 struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
454 struct f7188x_gpio_data *data;
455
456 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
457 if (!data)
458 return -ENOMEM;
459
460 switch (sio->type) {
461 case f71869:
462 data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
463 data->bank = f71869_gpio_bank;
464 break;
465 case f71869a:
466 data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
467 data->bank = f71869a_gpio_bank;
468 break;
469 case f71882fg:
470 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
471 data->bank = f71882_gpio_bank;
472 break;
473 case f71889a:
474 data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
475 data->bank = f71889a_gpio_bank;
476 break;
477 case f71889f:
478 data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
479 data->bank = f71889_gpio_bank;
480 break;
481 case f81866:
482 data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
483 data->bank = f81866_gpio_bank;
484 break;
485 case f81804:
486 data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
487 data->bank = f81804_gpio_bank;
488 break;
489 case f81865:
490 data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
491 data->bank = f81865_gpio_bank;
492 break;
493 case nct6126d:
494 data->nr_bank = ARRAY_SIZE(nct6126d_gpio_bank);
495 data->bank = nct6126d_gpio_bank;
496 break;
497 default:
498 return -ENODEV;
499 }
500 data->sio = sio;
501
502 platform_set_drvdata(pdev, data);
503
504 /* For each GPIO bank, register a GPIO chip. */
505 for (i = 0; i < data->nr_bank; i++) {
506 struct f7188x_gpio_bank *bank = &data->bank[i];
507
508 bank->chip.parent = &pdev->dev;
509 bank->data = data;
510
511 err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
512 if (err) {
513 dev_err(&pdev->dev,
514 "Failed to register gpiochip %d: %d\n",
515 i, err);
516 return err;
517 }
518 }
519
520 return 0;
521}
522
523static int __init f7188x_find(int addr, struct f7188x_sio *sio)
524{
525 int err;
526 u16 devid;
527 u16 manid;
528
529 err = superio_enter(addr);
530 if (err)
531 return err;
532
533 err = -ENODEV;
534
535 sio->device = SIO_LD_GPIO_FINTEK;
536 devid = superio_inw(addr, SIO_DEVID);
537 switch (devid) {
538 case SIO_F71869_ID:
539 sio->type = f71869;
540 break;
541 case SIO_F71869A_ID:
542 sio->type = f71869a;
543 break;
544 case SIO_F71882_ID:
545 sio->type = f71882fg;
546 break;
547 case SIO_F71889A_ID:
548 sio->type = f71889a;
549 break;
550 case SIO_F71889_ID:
551 sio->type = f71889f;
552 break;
553 case SIO_F81866_ID:
554 sio->type = f81866;
555 break;
556 case SIO_F81804_ID:
557 sio->type = f81804;
558 break;
559 case SIO_F81865_ID:
560 sio->type = f81865;
561 break;
562 case SIO_NCT6126D_ID:
563 sio->device = SIO_LD_GPIO_NUVOTON;
564 sio->type = nct6126d;
565 break;
566 default:
567 pr_info("Unsupported Fintek device 0x%04x\n", devid);
568 goto err;
569 }
570
571 /* double check manufacturer where possible */
572 if (sio->type != nct6126d) {
573 manid = superio_inw(addr, SIO_FINTEK_MANID);
574 if (manid != SIO_FINTEK_ID) {
575 pr_debug("Not a Fintek device at 0x%08x\n", addr);
576 goto err;
577 }
578 }
579
580 sio->addr = addr;
581 err = 0;
582
583 pr_info("Found %s at %#x\n", f7188x_names[sio->type], (unsigned int)addr);
584 if (sio->type != nct6126d)
585 pr_info(" revision %d\n", superio_inb(addr, SIO_FINTEK_DEVREV));
586
587err:
588 superio_exit(addr);
589 return err;
590}
591
592static struct platform_device *f7188x_gpio_pdev;
593
594static int __init
595f7188x_gpio_device_add(const struct f7188x_sio *sio)
596{
597 int err;
598
599 f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
600 if (!f7188x_gpio_pdev)
601 return -ENOMEM;
602
603 err = platform_device_add_data(f7188x_gpio_pdev,
604 sio, sizeof(*sio));
605 if (err) {
606 pr_err("Platform data allocation failed\n");
607 goto err;
608 }
609
610 err = platform_device_add(f7188x_gpio_pdev);
611 if (err) {
612 pr_err("Device addition failed\n");
613 goto err;
614 }
615
616 return 0;
617
618err:
619 platform_device_put(f7188x_gpio_pdev);
620
621 return err;
622}
623
624/*
625 * Try to match a supported Fintek device by reading the (hard-wired)
626 * configuration I/O ports. If available, then register both the platform
627 * device and driver to support the GPIOs.
628 */
629
630static struct platform_driver f7188x_gpio_driver = {
631 .driver = {
632 .name = DRVNAME,
633 },
634 .probe = f7188x_gpio_probe,
635};
636
637static int __init f7188x_gpio_init(void)
638{
639 int err;
640 struct f7188x_sio sio;
641
642 if (f7188x_find(0x2e, &sio) &&
643 f7188x_find(0x4e, &sio))
644 return -ENODEV;
645
646 err = platform_driver_register(&f7188x_gpio_driver);
647 if (!err) {
648 err = f7188x_gpio_device_add(&sio);
649 if (err)
650 platform_driver_unregister(&f7188x_gpio_driver);
651 }
652
653 return err;
654}
655subsys_initcall(f7188x_gpio_init);
656
657static void __exit f7188x_gpio_exit(void)
658{
659 platform_device_unregister(f7188x_gpio_pdev);
660 platform_driver_unregister(&f7188x_gpio_driver);
661}
662module_exit(f7188x_gpio_exit);
663
664MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
665MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
666MODULE_LICENSE("GPL");
1/*
2 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
3 *
4 * Copyright (C) 2010-2013 LaCie
5 *
6 * Author: Simon Guinot <simon.guinot@sequanux.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio/driver.h>
19#include <linux/bitops.h>
20
21#define DRVNAME "gpio-f7188x"
22
23/*
24 * Super-I/O registers
25 */
26#define SIO_LDSEL 0x07 /* Logical device select */
27#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
28#define SIO_DEVREV 0x22 /* Device revision */
29#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
30
31#define SIO_LD_GPIO 0x06 /* GPIO logical device */
32#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
33#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
34
35#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
36#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
37#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
38#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
39#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
40#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
41#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
42
43enum chips { f71869, f71869a, f71882fg, f71889a, f71889f, f81866 };
44
45static const char * const f7188x_names[] = {
46 "f71869",
47 "f71869a",
48 "f71882fg",
49 "f71889a",
50 "f71889f",
51 "f81866",
52};
53
54struct f7188x_sio {
55 int addr;
56 enum chips type;
57};
58
59struct f7188x_gpio_bank {
60 struct gpio_chip chip;
61 unsigned int regbase;
62 struct f7188x_gpio_data *data;
63};
64
65struct f7188x_gpio_data {
66 struct f7188x_sio *sio;
67 int nr_bank;
68 struct f7188x_gpio_bank *bank;
69};
70
71/*
72 * Super-I/O functions.
73 */
74
75static inline int superio_inb(int base, int reg)
76{
77 outb(reg, base);
78 return inb(base + 1);
79}
80
81static int superio_inw(int base, int reg)
82{
83 int val;
84
85 outb(reg++, base);
86 val = inb(base + 1) << 8;
87 outb(reg, base);
88 val |= inb(base + 1);
89
90 return val;
91}
92
93static inline void superio_outb(int base, int reg, int val)
94{
95 outb(reg, base);
96 outb(val, base + 1);
97}
98
99static inline int superio_enter(int base)
100{
101 /* Don't step on other drivers' I/O space by accident. */
102 if (!request_muxed_region(base, 2, DRVNAME)) {
103 pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
104 return -EBUSY;
105 }
106
107 /* According to the datasheet the key must be send twice. */
108 outb(SIO_UNLOCK_KEY, base);
109 outb(SIO_UNLOCK_KEY, base);
110
111 return 0;
112}
113
114static inline void superio_select(int base, int ld)
115{
116 outb(SIO_LDSEL, base);
117 outb(ld, base + 1);
118}
119
120static inline void superio_exit(int base)
121{
122 outb(SIO_LOCK_KEY, base);
123 release_region(base, 2);
124}
125
126/*
127 * GPIO chip.
128 */
129
130static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
131static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
132static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
133static int f7188x_gpio_direction_out(struct gpio_chip *chip,
134 unsigned offset, int value);
135static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
136static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
137 unsigned long config);
138
139#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
140 { \
141 .chip = { \
142 .label = DRVNAME, \
143 .owner = THIS_MODULE, \
144 .get_direction = f7188x_gpio_get_direction, \
145 .direction_input = f7188x_gpio_direction_in, \
146 .get = f7188x_gpio_get, \
147 .direction_output = f7188x_gpio_direction_out, \
148 .set = f7188x_gpio_set, \
149 .set_config = f7188x_gpio_set_config, \
150 .base = _base, \
151 .ngpio = _ngpio, \
152 .can_sleep = true, \
153 }, \
154 .regbase = _regbase, \
155 }
156
157#define gpio_dir(base) (base + 0)
158#define gpio_data_out(base) (base + 1)
159#define gpio_data_in(base) (base + 2)
160/* Output mode register (0:open drain 1:push-pull). */
161#define gpio_out_mode(base) (base + 3)
162
163static struct f7188x_gpio_bank f71869_gpio_bank[] = {
164 F7188X_GPIO_BANK(0, 6, 0xF0),
165 F7188X_GPIO_BANK(10, 8, 0xE0),
166 F7188X_GPIO_BANK(20, 8, 0xD0),
167 F7188X_GPIO_BANK(30, 8, 0xC0),
168 F7188X_GPIO_BANK(40, 8, 0xB0),
169 F7188X_GPIO_BANK(50, 5, 0xA0),
170 F7188X_GPIO_BANK(60, 6, 0x90),
171};
172
173static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
174 F7188X_GPIO_BANK(0, 6, 0xF0),
175 F7188X_GPIO_BANK(10, 8, 0xE0),
176 F7188X_GPIO_BANK(20, 8, 0xD0),
177 F7188X_GPIO_BANK(30, 8, 0xC0),
178 F7188X_GPIO_BANK(40, 8, 0xB0),
179 F7188X_GPIO_BANK(50, 5, 0xA0),
180 F7188X_GPIO_BANK(60, 8, 0x90),
181 F7188X_GPIO_BANK(70, 8, 0x80),
182};
183
184static struct f7188x_gpio_bank f71882_gpio_bank[] = {
185 F7188X_GPIO_BANK(0, 8, 0xF0),
186 F7188X_GPIO_BANK(10, 8, 0xE0),
187 F7188X_GPIO_BANK(20, 8, 0xD0),
188 F7188X_GPIO_BANK(30, 4, 0xC0),
189 F7188X_GPIO_BANK(40, 4, 0xB0),
190};
191
192static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
193 F7188X_GPIO_BANK(0, 7, 0xF0),
194 F7188X_GPIO_BANK(10, 7, 0xE0),
195 F7188X_GPIO_BANK(20, 8, 0xD0),
196 F7188X_GPIO_BANK(30, 8, 0xC0),
197 F7188X_GPIO_BANK(40, 8, 0xB0),
198 F7188X_GPIO_BANK(50, 5, 0xA0),
199 F7188X_GPIO_BANK(60, 8, 0x90),
200 F7188X_GPIO_BANK(70, 8, 0x80),
201};
202
203static struct f7188x_gpio_bank f71889_gpio_bank[] = {
204 F7188X_GPIO_BANK(0, 7, 0xF0),
205 F7188X_GPIO_BANK(10, 7, 0xE0),
206 F7188X_GPIO_BANK(20, 8, 0xD0),
207 F7188X_GPIO_BANK(30, 8, 0xC0),
208 F7188X_GPIO_BANK(40, 8, 0xB0),
209 F7188X_GPIO_BANK(50, 5, 0xA0),
210 F7188X_GPIO_BANK(60, 8, 0x90),
211 F7188X_GPIO_BANK(70, 8, 0x80),
212};
213
214static struct f7188x_gpio_bank f81866_gpio_bank[] = {
215 F7188X_GPIO_BANK(0, 8, 0xF0),
216 F7188X_GPIO_BANK(10, 8, 0xE0),
217 F7188X_GPIO_BANK(20, 8, 0xD0),
218 F7188X_GPIO_BANK(30, 8, 0xC0),
219 F7188X_GPIO_BANK(40, 8, 0xB0),
220 F7188X_GPIO_BANK(50, 8, 0xA0),
221 F7188X_GPIO_BANK(60, 8, 0x90),
222 F7188X_GPIO_BANK(70, 8, 0x80),
223 F7188X_GPIO_BANK(80, 8, 0x88),
224};
225
226static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
227{
228 int err;
229 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
230 struct f7188x_sio *sio = bank->data->sio;
231 u8 dir;
232
233 err = superio_enter(sio->addr);
234 if (err)
235 return err;
236 superio_select(sio->addr, SIO_LD_GPIO);
237
238 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
239
240 superio_exit(sio->addr);
241
242 return !(dir & 1 << offset);
243}
244
245static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
246{
247 int err;
248 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
249 struct f7188x_sio *sio = bank->data->sio;
250 u8 dir;
251
252 err = superio_enter(sio->addr);
253 if (err)
254 return err;
255 superio_select(sio->addr, SIO_LD_GPIO);
256
257 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
258 dir &= ~BIT(offset);
259 superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
260
261 superio_exit(sio->addr);
262
263 return 0;
264}
265
266static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
267{
268 int err;
269 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
270 struct f7188x_sio *sio = bank->data->sio;
271 u8 dir, data;
272
273 err = superio_enter(sio->addr);
274 if (err)
275 return err;
276 superio_select(sio->addr, SIO_LD_GPIO);
277
278 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
279 dir = !!(dir & BIT(offset));
280 if (dir)
281 data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
282 else
283 data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
284
285 superio_exit(sio->addr);
286
287 return !!(data & BIT(offset));
288}
289
290static int f7188x_gpio_direction_out(struct gpio_chip *chip,
291 unsigned offset, int value)
292{
293 int err;
294 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
295 struct f7188x_sio *sio = bank->data->sio;
296 u8 dir, data_out;
297
298 err = superio_enter(sio->addr);
299 if (err)
300 return err;
301 superio_select(sio->addr, SIO_LD_GPIO);
302
303 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
304 if (value)
305 data_out |= BIT(offset);
306 else
307 data_out &= ~BIT(offset);
308 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
309
310 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
311 dir |= BIT(offset);
312 superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
313
314 superio_exit(sio->addr);
315
316 return 0;
317}
318
319static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
320{
321 int err;
322 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
323 struct f7188x_sio *sio = bank->data->sio;
324 u8 data_out;
325
326 err = superio_enter(sio->addr);
327 if (err)
328 return;
329 superio_select(sio->addr, SIO_LD_GPIO);
330
331 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
332 if (value)
333 data_out |= BIT(offset);
334 else
335 data_out &= ~BIT(offset);
336 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
337
338 superio_exit(sio->addr);
339}
340
341static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
342 unsigned long config)
343{
344 int err;
345 enum pin_config_param param = pinconf_to_config_param(config);
346 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
347 struct f7188x_sio *sio = bank->data->sio;
348 u8 data;
349
350 if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
351 param != PIN_CONFIG_DRIVE_PUSH_PULL)
352 return -ENOTSUPP;
353
354 err = superio_enter(sio->addr);
355 if (err)
356 return err;
357 superio_select(sio->addr, SIO_LD_GPIO);
358
359 data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
360 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
361 data &= ~BIT(offset);
362 else
363 data |= BIT(offset);
364 superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
365
366 superio_exit(sio->addr);
367 return 0;
368}
369
370/*
371 * Platform device and driver.
372 */
373
374static int f7188x_gpio_probe(struct platform_device *pdev)
375{
376 int err;
377 int i;
378 struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
379 struct f7188x_gpio_data *data;
380
381 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
382 if (!data)
383 return -ENOMEM;
384
385 switch (sio->type) {
386 case f71869:
387 data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
388 data->bank = f71869_gpio_bank;
389 break;
390 case f71869a:
391 data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
392 data->bank = f71869a_gpio_bank;
393 break;
394 case f71882fg:
395 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
396 data->bank = f71882_gpio_bank;
397 break;
398 case f71889a:
399 data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
400 data->bank = f71889a_gpio_bank;
401 break;
402 case f71889f:
403 data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
404 data->bank = f71889_gpio_bank;
405 break;
406 case f81866:
407 data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
408 data->bank = f81866_gpio_bank;
409 break;
410 default:
411 return -ENODEV;
412 }
413 data->sio = sio;
414
415 platform_set_drvdata(pdev, data);
416
417 /* For each GPIO bank, register a GPIO chip. */
418 for (i = 0; i < data->nr_bank; i++) {
419 struct f7188x_gpio_bank *bank = &data->bank[i];
420
421 bank->chip.parent = &pdev->dev;
422 bank->data = data;
423
424 err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
425 if (err) {
426 dev_err(&pdev->dev,
427 "Failed to register gpiochip %d: %d\n",
428 i, err);
429 return err;
430 }
431 }
432
433 return 0;
434}
435
436static int __init f7188x_find(int addr, struct f7188x_sio *sio)
437{
438 int err;
439 u16 devid;
440
441 err = superio_enter(addr);
442 if (err)
443 return err;
444
445 err = -ENODEV;
446 devid = superio_inw(addr, SIO_MANID);
447 if (devid != SIO_FINTEK_ID) {
448 pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
449 goto err;
450 }
451
452 devid = superio_inw(addr, SIO_DEVID);
453 switch (devid) {
454 case SIO_F71869_ID:
455 sio->type = f71869;
456 break;
457 case SIO_F71869A_ID:
458 sio->type = f71869a;
459 break;
460 case SIO_F71882_ID:
461 sio->type = f71882fg;
462 break;
463 case SIO_F71889A_ID:
464 sio->type = f71889a;
465 break;
466 case SIO_F71889_ID:
467 sio->type = f71889f;
468 break;
469 case SIO_F81866_ID:
470 sio->type = f81866;
471 break;
472 default:
473 pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
474 goto err;
475 }
476 sio->addr = addr;
477 err = 0;
478
479 pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
480 f7188x_names[sio->type],
481 (unsigned int) addr,
482 (int) superio_inb(addr, SIO_DEVREV));
483
484err:
485 superio_exit(addr);
486 return err;
487}
488
489static struct platform_device *f7188x_gpio_pdev;
490
491static int __init
492f7188x_gpio_device_add(const struct f7188x_sio *sio)
493{
494 int err;
495
496 f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
497 if (!f7188x_gpio_pdev)
498 return -ENOMEM;
499
500 err = platform_device_add_data(f7188x_gpio_pdev,
501 sio, sizeof(*sio));
502 if (err) {
503 pr_err(DRVNAME "Platform data allocation failed\n");
504 goto err;
505 }
506
507 err = platform_device_add(f7188x_gpio_pdev);
508 if (err) {
509 pr_err(DRVNAME "Device addition failed\n");
510 goto err;
511 }
512
513 return 0;
514
515err:
516 platform_device_put(f7188x_gpio_pdev);
517
518 return err;
519}
520
521/*
522 * Try to match a supported Fintek device by reading the (hard-wired)
523 * configuration I/O ports. If available, then register both the platform
524 * device and driver to support the GPIOs.
525 */
526
527static struct platform_driver f7188x_gpio_driver = {
528 .driver = {
529 .name = DRVNAME,
530 },
531 .probe = f7188x_gpio_probe,
532};
533
534static int __init f7188x_gpio_init(void)
535{
536 int err;
537 struct f7188x_sio sio;
538
539 if (f7188x_find(0x2e, &sio) &&
540 f7188x_find(0x4e, &sio))
541 return -ENODEV;
542
543 err = platform_driver_register(&f7188x_gpio_driver);
544 if (!err) {
545 err = f7188x_gpio_device_add(&sio);
546 if (err)
547 platform_driver_unregister(&f7188x_gpio_driver);
548 }
549
550 return err;
551}
552subsys_initcall(f7188x_gpio_init);
553
554static void __exit f7188x_gpio_exit(void)
555{
556 platform_device_unregister(f7188x_gpio_pdev);
557 platform_driver_unregister(&f7188x_gpio_driver);
558}
559module_exit(f7188x_gpio_exit);
560
561MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
562MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
563MODULE_LICENSE("GPL");