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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7#include <linux/acpi.h>
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/property.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23
24#include "gpiolib-acpi.h"
25
26#define GPIO_SWPORTA_DR 0x00
27#define GPIO_SWPORTA_DDR 0x04
28#define GPIO_SWPORTB_DR 0x0c
29#define GPIO_SWPORTB_DDR 0x10
30#define GPIO_SWPORTC_DR 0x18
31#define GPIO_SWPORTC_DDR 0x1c
32#define GPIO_SWPORTD_DR 0x24
33#define GPIO_SWPORTD_DDR 0x28
34#define GPIO_INTEN 0x30
35#define GPIO_INTMASK 0x34
36#define GPIO_INTTYPE_LEVEL 0x38
37#define GPIO_INT_POLARITY 0x3c
38#define GPIO_INTSTATUS 0x40
39#define GPIO_PORTA_DEBOUNCE 0x48
40#define GPIO_PORTA_EOI 0x4c
41#define GPIO_EXT_PORTA 0x50
42#define GPIO_EXT_PORTB 0x54
43#define GPIO_EXT_PORTC 0x58
44#define GPIO_EXT_PORTD 0x5c
45
46#define DWAPB_DRIVER_NAME "gpio-dwapb"
47#define DWAPB_MAX_PORTS 4
48#define DWAPB_MAX_GPIOS 32
49
50#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
51#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
52#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
53
54#define GPIO_REG_OFFSET_V1 0
55#define GPIO_REG_OFFSET_V2 1
56#define GPIO_REG_OFFSET_MASK BIT(0)
57
58#define GPIO_INTMASK_V2 0x44
59#define GPIO_INTTYPE_LEVEL_V2 0x34
60#define GPIO_INT_POLARITY_V2 0x38
61#define GPIO_INTSTATUS_V2 0x3c
62#define GPIO_PORTA_EOI_V2 0x40
63
64#define DWAPB_NR_CLOCKS 2
65
66struct dwapb_gpio;
67
68struct dwapb_port_property {
69 struct fwnode_handle *fwnode;
70 unsigned int idx;
71 unsigned int ngpio;
72 unsigned int gpio_base;
73 int irq[DWAPB_MAX_GPIOS];
74};
75
76struct dwapb_platform_data {
77 struct dwapb_port_property *properties;
78 unsigned int nports;
79};
80
81#ifdef CONFIG_PM_SLEEP
82/* Store GPIO context across system-wide suspend/resume transitions */
83struct dwapb_context {
84 u32 data;
85 u32 dir;
86 u32 ext;
87 u32 int_en;
88 u32 int_mask;
89 u32 int_type;
90 u32 int_pol;
91 u32 int_deb;
92 u32 wake_en;
93};
94#endif
95
96struct dwapb_gpio_port_irqchip {
97 unsigned int nr_irqs;
98 unsigned int irq[DWAPB_MAX_GPIOS];
99};
100
101struct dwapb_gpio_port {
102 struct gpio_chip gc;
103 struct dwapb_gpio_port_irqchip *pirq;
104 struct dwapb_gpio *gpio;
105#ifdef CONFIG_PM_SLEEP
106 struct dwapb_context *ctx;
107#endif
108 unsigned int idx;
109};
110#define to_dwapb_gpio(_gc) \
111 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
112
113struct dwapb_gpio {
114 struct device *dev;
115 void __iomem *regs;
116 struct dwapb_gpio_port *ports;
117 unsigned int nr_ports;
118 unsigned int flags;
119 struct reset_control *rst;
120 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
121};
122
123static inline u32 gpio_reg_v2_convert(unsigned int offset)
124{
125 switch (offset) {
126 case GPIO_INTMASK:
127 return GPIO_INTMASK_V2;
128 case GPIO_INTTYPE_LEVEL:
129 return GPIO_INTTYPE_LEVEL_V2;
130 case GPIO_INT_POLARITY:
131 return GPIO_INT_POLARITY_V2;
132 case GPIO_INTSTATUS:
133 return GPIO_INTSTATUS_V2;
134 case GPIO_PORTA_EOI:
135 return GPIO_PORTA_EOI_V2;
136 }
137
138 return offset;
139}
140
141static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
142{
143 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
144 return gpio_reg_v2_convert(offset);
145
146 return offset;
147}
148
149static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
150{
151 struct gpio_chip *gc = &gpio->ports[0].gc;
152 void __iomem *reg_base = gpio->regs;
153
154 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
155}
156
157static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
158 u32 val)
159{
160 struct gpio_chip *gc = &gpio->ports[0].gc;
161 void __iomem *reg_base = gpio->regs;
162
163 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
164}
165
166static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
167{
168 struct dwapb_gpio_port *port;
169 int i;
170
171 for (i = 0; i < gpio->nr_ports; i++) {
172 port = &gpio->ports[i];
173 if (port->idx == offs / DWAPB_MAX_GPIOS)
174 return port;
175 }
176
177 return NULL;
178}
179
180static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
181{
182 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
183 struct gpio_chip *gc;
184 u32 pol;
185 int val;
186
187 if (!port)
188 return;
189 gc = &port->gc;
190
191 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
192 /* Just read the current value right out of the data register */
193 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
194 if (val)
195 pol &= ~BIT(offs);
196 else
197 pol |= BIT(offs);
198
199 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
200}
201
202static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
203{
204 struct gpio_chip *gc = &gpio->ports[0].gc;
205 unsigned long irq_status;
206 irq_hw_number_t hwirq;
207
208 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
209 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
210 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
211 u32 irq_type = irq_get_trigger_type(gpio_irq);
212
213 generic_handle_irq(gpio_irq);
214
215 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
216 dwapb_toggle_trigger(gpio, hwirq);
217 }
218
219 return irq_status;
220}
221
222static void dwapb_irq_handler(struct irq_desc *desc)
223{
224 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
225 struct irq_chip *chip = irq_desc_get_chip(desc);
226
227 chained_irq_enter(chip, desc);
228 dwapb_do_irq(gpio);
229 chained_irq_exit(chip, desc);
230}
231
232static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
233{
234 return IRQ_RETVAL(dwapb_do_irq(dev_id));
235}
236
237static void dwapb_irq_ack(struct irq_data *d)
238{
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
241 u32 val = BIT(irqd_to_hwirq(d));
242 unsigned long flags;
243
244 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
245 dwapb_write(gpio, GPIO_PORTA_EOI, val);
246 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
247}
248
249static void dwapb_irq_mask(struct irq_data *d)
250{
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
253 irq_hw_number_t hwirq = irqd_to_hwirq(d);
254 unsigned long flags;
255 u32 val;
256
257 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
258 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
259 dwapb_write(gpio, GPIO_INTMASK, val);
260 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
261
262 gpiochip_disable_irq(gc, hwirq);
263}
264
265static void dwapb_irq_unmask(struct irq_data *d)
266{
267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
269 irq_hw_number_t hwirq = irqd_to_hwirq(d);
270 unsigned long flags;
271 u32 val;
272
273 gpiochip_enable_irq(gc, hwirq);
274
275 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
276 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
277 dwapb_write(gpio, GPIO_INTMASK, val);
278 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
279}
280
281static void dwapb_irq_enable(struct irq_data *d)
282{
283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
284 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
285 irq_hw_number_t hwirq = irqd_to_hwirq(d);
286 unsigned long flags;
287 u32 val;
288
289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
290 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
291 dwapb_write(gpio, GPIO_INTEN, val);
292 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
293 dwapb_write(gpio, GPIO_INTMASK, val);
294 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
295}
296
297static void dwapb_irq_disable(struct irq_data *d)
298{
299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
300 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
301 irq_hw_number_t hwirq = irqd_to_hwirq(d);
302 unsigned long flags;
303 u32 val;
304
305 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
306 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
307 dwapb_write(gpio, GPIO_INTMASK, val);
308 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
309 dwapb_write(gpio, GPIO_INTEN, val);
310 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
311}
312
313static int dwapb_irq_set_type(struct irq_data *d, u32 type)
314{
315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
316 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
317 irq_hw_number_t bit = irqd_to_hwirq(d);
318 unsigned long level, polarity, flags;
319
320 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
321 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
322 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
323
324 switch (type) {
325 case IRQ_TYPE_EDGE_BOTH:
326 level |= BIT(bit);
327 dwapb_toggle_trigger(gpio, bit);
328 break;
329 case IRQ_TYPE_EDGE_RISING:
330 level |= BIT(bit);
331 polarity |= BIT(bit);
332 break;
333 case IRQ_TYPE_EDGE_FALLING:
334 level |= BIT(bit);
335 polarity &= ~BIT(bit);
336 break;
337 case IRQ_TYPE_LEVEL_HIGH:
338 level &= ~BIT(bit);
339 polarity |= BIT(bit);
340 break;
341 case IRQ_TYPE_LEVEL_LOW:
342 level &= ~BIT(bit);
343 polarity &= ~BIT(bit);
344 break;
345 }
346
347 if (type & IRQ_TYPE_LEVEL_MASK)
348 irq_set_handler_locked(d, handle_level_irq);
349 else if (type & IRQ_TYPE_EDGE_BOTH)
350 irq_set_handler_locked(d, handle_edge_irq);
351
352 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
353 if (type != IRQ_TYPE_EDGE_BOTH)
354 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
355 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
356
357 return 0;
358}
359
360#ifdef CONFIG_PM_SLEEP
361static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
362{
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
364 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
365 struct dwapb_context *ctx = gpio->ports[0].ctx;
366 irq_hw_number_t bit = irqd_to_hwirq(d);
367
368 if (enable)
369 ctx->wake_en |= BIT(bit);
370 else
371 ctx->wake_en &= ~BIT(bit);
372
373 return 0;
374}
375#else
376#define dwapb_irq_set_wake NULL
377#endif
378
379static const struct irq_chip dwapb_irq_chip = {
380 .name = DWAPB_DRIVER_NAME,
381 .irq_ack = dwapb_irq_ack,
382 .irq_mask = dwapb_irq_mask,
383 .irq_unmask = dwapb_irq_unmask,
384 .irq_set_type = dwapb_irq_set_type,
385 .irq_enable = dwapb_irq_enable,
386 .irq_disable = dwapb_irq_disable,
387 .irq_set_wake = dwapb_irq_set_wake,
388 .flags = IRQCHIP_IMMUTABLE,
389 GPIOCHIP_IRQ_RESOURCE_HELPERS,
390};
391
392static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
393 unsigned offset, unsigned debounce)
394{
395 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
396 struct dwapb_gpio *gpio = port->gpio;
397 unsigned long flags, val_deb;
398 unsigned long mask = BIT(offset);
399
400 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
401
402 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
403 if (debounce)
404 val_deb |= mask;
405 else
406 val_deb &= ~mask;
407 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
408
409 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
410
411 return 0;
412}
413
414static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
415 unsigned long config)
416{
417 u32 debounce;
418
419 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
420 debounce = pinconf_to_config_argument(config);
421 return dwapb_gpio_set_debounce(gc, offset, debounce);
422 }
423
424 return gpiochip_generic_config(gc, offset, config);
425}
426
427static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
428 struct dwapb_port_property *pp)
429{
430 int i;
431
432 /* Group all available IRQs into an array of parental IRQs. */
433 for (i = 0; i < pp->ngpio; ++i) {
434 if (!pp->irq[i])
435 continue;
436
437 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
438 }
439
440 return pirq->nr_irqs ? 0 : -ENOENT;
441}
442
443static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
444 struct dwapb_gpio_port *port,
445 struct dwapb_port_property *pp)
446{
447 struct dwapb_gpio_port_irqchip *pirq;
448 struct gpio_chip *gc = &port->gc;
449 struct gpio_irq_chip *girq;
450 int err;
451
452 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
453 if (!pirq)
454 return;
455
456 if (dwapb_convert_irqs(pirq, pp)) {
457 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
458 goto err_kfree_pirq;
459 }
460
461 girq = &gc->irq;
462 girq->handler = handle_bad_irq;
463 girq->default_type = IRQ_TYPE_NONE;
464
465 port->pirq = pirq;
466
467 /*
468 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
469 * IRQ lane shared between several devices. In that case the parental
470 * IRQ has to be handled in the shared way so to be properly delivered
471 * to all the connected devices.
472 */
473 if (has_acpi_companion(gpio->dev)) {
474 girq->num_parents = 0;
475 girq->parents = NULL;
476 girq->parent_handler = NULL;
477
478 err = devm_request_irq(gpio->dev, pp->irq[0],
479 dwapb_irq_handler_mfd,
480 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
481 if (err) {
482 dev_err(gpio->dev, "error requesting IRQ\n");
483 goto err_kfree_pirq;
484 }
485 } else {
486 girq->num_parents = pirq->nr_irqs;
487 girq->parents = pirq->irq;
488 girq->parent_handler_data = gpio;
489 girq->parent_handler = dwapb_irq_handler;
490 }
491
492 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
493
494 return;
495
496err_kfree_pirq:
497 devm_kfree(gpio->dev, pirq);
498}
499
500static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
501 struct dwapb_port_property *pp,
502 unsigned int offs)
503{
504 struct dwapb_gpio_port *port;
505 void __iomem *dat, *set, *dirout;
506 int err;
507
508 port = &gpio->ports[offs];
509 port->gpio = gpio;
510 port->idx = pp->idx;
511
512#ifdef CONFIG_PM_SLEEP
513 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
514 if (!port->ctx)
515 return -ENOMEM;
516#endif
517
518 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
519 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
520 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
521
522 /* This registers 32 GPIO lines per port */
523 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
524 NULL, 0);
525 if (err) {
526 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
527 port->idx);
528 return err;
529 }
530
531 port->gc.fwnode = pp->fwnode;
532 port->gc.ngpio = pp->ngpio;
533 port->gc.base = pp->gpio_base;
534 port->gc.request = gpiochip_generic_request;
535 port->gc.free = gpiochip_generic_free;
536
537 /* Only port A support debounce */
538 if (pp->idx == 0)
539 port->gc.set_config = dwapb_gpio_set_config;
540 else
541 port->gc.set_config = gpiochip_generic_config;
542
543 /* Only port A can provide interrupts in all configurations of the IP */
544 if (pp->idx == 0)
545 dwapb_configure_irqs(gpio, port, pp);
546
547 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
548 if (err) {
549 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
550 port->idx);
551 return err;
552 }
553
554 return 0;
555}
556
557static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
558 struct dwapb_port_property *pp)
559{
560 int irq, j;
561
562 for (j = 0; j < pp->ngpio; j++) {
563 if (has_acpi_companion(dev))
564 irq = platform_get_irq_optional(to_platform_device(dev), j);
565 else
566 irq = fwnode_irq_get(fwnode, j);
567 if (irq > 0)
568 pp->irq[j] = irq;
569 }
570}
571
572static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
573{
574 struct dwapb_platform_data *pdata;
575 struct dwapb_port_property *pp;
576 int nports;
577 int i;
578
579 nports = device_get_child_node_count(dev);
580 if (nports == 0)
581 return ERR_PTR(-ENODEV);
582
583 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
584 if (!pdata)
585 return ERR_PTR(-ENOMEM);
586
587 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
588 if (!pdata->properties)
589 return ERR_PTR(-ENOMEM);
590
591 pdata->nports = nports;
592
593 i = 0;
594 device_for_each_child_node_scoped(dev, fwnode) {
595 pp = &pdata->properties[i++];
596 pp->fwnode = fwnode;
597
598 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
599 pp->idx >= DWAPB_MAX_PORTS) {
600 dev_err(dev,
601 "missing/invalid port index for port%d\n", i);
602 return ERR_PTR(-EINVAL);
603 }
604
605 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
606 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
607 dev_info(dev,
608 "failed to get number of gpios for port%d\n",
609 i);
610 pp->ngpio = DWAPB_MAX_GPIOS;
611 }
612
613 pp->gpio_base = -1;
614
615 /* For internal use only, new platforms mustn't exercise this */
616 if (is_software_node(fwnode))
617 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
618
619 /*
620 * Only port A can provide interrupts in all configurations of
621 * the IP.
622 */
623 if (pp->idx == 0)
624 dwapb_get_irq(dev, fwnode, pp);
625 }
626
627 return pdata;
628}
629
630static void dwapb_assert_reset(void *data)
631{
632 struct dwapb_gpio *gpio = data;
633
634 reset_control_assert(gpio->rst);
635}
636
637static int dwapb_get_reset(struct dwapb_gpio *gpio)
638{
639 int err;
640
641 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
642 if (IS_ERR(gpio->rst))
643 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
644 "Cannot get reset descriptor\n");
645
646 err = reset_control_deassert(gpio->rst);
647 if (err) {
648 dev_err(gpio->dev, "Cannot deassert reset lane\n");
649 return err;
650 }
651
652 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
653}
654
655static void dwapb_disable_clks(void *data)
656{
657 struct dwapb_gpio *gpio = data;
658
659 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
660}
661
662static int dwapb_get_clks(struct dwapb_gpio *gpio)
663{
664 int err;
665
666 /* Optional bus and debounce clocks */
667 gpio->clks[0].id = "bus";
668 gpio->clks[1].id = "db";
669 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
670 gpio->clks);
671 if (err)
672 return dev_err_probe(gpio->dev, err,
673 "Cannot get APB/Debounce clocks\n");
674
675 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
676 if (err) {
677 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
678 return err;
679 }
680
681 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
682}
683
684static const struct of_device_id dwapb_of_match[] = {
685 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
686 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
687 { /* Sentinel */ }
688};
689MODULE_DEVICE_TABLE(of, dwapb_of_match);
690
691static const struct acpi_device_id dwapb_acpi_match[] = {
692 {"HISI0181", GPIO_REG_OFFSET_V1},
693 {"APMC0D07", GPIO_REG_OFFSET_V1},
694 {"APMC0D81", GPIO_REG_OFFSET_V2},
695 {"FUJI200A", GPIO_REG_OFFSET_V1},
696 { }
697};
698MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
699
700static int dwapb_gpio_probe(struct platform_device *pdev)
701{
702 unsigned int i;
703 struct dwapb_gpio *gpio;
704 int err;
705 struct dwapb_platform_data *pdata;
706 struct device *dev = &pdev->dev;
707
708 pdata = dwapb_gpio_get_pdata(dev);
709 if (IS_ERR(pdata))
710 return PTR_ERR(pdata);
711
712 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
713 if (!gpio)
714 return -ENOMEM;
715
716 gpio->dev = &pdev->dev;
717 gpio->nr_ports = pdata->nports;
718
719 err = dwapb_get_reset(gpio);
720 if (err)
721 return err;
722
723 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
724 sizeof(*gpio->ports), GFP_KERNEL);
725 if (!gpio->ports)
726 return -ENOMEM;
727
728 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
729 if (IS_ERR(gpio->regs))
730 return PTR_ERR(gpio->regs);
731
732 err = dwapb_get_clks(gpio);
733 if (err)
734 return err;
735
736 gpio->flags = (uintptr_t)device_get_match_data(dev);
737
738 for (i = 0; i < gpio->nr_ports; i++) {
739 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
740 if (err)
741 return err;
742 }
743
744 platform_set_drvdata(pdev, gpio);
745
746 return 0;
747}
748
749#ifdef CONFIG_PM_SLEEP
750static int dwapb_gpio_suspend(struct device *dev)
751{
752 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
753 struct gpio_chip *gc = &gpio->ports[0].gc;
754 unsigned long flags;
755 int i;
756
757 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
758 for (i = 0; i < gpio->nr_ports; i++) {
759 unsigned int offset;
760 unsigned int idx = gpio->ports[i].idx;
761 struct dwapb_context *ctx = gpio->ports[i].ctx;
762
763 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
764 ctx->dir = dwapb_read(gpio, offset);
765
766 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
767 ctx->data = dwapb_read(gpio, offset);
768
769 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
770 ctx->ext = dwapb_read(gpio, offset);
771
772 /* Only port A can provide interrupts */
773 if (idx == 0) {
774 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
775 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
776 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
777 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
778 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
779
780 /* Mask out interrupts */
781 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
782 }
783 }
784 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
785
786 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
787
788 return 0;
789}
790
791static int dwapb_gpio_resume(struct device *dev)
792{
793 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
794 struct gpio_chip *gc = &gpio->ports[0].gc;
795 unsigned long flags;
796 int i, err;
797
798 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
799 if (err) {
800 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
801 return err;
802 }
803
804 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
805 for (i = 0; i < gpio->nr_ports; i++) {
806 unsigned int offset;
807 unsigned int idx = gpio->ports[i].idx;
808 struct dwapb_context *ctx = gpio->ports[i].ctx;
809
810 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
811 dwapb_write(gpio, offset, ctx->data);
812
813 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
814 dwapb_write(gpio, offset, ctx->dir);
815
816 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
817 dwapb_write(gpio, offset, ctx->ext);
818
819 /* Only port A can provide interrupts */
820 if (idx == 0) {
821 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
822 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
823 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
824 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
825 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
826
827 /* Clear out spurious interrupts */
828 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
829 }
830 }
831 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
832
833 return 0;
834}
835#endif
836
837static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
838 dwapb_gpio_resume);
839
840static struct platform_driver dwapb_gpio_driver = {
841 .driver = {
842 .name = DWAPB_DRIVER_NAME,
843 .pm = &dwapb_gpio_pm_ops,
844 .of_match_table = dwapb_of_match,
845 .acpi_match_table = dwapb_acpi_match,
846 },
847 .probe = dwapb_gpio_probe,
848};
849
850module_platform_driver(dwapb_gpio_driver);
851
852MODULE_LICENSE("GPL");
853MODULE_AUTHOR("Jamie Iles");
854MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
855MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
1/*
2 * Copyright (c) 2011 Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/acpi.h>
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/gpio/driver.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_irq.h>
25#include <linux/platform_device.h>
26#include <linux/property.h>
27#include <linux/reset.h>
28#include <linux/spinlock.h>
29#include <linux/platform_data/gpio-dwapb.h>
30#include <linux/slab.h>
31
32#include "gpiolib.h"
33
34#define GPIO_SWPORTA_DR 0x00
35#define GPIO_SWPORTA_DDR 0x04
36#define GPIO_SWPORTB_DR 0x0c
37#define GPIO_SWPORTB_DDR 0x10
38#define GPIO_SWPORTC_DR 0x18
39#define GPIO_SWPORTC_DDR 0x1c
40#define GPIO_SWPORTD_DR 0x24
41#define GPIO_SWPORTD_DDR 0x28
42#define GPIO_INTEN 0x30
43#define GPIO_INTMASK 0x34
44#define GPIO_INTTYPE_LEVEL 0x38
45#define GPIO_INT_POLARITY 0x3c
46#define GPIO_INTSTATUS 0x40
47#define GPIO_PORTA_DEBOUNCE 0x48
48#define GPIO_PORTA_EOI 0x4c
49#define GPIO_EXT_PORTA 0x50
50#define GPIO_EXT_PORTB 0x54
51#define GPIO_EXT_PORTC 0x58
52#define GPIO_EXT_PORTD 0x5c
53
54#define DWAPB_MAX_PORTS 4
55#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
56#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
57#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
58
59#define GPIO_REG_OFFSET_V2 1
60
61#define GPIO_INTMASK_V2 0x44
62#define GPIO_INTTYPE_LEVEL_V2 0x34
63#define GPIO_INT_POLARITY_V2 0x38
64#define GPIO_INTSTATUS_V2 0x3c
65#define GPIO_PORTA_EOI_V2 0x40
66
67struct dwapb_gpio;
68
69#ifdef CONFIG_PM_SLEEP
70/* Store GPIO context across system-wide suspend/resume transitions */
71struct dwapb_context {
72 u32 data;
73 u32 dir;
74 u32 ext;
75 u32 int_en;
76 u32 int_mask;
77 u32 int_type;
78 u32 int_pol;
79 u32 int_deb;
80 u32 wake_en;
81};
82#endif
83
84struct dwapb_gpio_port {
85 struct gpio_chip gc;
86 bool is_registered;
87 struct dwapb_gpio *gpio;
88#ifdef CONFIG_PM_SLEEP
89 struct dwapb_context *ctx;
90#endif
91 unsigned int idx;
92};
93
94struct dwapb_gpio {
95 struct device *dev;
96 void __iomem *regs;
97 struct dwapb_gpio_port *ports;
98 unsigned int nr_ports;
99 struct irq_domain *domain;
100 unsigned int flags;
101 struct reset_control *rst;
102 struct clk *clk;
103};
104
105static inline u32 gpio_reg_v2_convert(unsigned int offset)
106{
107 switch (offset) {
108 case GPIO_INTMASK:
109 return GPIO_INTMASK_V2;
110 case GPIO_INTTYPE_LEVEL:
111 return GPIO_INTTYPE_LEVEL_V2;
112 case GPIO_INT_POLARITY:
113 return GPIO_INT_POLARITY_V2;
114 case GPIO_INTSTATUS:
115 return GPIO_INTSTATUS_V2;
116 case GPIO_PORTA_EOI:
117 return GPIO_PORTA_EOI_V2;
118 }
119
120 return offset;
121}
122
123static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
124{
125 if (gpio->flags & GPIO_REG_OFFSET_V2)
126 return gpio_reg_v2_convert(offset);
127
128 return offset;
129}
130
131static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
132{
133 struct gpio_chip *gc = &gpio->ports[0].gc;
134 void __iomem *reg_base = gpio->regs;
135
136 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
137}
138
139static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
140 u32 val)
141{
142 struct gpio_chip *gc = &gpio->ports[0].gc;
143 void __iomem *reg_base = gpio->regs;
144
145 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
146}
147
148static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
149{
150 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
151 struct dwapb_gpio *gpio = port->gpio;
152
153 return irq_find_mapping(gpio->domain, offset);
154}
155
156static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
157{
158 struct dwapb_gpio_port *port;
159 int i;
160
161 for (i = 0; i < gpio->nr_ports; i++) {
162 port = &gpio->ports[i];
163 if (port->idx == offs / 32)
164 return port;
165 }
166
167 return NULL;
168}
169
170static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
171{
172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
173 struct gpio_chip *gc;
174 u32 pol;
175 int val;
176
177 if (!port)
178 return;
179 gc = &port->gc;
180
181 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
182 /* Just read the current value right out of the data register */
183 val = gc->get(gc, offs % 32);
184 if (val)
185 pol &= ~BIT(offs);
186 else
187 pol |= BIT(offs);
188
189 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
190}
191
192static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
193{
194 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
195 u32 ret = irq_status;
196
197 while (irq_status) {
198 int hwirq = fls(irq_status) - 1;
199 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
200
201 generic_handle_irq(gpio_irq);
202 irq_status &= ~BIT(hwirq);
203
204 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
205 == IRQ_TYPE_EDGE_BOTH)
206 dwapb_toggle_trigger(gpio, hwirq);
207 }
208
209 return ret;
210}
211
212static void dwapb_irq_handler(struct irq_desc *desc)
213{
214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
215 struct irq_chip *chip = irq_desc_get_chip(desc);
216
217 dwapb_do_irq(gpio);
218
219 if (chip->irq_eoi)
220 chip->irq_eoi(irq_desc_get_irq_data(desc));
221}
222
223static void dwapb_irq_enable(struct irq_data *d)
224{
225 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
226 struct dwapb_gpio *gpio = igc->private;
227 struct gpio_chip *gc = &gpio->ports[0].gc;
228 unsigned long flags;
229 u32 val;
230
231 spin_lock_irqsave(&gc->bgpio_lock, flags);
232 val = dwapb_read(gpio, GPIO_INTEN);
233 val |= BIT(d->hwirq);
234 dwapb_write(gpio, GPIO_INTEN, val);
235 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
236}
237
238static void dwapb_irq_disable(struct irq_data *d)
239{
240 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
241 struct dwapb_gpio *gpio = igc->private;
242 struct gpio_chip *gc = &gpio->ports[0].gc;
243 unsigned long flags;
244 u32 val;
245
246 spin_lock_irqsave(&gc->bgpio_lock, flags);
247 val = dwapb_read(gpio, GPIO_INTEN);
248 val &= ~BIT(d->hwirq);
249 dwapb_write(gpio, GPIO_INTEN, val);
250 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
251}
252
253static int dwapb_irq_reqres(struct irq_data *d)
254{
255 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
256 struct dwapb_gpio *gpio = igc->private;
257 struct gpio_chip *gc = &gpio->ports[0].gc;
258
259 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
260 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
261 irqd_to_hwirq(d));
262 return -EINVAL;
263 }
264 return 0;
265}
266
267static void dwapb_irq_relres(struct irq_data *d)
268{
269 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
270 struct dwapb_gpio *gpio = igc->private;
271 struct gpio_chip *gc = &gpio->ports[0].gc;
272
273 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
274}
275
276static int dwapb_irq_set_type(struct irq_data *d, u32 type)
277{
278 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
279 struct dwapb_gpio *gpio = igc->private;
280 struct gpio_chip *gc = &gpio->ports[0].gc;
281 int bit = d->hwirq;
282 unsigned long level, polarity, flags;
283
284 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
285 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
286 return -EINVAL;
287
288 spin_lock_irqsave(&gc->bgpio_lock, flags);
289 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
290 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
291
292 switch (type) {
293 case IRQ_TYPE_EDGE_BOTH:
294 level |= BIT(bit);
295 dwapb_toggle_trigger(gpio, bit);
296 break;
297 case IRQ_TYPE_EDGE_RISING:
298 level |= BIT(bit);
299 polarity |= BIT(bit);
300 break;
301 case IRQ_TYPE_EDGE_FALLING:
302 level |= BIT(bit);
303 polarity &= ~BIT(bit);
304 break;
305 case IRQ_TYPE_LEVEL_HIGH:
306 level &= ~BIT(bit);
307 polarity |= BIT(bit);
308 break;
309 case IRQ_TYPE_LEVEL_LOW:
310 level &= ~BIT(bit);
311 polarity &= ~BIT(bit);
312 break;
313 }
314
315 irq_setup_alt_chip(d, type);
316
317 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
318 if (type != IRQ_TYPE_EDGE_BOTH)
319 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
320 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
321
322 return 0;
323}
324
325#ifdef CONFIG_PM_SLEEP
326static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
327{
328 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
329 struct dwapb_gpio *gpio = igc->private;
330 struct dwapb_context *ctx = gpio->ports[0].ctx;
331
332 if (enable)
333 ctx->wake_en |= BIT(d->hwirq);
334 else
335 ctx->wake_en &= ~BIT(d->hwirq);
336
337 return 0;
338}
339#endif
340
341static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
342 unsigned offset, unsigned debounce)
343{
344 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
345 struct dwapb_gpio *gpio = port->gpio;
346 unsigned long flags, val_deb;
347 unsigned long mask = BIT(offset);
348
349 spin_lock_irqsave(&gc->bgpio_lock, flags);
350
351 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
352 if (debounce)
353 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
354 else
355 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
356
357 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
358
359 return 0;
360}
361
362static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
363 unsigned long config)
364{
365 u32 debounce;
366
367 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
368 return -ENOTSUPP;
369
370 debounce = pinconf_to_config_argument(config);
371 return dwapb_gpio_set_debounce(gc, offset, debounce);
372}
373
374static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
375{
376 u32 worked;
377 struct dwapb_gpio *gpio = dev_id;
378
379 worked = dwapb_do_irq(gpio);
380
381 return worked ? IRQ_HANDLED : IRQ_NONE;
382}
383
384static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
385 struct dwapb_gpio_port *port,
386 struct dwapb_port_property *pp)
387{
388 struct gpio_chip *gc = &port->gc;
389 struct fwnode_handle *fwnode = pp->fwnode;
390 struct irq_chip_generic *irq_gc = NULL;
391 unsigned int hwirq, ngpio = gc->ngpio;
392 struct irq_chip_type *ct;
393 int err, i;
394
395 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
396 &irq_generic_chip_ops, gpio);
397 if (!gpio->domain)
398 return;
399
400 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
401 "gpio-dwapb", handle_level_irq,
402 IRQ_NOREQUEST, 0,
403 IRQ_GC_INIT_NESTED_LOCK);
404 if (err) {
405 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
406 irq_domain_remove(gpio->domain);
407 gpio->domain = NULL;
408 return;
409 }
410
411 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
412 if (!irq_gc) {
413 irq_domain_remove(gpio->domain);
414 gpio->domain = NULL;
415 return;
416 }
417
418 irq_gc->reg_base = gpio->regs;
419 irq_gc->private = gpio;
420
421 for (i = 0; i < 2; i++) {
422 ct = &irq_gc->chip_types[i];
423 ct->chip.irq_ack = irq_gc_ack_set_bit;
424 ct->chip.irq_mask = irq_gc_mask_set_bit;
425 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
426 ct->chip.irq_set_type = dwapb_irq_set_type;
427 ct->chip.irq_enable = dwapb_irq_enable;
428 ct->chip.irq_disable = dwapb_irq_disable;
429 ct->chip.irq_request_resources = dwapb_irq_reqres;
430 ct->chip.irq_release_resources = dwapb_irq_relres;
431#ifdef CONFIG_PM_SLEEP
432 ct->chip.irq_set_wake = dwapb_irq_set_wake;
433#endif
434 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
435 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
436 ct->type = IRQ_TYPE_LEVEL_MASK;
437 }
438
439 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
440 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
441 irq_gc->chip_types[1].handler = handle_edge_irq;
442
443 if (!pp->irq_shared) {
444 irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
445 gpio);
446 } else {
447 /*
448 * Request a shared IRQ since where MFD would have devices
449 * using the same irq pin
450 */
451 err = devm_request_irq(gpio->dev, pp->irq,
452 dwapb_irq_handler_mfd,
453 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
454 if (err) {
455 dev_err(gpio->dev, "error requesting IRQ\n");
456 irq_domain_remove(gpio->domain);
457 gpio->domain = NULL;
458 return;
459 }
460 }
461
462 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
463 irq_create_mapping(gpio->domain, hwirq);
464
465 port->gc.to_irq = dwapb_gpio_to_irq;
466}
467
468static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
469{
470 struct dwapb_gpio_port *port = &gpio->ports[0];
471 struct gpio_chip *gc = &port->gc;
472 unsigned int ngpio = gc->ngpio;
473 irq_hw_number_t hwirq;
474
475 if (!gpio->domain)
476 return;
477
478 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
479 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
480
481 irq_domain_remove(gpio->domain);
482 gpio->domain = NULL;
483}
484
485static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
486 struct dwapb_port_property *pp,
487 unsigned int offs)
488{
489 struct dwapb_gpio_port *port;
490 void __iomem *dat, *set, *dirout;
491 int err;
492
493 port = &gpio->ports[offs];
494 port->gpio = gpio;
495 port->idx = pp->idx;
496
497#ifdef CONFIG_PM_SLEEP
498 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
499 if (!port->ctx)
500 return -ENOMEM;
501#endif
502
503 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
504 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
505 dirout = gpio->regs + GPIO_SWPORTA_DDR +
506 (pp->idx * GPIO_SWPORT_DDR_STRIDE);
507
508 /* This registers 32 GPIO lines per port */
509 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
510 NULL, 0);
511 if (err) {
512 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
513 port->idx);
514 return err;
515 }
516
517#ifdef CONFIG_OF_GPIO
518 port->gc.of_node = to_of_node(pp->fwnode);
519#endif
520 port->gc.ngpio = pp->ngpio;
521 port->gc.base = pp->gpio_base;
522
523 /* Only port A support debounce */
524 if (pp->idx == 0)
525 port->gc.set_config = dwapb_gpio_set_config;
526
527 if (pp->irq)
528 dwapb_configure_irqs(gpio, port, pp);
529
530 err = gpiochip_add_data(&port->gc, port);
531 if (err)
532 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
533 port->idx);
534 else
535 port->is_registered = true;
536
537 /* Add GPIO-signaled ACPI event support */
538 if (pp->irq)
539 acpi_gpiochip_request_interrupts(&port->gc);
540
541 return err;
542}
543
544static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
545{
546 unsigned int m;
547
548 for (m = 0; m < gpio->nr_ports; ++m)
549 if (gpio->ports[m].is_registered)
550 gpiochip_remove(&gpio->ports[m].gc);
551}
552
553static struct dwapb_platform_data *
554dwapb_gpio_get_pdata(struct device *dev)
555{
556 struct fwnode_handle *fwnode;
557 struct dwapb_platform_data *pdata;
558 struct dwapb_port_property *pp;
559 int nports;
560 int i;
561
562 nports = device_get_child_node_count(dev);
563 if (nports == 0)
564 return ERR_PTR(-ENODEV);
565
566 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
567 if (!pdata)
568 return ERR_PTR(-ENOMEM);
569
570 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
571 if (!pdata->properties)
572 return ERR_PTR(-ENOMEM);
573
574 pdata->nports = nports;
575
576 i = 0;
577 device_for_each_child_node(dev, fwnode) {
578 pp = &pdata->properties[i++];
579 pp->fwnode = fwnode;
580
581 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
582 pp->idx >= DWAPB_MAX_PORTS) {
583 dev_err(dev,
584 "missing/invalid port index for port%d\n", i);
585 fwnode_handle_put(fwnode);
586 return ERR_PTR(-EINVAL);
587 }
588
589 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
590 &pp->ngpio)) {
591 dev_info(dev,
592 "failed to get number of gpios for port%d\n",
593 i);
594 pp->ngpio = 32;
595 }
596
597 /*
598 * Only port A can provide interrupts in all configurations of
599 * the IP.
600 */
601 if (dev->of_node && pp->idx == 0 &&
602 fwnode_property_read_bool(fwnode,
603 "interrupt-controller")) {
604 pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0);
605 if (!pp->irq)
606 dev_warn(dev, "no irq for port%d\n", pp->idx);
607 }
608
609 if (has_acpi_companion(dev) && pp->idx == 0)
610 pp->irq = platform_get_irq(to_platform_device(dev), 0);
611
612 pp->irq_shared = false;
613 pp->gpio_base = -1;
614 }
615
616 return pdata;
617}
618
619static const struct of_device_id dwapb_of_match[] = {
620 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
621 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
622 { /* Sentinel */ }
623};
624MODULE_DEVICE_TABLE(of, dwapb_of_match);
625
626static const struct acpi_device_id dwapb_acpi_match[] = {
627 {"HISI0181", 0},
628 {"APMC0D07", 0},
629 {"APMC0D81", GPIO_REG_OFFSET_V2},
630 { }
631};
632MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
633
634static int dwapb_gpio_probe(struct platform_device *pdev)
635{
636 unsigned int i;
637 struct resource *res;
638 struct dwapb_gpio *gpio;
639 int err;
640 struct device *dev = &pdev->dev;
641 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
642
643 if (!pdata) {
644 pdata = dwapb_gpio_get_pdata(dev);
645 if (IS_ERR(pdata))
646 return PTR_ERR(pdata);
647 }
648
649 if (!pdata->nports)
650 return -ENODEV;
651
652 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
653 if (!gpio)
654 return -ENOMEM;
655
656 gpio->dev = &pdev->dev;
657 gpio->nr_ports = pdata->nports;
658
659 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
660 if (IS_ERR(gpio->rst))
661 return PTR_ERR(gpio->rst);
662
663 reset_control_deassert(gpio->rst);
664
665 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
666 sizeof(*gpio->ports), GFP_KERNEL);
667 if (!gpio->ports)
668 return -ENOMEM;
669
670 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
671 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
672 if (IS_ERR(gpio->regs))
673 return PTR_ERR(gpio->regs);
674
675 /* Optional bus clock */
676 gpio->clk = devm_clk_get(&pdev->dev, "bus");
677 if (!IS_ERR(gpio->clk)) {
678 err = clk_prepare_enable(gpio->clk);
679 if (err) {
680 dev_info(&pdev->dev, "Cannot enable clock\n");
681 return err;
682 }
683 }
684
685 gpio->flags = 0;
686 if (dev->of_node) {
687 const struct of_device_id *of_devid;
688
689 of_devid = of_match_device(dwapb_of_match, dev);
690 if (of_devid) {
691 if (of_devid->data)
692 gpio->flags = (uintptr_t)of_devid->data;
693 }
694 } else if (has_acpi_companion(dev)) {
695 const struct acpi_device_id *acpi_id;
696
697 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
698 if (acpi_id) {
699 if (acpi_id->driver_data)
700 gpio->flags = acpi_id->driver_data;
701 }
702 }
703
704 for (i = 0; i < gpio->nr_ports; i++) {
705 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
706 if (err)
707 goto out_unregister;
708 }
709 platform_set_drvdata(pdev, gpio);
710
711 return 0;
712
713out_unregister:
714 dwapb_gpio_unregister(gpio);
715 dwapb_irq_teardown(gpio);
716
717 return err;
718}
719
720static int dwapb_gpio_remove(struct platform_device *pdev)
721{
722 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
723
724 dwapb_gpio_unregister(gpio);
725 dwapb_irq_teardown(gpio);
726 reset_control_assert(gpio->rst);
727 clk_disable_unprepare(gpio->clk);
728
729 return 0;
730}
731
732#ifdef CONFIG_PM_SLEEP
733static int dwapb_gpio_suspend(struct device *dev)
734{
735 struct platform_device *pdev = to_platform_device(dev);
736 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
737 struct gpio_chip *gc = &gpio->ports[0].gc;
738 unsigned long flags;
739 int i;
740
741 spin_lock_irqsave(&gc->bgpio_lock, flags);
742 for (i = 0; i < gpio->nr_ports; i++) {
743 unsigned int offset;
744 unsigned int idx = gpio->ports[i].idx;
745 struct dwapb_context *ctx = gpio->ports[i].ctx;
746
747 BUG_ON(!ctx);
748
749 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
750 ctx->dir = dwapb_read(gpio, offset);
751
752 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
753 ctx->data = dwapb_read(gpio, offset);
754
755 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
756 ctx->ext = dwapb_read(gpio, offset);
757
758 /* Only port A can provide interrupts */
759 if (idx == 0) {
760 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
761 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
762 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
763 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
764 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
765
766 /* Mask out interrupts */
767 dwapb_write(gpio, GPIO_INTMASK,
768 0xffffffff & ~ctx->wake_en);
769 }
770 }
771 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
772
773 clk_disable_unprepare(gpio->clk);
774
775 return 0;
776}
777
778static int dwapb_gpio_resume(struct device *dev)
779{
780 struct platform_device *pdev = to_platform_device(dev);
781 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
782 struct gpio_chip *gc = &gpio->ports[0].gc;
783 unsigned long flags;
784 int i;
785
786 if (!IS_ERR(gpio->clk))
787 clk_prepare_enable(gpio->clk);
788
789 spin_lock_irqsave(&gc->bgpio_lock, flags);
790 for (i = 0; i < gpio->nr_ports; i++) {
791 unsigned int offset;
792 unsigned int idx = gpio->ports[i].idx;
793 struct dwapb_context *ctx = gpio->ports[i].ctx;
794
795 BUG_ON(!ctx);
796
797 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
798 dwapb_write(gpio, offset, ctx->data);
799
800 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
801 dwapb_write(gpio, offset, ctx->dir);
802
803 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
804 dwapb_write(gpio, offset, ctx->ext);
805
806 /* Only port A can provide interrupts */
807 if (idx == 0) {
808 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
809 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
810 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
811 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
812 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
813
814 /* Clear out spurious interrupts */
815 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
816 }
817 }
818 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
819
820 return 0;
821}
822#endif
823
824static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
825 dwapb_gpio_resume);
826
827static struct platform_driver dwapb_gpio_driver = {
828 .driver = {
829 .name = "gpio-dwapb",
830 .pm = &dwapb_gpio_pm_ops,
831 .of_match_table = of_match_ptr(dwapb_of_match),
832 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
833 },
834 .probe = dwapb_gpio_probe,
835 .remove = dwapb_gpio_remove,
836};
837
838module_platform_driver(dwapb_gpio_driver);
839
840MODULE_LICENSE("GPL");
841MODULE_AUTHOR("Jamie Iles");
842MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");